Flip-chip light emitting diode chip and method of manufacturing the same

Abstract

This invention provides a flip-chip light-emitting diode (LED) and its fabrication method. The flip-chip LED includes a substrate; a semiconductor epitaxial layer located on the substrate, comprising an N-type semiconductor layer, an active light-emitting layer, and a P-type semiconductor layer in sequence; and a reflective layer disposed above the P-type semiconductor layer. The reflective layer includes a first sub-layer of the reflective layer and a second sub-layer of the reflective layer located above the first sub-layer of the reflective layer. The first sub-layer of the reflective layer is an Ag metal layer. The second sub-layer of the reflective layer includes at least one pair of Ti metal layers and Ni metal layers stacked together, and a PdPt alloy layer is inserted at the interface between each Ti metal layer and the Ni metal layer. Furthermore, the thickness of the PdPt alloy layer increases linearly from the interface between the Ti metal layer and the Ni metal layer near the first sub-layer of the reflective layer to the interface away from the first sub-layer of the reflective layer, thus avoiding the formation of voids inside the Ni layer.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor technology, and specifically relates to a flip-chip light-emitting diode and its fabrication method. Background Technology

[0002] Flip-chip LEDs are widely used due to their advantages such as back-side light emission, good solderability, high thrust, and high reliability. In recent years, flip-chip LEDs using Ag metal as the reflective layer have significantly improved luminous brightness compared to traditional Bragg mirrors. However, Ag metal is prone to electromigration, requiring a Ti and Ni metal stacked structure on top for protection.

[0003] In the actual fabrication process, the Ti / Ni stack needs to undergo high-temperature annealing. During this process, Ni metal diffuses into the Ti metal layer, causing voids to form inside the Ni layer. These voids reduce the chip's heat dissipation capacity, thus affecting the device's reliability and lifespan.

[0004] To address the above problems, this invention provides a flip-chip light-emitting diode and its fabrication method, aiming to solve the technical problem of voids in the Ni layer during the high-temperature annealing process of Ti / Ni stacks. Summary of the Invention

[0005] To address the aforementioned technical problems, this invention provides a flip-chip light-emitting diode and its fabrication method, thereby resolving the technical issues described in the background section.

[0006] On the one hand, the invention provides the following technical solution: a flip-chip light-emitting diode, comprising: Substrate; A semiconductor epitaxial layer, located on the substrate, comprises, in sequence, an N-type semiconductor layer, an active light-emitting layer, and a P-type semiconductor layer; A reflective layer is disposed above the P-type semiconductor layer, the reflective layer including a first sub-layer of reflective layer and a second sub-layer of reflective layer located above the first sub-layer of reflective layer; The first sub-layer of the reflective layer is an Ag metal layer; the second sub-layer of the reflective layer includes a stack of at least one pair of Ti metal layers and Ni metal layers, and a PdPt alloy layer is inserted at the interface between each Ti metal layer and the Ni metal layer; and the thickness of the PdPt alloy layer increases linearly from the interface between the Ti metal layer and the Ni metal layer near the first sub-layer of the reflective layer to the interface between the Ti metal layer and the Ni metal layer away from the first sub-layer of the reflective layer.

[0007] Compared with the prior art, the beneficial effects of the present invention are: by inserting a PdPt alloy layer at the Ti / Ni stack interface of the reflective layer, the excellent diffusion blocking properties of the PdPt alloy significantly suppress the diffusion of Ni atoms into the Ti layer during high-temperature annealing, thus avoiding the formation of voids inside the Ni layer.

[0008] Furthermore, the second sub-layer of the reflective layer comprises a stack of 2 to 3 pairs of Ti metal layers and Ni metal layers.

[0009] Furthermore, the thickness of the first sublayer of the reflective layer is 1200–2000 Å; In the second sub-layer of the reflective layer, the thickness of a single Ti metal layer is 1000–2000 Å, and the thickness of a single Ni metal layer is 1000–2000 Å.

[0010] Furthermore, the mass ratio of Pd to Pt in the PdPt alloy layer is 7:3 to 5:5; The thickness of the PdPt alloy layer is 5–50 Å.

[0011] Furthermore, the thickness of the PdPt alloy layer increases linearly from the interface between the Ti metal layer and the Ni metal layer near the first sub-layer of the reflective layer to the interface between the Ti metal layer and the Ni metal layer away from the first sub-layer of the reflective layer, with the thickness gradually increasing.

[0012] Furthermore, it also includes: A current spreading layer is disposed on the P-type semiconductor layer; A current blocking layer and a Bragg reflector layer are sequentially disposed between the current spreading layer and the reflector layer; A first insulating layer is disposed above the reflective layer; A connecting metal layer is disposed above the first insulating layer; A second insulating layer is disposed above the connecting metal layer; P-type pad layers and N-type pad layers are disposed above the second insulating layer.

[0013] On the other hand, the present invention also proposes a method for fabricating a flip-chip light-emitting diode, the method comprising the following steps: A substrate is provided, on which an N-type semiconductor layer, an active light-emitting layer, and a P-type semiconductor layer are sequentially deposited, and conductive steps of the N-type semiconductor layer are etched. A current spreading layer is formed on the surface of the conductive steps of the P-type semiconductor layer and the N-type semiconductor layer; The conductive steps of the N-type semiconductor layer are etched to form isolation trenches; A current blocking layer is formed above the current spreading layer; Alternating layers of first and second refractive index material are deposited over the current blocking layer to form a Bragg reflection layer, and the Bragg reflection layer is etched to form P-type and N-type vias that expose the current blocking layer. Remove the current blocking layer at the bottom of the P-type and N-type vias to expose the underlying current spreading layer or the conductive step of the N-type semiconductor layer. A reflective layer is formed on the Bragg reflective layer, the reflective layer comprising a first sub-layer and a second sub-layer above the first sub-layer; wherein the first sub-layer is an Ag metal layer; the second sub-layer comprises at least one pair of Ti metal layers and Ni metal layers, and a PdPt alloy layer is inserted at the interface between each Ti metal layer and Ni metal layer; and the thickness of the PdPt alloy layer increases linearly from the Ti / Ni interface near the first sub-layer to the Ti / Ni interface away from the first sub-layer; the reflective layer is then subjected to rapid annealing. A first insulating material layer and a second insulating material layer are sequentially deposited on top of the reflective layer to form a first insulating layer with a composite structure, and P-type first insulating layer vias and N-type first insulating layer vias that expose part of the reflective layer are etched. A connecting metal layer is formed in the first insulating layer and the P-type and N-type first insulating layer through holes, the connecting metal layer including a P-type connecting metal layer and an N-type connecting metal layer; A second insulating material layer is deposited over the connecting metal layer to form a second insulating layer; A P-type pad layer and an N-type pad layer are formed on the second insulating layer.

[0014] Furthermore, the rapid annealing conditions are as follows: annealing at 400–450°C for 160–200 seconds in an N2 atmosphere.

[0015] Furthermore, the current blocking layer is a SiO2 layer with a thickness greater than 5000 Å; the Bragg reflector layer is an alternating stack of 3 to 5 groups of TiO2 layers and SiO2 layers.

[0016] Furthermore, the first insulating layer is formed by depositing an Al2O3 thin film using an ALD process and then depositing a SiO2 thin film using a PECVD process. Attached Figure Description

[0017] Figure 1 This is a schematic diagram of the overall structure of the flip-chip light-emitting diode in the first embodiment of the present invention; Figure 2 This is a schematic diagram of the structure of the N-type semiconductor layer conductive steps formed after step S01 is completed in the second embodiment of the present invention; Figure 3This is a schematic diagram of the structure of the current spreading layer formed after step S02 in the second embodiment of the present invention; Figure 4 This is a schematic diagram of the structure of the isolation groove formed after step S03 in the second embodiment of the present invention; Figure 5 This is a schematic diagram of the structure of the Bragg reflector layer and its through-hole formed after step S04 in the second embodiment of the present invention; Figure 6 This is a schematic diagram of the structure after step S05 of the second embodiment of the present invention, showing the removal of the current blocking layer at the bottom of the through hole; Figure 7 This is a schematic diagram of the structure of the reflective layer formed after step S06 in the second embodiment of the present invention; Figure 8 This is a schematic diagram of the structure of the first insulating layer and its through hole formed after step S07 is completed in the second embodiment of the present invention; Figure 9 This is a schematic diagram of the structure formed after step S08 in the second embodiment of the present invention; Figure 10 This is a partial structural diagram of the second sub-layer of the reflective layer on the first sub-layer of the reflective layer in the second embodiment of the present invention, used to illustrate the insertion positions of the Ti / Ni stack and the PdPt alloy layer.

[0018] Key component symbols: 10. Substrate; 111. N-type semiconductor layer; 112. Active light-emitting layer; 113. P-type semiconductor layer; 114. Conductive step of N-type semiconductor layer; 115. Isolation trench; 12. Current spreading layer; 13. Current blocking layer; 14. Bragg reflector layer; 141. P-type Bragg reflector layer via; 142. N-type Bragg reflector layer via; 15. Reflective layer; 16. First insulating layer; 161. P-type first insulating layer via; 162. N-type first insulating layer via; 17. Connecting metal layer; 171. P-type connecting metal layer; 172. N-type connecting metal layer; 18. Second insulating layer; 191. P-type pad layer; 192. N-type pad layer. 131 The following detailed description, in conjunction with the accompanying drawings, will further illustrate the present invention. Detailed Implementation

[0019] To facilitate understanding of the present invention, a more complete description will be given below with reference to the accompanying drawings. Several embodiments of the invention are illustrated in the drawings. However, the invention can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

[0020] It should be noted that when a component is said to be "fixed to" another component, it can be directly on the other component or there may be an intervening component. When a component is said to be "connected to" another component, it can be directly connected to the other component or there may be an intervening component. The terms "vertical," "horizontal," "left," "right," and similar expressions used in this document are for illustrative purposes only.

[0021] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used herein in the description of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0022] Example 1 Please see Figure 1 The image shows a flip-chip light-emitting diode (LED) according to Embodiment 1 of the present invention, comprising: Substrate 10; The semiconductor epitaxial layer, located on the substrate 10, comprises, in sequence, an N-type semiconductor layer 111, an active light-emitting layer 112, and a P-type semiconductor layer 113; A reflective layer 15 is disposed above the P-type semiconductor layer 113. The reflective layer 15 includes a first sub-layer of the reflective layer and a second sub-layer of the reflective layer located above the first sub-layer of the reflective layer. The first sub-layer of the reflective layer is an Ag metal layer; the second sub-layer of the reflective layer includes a stack of at least one pair of Ti metal layers and Ni metal layers, and a PdPt alloy layer is inserted at the interface between each Ti metal layer and the Ni metal layer; and the thickness of the PdPt alloy layer increases linearly from the interface between the Ti metal layer and the Ni metal layer near the first sub-layer of the reflective layer to the interface between the Ti metal layer and the Ni metal layer away from the first sub-layer of the reflective layer.

[0023] Optionally, the second sub-layer of the reflective layer comprises a stack of 2 to 3 pairs of Ti metal layers and Ni metal layers; The thickness of the first sublayer of the reflective layer is 1200–2000 Å; In the second sub-layer of the reflective layer, the thickness of a single Ti metal layer is 1000–2000 Å, and the thickness of a single Ni metal layer is 1000–2000 Å.

[0024] Optionally, the mass ratio of Pd to Pt in the PdPt alloy layer is 7:3 to 5:5; The thickness of the PdPt alloy layer is 5–50 Å.

[0025] Specifically, the thickness of the PdPt alloy layer increases linearly from the interface between the Ti metal layer and the Ni metal layer near the first sub-layer of the reflective layer to the interface between the Ti metal layer and the Ni metal layer away from the first sub-layer of the reflective layer, with the thickness gradually increasing.

[0026] The interface design of gradient thickness PdPt alloy and Ti / Ni metal layer is adopted, which is not a simple uniform insertion. The thickness of PdPt alloy increases linearly from near the Ag layer (the first sub-layer of the reflective layer) to far away from the Ag layer.

[0027] Near the Ti / Ni interface of the Ag layer, the PdPt alloy thickness is 5-20 Å, which is suitable for the low-temperature stability requirements of the Ag layer and avoids the reflection efficiency of the Ag layer being affected by excessively thick alloys; far from the Ti / Ni interface of the Ag layer, the PdPt alloy thickness is 30-50 Å, which specifically improves the tolerance to subsequent high-temperature processes (200-450℃) and strengthens the diffusion blocking effect.

[0028] Meanwhile, the PdPt alloy adopts an atomic ratio optimization of 7:3-5:5. This ratio has been verified by multiple experiments and can accurately match the single-layer thickness of Ti (1000-2000A) and Ni (1000-2000A) to form a "Ti-PdPt-Ni" transition structure. This not only blocks the diffusion of Ni to Ti, but also reduces the stress concentration at the Ti / Ni interface, further suppressing the generation of voids, while improving the overall adhesion of the second sublayer of the reflective layer.

[0029] Specifically, it also includes: A current spreading layer 12 is disposed on the P-type semiconductor layer 113; A current blocking layer 13 and a Bragg reflector layer 14 are sequentially disposed between the current spreading layer 12 and the reflector layer 15; A first insulating layer 16 is disposed above the reflective layer 15; The connecting metal layer 17 is disposed above the first insulating layer 16; The second insulating layer 18 is disposed above the connecting metal layer 17; P-type pad layer 191 and N-type pad layer 192 are disposed above the second insulating layer 18.

[0030] To further explain, the structure of a flip-chip LED is as follows: Figure 1 As shown, it includes: Substrate 10: Selected from GaN substrate 10, Al2O3 substrate 10 or Si substrate 10, and Al2O3 substrate 10 is preferred in this embodiment.

[0031] Semiconductor epitaxial layer: Located on substrate 10, it sequentially includes an N-type semiconductor layer 111, an active light-emitting layer 112, and a P-type semiconductor layer 113. The N-type semiconductor layer 111 has N-type semiconductor layer conductive steps 114, and the P-type semiconductor layer 113 is electrically isolated from the N-type semiconductor layer conductive steps 114 by an isolation trench 115.

[0032] Current spreading layer 12: disposed on the surface 114 of the conductive step of the P-type semiconductor layer 113 and the N-type semiconductor layer, and the material is indium tin oxide.

[0033] Current blocking layer 13: disposed above current spreading layer 12, made of SiO2, with a thickness greater than 5000 Å.

[0034] Bragg reflector layer 14: disposed above the current blocking layer 13, composed of 3 to 5 groups of alternating TiO2 / SiO2 layers, and having P-type and N-type through holes, with the bottom of the through holes exposing the current blocking layer 13.

[0035] Reflective layer 15: disposed above the Bragg reflective layer 14 and filling the through-hole. The reflective layer 15 includes: The first sublayer of the reflective layer is an Ag metal layer with a thickness of 1200–2000 Å.

[0036] The second sub-layer of the reflective layer is located above the first sub-layer and comprises at least one pair of Ti and Ni metal layers in a stack, with a PdPt alloy layer inserted at the interface between each pair of Ti and Ni metal layers. The mass ratio of Pd to Pt in the PdPt alloy layer is 7:3 to 5:5, and the thickness of a single layer is 5 to 50 Å. Furthermore, the thickness of the PdPt alloy layer increases linearly from the Ti / Ni interface near the first sub-layer to the Ti / Ni interface away from the first sub-layer.

[0037] First insulating layer 16: disposed above reflective layer 15, is a composite layer of Al2O3 thin film and SiO2 thin film, and has P-type first insulating layer through hole 161 and N-type first insulating layer through hole 162.

[0038] Connecting metal layer 17: disposed above the first insulating layer 16 and filling the through hole, including a P-type connecting metal layer 171 and an N-type connecting metal layer 172, the material being a Cr / Al / Ti / Pt / Ti / Pt / Ti / Au / Pt / Ti stack.

[0039] The second insulating layer 18 is disposed above the connecting metal layer 17. It is a SiO2 layer with a thickness of 8000 to 10000 Å and has through holes that expose the connecting metal layer 17.

[0040] P-type pad layer 191 and N-type pad layer 192: disposed above the second insulating layer 18 and filled with vias, the material is a Ti / Al / Ti / Pt / Ni / Au stack.

[0041] In this embodiment, the chip inserts a PdPt alloy layer with linearly increasing thickness at the Ti / Ni interface in the reflective layer 15, which effectively suppresses the diffusion of Ni to Ti during high-temperature annealing and avoids the formation of voids in the Ni layer, thereby significantly improving heat dissipation capacity.

[0042] Example 2 The present invention provides a method for fabricating a flip-chip light-emitting diode (LED) in Embodiment 2, wherein the fabricated chip structure is as described in Embodiment 1. In this embodiment, the second sub-layer of the reflective layer consists of three pairs of Ti / Ni stacks, and there are five PdPt alloy layers with thicknesses of 10 Å, 20 Å, 30 Å, 40 Å, and 50 Å respectively from the Ag side to the Ag side, and the Pd:Pt mass ratio is 7:3. Specifically, the method includes the following steps S01 to S09: S01, a substrate 10 is provided, and an N-type semiconductor layer 111, an active light-emitting layer 112 and a P-type semiconductor layer 113 are sequentially deposited on the substrate 10, and an N-type semiconductor layer conductive step 114 is formed by etching. Please see Figure 2 As shown, a substrate 10 is first provided, and an N-type semiconductor layer 111, an active light-emitting layer 112, and a P-type semiconductor layer 113 are sequentially deposited on the substrate 10 using an MOCVD process. The substrate 10 can be a GaN substrate 10, an Al2O3 substrate 10, or a Si substrate 10. Next, photoresist is coated on the surface of the P-type semiconductor layer 113, and part of the photoresist is removed by exposure and development processes to expose part of the P-type semiconductor layer 113. Then, the exposed P-type semiconductor layer 113 and the underlying active light-emitting layer 112 are removed using an inductively coupled plasma etching process to form a conductive step 114 of the N-type semiconductor layer. Finally, the photoresist is removed.

[0043] S02, a current spreading layer 12 is formed on the surface of the P-type semiconductor layer 113 and the conductive step 114 of the N-type semiconductor layer; Please see Figure 3 As shown, indium tin oxide (ITO) is deposited on the surfaces of the P-type semiconductor layer 113 and the conductive steps 114 of the N-type semiconductor layer using a magnetron sputtering process. Next, photoresist is coated on the ITO surface, and some of the photoresist is removed by exposure and development to expose some of the ITO. Then, the exposed ITO is removed using an ITO etching solution to form a current spreading layer 12. Finally, the photoresist is removed.

[0044] S03, the conductive step 114 of the N-type semiconductor layer is etched to form an isolation trench 115; Please see Figure 4As shown, photoresist is applied to the current spreading layer 12 and the areas not covered by the current spreading layer 12. Part of the photoresist is removed by exposure and development, exposing part of the N-type semiconductor layer conductive steps 114. Then, the exposed N-type semiconductor layer conductive steps 114 are removed by ICP etching process to form an isolation trench 115. Finally, the photoresist is removed.

[0045] S04, a current blocking layer 13 is formed above the current spreading layer 12; alternating first refractive index material layers and second refractive index material layers are deposited above the current blocking layer 13 to form a Bragg reflection layer 14, and the Bragg reflection layer 14 is etched to form P-type vias and N-type vias that expose the current blocking layer 13. Please see Figure 5 As shown, a SiO2 thin film is deposited as a current blocking layer 13 using PECVD on the surface of the current spreading layer 12 and the areas not covered by the current spreading layer 12. The thickness of the current blocking layer 13 is greater than 5000 Å. Next, 3 to 5 sets of TiO2 and SiO2 stacks are sequentially deposited on the surface of the current blocking layer 13 using electron beam evaporation to form a Bragg reflector layer 14. Then, photoresist is coated on the surface of the Bragg reflector layer 14, and part of the photoresist is removed by exposure and development to expose the underlying Bragg reflector layer 14. The exposed Bragg reflector layer 14 is removed using ICP etching to form a P-type Bragg reflector via 141 (P-type via) and an N-type Bragg reflector via 142 (N-type via). Finally, the photoresist is removed.

[0046] S05, remove the current blocking layer 13 at the bottom of the P-type via and N-type via to expose the current spreading layer 12 or the conductive step 114 of the N-type semiconductor layer below. Please see Figure 6 As shown, photoresist is coated in the Bragg reflector layer 14 and the via of the Bragg reflector layer 14. Part of the photoresist in the via of the Bragg reflector layer 14 is removed by exposure and development, exposing the current blocking layer 13 at the bottom of the via. Then, the exposed current blocking layer 13 is etched away with BOE solution to expose the current spreading layer 12 or the conductive step 114 of the N-type semiconductor layer below. Finally, the photoresist is removed.

[0047] S06, a reflective layer 15 is formed on the Bragg reflective layer 14, the reflective layer 15 including a first sub-layer of reflective layer and a second sub-layer of reflective layer located above the first sub-layer of reflective layer; wherein, the first sub-layer of reflective layer is an Ag metal layer; the second sub-layer of reflective layer includes at least one pair of Ti metal layers and Ni metal layers, and a PdPt alloy layer is inserted at the interface between each Ti metal layer and Ni metal layer; and the thickness of the PdPt alloy layer increases linearly from the Ti / Ni interface near the first sub-layer of reflective layer to the Ti / Ni interface away from the first sub-layer of reflective layer; the reflective layer 15 is then subjected to rapid annealing. Please see Figure 7 and Figure 10 As shown, negative photoresist is coated into the Bragg reflective layer 14 and its vias. Part of the photoresist is removed by exposure and development. Then, the first and second sub-layers of the reflective layer are sequentially deposited using electron beam evaporation to form the reflective layer 15. After evaporation, the metal on top of the photoresist is removed using a blue film stripping process, and then the photoresist is removed. Next, the reflective layer 15 is rapidly annealed at 400–450°C in an N2 atmosphere for 160–200 seconds.

[0048] Specifically, the first sublayer of the reflective layer is metallic Ag with a thickness between 1200 and 2000 Å. The second sublayer of the reflective layer is located above the first sublayer and has a main structure consisting of a stack of 2 to 3 pairs of Ti and Ni metal layers, wherein the thickness of a single Ti metal layer is between 1000 and 2000 Å, and the thickness of a single Ni metal layer is between 1000 and 2000 Å. A PdPt alloy layer is inserted at the interface between each Ti and Ni metal layer, wherein the mass ratio of Pd to Pt in the PdPt alloy layer is 7:3 to 5:5, and the thickness of each PdPt alloy layer is between 5 and 50 Å. Furthermore, the thickness of the PdPt alloy layer increases linearly from the Ti / Ni interface near the first sublayer of the reflective layer to the Ti / Ni interface away from the first sublayer of the reflective layer.

[0049] The function of the second sublayer of the reflective layer is to protect the Ag metal of the first sublayer of the reflective layer and prevent its migration. During high-temperature rapid annealing, Ni metal easily diffuses into Ti metal, forming voids and affecting the heat dissipation capacity of the LED chip. This invention inserts a PdPt alloy at the interface between Ti and Ni metals, effectively blocking the diffusion of Ni metal. Furthermore, since Al2O3 and SiO2 films will be subsequently prepared on the reflective layer 15, and these preparation processes are all carried out at high temperatures, this invention further proposes that the thickness of the PdPt alloy layer increases linearly from the Ti / Ni interface near the first sublayer of the reflective layer to the Ti / Ni interface farther away from the first sublayer of the reflective layer, thereby more effectively enhancing the anti-diffusion capability of the second sublayer of the reflective layer.

[0050] In this embodiment, the first sublayer of the reflective layer is Ag with a thickness of 1200 Å. The second sublayer of the reflective layer (from bottom to top) is: Ti (1000 Å) / PdPt (10 Å, mass ratio 7:3) / Ni (1000 Å) / PdPt (20 Å) / Ti (1000 Å) / PdPt (30 Å) / Ni (1000 Å) / PdPt (40 Å) / Ti (1000 Å) / PdPt (50 Å) / Ni (1000 Å). After evaporation, the metal on the photoresist is removed using a blue film stripping process, and then the film is rapidly annealed at 420°C for 180 seconds in an N2 atmosphere.

[0051] S07, a first insulating material layer and a second insulating material layer are sequentially deposited on the reflective layer 15 to form a first insulating layer 16 with a composite structure, and P-type first insulating layer via 161 and N-type first insulating layer via 162 are etched to expose part of the reflective layer 15. Please see Figure 8 As shown, in the areas covered by the reflective layer 15 and the areas not covered by the reflective layer 15, an Al2O3 thin film is first prepared using the ALD process, and then a SiO2 thin film is prepared on the surface of the Al2O3 thin film using the PECVD process. The Al2O3 thin film and the SiO2 thin film together constitute the first insulating layer 16. Then, photoresist is coated on the surface of the first insulating layer 16, and part of the photoresist is removed by exposure and development to expose the underlying first insulating layer 16. The exposed first insulating layer 16 is removed using the ICP etching process to form P-type first insulating layer vias 161 and N-type first insulating layer vias 162. Finally, the photoresist is removed.

[0052] In the ALD process, the temperature is gradually increased from 150℃ to 200℃ at a rate of 5-10℃ / min, with a holding time of 10-20 minutes for every 20℃ increase. This slow, gradual temperature increase allows for overall stress relaxation of the reflective layer, effectively releasing the internal stress accumulated during the rapid annealing and metal deposition processes. Simultaneously, this phased temperature increase in the ALD process avoids PdPt alloy agglomeration caused by prolonged high temperatures, preventing the formation of local structural defects and thus avoiding a decrease in its anti-diffusion performance and the inability to effectively block Ni diffusion into Ti. This ensures the stable achievement of the core effects of this invention: suppressing Ni layer voids and improving chip heat dissipation.

[0053] S08, a connecting metal layer 17 is formed in the first insulating layer 16 and the P-type first insulating layer through hole 161 and N-type first insulating layer through hole 162, the connecting metal layer 17 including P-type connecting metal layer 171 and N-type connecting metal layer 172. Please see Figure 9 As shown, negative photoresist is coated on the surface of the first insulating layer 16 and the through-hole of the insulating layer. Part of the photoresist is removed by exposure and development. Then, a Cr / Al / Ti / Pt / Ti / Pt / Ti / Au / Pt / Ti metal stack is sequentially deposited using an electron beam evaporation process to form a connecting metal layer 17. The metal on top of the photoresist is removed using a blue film stripping process, and then the photoresist is removed. The connecting metal layer 17 includes a P-type connecting metal layer 171 and an N-type connecting metal layer 172.

[0054] S09, a second insulating material layer is deposited above the connecting metal layer 17 to form a second insulating layer 18; a P-type pad layer 191 and an N-type pad layer 192 are formed on the second insulating layer 18.

[0055] Please see Figure 1 As shown, a SiO2 thin film with a thickness between 8000 and 10000 Å is prepared as a second insulating layer 18 on the surface of the connecting metal layer 17 and the areas not covered by the connecting metal layer 17 using a PECVD process. Then, a negative photoresist is coated on the surface of the second insulating layer 18. Part of the photoresist is removed by exposure and development, exposing the underlying second insulating layer 18. The exposed second insulating layer 18 is then removed by BOE etching to form vias in the second insulating layer 18. Next, Ti metal, Al metal, Ti metal, Pt metal, Ni metal, and Au metal are sequentially deposited using an electron beam evaporation process. Then, the metals above the photoresist are removed using a blue film stripping process. Finally, the photoresist is removed, forming a P-type pad layer 191 and an N-type pad layer 192.

[0056] This completes the fabrication of the flip-chip LED. The LED chip fabricated in this invention has a size of 1400 × 1400 μm². After fabrication, a 1500 mA current was applied to the chip at an ambient temperature of 85°C, and its junction temperature was measured. The lower the junction temperature, the better the chip's heat dissipation capability.

[0057] Example 3 The preparation method of this embodiment is basically the same as that of Embodiment 2, the only difference being the structure of the second sublayer of the reflective layer in step S06. Specifically: The first sublayer of the reflective layer is still an Ag metal layer with a thickness of 1200 Å.

[0058] The second sublayer of the reflective layer consists of two pairs of Ti / Ni stacks (i.e., two Ti layers and two Ni layers alternating), with the specific structure (from bottom to top) as follows: Ti (2000 Å) / PdPt (5 Å, mass ratio 7:3) / Ni (2000 Å) / PdPt (20 Å) / Ti (2000 Å) / PdPt (45 Å) / Ni (2000 Å).

[0059] The PdPt alloy layer consists of three layers, with thicknesses of 5 Å, 20 Å, and 45 Å increasing linearly from the Ag side to the Ag side.

[0060] The remaining steps (S01 to S05, S07 to S09) are the same as in Example 2.

[0061] The junction temperature of the chip prepared in this embodiment was tested to be 119.45℃ (see Table 1).

[0062] Example 4 The difference between this embodiment and Embodiment 3 lies in the thickness of the PdPt alloy layer in the second sub-layer of the reflective layer. In this embodiment: First sublayer of the reflective layer: Ag, 1200 Å.

[0063] The structure of the second sublayer of the reflective layer (from bottom to top) is: Ti (2000 Å) / PdPt (10 Å, mass ratio 7:3) / Ni (2000 Å) / PdPt (30 Å) / Ti (2000 Å) / PdPt (50 Å) / Ni (2000 Å).

[0064] The thickness of the PdPt alloy layer increases linearly from the Ag side to the Ag side, being 10 Å, 30 Å, and 50 Å respectively.

[0065] The remaining steps are the same as in Example 2.

[0066] The junction temperature of the chip prepared in this embodiment was tested to be 117.26℃ (see Table 1).

[0067] Example 5 The only difference between this embodiment and Embodiment 4 is the mass ratio of the PdPt alloy layer. In this embodiment: First sublayer of the reflective layer: Ag, 1200 Å.

[0068] The structure of the second sublayer of the reflective layer (from bottom to top) is: Ti (2000 Å) / PdPt (10 Å, mass ratio 5:5, i.e. Pd:Pt=1:1) / Ni (2000 Å) / PdPt (30 Å) / Ti (2000 Å) / PdPt (50 Å) / Ni (2000 Å).

[0069] The thickness of the PdPt alloy layer also increases linearly from the side closer to Ag to the side farther away from Ag: 10 Å, 30 Å, 50 Å.

[0070] The remaining steps are the same as in Example 2.

[0071] The junction temperature of the chip prepared in this embodiment was tested to be 116.67℃ (see Table 1).

[0072] Comparative Example 1 The difference between this comparative example and Example 2 is that the second sublayer of the reflective layer does not contain any PdPt alloy layer, and it does not employ a linear thickness increase design. Specifically: First sublayer of the reflective layer: Ag, 1200 Å.

[0073] The second sublayer of the reflective layer consists of three pairs of Ti / Ni stacks (without PdPt insertion layers), and the structure (from bottom to top) is: Ti(1000Å) / Ni(1000Å) / Ti(1000Å) / Ni(1000Å) / Ti(1000Å) / Ni(1000Å).

[0074] The remaining steps are the same as in Example 2.

[0075] The junction temperature of the chip prepared in this comparative example was tested to be 135.63℃.

[0076] Comparative Example 2 The difference between this comparative example and Example 3 is that the second sublayer of the reflective layer does not contain any PdPt alloy layer. Specifically: First sublayer of the reflective layer: Ag, 1200 Å.

[0077] The second sublayer of the reflective layer consists of two pairs of Ti / Ni stacks, with the structure (from bottom to top) as follows: Ti(2000Å) / Ni(2000Å) / Ti(2000Å) / Ni(2000Å).

[0078] The remaining steps are the same as in Example 2.

[0079] The junction temperature of the chip prepared in this comparative example was tested to be 136.32℃.

[0080] The junction temperature test results of the chips prepared in Examples 2 to 5 and Comparative Examples 1 and 2 are summarized in Table 1.

[0081]

[0082] As shown in Table 1, inserting a PdPt alloy layer at the Ti / Ni interface of the second sub-layer of the reflective layer, and linearly increasing its thickness from the Ag side to the Ag side, can significantly reduce the chip junction temperature by approximately 16–19 °C. This indicates that the technical solution of the present invention effectively suppresses Ni diffusion into Ti, avoids the formation of voids in the Ni layer, and thus greatly improves the heat dissipation capability of the flip-chip LED. Among them, Example 5 (PdPt mass ratio of 5:5, thickness gradient of 10 / 30 / 50 Å) exhibits the lowest junction temperature of 116.67 °C, which is the preferred solution.

[0083] In summary, the flip-chip light-emitting diode and its fabrication method described in the above embodiments of the present invention have the following beneficial effects: By inserting a PdPt alloy layer at the Ti / Ni stack interface of the reflective layer, the excellent diffusion-blocking properties of PdPt alloy significantly suppress the diffusion of Ni atoms into the Ti layer during high-temperature annealing, thus preventing the formation of voids within the Ni layer. Experiments show that the flip-chip using the structure of this invention has a dense, void-free Ni layer, significantly improved heat dissipation, reduced chip thermal resistance, and enhanced reliability.

[0084] The Ag reflective layer is effectively protected by a Ti / Ni stack and a PdPt alloy barrier layer, preventing Ag migration or oxidation, and avoiding a decrease in reflectivity due to voids. Compared to traditional Bragg reflectors, the chip of this invention can still maintain the high reflectivity of the Ag reflective layer, thereby achieving higher luminous brightness.

[0085] The thickness of the PdPt alloy layer increases linearly from the Ti / Ni interface near the first sublayer of the Ag reflective layer to the Ti / Ni interface away from the first sublayer of the Ag reflective layer. This gradient design makes the barrier capability stronger on the side away from Ag, and can withstand the thermal shock of subsequent high-temperature processes (such as ALD deposition of Al2O3, PECVD deposition of SiO2, etc.), achieving a continuous and stable anti-diffusion effect throughout the thickness direction of the reflective layer.

[0086] In the description of this specification, references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0087] The embodiments described above are merely illustrative of several implementations of the present invention, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of the present invention. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these modifications and improvements all fall within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the appended claims.

Claims

1. An inverted light emitting diode chip, characterized by, include: Substrate; A semiconductor epitaxial layer, located on the substrate, comprises, in sequence, an N-type semiconductor layer, an active light-emitting layer, and a P-type semiconductor layer; A reflective layer is disposed above the P-type semiconductor layer, the reflective layer including a first sub-layer of the reflective layer and a second sub-layer of the reflective layer located above the first sub-layer of the reflective layer; The first sub-layer of the reflective layer is an Ag metal layer; the second sub-layer of the reflective layer includes a stack of at least one pair of Ti metal layers and Ni metal layers, and a PdPt alloy layer is inserted at the interface between each Ti metal layer and the Ni metal layer; and the thickness of the PdPt alloy layer increases linearly from the interface between the Ti metal layer and the Ni metal layer near the first sub-layer of the reflective layer to the interface between the Ti metal layer and the Ni metal layer away from the first sub-layer of the reflective layer.

2. The flip-chip light emitting diode chip of claim 1, wherein, The second sublayer of the reflective layer comprises a stack of 2 to 3 pairs of Ti metal layers and Ni metal layers.

3. The flip-chip LED according to claim 1, characterized in that, The thickness of the first sublayer of the reflective layer is 1200–2000 Å; In the second sub-layer of the reflective layer, the thickness of a single Ti metal layer is 1000–2000 Å, and the thickness of a single Ni metal layer is 1000–2000 Å.

4. The flip-chip LED according to claim 1, characterized in that, The mass ratio of Pd to Pt in the PdPt alloy layer is 7:3 to 5:

5. The thickness of the PdPt alloy layer is 5–50 Å.

5. The flip-chip LED according to claim 1, characterized in that, The thickness of the PdPt alloy layer increases linearly from the interface between the Ti and Ni metal layers near the first sub-layer of the reflective layer to the interface between the Ti and Ni metal layers away from the first sub-layer of the reflective layer, with the thickness gradually increasing.

6. The flip-chip LED according to claim 1, characterized in that, Also includes: A current spreading layer is disposed on the P-type semiconductor layer; A current blocking layer and a Bragg reflector layer are sequentially disposed between the current spreading layer and the reflector layer; A first insulating layer is disposed above the reflective layer; A connecting metal layer is disposed above the first insulating layer; A second insulating layer is disposed above the connecting metal layer; P-type pad layers and N-type pad layers are disposed above the second insulating layer.

7. A method for fabricating a flip-chip light-emitting diode as described in any one of claims 1-6, characterized in that, Includes the following steps: A substrate is provided, on which an N-type semiconductor layer, an active light-emitting layer, and a P-type semiconductor layer are sequentially deposited, and conductive steps of the N-type semiconductor layer are etched. A current spreading layer is formed on the surface of the conductive steps of the P-type semiconductor layer and the N-type semiconductor layer; The conductive steps of the N-type semiconductor layer are etched to form isolation trenches; A current blocking layer is formed above the current spreading layer; Alternating layers of first and second refractive index material are deposited over the current blocking layer to form a Bragg reflection layer, and the Bragg reflection layer is etched to form P-type and N-type vias that expose the current blocking layer. Remove the current blocking layer at the bottom of the P-type and N-type vias to expose the underlying current spreading layer or the conductive step of the N-type semiconductor layer. A reflective layer is formed on the Bragg reflective layer, the reflective layer comprising a first sub-layer and a second sub-layer above the first sub-layer; wherein the first sub-layer is an Ag metal layer; the second sub-layer comprises at least one pair of Ti metal layers and Ni metal layers, and a PdPt alloy layer is inserted at the interface between each Ti metal layer and Ni metal layer; and the thickness of the PdPt alloy layer increases linearly from the Ti / Ni interface near the first sub-layer to the Ti / Ni interface away from the first sub-layer; the reflective layer is then subjected to rapid annealing. A first insulating material layer and a second insulating material layer are sequentially deposited on top of the reflective layer to form a first insulating layer with a composite structure, and P-type first insulating layer vias and N-type first insulating layer vias that expose part of the reflective layer are etched. A connecting metal layer is formed in the first insulating layer and the P-type and N-type first insulating layer through holes, the connecting metal layer including a P-type connecting metal layer and an N-type connecting metal layer; A second insulating material layer is deposited over the connecting metal layer to form a second insulating layer; A P-type pad layer and an N-type pad layer are formed on the second insulating layer.

8. The method for fabricating a flip-chip light-emitting diode according to claim 7, characterized in that, The conditions for rapid annealing are: annealing at 400–450°C for 160–200 seconds in an N2 atmosphere.

9. The method for fabricating a flip-chip light-emitting diode according to claim 7, characterized in that, The current blocking layer is a SiO2 layer with a thickness greater than 5000 Å; the Bragg reflector layer is an alternating stack of 3 to 5 groups of TiO2 layers and SiO2 layers.

10. The method for fabricating a flip-chip light-emitting diode according to claim 7, characterized in that, The first insulating layer is formed by depositing an Al2O3 thin film using an ALD process and then depositing a SiO2 thin film using a PECVD process.

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