Mip display device and method of manufacturing the same

Abstract

This application relates to a Micro-In-Pack (MIP) display device and its fabrication method. The MIP display device includes a glass substrate, a first conductive layer, a MIP chip, a second conductive layer, and external pads. The glass substrate has a first side and a second side disposed opposite to each other, and a through-hole is provided in the glass substrate. The first conductive layer is disposed on the first side, the MIP chip is disposed on the first conductive layer, the second conductive layer is disposed on the second side, and the external pads are disposed on the second conductive layer. The first and second conductive layers are connected through conductors in the through-holes. By using a glass substrate as a permanent encapsulation support framework, the process eliminates the need for carrier peeling and secondary transfer mounting, simplifying the encapsulation process, reducing steps, improving production efficiency, and lowering manufacturing costs.

Description

Technical Field

[0001] This application relates to the field of display technology, and in particular to a MIP display device and its fabrication method. Background Technology

[0002] In recent years, Micro LED has become the mainstream development direction for next-generation displays due to its advantages such as high brightness, high contrast, long lifespan, low power consumption, and fast response speed. It has broad application prospects in high-end displays, automotive electronics, AR / VR, and other fields. MIP (Micro LED in Package) technology integrates Micro LED chips and driver chips into a single package, enabling modular and standardized supply. This effectively reduces the difficulty and cost of downstream display panel manufacturing and is a key path to promote the large-scale mass production of Micro LED technology.

[0003] Traditional MIP display devices primarily use organic substrates (such as FR-4 and ABF substrates) or ceramic carriers as the packaging substrate. The coefficient of thermal expansion of organic substrates (approximately 30-50 ppm / ℃) differs significantly from that of silicon chips (approximately 3 ppm / ℃), making them prone to warping and deformation during high-temperature processes and long-term operation. This can lead to chip misalignment and solder joint cracking, severely impacting packaging yield and device reliability. Furthermore, the high surface roughness of organic substrates makes it difficult to achieve high-precision wiring, hindering the development of MIP display devices towards higher density and smaller pitch. While ceramic carriers offer higher dimensional stability and reliability, they suffer from high cost, long processing cycles, and difficulty in large-area array processing, failing to meet the demands of low-cost, large-scale mass production.

[0004] Some traditional technologies attempt to use glass substrates as temporary carriers, peeling off the glass carrier after the mass transfer of chips, and then transferring them to an organic substrate for subsequent packaging. This method has a complex process flow, requiring additional steps such as carrier peeling and secondary mounting, which not only reduces production efficiency but also easily introduces interface defects and failure risks. Summary of the Invention

[0005] Therefore, it is necessary to provide a MIP display device and its fabrication method to solve the technical problems of low wiring density and complex process flow in traditional solutions.

[0006] A MIP display device includes a glass substrate, a first conductive layer, a MIP chip, a second conductive layer, and external pads; the glass substrate has a first side and a second side disposed opposite to each other, and the glass substrate is provided with a through conductive via; the first conductive layer is disposed on the first side, the MIP chip is disposed on the first conductive layer, the second conductive layer is disposed on the second side, the external pads are disposed on the second conductive layer, and the first conductive layer and the second conductive layer are connected through a conductor in the conductive via.

[0007] In one embodiment, the MIP display device further includes an encapsulation layer that covers the first conductive layer and the MIP chip.

[0008] In one embodiment, the material of the encapsulation layer includes at least one of epoxy resin and silicone.

[0009] In one embodiment, the thickness of the encapsulation layer is 0.2 mm to 0.5 mm.

[0010] In one embodiment, the coefficient of thermal expansion of the encapsulation layer is 8ppm / ℃ to 15ppm / ℃.

[0011] In one embodiment, the MIP display device further includes a light-shielding layer disposed on the first side and surrounding the MIP chip.

[0012] In one embodiment, the thickness of the light-shielding layer is 4μm to 5μm.

[0013] In one embodiment, the light-shielding OD value of the light-shielding layer is above 3.

[0014] In one embodiment, the first conductive layer includes a first titanium layer, a first copper layer, a first nickel layer, and a first gold layer stacked sequentially from the glass substrate in order of proximity to the substrate.

[0015] In one embodiment, the second conductive layer includes a second titanium layer, a second copper layer, a second nickel layer, and a second gold layer stacked sequentially from the glass substrate in order of proximity to the substrate.

[0016] A method for fabricating a MIP display device includes the following steps:

[0017] A glass substrate is provided, the glass substrate having a first side and a second side disposed opposite to each other, and the glass substrate having a through conductive via.

[0018] A first conductive layer is prepared on the first side;

[0019] A second conductive layer is prepared on the second side, and the first conductive layer and the second conductive layer are connected through a conductor in the conductive via.

[0020] Multiple MIP chips are connected on the first conductive layer;

[0021] Multiple external pads are fabricated on the second conductive layer, and the multiple external pads correspond to the multiple MIP chips to obtain an integrated MIP device packaging structure;

[0022] The integrated package structure of the MIP device is divided to obtain multiple MIP display devices. Each MIP display device includes the glass substrate, the first conductive layer, the MIP chip, the second conductive layer, and the external pad.

[0023] In one embodiment, prior to the step of dividing the integrated package structure of the MIP device, the method for fabricating the MIP display device further includes the following steps:

[0024] A light-shielding layer is prepared on the first side, the light-shielding layer being disposed on the first side and surrounding the first conductor layer;

[0025] Each of the prepared MIP display devices further includes the light-shielding layer.

[0026] In one embodiment, prior to the step of dividing the integrated package structure of the MIP device, the method for fabricating the MIP display device further includes the following steps:

[0027] An encapsulation layer is prepared on the first side, the encapsulation layer covering the first conductive layer and the MIP chip;

[0028] Each of the prepared MIP display devices further includes the encapsulation layer.

[0029] In one embodiment, the connection between the MIP chip and the first conductive layer is at least one of flip-chip bonding, eutectic bonding, and solder paste bonding.

[0030] Compared with traditional technologies, the above-mentioned MIP display devices and their fabrication methods have the following advantages:

[0031] The aforementioned MIP display device uses a glass substrate with conductive vias for connecting the first and second conductive layers, enabling conductive interconnection between the MIP chip electrodes and external pads. Compared to traditional side wiring, this increases wiring density, reduces device package size, and allows for smaller, thinner devices. The high thermal expansion coefficient matching between the glass substrate and the silicon chip prevents warping and deformation during high-temperature processes and long-term operation, avoiding chip misalignment and solder joint cracking, thus improving device reliability and display consistency. By using a glass substrate as a permanent packaging support framework, the need for carrier stripping and secondary transfer mounting is eliminated, simplifying the packaging process, reducing steps, increasing production efficiency, and lowering manufacturing costs.

[0032] The above-described fabrication method uses a single glass substrate to encapsulate multiple MIP display devices. After overall molding, the devices are cut into individual units, making it suitable for mass production and meeting the mass production requirements of MIP display devices. The integrated packaging structure offers high integration and stability, adapting to the trend of MIP chip miniaturization and high-density packaging, and expanding the application range of MIP display devices in high-end displays, automotive, AR / VR, and other scenarios. Attached Figure Description

[0033] Figure 1 This is a schematic diagram of the structure of a MIP display device according to an embodiment;

[0034] Figure 2 This is a schematic diagram of the glass substrate structure;

[0035] Figure 3 A schematic diagram showing the fabrication of a first conductive layer and a second conductive layer on a first side and a second side of a glass substrate, respectively.

[0036] Figure 4 A schematic diagram showing the fabrication of a light-shielding layer on the first side of a glass substrate;

[0037] Figure 5 A schematic diagram showing the placement of a MIP chip on the first conductive layer;

[0038] Figure 6 A schematic diagram showing the fabrication of an encapsulation layer on the first side of a glass substrate;

[0039] Figure 7 A schematic diagram showing the fabrication of external pads on the second conductive layer.

[0040] Explanation of reference numerals in the attached figures:

[0041] 100: MIP display device; 110: Glass substrate; 111: Conductive via; 120: First conductive layer; 121: First titanium layer; 122: First copper layer; 123: First nickel layer; 124: First gold layer; 130: MIP chip; 140: Second conductive layer; 141: Second titanium layer; 142: Second copper layer; 143: Second nickel layer; 144: Second gold layer; 150: External pad; 160: Encapsulation layer; 170: Light-shielding layer. Detailed Implementation

[0042] To make the above-mentioned objectives, features, and advantages of this application more apparent and understandable, the specific embodiments of this application are described in detail below with reference to the accompanying drawings. Many specific details are set forth in the following description to provide a thorough understanding of this application. However, this application can be implemented in many other ways different from those described herein, and those skilled in the art can make similar modifications without departing from the spirit of this application. Therefore, this application is not limited to the specific embodiments disclosed below.

[0043] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0044] In the description of this application, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc., indicating the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application.

[0045] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this application, "multiple" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0046] In this application, unless otherwise expressly specified and limited, the terms "installation," "connection," "joining," and "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components, unless otherwise expressly limited. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0047] Unless otherwise specified, all steps in this application may be performed sequentially or randomly. For example, the method includes steps (a) and (b), indicating that the method may include steps (a) and (b) performed sequentially, or it may include steps (b) and (a) performed sequentially. For example, the method may also include step (c), indicating that step (c) may be added to the method in any order. For example, the method may include steps (a), (b), and (c), or it may include steps (a), (c), and (b), or it may include steps (c), (a), and (b), etc.

[0048] like Figure 1 As shown, a MIP display device 100 according to one embodiment includes a glass substrate 110, a first conductive layer 120, a MIP chip 130, a second conductive layer 140, and an external bonding pad 150. The glass substrate 110 has a first side and a second side disposed opposite to each other, and the glass substrate 110 is provided with a through-hole conductive via 111. The first conductive layer 120 is disposed on the first side. The MIP chip 130 is disposed on the first conductive layer 120. The second conductive layer 140 is disposed on the second side. The external bonding pad 150 is disposed on the second conductive layer 140. The first conductive layer 120 and the second conductive layer 140 are connected through a conductor in the conductive via 111.

[0049] The aforementioned MIP display device 100 uses a glass substrate 110, which has conductive vias 111 for connecting the first conductive layer 120 and the second conductive layer 140. This enables conductive interconnection between the electrodes of the MIP chip 130 and external pads. Compared to traditional side wiring, this increases wiring density, reduces device package size, and makes the device smaller and thinner. The glass substrate 110 has a high coefficient of thermal expansion matching with the silicon chip, making it less prone to warping and deformation during high-temperature processes and long-term operation. This avoids chip misalignment and solder joint cracking, improving device reliability and display consistency. By using the glass substrate 110 as a permanent packaging support framework, there is no need for carrier peeling and secondary transfer mounting operations, simplifying the packaging process, reducing steps, improving production efficiency, and lowering manufacturing costs.

[0050] The glass substrate 110 serves as the permanent encapsulation support structure for the device and is preferably made of semiconductor-grade alkali-free borosilicate glass or high-strain-point glass. The thickness of the glass substrate 110 is controlled between 0.15 mm and 0.3 mm. The surface roughness Ra of the glass substrate 110 is below 1 nm. The coefficient of thermal expansion (CTE) of the glass substrate 110 is 3 ppm / ℃ to 5 ppm / ℃, which matches the silicon chip and can effectively reduce the risk of warpage during high-temperature processes and operation.

[0051] The glass substrate 110 has a plurality of through-holes 111 (TGV vias). The through-holes 111 are filled with conductors to connect the first conductive layer 120 and the second conductive layer 140, achieving vertical conductive interconnection between the chip electrodes and external pads, replacing traditional side wiring and increasing wiring density. The diameter of the through-holes 111 is, for example, 30μm to 50μm, with an aspect ratio of 5:1 or higher. In some examples, the through-holes 111 are filled with copper paste to form copper conductive pillars, with a single-hole resistance of, for example, 3mΩ to 5mΩ.

[0052] The first conductive layer 120 connects to the electrodes of the MIP chip 130, and the connection method can be, but is not limited to, flip-chip bonding, eutectic bonding, solder paste bonding, etc. The second conductive layer 140 connects to the external pad 150. The first conductive layer 120 and the second conductive layer 140 are connected through a conductor in the conductive via 111. In this way, the wiring density is increased, and the device package area is reduced by more than 30% compared with the traditional solution.

[0053] In some examples, the first conductive layer 120 includes a first titanium layer 121, a first copper layer 122, a first nickel layer 123, and a first gold layer 124, which are sequentially stacked from the glass substrate 110 in order of proximity. The first copper layer 122 serves as the conductive host layer. The first titanium layer 121 can improve the adhesion between the first copper layer 122 and the glass substrate 110. The first nickel layer 123 and the first gold layer 124 can effectively protect the metal circuitry, prevent oxidation, and improve the solderability and conductivity stability of the circuitry.

[0054] In some examples, the thickness of the first copper layer 122 is 2 μm to 3 μm. The thickness of the first nickel layer 123 is 3 ± 0.5 μm. The thickness of the first gold layer 124 is 50 nm to 80 nm.

[0055] In some examples, the linewidth of the first conductor layer 120 is less than 20 μm. The line spacing of the first conductor layer 120 is less than 20 μm.

[0056] In some examples, the second conductive layer 140 includes a second titanium layer 141, a second copper layer 142, a second nickel layer 143, and a second gold layer 144, which are sequentially stacked from the glass substrate 110 in order of proximity. The second copper layer 142 serves as the conductive host layer. The second titanium layer 141 can improve the adhesion between the second copper layer 142 and the glass substrate 110. The second nickel layer 143 and the second gold layer 144 can effectively protect the metal circuitry, prevent oxidation, and improve the solderability and conductivity stability of the circuitry.

[0057] In some examples, the thickness of the second copper layer 142 is 2 μm to 3 μm. The thickness of the second nickel layer 143 is 3 ± 0.5 μm. The thickness of the second gold layer 144 is 50 nm to 80 nm.

[0058] In some examples, the linewidth of the second conductor layer 140 is less than 20 μm. The line spacing of the second conductor layer 140 is less than 20 μm.

[0059] The MIP chip 130 is disposed on a preset pad area of ​​the first conductive layer 120. In some examples, the MIP chip 130 consists of a Micro LED chip, a driver chip, a control chip, or an integrated chipset, and different chip specifications can be selected according to the application requirements. The MIP chip 130 is fixed by flip-chip bonding, eutectic bonding, solder paste bonding, etc., with a mounting alignment accuracy within 2μm, ensuring pixel consistency of small-pitch displays and meeting the display requirements of different scenarios.

[0060] External pad 150 is used to achieve SMT mounting connection between MIP display device 100 and downstream driver board or display panel, complete the vertical signal lead-out of device, and ensure stable conduction between device and external circuit. In some examples, external pad 150 is a solder ball.

[0061] In some examples, the MIP display device 100 further includes an encapsulation layer 160 covering the first conductive layer 120 and the MIP chip 130. The encapsulation layer 160 provides protection for the first conductive layer 120 and the MIP chip 130. The material of the encapsulation layer 160 includes, for example, at least one of epoxy resin and silicone, and may also be filled with inorganic fillers, giving the encapsulation layer 160 a suitable thickness and coefficient of thermal expansion, for example, 8ppm / ℃ to 15ppm / ℃, enabling good thermal matching with the glass substrate 110, effectively protecting the chip from moisture, vibration, and physical damage, and improving the overall environmental adaptability of the device. In some examples, the thickness of the encapsulation layer 160 is 0.2mm to 0.5mm.

[0062] In some examples, the MIP display device 100 also includes a light-shielding layer 170 disposed on a first side and surrounding the MIP chip 130.

[0063] The light-shielding layer 170 has a suitable thickness and light-shielding capability, effectively absorbing stray light, suppressing reflections, and improving display contrast. Simultaneously, it blocks light crosstalk between adjacent MIP chips 130, preventing issues such as color mixing, color shift, and edge blurring, thus improving display consistency. In some examples, the light-shielding layer 170 is a black adhesive layer. The thickness of the light-shielding layer 170 is 4μm~5μm. The light-shielding OD value of the light-shielding layer 170 is above 3.

[0064] Furthermore, this application also provides a method for fabricating the MIP display device 100 of any of the above examples.

[0065] A method for fabricating a MIP display device 100 according to one embodiment includes the following steps:

[0066] Step S1: A glass substrate 110 is provided. The glass substrate 110 has a first side and a second side disposed opposite to each other. The glass substrate 110 is provided with a through conductive via 111.

[0067] Step S2: Prepare a first conductive layer 120 on the first side.

[0068] Step S3: A second conductive layer 140 is prepared on the second side, and the first conductive layer 120 and the second conductive layer 140 are connected through a conductor in a conductive via 111.

[0069] Step S4: Connect multiple MIP chips 130 on the first conductor layer 120.

[0070] Step S5: Multiple external pads 150 are prepared on the second conductive layer 140, so that the multiple external pads 150 correspond to multiple MIP chips 130, and an integrated package structure of MIP devices is obtained.

[0071] Step S6: Divide the integrated packaging structure of the MIP device to obtain multiple MIP display devices 100. Each MIP display device 100 includes a glass substrate 110, a first conductive layer 120, a MIP chip 130, a second conductive layer 140, and an external pad 150.

[0072] The above-described fabrication method utilizes a glass substrate 110, which has conductive vias 111 for connecting the first conductive layer 120 and the second conductive layer 140. This enables conductive interconnection between the electrodes of the MIP chip 130 and external pads. Compared to traditional side wiring, this method increases wiring density, reduces device package size, and makes the device smaller and thinner. The glass substrate 110 has a high coefficient of thermal expansion matching with the silicon chip, making it less prone to warping and deformation during high-temperature processes and long-term operation. This prevents chip misalignment and solder joint cracking, improving device reliability and display consistency. By using the glass substrate 110 as a permanent packaging support framework, there is no need for carrier peeling or secondary transfer mounting operations, simplifying the packaging process, reducing steps, improving production efficiency, and lowering manufacturing costs.

[0073] The above-described fabrication method uses a single glass substrate 110 to encapsulate multiple MIP display devices 100. After overall molding, the devices are cut into individual units, making it suitable for mass production and meeting the mass production requirements of MIP display devices 100. The integrated packaging structure has high integration and strong stability, and can adapt to the trend of miniaturization and high-density packaging of MIP chips 130, expanding the application range of MIP display devices 100 in high-end displays, automotive, AR / VR and other scenarios.

[0074] In some examples, the step (step S4) of connecting multiple MIP chips 130 on the first conductor layer 120 includes:

[0075] Step S41: Apply flux to the first conductor layer 120.

[0076] Step S42: Align and mount the MIP chip 130 unit onto the flux.

[0077] Step S43: The mounted substrate is soldered using vacuum reflow soldering.

[0078] In step S41, the flux thickness is 20±5μm. The mounting alignment accuracy is ±2μm, and the mounting pressure is 6gf~8gf.

[0079] In step S43, the preheating temperature is 80℃~150℃, the time is 60s~90s, the constant temperature zone temperature is 150℃~180℃, the time is 60s~120s, the reflux zone temperature is greater than 220℃, the time is 30s~60s, the vacuum degree is 0.1±0.02MPa, and the pressure holding time is 30±5s.

[0080] In some examples, the external pads 150 are solder balls. The step of fabricating multiple external pads 150 on the second conductive layer 140 (step S5) includes:

[0081] The second side undergoes plasma activation treatment to enhance the surface activity of the solder pads. Special solder paste for ball placement is used for printing, with a printing thickness of 50±10μm. Ball placement is performed using a vacuum nozzle at a vacuum level of -80±5MPa, a placement pressure of 5±2gf, a ball height of 15±2μm, and an alignment accuracy of ±5μm. After ball placement, vacuum reflow soldering is used for soldering.

[0082] In some examples, prior to the step of segmenting the integrated package structure of the MIP device (step S6), the fabrication method of the MIP display device 100 further includes the following steps:

[0083] Step S7: Prepare a light-shielding layer 170 on the first side. The light-shielding layer 170 is disposed on the first side and surrounds the first conductor layer 120.

[0084] In the above example, each MIP display device 100 also includes a light-shielding layer 170.

[0085] In some examples, prior to the step of segmenting the integrated package structure of the MIP device (step S6), the fabrication method of the MIP display device 100 further includes the following steps:

[0086] Step S8: A packaging layer 160 is prepared on the first side, the packaging layer 160 covering the first conductive layer 120 and the MIP chip 130.

[0087] In the above example, each MIP display device 100 also includes an encapsulation layer 160.

[0088] In some examples, the step of fabricating the encapsulation layer 160 on the first side includes:

[0089] A protective film is applied again to the back of the flip-chip soldered substrate, and it is placed in a molding fixture. Liquid encapsulant is injected using a vacuum encapsulation method to completely cover the front circuitry and the MIP chip 130. The vacuum level is 1±0.2MPa, the mold closing pressure is 8±2MPa, the encapsulation pressure is 0.5±0.2MPa, the filling time is 5±0.5min, the preheating temperature is 100±5℃, the filling temperature is 120±5℃, the curing temperature is 150±5℃, and the curing time is 60±5min. After curing, the mold is opened, and the back protective film is peeled off.

[0090] The following specific embodiments further illustrate this application. These specific embodiments are provided to better understand this application, but are not limited to them and do not constitute a limitation on the content or scope of protection of this application.

[0091] Example 1

[0092] This embodiment provides a method for fabricating a MIP display device 100, including the following steps:

[0093] Step 1, as follows Figure 2 As shown, a glass substrate 110 is provided, made of borosilicate glass, with dimensions of 510×510×0.4mm. An automatic flatbed cleaning machine is used to clean the glass substrate 110 to remove surface contaminants. The cleaning pressure is 3±0.5kg / cm². 2 The cleaning temperature is 35±2℃, and the cleaning speed is 1.5±0.5m / min. High-pressure spraying is then used to thoroughly clean the substrate surface, providing a clean substrate for subsequent processes.

[0094] Step 2: The glass substrate 110 is laser-drilled using a high-precision laser drilling machine. The laser wavelength is 355nm, the laser energy is 50±5μJ, and the power is 100±10W. The glass is bombarded by the aforementioned high-energy ultraviolet laser beam, causing the material to vaporize and melt instantaneously. The molten slag is then removed by high-pressure gas, forming conductive vias 111 with a predetermined aperture and distribution. The laser-drilled glass substrate 110 is then subjected to double-sided thinning and via enlargement using an automated HF acid etching line. The HF acid concentration is 8%, and the etching time is 30±5min. The glass substrate 110 is thinned to a thickness of 0.2mm±20μm, and the via size is controlled to 50±5μm.

[0095] Step 3: The glass substrate 110 is cleaned using an ultrasonic cleaning device. Ultrasonic vibration removes glass dust and residual acid from the holes, cleaning the inner walls of the through-holes and preventing impurities from affecting the conductivity of subsequent metallization. The ultrasonic current is 2.5±0.5A, the power is 40±5KHz, and the cleaning time is 20±5min.

[0096] Step 4: Using a vacuum printer, conductive copper paste is printed and filled into the conductive through-hole 111 to form a copper conductive pillar structure. The printing speed is 100±20mm / s, the squeegee pressure is 0.3±0.5MPa, the vacuum pressure is 1±0.2MPa, and the vacuum holding time is 60±5s.

[0097] Step 5: Place the glass substrate 110 in a nitrogen oven for curing. High-temperature baking in a nitrogen atmosphere decomposes and volatilizes the organic components in the copper paste, causing the metal particles to sinter densely, thus improving the mechanical strength and electrical stability of the copper conductive pillars. The curing temperature is 150±5℃, the curing time is 60±5min, and the oxygen content is less than 100ppm.

[0098] Step 6: Use a double-sided polishing machine to polish the glass substrate 110 on both sides to remove excess copper paste outside the holes, smooth the surface, trim the copper pillars, and eliminate burrs to ensure the yield of subsequent circuits. The rough polishing pressure is 15±5 kPa and the polishing time is 5±2 min; the fine polishing pressure is 10±5 kPa and the polishing time is 5±2 min; the final polishing pressure is 5±2 kPa and the polishing time is 3±1 min.

[0099] Step 7: Use an automatic flatbed cleaning machine to clean the glass substrate 110 to remove residual polishing dust and debris, preventing impurities from interfering with subsequent coating and circuit processing. The cleaning pressure is 2±0.5 kg / cm². 2 The temperature was 35±5℃ and the cleaning speed was 1.5±0.5m / min.

[0100] Step 8: Use a double-sided flying probe tester to perform TGV conductive copper pillar resistance testing on the glass substrate 110 to screen for open circuit and short circuit defects, ensuring that the conductivity of the through holes meets the standards. The flying probe test pressure is 20±5g, the test current is 20±5MA, and the test speed is 1500±200 points / min. A single hole resistance of 3~5mΩ is considered as qualified for conductivity.

[0101] Step 9, as follows Figure 3 As shown, the glass substrate 110, which passed the flying probe test, was cleaned using a coating and cleaning machine, followed by double-sided magnetron sputtering coating. A titanium layer and a copper layer were deposited sequentially, with a titanium layer thickness of 80±10 nm and a copper layer thickness of 3 μm±200 nm. The coating temperature was 80±5℃, and the vacuum degree was below 5×10⁻⁶. -3 Pa, with a pure argon gas flow rate of 30±10 sccm, argon ions bombard the metal target in the vacuum chamber, and the target atoms are deposited on the glass surface and hole walls to form a dense metal layer, providing a conductive substrate for subsequent circuit fabrication.

[0102] Step 10: Clean the double-sided coated glass substrate 110 using an automatic flatbed cleaning machine. Then, a negative dry film is laminated using a double-sided laminating machine at a lamination speed of 1±0.2 m / min, a lamination temperature of 100±5℃, and a lamination pressure of 5±0.5 kg / cm². 2 When heated, the dry film adheres tightly to the substrate, forming a photosensitive protective coating.

[0103] Step 11: Expose the circuit pattern on the laminated substrate using a double-sided proximity exposure machine at an exposure energy of 60±5 mJ / cm². 2 The exposure temperature is 20±2℃, the exposure wavelength is I line 365nm, and the ultraviolet light passes through the mask to cause a photochemical reaction in the exposed area of ​​the dry film, changing the molecular cross-linking properties.

[0104] Step 12: Develop the exposed substrate using a double-sided automatic developing machine to dissolve the dry film in the unexposed areas and restore the target pattern of the metal layer. The developing speed is 2±0.5 m / min, the developing temperature is 25±2℃, and the developing conductivity is 20±2 mS / cm. 2 The developing spray pressure is 2±0.5 kg / cm². 2 The water washing pressure is 1.5 ± 0.5 kg / cm². 2 The developing solution used is sodium carbonate solution.

[0105] Step 13: An AOI (Automated Optical Inspection) machine is used to inspect the developed substrate for pattern detection, accurately identifying defects in the developed pattern and controlling line width and alignment accuracy. The light source uses coaxial white light and ring-shaped side lighting. The inspection speed is 120±5 s / substrate (110mm total), with an alignment accuracy of ±5μm and a resolution of 5μm.

[0106] Step 14: The AOI-compliant substrate is etched using a double-sided vacuum etching machine to remove copper areas not protected by dry film, retaining the target circuit pattern. The etching speed is 2±0.5 m / min, and the top and bottom etching spray pressure is 1.5±0.5 kg / cm². 2 The vacuum pressure is 2±0.5 kg / cm². 2 The water washing spray pressure is 1.5 ± 0.5 kg / cm². 2 The etching solution used is a sodium chloride-based etching solution.

[0107] Step 15: The etched substrate is subjected to an automatic demolding machine to remove the remaining dry film, exposing the complete metal wiring, forming the first conductive layer 120 and the second conductive layer 140. The demolding speed is 2±0.5 m / min, and the top and bottom spray pressure is 2±0.5 kg / cm². 2 The water washing spray pressure is 1.5 ± 0.5 kg / cm². 2 The release solution uses a low-concentration sodium hydroxide organic base.

[0108] Step 16: After demolding, the substrate is inspected again using AOI equipment with an alignment accuracy of ±5μm and a resolution of 5μm. The line width, spacing, continuity and solder joint quality are verified to ensure that the circuit conductivity and dimensional accuracy meet the standards.

[0109] Step 17: The substrate that has passed the circuit inspection undergoes double-sided electroless nickel-gold plating, sequentially completing pretreatment micro-etching, palladium activation, electroless nickel plating, and electroless gold plating. Pretreatment uses a 5% sulfuric acid solution at 30±5℃ for 120±5s. Activation uses an acidic ionic palladium solution at 25±2℃ for 60±5s. Electroless nickel plating uses a nickel sulfate solution at 85±2℃ for 15±2min. Electroless gold plating uses a potassium gold cyanide solution at 85±2℃ for 10±2min, with a pH of 5.5. A nickel layer and a gold layer are sequentially deposited on the copper layer surface to form an antioxidant, highly solderable protective coating. The nickel layer thickness is 3±0.5μm, and the gold layer thickness is 60nm.

[0110] Step 18: Using an automatic wire mesh laminating machine, a PET protective film is applied to the back of the nickel-gold coated substrate to protect the gold layer and circuitry from scratches and corrosion. The laminating pressure is 3 ± 0.5 kg / cm². 2 The film application speed is 2±0.5m / min, and the film application temperature is 80±5℃.

[0111] Step 19: The substrate with the back film applied is cleaned using an automatic flatbed cleaning machine to remove protective film residue and process impurities. The cleaning speed is 1±0.2 m / min, and the spray pressure is 1.2±0.2 kg / cm². 2 The temperature is 35±5℃.

[0112] Step 20, as follows Figure 4 As shown, BM adhesive was uniformly coated onto the front side of the cleaned substrate using a slot coater. The adhesive film thickness was 4.5±0.5μm, the coating speed was 30mm / s, and the injection pressure was 0.5±0.1kg / cm². 2 .

[0113] Step 21: Pre-bake the substrate coated with BM adhesive using a pre-baking oven. The pre-baking temperature is 100±5℃, and the pre-baking time is 100±5s to allow the BM adhesive to initially cure and set.

[0114] Step 22: The BM resin is patterned using an automatic exposure machine. Ultraviolet light causes a photocrosslinking reaction in the exposed areas of the BM resin. The exposure illuminance is 15 ± 2 mJ / cm². 2 The exposure time was 8 seconds, and the exposure GAP value was 200±50μm.

[0115] Step 23: Develop the exposed BM resin using an automatic developing machine. The developing speed is 1.5 ± 0.5 m / min, and the developing pressure is 1.2 ± 0.2 kg / cm². 2 The developing temperature is 25±2℃, and the washing pressure is 1.5±0.5kg / cm. 2The developer used is a 5% sodium hydroxide solution. This removes the unexposed BM adhesive, exposing critical areas such as circuit pads, and simultaneously peels off the back protective film.

[0116] Step 24: The developed substrate is baked in a nitrogen oven to fully cross-link and cure the BM adhesive, forming the light-shielding layer 170. The baking temperature is 230±5℃, the baking time is 30±5min, and the oxygen content is below 50ppm. The adhesion of the light-shielding layer 170 is tested using a cross-cut adhesion test (5B), and the light-shielding OD value is greater than 3.

[0117] Step 25: The completed light-shielding layer 170 is inspected using AOI inspection equipment to check the adhesive layer thickness, pattern integrity, and alignment accuracy, and to remove defects such as missing adhesive or deformation.

[0118] Step 26, as follows Figure 5 As shown, the AOI-inspected substrate was coated with flux to a thickness of 20±5μm. The 130-cell MIP chip was then flip-mounted onto the front pad area with high precision alignment, achieving an alignment accuracy of ±2μm and a mounting pressure of 7±1gf.

[0119] The mounted substrate is then soldered using vacuum reflow soldering. The preheating temperature is 110±30℃ for 75±15s, the isothermal zone temperature is 160±10℃ for 90±30s, the reflow zone temperature is greater than 220℃ for 90±30s, the vacuum level is 0.1±0.02MPa, and the holding pressure time is 30±5s. The solder balls melt to form reliable interconnects, achieving electrical connection between the chip and the substrate. After soldering, flux residue is removed by cleaning.

[0120] Step 27, as follows Figure 6 As shown, a PET protective film is applied again to the back of the flip-chip soldered substrate, and it is placed in a molding fixture. Liquid encapsulant is injected using a vacuum encapsulation method to completely cover the front circuitry and MIP chip 130. The vacuum level is 1±0.2MPa, the mold closing pressure is 8±2MPa, the injection pressure is 0.5±0.2MPa, the filling time is 5±0.5min, the preheating temperature is 100±5℃, the filling temperature is 120±5℃, the curing temperature is 150±5℃, and the curing time is 60±5min. After curing, the mold is opened, the back protective film is peeled off, and the encapsulation layer 160 is formed.

[0121] Step 28, as follows Figure 7As shown, the back side of the encapsulated substrate undergoes plasma activation treatment to enhance the surface activity of the solder pads. Solder paste specifically designed for ball placement is used for printing, with a printing thickness of 50±10μm. Ball placement is performed using a vacuum nozzle at a vacuum level of -80±5MPa, a placement pressure of 5±2gf, a ball height of 15±2μm, and an alignment accuracy of ±5μm. After ball placement, vacuum reflow soldering is performed using parameters consistent with those for chip soldering. The solder balls melt to form stable solder pillars, completing the preparation of external solder pad 150.

[0122] Step 29: The product with implanted balls is cut using an ultraviolet picosecond laser cutting machine. The laser precisely cuts through the board along the cutting path between the array units, separating the individual MIP display devices 100. The laser wavelength is 355nm, the power is 15±5W, the cutting speed is 200±50mm / s, the alignment accuracy is ±5μm, and the cutting precision is ±10μm.

[0123] Step 30: Use a flying probe tester to perform continuity testing on the MIP display device 100, and use AOI inspection equipment to check the integrity and appearance quality of the solder balls on the back side. Remove defective products such as short circuits and appearance damage, and select qualified devices that meet the performance and appearance standards.

[0124] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0125] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A MIP display device, characterized by, The device includes a glass substrate, a first conductive layer, a MIP chip, a second conductive layer, and external pads. The glass substrate has a first side and a second side disposed opposite to each other, and the glass substrate is provided with a through conductive via. The first conductive layer is disposed on the first side, the MIP chip is disposed on the first conductive layer, the second conductive layer is disposed on the second side, and the external pads are disposed on the second conductive layer. The first conductive layer and the second conductive layer are connected through a conductor in the conductive via.

2. The MIP display device of claim 1, wherein, The MIP display device further includes a packaging layer that covers the first conductive layer and the MIP chip.

3. The MIP display device of claim 2, wherein, It meets at least one of the following characteristics (1) to (3): (1) The material of the encapsulation layer includes at least one of epoxy resin and organosilicon; (2) The thickness of the encapsulation layer is 0.2mm~0.5mm; (3) The thermal expansion coefficient of the encapsulation layer is 8ppm / ℃~15ppm / ℃.

4. The MIP display device according to any one of claims 1 to 3, wherein, The MIP display device further includes a light-shielding layer disposed on the first side and surrounding the MIP chip.

5. The MIP display device of claim 4, wherein, It meets at least one of the following characteristics (1) to (2): (1) The thickness of the light-shielding layer is 4μm~5μm; (2) The light-shielding OD value of the light-shielding layer is above 3.

6. The MIP display device according to any one of claims 1 to 3, 5, wherein It meets at least one of the following characteristics (1) to (2): (1) The first conductive layer includes a first titanium layer, a first copper layer, a first nickel layer and a first gold layer stacked sequentially from near to far from the glass substrate; (2) The second conductive layer includes a second titanium layer, a second copper layer, a second nickel layer and a second gold layer stacked sequentially from the glass substrate from near to far.

7. A method for producing a MIP display device, characterized by, Includes the following steps: A glass substrate is provided, the glass substrate having a first side and a second side disposed opposite to each other, and the glass substrate having a through conductive via; A first conductive layer is prepared on the first side; A second conductive layer is prepared on the second side, and the first conductive layer and the second conductive layer are connected through a conductor in the conductive via. Multiple MIP chips are connected on the first conductive layer; Multiple external pads are fabricated on the second conductive layer, and the multiple external pads correspond to the multiple MIP chips to obtain an integrated MIP device packaging structure; The integrated package structure of the MIP device is divided to obtain multiple MIP display devices. Each MIP display device includes the glass substrate, the first conductive layer, the MIP chip, the second conductive layer, and the external pad.

8. The method for producing a MIP display device according to claim 7, wherein Before the step of dividing the integrated package structure of the MIP device, the method for fabricating the MIP display device further includes the following steps: A light-shielding layer is prepared on the first side, the light-shielding layer being disposed on the first side and surrounding the first conductor layer; Each of the prepared MIP display devices further includes the light-shielding layer.

9. The method for producing a MIP display device according to claim 7, wherein Before the step of dividing the integrated package structure of the MIP device, the method for fabricating the MIP display device further includes the following steps: An encapsulation layer is prepared on the first side, the encapsulation layer covering the first conductive layer and the MIP chip; Each of the prepared MIP display devices further includes the encapsulation layer.

10. The production method of a MIP display device according to any one of claims 7 to 9, wherein The connection method between the MIP chip and the first conductive layer is at least one of flip-chip bonding, eutectic bonding, and solder paste bonding.

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