A chip, a semiconductor package structure and an electronic device

Abstract

This application discloses a chip, a semiconductor packaging structure, and an electronic device, relating to the field of semiconductor technology. The chip includes a carbon nanotube field-effect transistor (CNTPT). In the CNTPT, the carbon nanotubes form end contacts with a first electrode and a second electrode, enabling the carbon nanotubes to form covalent bond contacts with the first and second electrodes, thereby improving conductivity. An isolation dielectric structure exists between the gate and the first and second electrodes. This isolation dielectric structure includes a first isolation dielectric layer. This first isolation dielectric layer not only provides electrical isolation between the gate and the first and second electrodes but also allows for the control of the type and concentration of charge carriers in the carbon nanotubes. This reduces the contact resistance between the carbon nanotubes and the first and second electrodes, maximizing the formation of ohmic contacts between them, and broadening the range of materials that can be selected for the first and second electrodes, thus improving design flexibility.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a chip, a semiconductor packaging structure, and an electronic device. Background Technology

[0002] Carbon nanotubes (CNTs) possess advantages such as high carrier mobility, narrow band gap, excellent thermal conductivity, and stable chemical properties. Carbon nanotube field-effect transistors (CNTFETs) fabricated using CNTs as semiconductor channel materials have shown great performance potential in the field of integrated circuits (ICs).

[0003] Typically, in CNTFETs, there is contact resistance between the CNT and the electrode. This contact resistance reduces the carrier transport efficiency and performance of the CNTFET. However, in existing technologies, reducing contact resistance is mainly achieved by adjusting the work function of the electrode. However, different electrode materials have different work functions, resulting in varying contact resistances when the electrode contacts the CNT. This limits the electrode materials that can achieve low contact resistance, hindering the design flexibility of CNTFETs. Therefore, how to balance reducing contact resistance with expanding the range of electrode material choices is a pressing problem in this field. Summary of the Invention

[0004] This application provides a chip, a semiconductor packaging structure, and an electronic device to reduce contact resistance and increase the range of electrode materials that can be selected.

[0005] In a first aspect, this application provides a chip including a substrate and a plurality of CNTFETs located on the substrate. Each CNTFET includes a carbon nanotube, a first electrode, a second electrode, a gate, and two isolation dielectric structures. The carbon nanotube extends along a first direction parallel to the substrate layer. The first and second electrodes are located at opposite ends of the carbon nanotube along the first direction. The gate is located between the first and second electrodes and surrounds a portion of the sidewall of the carbon nanotube. A gate dielectric layer is also disposed between the gate and the carbon nanotube. Furthermore, one isolation dielectric structure is located between the gate and the first electrode, and the other is located between the gate and the second electrode. Each isolation dielectric structure includes a first isolation dielectric layer surrounding a portion of the sidewall of the carbon nanotube. Thus, the first isolation dielectric layer not only provides electrical isolation between the gate and the first and second electrodes but also allows for the control of the type and concentration of charge carriers in the carbon nanotube, thereby reducing the contact resistance between the carbon nanotube and the first and second electrodes and maximizing the formation of an ohmic contact between the carbon nanotube and the first and second electrodes.

[0006] Furthermore, these multiple CNTFETs can include one or a combination of P-type and N-type CNTFETs. In the P-type CNTFET, the material of the first isolation dielectric layer is a first dielectric material, and the work function of the first dielectric material is not less than 6 eV. Therefore, by using the high work function of the first isolation dielectric layer, the type of charge carriers in the carbon nanotubes can be controlled, and the charge carrier concentration can be increased, causing the energy band of the carbon nanotubes to bend, equivalent to the effect of P-type doping. This reduces the Schottky barrier width between the carbon nanotubes and the first and second electrodes, making it easier for charge carriers to tunnel, thereby reducing the contact resistance between the carbon nanotubes and the first and second electrodes, achieving ohmic contact, and making it suitable for P-type CNTFET applications.

[0007] Furthermore, in the N-type CNTFET, the material of the first isolation dielectric layer is a second dielectric material, and this second dielectric material has positively charged defects. These defects, carrying positive charges, electrostatically dope the carbon nanotubes, controlling the type of charge carriers and increasing the carrier concentration. This causes the energy bands of the carbon nanotubes to bend, effectively creating an N-type doping effect. This reduces the Schottky barrier width between the carbon nanotubes and the first and second electrodes, making it easier for charge carriers to tunnel. Consequently, it reduces the contact resistance between the carbon nanotubes and the first and second electrodes, achieving ohmic contact suitable for N-type CNTFET applications.

[0008] In one possible implementation, the carbon nanotube has a first end and a second end opposite to each other in a first direction. A first electrode is located at the first end of the carbon nanotube and covers the end face of the first end facing away from the second end. A second electrode is located at the second end of the carbon nanotube and covers the end face of the second end facing away from the first end. This allows the first electrode to form a covalent bond contact with the end face of the first end facing away from the second end, and the second electrode to form a covalent bond contact with the end face of the second end facing away from the first end, achieving end contact. This enables the carbon nanotube to form a covalent bond contact with the first and second electrodes, thereby connecting the carbon nanotube to the first and second electrodes for signal transmission. Furthermore, the covalent bond contact between the carbon nanotube and the first and second electrodes improves the conductivity between the carbon nanotube and the first and second electrodes, further reducing the wettability requirements between the first and second electrodes and the carbon nanotube, broadening the range of materials that can be selected for the first and second electrodes, and further improving the design flexibility of CNTFETs.

[0009] In one possible implementation, the end face of the first carbon nanotube facing away from the second end contacts the surface of the first electrode facing the gate, and the end face of the second carbon nanotube facing away from the first end contacts the surface of the second electrode facing the gate. This allows for a relatively simple implementation of covalent bonding between the carbon nanotube and the first and second electrodes, thereby reducing the design complexity and production cost of CNTFETs.

[0010] In one possible implementation, the end face of the carbon nanotube facing away from the second end is embedded in the first electrode, and the end face of the carbon nanotube facing away from the first end is embedded in the second electrode. With this configuration, the first and second electrodes can also surround a portion of the sidewall of the carbon nanotube, allowing them to contact the sidewall of the carbon nanotube. This enables the carbon nanotube to form a covalent bond contact with both the first and second electrodes, and further allows them to form van der Waals force contacts, thus combining the covalent bond contact and the van der Waals force contact to further improve the conductivity between the carbon nanotube and the first and second electrodes.

[0011] In one possible implementation, the first dielectric material is a metal oxide. Therefore, the first dielectric material can be implemented using a metal oxide. Since metal oxides with a work function of not less than 6 eV are relatively mature, the implementation of the first dielectric material is relatively simple, thereby reducing the design difficulty of P-type CNTFETs and lowering production costs.

[0012] In one possible implementation, the metal oxide includes one or a combination of oxides of tungsten, vanadium, molybdenum, cobalt, and ruthenium.

[0013] Exemplarily, the chemical formula of tungsten oxide can be WO y1 , the chemical formula of vanadium oxide can be VO y2 , the chemical formula of molybdenum oxide can be MoO y3 , the chemical formula of cobalt oxide can be CoO y4 , the chemical formula of ruthenium oxide can be RuO y5 .

[0014] In a possible implementation, the second dielectric material includes: one or a combination of aluminum oxide, silicon oxide, aluminum nitride, silicon nitride, aluminum oxynitride, and silicon oxynitride. Thereby, the first dielectric material can be relatively simple to implement, thereby reducing the design difficulty of the P-type CNTFET and reducing the production cost.

[0015] In a possible implementation, the chemical formula of aluminum oxide is AlO x1 , 0 < x1 < 3 / 2; or, the chemical formula of silicon oxide is SiO x2 , 0 < x2 < 2; or, the chemical formula of aluminum nitride is AlN x3 , 0 < x3 < 1; or, the chemical formula of silicon nitride is SiN x4 , x4 > 4 / 3. Thereby, the first isolation dielectric layer can have positively charged defects, which is equivalent to achieving N-type doping to reduce the contact resistance between the carbon nanotube and the first electrode and the second electrode and achieve ohmic contact. In a possible implementation, each isolation dielectric structure further includes a second isolation dielectric layer. In the same isolation dielectric structure, the second isolation dielectric layer is located between the first isolation dielectric layer and the gate and surrounds the sidewalls of part of the carbon nanotubes. Thereby, the gate can be further electrically isolated from the first electrode and the second electrode, improving the electrical isolation performance.

[0016] Exemplarily, in any CNTFET, in the same isolation dielectric structure, the relative dielectric constant of the second isolation dielectric layer is less than that of the first isolation dielectric layer, which can reduce the parasitic capacitance between the gate and the first electrode and the second electrode.

[0017] Exemplarily, in a P-type CNTFET, in the same isolation dielectric structure, the work function of the second isolation dielectric layer is less than that of the first isolation dielectric layer. Thereby, the carrier concentration of the part of the carbon nanotube covered by the isolation dielectric structure can be gradually changed to regulate the band bending degree, thereby reducing the problem of leakage due to band-to-band tunneling (BTBT) in the off state.

[0018] For example, in an N-type CNTFET, the material of the second isolation dielectric layer is a third dielectric material, and the third dielectric material has positively charged defects. In the same isolation dielectric structure, the concentration of positive charge of defects in the second isolation dielectric layer is less than the concentration of positive charge of defects in the first isolation dielectric layer. Therefore, the carrier concentration of the portion of the carbon nanotubes covered by the isolation dielectric structure can be gradually varied to control the degree of band bending, thereby reducing the leakage current problem of the BTBT in the off-state.

[0019] In one possible implementation, the relative permittivity of the second isolation dielectric layer is no greater than 4, further reducing the parasitic capacitance between the gate and the first and second electrodes.

[0020] In one possible implementation, the second insulating dielectric layer is in contact with the sidewall of the carbon nanotube, which can better electrically isolate the first electrode and the second electrode from the gate, respectively.

[0021] In one possible implementation, the second isolation dielectric layer is in contact with the substrate, which can better electrically isolate the first electrode and the second electrode from the gate, respectively.

[0022] In one possible implementation, each isolation dielectric structure includes multiple second isolation dielectric layers to further electrically isolate the gate from the first electrode and the second electrode, thereby improving electrical isolation performance.

[0023] For example, in a P-type CNTFET, the work function of the second isolation dielectric layer farther from the gate is larger in the same isolation dielectric structure. This allows the carrier concentration in the carbon nanotube portion covered by the isolation dielectric structure to gradually increase in the direction away from the gate, further improving the band bending degree and further reducing the BTBT leakage problem in the off state.

[0024] For example, in an N-type CNTFET, in the same isolation dielectric structure, the concentration of positive charge of defects in the second isolation dielectric layer farther away from the gate is greater. This allows the carrier concentration in the carbon nanotube portion covered by the isolation dielectric structure to gradually increase in the direction away from the gate, further improving the band bending degree and further reducing the BTBT leakage problem in the off state.

[0025] In one possible implementation, within the same isolation medium structure, the first isolation medium layer is also located between the second isolation medium layer and the sidewall of the carbon nanotube, which can further enable the regulation of the type and concentration of charge carriers in the carbon nanotube.

[0026] In one possible implementation, within the same isolation dielectric structure, the first isolation dielectric layer is also located between the second isolation dielectric layer and the substrate, further electrically isolating the gate from the first electrode and the second electrode, thereby improving the electrical isolation performance.

[0027] In one possible implementation, each isolation dielectric structure includes a plurality of second isolation dielectric layers, including an m-th second isolation dielectric layer and an (m+1)-th second isolation dielectric layer, wherein the (m+1)-th second isolation dielectric layer is located between the m-th second isolation dielectric layer and the gate, where m is a positive integer, thereby further electrically isolating the gate from the first electrode and the second electrode and improving the electrical isolation performance.

[0028] For example, in the same isolation dielectric structure, there is also an m-th second isolation dielectric layer between the (m+1)-th second isolation dielectric layer and the sidewall of the carbon nanotube, which further electrically isolates the gate from the first electrode and the second electrode, thereby improving the electrical isolation performance.

[0029] For example, in the same isolation dielectric structure, there is also an m-th second isolation dielectric layer between the (m+1)-th second isolation dielectric layer and the substrate, which further electrically isolates the gate from the first electrode and the second electrode, thereby improving the electrical isolation performance.

[0030] In one possible implementation, in any CNTFET, within the same isolation dielectric structure, the relative permittivity of the m-th second isolation dielectric layer is greater than that of the (m+1)-th second isolation dielectric layer, further reducing the parasitic capacitance between the gate and the first and second electrodes.

[0031] In one possible implementation, in a P-type CNTFET, within the same isolation dielectric structure, the work function of the m-th second isolation dielectric layer is greater than that of the (m+1)-th second isolation dielectric layer, which can further enable the regulation of the type and concentration of charge carriers in the carbon nanotubes.

[0032] In one possible implementation, in an N-type CNTFET, within the same isolation dielectric structure, the concentration of positive charge of defects in the m-th second isolation dielectric layer is greater than the concentration of positive charge of defects in the (m+1)-th second isolation dielectric layer, which can further enable the regulation of the type and concentration of charge carriers in the carbon nanotube.

[0033] In one possible implementation, each isolation dielectric structure further includes a third isolation dielectric layer surrounding a portion of the sidewall of the carbon nanotube. In the same isolation dielectric structure, the third isolation dielectric layer is located on the side of the first isolation dielectric layer facing away from the gate and between the first isolation dielectric layer and the sidewall of the carbon nanotube, further electrically isolating the gate from the first electrode and the second electrode, thereby improving the electrical isolation performance.

[0034] For example, in a P-type CNTFET, within the same isolation dielectric structure, the work function of the third isolation dielectric layer is less than that of the first isolation dielectric layer. Therefore, the distance between the first isolation dielectric layer and its sidewalls can be controlled by adjusting the thickness of the third isolation dielectric layer, thereby controlling the type and concentration of charge carriers in the first isolation dielectric layer pair.

[0035] For example, in an N-type CNTFET, within the same isolation dielectric structure, the concentration of positive charge from defects in the third isolation dielectric layer is less than the concentration of positive charge from defects in the first isolation dielectric layer. Therefore, the distance between the first isolation dielectric layer and its sidewalls can be controlled by adjusting the thickness of the third isolation dielectric layer, thereby controlling the type and concentration of charge carriers in the first isolation dielectric layer pair.

[0036] In one possible implementation, each isolation dielectric structure further includes a fourth isolation dielectric layer, which is located between the first isolation dielectric layer and the carbon nanotube within the same isolation dielectric structure. Furthermore, the relative permittivity of the fourth isolation dielectric layer is lower than that of the first isolation dielectric layer. This not only enables electrical isolation between the gate and the first and second electrodes but also reduces the parasitic capacitance between the gate and the first and second electrodes.

[0037] In one possible implementation, the relative permittivity of the fourth isolation dielectric layer is no greater than 4, further reducing the parasitic capacitance between the gate and the first and second electrodes.

[0038] In one possible implementation, each isolation dielectric structure further includes a fifth isolation dielectric layer, in which the fifth isolation dielectric layer surrounds the first isolation dielectric layer, and the relative permittivity of the fifth isolation dielectric layer is less than that of the first isolation dielectric layer, thereby further reducing the parasitic capacitance between the gate and the first electrode and the second electrode.

[0039] In one possible implementation, the relative permittivity of the fifth isolation dielectric layer is no greater than 4, further reducing the parasitic capacitance between the gate and the first and second electrodes.

[0040] In one possible implementation, each isolation dielectric structure includes multiple fifth isolation dielectric layers. Within the same isolation dielectric structure, the relative permittivity of the fifth isolation dielectric layer farther away from the carbon nanotube is smaller or larger, further reducing the parasitic capacitance between the gate and the first and second electrodes.

[0041] In one possible implementation, the first insulating dielectric layer contacts the sidewall of the carbon nanotube, which can better electrically isolate the first and second electrodes from the gate. Furthermore, the first insulating dielectric layer can directly act on the carbon nanotube, improving the precision of controlling the type and concentration of charge carriers in the carbon nanotube.

[0042] In one possible implementation, the first insulating dielectric layer is in contact with the substrate, which can better electrically isolate the first electrode and the second electrode from the gate.

[0043] In one possible implementation, a gate dielectric layer is also located between each isolation dielectric structure and the gate, further electrically isolating the first electrode and the second electrode from the gate.

[0044] In one possible implementation, the gate dielectric layer is also located on the side of each isolation dielectric structure away from the gate, and also between each isolation dielectric structure and the carbon nanotube, further electrically isolating the first electrode and the second electrode from the gate.

[0045] Secondly, this application provides a semiconductor packaging structure, which includes a packaging substrate and a chip, with the chip packaged on the packaging substrate. The chip is as described in the first aspect or its embodiments. Because the chip in the embodiments of this application has good performance, the semiconductor packaging structure including the chip also has good performance.

[0046] Thirdly, this application provides an electronic device comprising: a circuit board and a semiconductor package structure, wherein the semiconductor package structure is disposed on the circuit board. The semiconductor package structure is as described in the second aspect or in the embodiments of the second aspect. Because the semiconductor package structure in the embodiments of this application has better performance, the electronic device incorporating this semiconductor package structure also has better performance.

[0047] Furthermore, the technical effects of the corresponding solutions in the second and third aspects can be referenced to the technical effects that can be obtained by the corresponding solutions in the first aspect, and the repetitions will not be detailed. Attached Figure Description

[0048] Figure 1 This is a schematic diagram of the structure of an electronic device in an embodiment of this application;

[0049] Figure 2 This is a schematic diagram of the structure of a chip in an embodiment of this application;

[0050] Figure 3 This is another schematic diagram of the chip structure in the embodiments of this application;

[0051] Figure 4A and Figure 4B These are schematic diagrams of another structure of the chip in the embodiments of this application;

[0052] Figure 5 This is another schematic diagram of the chip structure in the embodiments of this application;

[0053] Figure 6 This is another schematic diagram of the chip structure in the embodiments of this application;

[0054] Figure 7 This is another schematic diagram of the chip structure in the embodiments of this application;

[0055] Figure 8 This is another schematic diagram of the chip structure in the embodiments of this application;

[0056] Figure 9 This is another schematic diagram of the chip structure in the embodiments of this application;

[0057] Figure 10 This is another schematic diagram of the chip structure in the embodiments of this application;

[0058] Figure 11 This is another schematic diagram of the chip structure in the embodiments of this application;

[0059] Figure 12 This is another schematic diagram of the chip structure in the embodiments of this application.

[0060] Figure label:

[0061] 100 - Housing; 200 - Circuit board; 210 - Semiconductor package structure; 300 - Chip; 310 - Substrate; 311 - Substrate body layer; 312 - Support layer; 320 - CNT; 330 - First electrode; 340 - Second electrode; 351 - Gate; 352 - Gate dielectric layer; 360a / 360b - Isolation dielectric structure; 361a / 361b - First isolation dielectric layer; 362a1 / 362a2 / 362a3 / 362b 1 / 362b2 / 362b3 - Second isolation dielectric layer; 363a / 363b - Third isolation dielectric layer; 364a / 364b - Fourth isolation dielectric layer; 365a1 / 365a2 / 365a3 / 365b1 / 365b2 / 365b3 - Fifth isolation dielectric layer; 370 - Interlayer dielectric layer; S1a / S1b - End face; S2a / S2b - Surface; DA1 - First end; DA2 - Second end; F1 - First direction. Detailed Implementation

[0062] To make the objectives, technical solutions, and advantages of this application clearer, the application will be further described in detail below with reference to the accompanying drawings. The specific operational methods in the method embodiments can also be applied to the device embodiments or system embodiments. It should be noted that in the description of this application, "multiple" can be understood as "at least two". Furthermore, it should be understood that in the description of this application, terms such as "first" and "second" are used only for distinguishing purposes and should not be construed as indicating or implying relative importance, nor as indicating or implying order.

[0063] It should be noted that the same reference numerals in the accompanying drawings of this application denote the same or similar structures, and therefore repeated descriptions of them will be omitted. Terms expressing position and direction described in this application are illustrative based on the accompanying drawings, but may be modified as needed, and all modifications are included within the scope of protection of this application. The accompanying drawings of this application are for illustrating relative positional relationships only and do not represent actual scale.

[0064] The chip, fabrication method, semiconductor packaging structure, and electronic device provided in the embodiments of this application are described below with reference to the accompanying drawings.

[0065] Figure 1 This is a schematic diagram of the structure of an electronic device according to an embodiment of this application. (Refer to...) Figure 1 The electronic device includes a circuit board 200 and a semiconductor package structure 210, with the semiconductor package structure 210 disposed on the circuit board 200. Exemplarily, the semiconductor package structure 210 and the circuit board 200 can be connected by bonding or other methods to achieve an electrical connection between them, thereby enabling signal transmission between them. Furthermore, the electronic device also includes a housing 100 with a receiving space, in which the circuit board 200 is disposed and fixed.

[0066] For example, electronic devices include, but are not limited to, terminal devices and communication devices. Terminal devices include, but are not limited to, mobile phones, computers, televisions, set-top boxes, watches, personal computers (PCs), wearable devices, workstations, etc. Communication devices include, but are not limited to, wireless network devices, fixed network devices, servers, smart broadband devices, etc. It is understood that the specific implementation of the electronic device can be determined according to the actual application scenario and is not limited herein.

[0067] For example, circuit board 200 includes, but is not limited to, a printed circuit board (PCB).

[0068] For example, the semiconductor package structure 210 includes, but is not limited to, logic circuits, memory circuits, and system-on-chips (SOCs) that integrate logic circuits and memory circuits, etc., which will not be listed here.

[0069] As an example, logic circuits are processors and input / output (IO) devices. Processors include, but are not limited to, central processing units (CPUs), graphics processing units (GPUs), artificial intelligence (AI) processors, digital signal processors, and neural network processors.

[0070] As an example, the storage circuit is a memory, which includes, but is not limited to, Random Access Memory (RAM) and Read-Only Memory (ROM). Among them, Random Access Memory includes, but is not limited to, Dynamic Random Access Memory (DRAM), Static Random Access Memory (SRAM), Magnetoresistive Random Access Memory (MRAM), and Phase Change Memory (PCM).

[0071] For example, the semiconductor package structure 210 can be a packaged device. For instance, the semiconductor package structure 210 includes a package substrate and a chip, with the chip packaged on the package substrate. The semiconductor package structure 210 may have one or more chips. When the semiconductor package structure 210 has multiple chips, the multiple chips may be packaged using 3D, 2.5D, or other packaging methods.

[0072] When the semiconductor package structure 210 includes logic circuits, the chip can be a logic circuit die or a device with the logic circuit die packaged. Therefore, the standard cells in the embodiments of this application can be standard cells applied in logic circuits.

[0073] When the semiconductor package structure 210 includes a memory circuit, the chip can also be a bare die of the processing circuit or a device after packaging the bare die of the processing circuit. Therefore, the standard unit in the embodiments of this application can be a standard unit applied in a logic circuit. For example, the memory circuit includes a controller and a memory array, the controller is electrically connected to the memory array, and the controller accesses the memory array to implement data access functions. The memory array can be one or more, and the standard unit in the embodiments of this application can be a standard unit applied in the memory array.

[0074] Furthermore, the semiconductor package structure 210 may also include electronic devices that are connected to the chip. In specific implementations, the inclusion of electronic devices in the semiconductor package structure 210 is optional and can be determined based on the needs of the application scenario. For example, when the semiconductor package structure 210 includes logic circuits, the electronic devices include, but are not limited to, passive devices connected to the logic circuits to achieve impedance matching. Passive devices include, but are not limited to, one or a combination of resistors, inductors, and capacitors. When the semiconductor package structure 210 includes memory circuits, the electronic devices include, but are not limited to, the controller within the memory circuits.

[0075] Figure 2 This is a schematic diagram of a chip structure in an embodiment of this application, with reference to... Figure 2 The chip 300 in this embodiment may include a substrate 310 and a plurality of CNTFETs located on the substrate 310. Exemplarily, the substrate 310 may include a substrate body layer 311 and a support layer 312. As an example, the substrate body layer 311 is made of a semiconductor material (e.g., Si, SiGe, SiC, etc.), an insulating material (e.g., glass), or a conductive material. The support layer 312 is made of an insulating material; for example, the support layer 312 is one or more layers of SiO2, Si3N4, SiON, SiOC, SiOCN, and SiCN or other suitable insulating materials. Furthermore, one or more support layers 312 may be fabricated using thin film deposition processes such as thermal oxidation or atomic layer deposition (ALD). In other embodiments, when the substrate body layer 311 is made of an insulating material, the support layer 312 may not be provided, and the CNTFETs may be directly fabricated on the substrate body layer 311.

[0076] Exemplarily, an interlayer dielectric (ILD) 370 is also disposed on the substrate 310, the interlayer dielectric 370 being located between adjacent CNTFETs to electrically isolate the adjacent CNTFETs. Exemplarily, the material of the interlayer dielectric 370 is an insulating dielectric material.

[0077] In one embodiment of this application, reference is made to... Figure 2The CNTFET may include: a CNT320, a first electrode 330, a second electrode 340, a gate 351, and two isolation dielectric structures 360a and 360b. The CNT320 serves as the channel of the CNTFET, extending along a first direction F1, i.e., the axial direction of the CNT320 is the first direction F1. The first direction F1 is parallel to the layer containing the substrate 310. It is understood that the description of "the first direction F1 being parallel to the layer containing the substrate 310" above can be a parallelism within an acceptable tolerance range. Furthermore, to clearly illustrate the structure of the CNTFET in the embodiments of this application, Figure 2 The following example illustrates the formation of CNT320 in a CNTFET as a single-layer carbon nanotube layer. In this single-layer carbon nanotube layer, there can be one or more CNT320s. When there are multiple CNT320s, they can be arranged in an array, a grid, or other feasible arrangements; no specific limitation is made here. Furthermore, CNT320s can include semiconductor-type CNTs.

[0078] In one embodiment of this application, reference is made to... Figure 2 The first electrode 330 and the second electrode 340 are located at opposite ends of the CNT320 in the first direction F1. The gate 351 is located between the first electrode 330 and the second electrode 340. The gate 351 surrounds a portion of the sidewall of the CNT320, and a gate dielectric layer 352 is also disposed between the gate 351 and the CNT320. Thus, the CNTFET can be formed as a Gate All Around (GAA) CNTFET, which avoids contact between the CNT320 and the substrate 310 material, effectively suppresses current fluctuations, and greatly enhances gate control capability. For example, if the CNT320 includes a first portion DB1, then the gate 351 surrounds the sidewall of the CNT320 in the first portion DB1 through the gate dielectric layer 352.

[0079] For example, the gate 351 can be a single conductive layer or a multi-layer conductive layer, and the material of the single conductive layer or the multi-layer conductive layer includes, but is not limited to, one or a combination of Pd, W, Ti, TiN, and TaN.

[0080] For example, the gate dielectric layer 352 includes, but is not limited to, one or a combination of HfO2, Al2O3, Y2O3, or other suitable dielectric materials.

[0081] In one embodiment of this application, reference is made to... Figure 2The CNT320 has a first end DA1 and a second end DA2 opposite each other in the first direction F1. The first electrode 330 is located at the first end DA1 of the CNT320, and the second electrode 340 is located at the second end DA2 of the CNT320. That is, the first electrode 330 covers the end face S1a of the first end DA1 of the CNT320 facing away from the second end DA2, and the second electrode 340 covers the end face S1b of the second end DA2 of the CNT320 facing away from the first end DA1. This is equivalent to the end face S1a of the CNT320 contacting the first electrode 330 and the end face S1b contacting the second electrode 340, which can achieve end contact. This allows the end face S1a of the CNT320 to form a covalent bond contact with the first electrode 330, and the end face S1b to form a covalent bond contact with the second electrode 340. Thus, the CNT320 can be connected to the first electrode 330 and the second electrode 340 based on the covalent bond contact, thereby realizing signal transmission. However, in existing CNTFETs, the first electrode 330 and the second electrode 340 typically cover the upper sidewall of the CNT 320, forming a side contact. This allows the first electrode 330 and the second electrode 340 to connect with the CNT 320 via van der Waals force contact to achieve signal transmission. Here, van der Waals force contact means that the first electrode 330 and the second electrode 340 interact with the CNT 320 through van der Waals forces, rather than being bonded by chemical bonds. Because van der Waals force contact requires high wettability between the first electrode 330 and the second electrode 340 and the CNT 320, it limits the flexibility in material selection for the first electrode 330 and the second electrode 340, thus limiting the design flexibility of the CNTFET. In this embodiment, CNT320 forms a covalent bond contact with the first electrode 330 and the second electrode 340, which can improve the conductivity between CNT320 and the first electrode 330 and the second electrode 340. The requirement for wettability between the first electrode 330 and the second electrode 340 and CNT320 can be reduced, making the material selection range of the first electrode 330 and the second electrode 340 wider and improving the design flexibility of CNTFET.

[0082] Understandably, in existing CNTFET technologies, the first and second electrodes typically cover the sidewalls above the CNT, forming a side contact. During fabrication, dry etching exposes the CNT before forming the first and second electrodes, which can damage the CNT and affect the CNTFET's performance. Alternatively, wet etching exposes the CNT before forming the first and second electrodes, which can cause side cut-outs, increasing the parasitic capacitance between the gate and the first and second electrodes. In this embodiment, by having the first electrode 330 cover the end face S1a of the first terminal DA1 of the CNT 320 facing away from the second terminal DA2, and the second electrode 340 cover the end face S1b of the second terminal DA2 of the CNT 320 facing away from the first terminal DA1, the problems of CNT damage caused by dry etching and side cut-outs caused by wet etching in existing CNTFET fabrication technologies can be solved. Furthermore, it reduces the fabrication difficulty of the CNT and the first and second electrodes, while controlling the contact length and side cut-outs between the CNT and the first and second electrodes, providing space for device size reduction. Furthermore, combining end-contact control of contact length with GAA process can better accommodate advanced processes and improve size reduction space, making it suitable for the realization of high-performance CNTFETs.

[0083] For example, refer to Figure 2 The end face S1a of the first terminal DA1 of CNT320 facing away from the second terminal DA2 is in contact with the surface S2a of the first electrode 330 facing the gate 351. Thus, the end face S1a and the surface S2a can form a covalent bond contact, making it relatively simple to implement the covalent bond contact between CNT320 and the first electrode 330, thereby reducing the design difficulty of CNTFET and reducing production costs.

[0084] For example, refer to Figure 2 The end face S1b of the second terminal DA2 of CNT320 facing away from the first terminal DA1 contacts the surface S2b of the second electrode 340 facing the gate 351. This allows the end face S1b and the surface S2b to form a covalent bond contact, making it relatively simple to implement the covalent bond contact between CNT320 and the second electrode 340, thereby reducing the design difficulty of CNTFET and reducing production costs.

[0085] For example, the first electrode 330 and the second electrode 340 can be a single-layer conductive layer or a multi-layer conductive layer. The material of the single-layer conductive layer or the multi-layer conductive layer includes, but is not limited to, one or a combination of Au, Pd, Sc, Ti, TiN, W, Pt, Co, Mo, Ni, Al, and AlSc, or an alloy thereof.

[0086] In one embodiment of this application, reference is made to... Figure 2Of the two isolation dielectric structures 360a and 360b, one isolation dielectric structure 360a is located between the gate 351 and the first electrode 330 to electrically isolate the gate 351 from the first electrode 330. The other isolation dielectric structure 360b is located between the gate 351 and the second electrode 340 to electrically isolate the gate 351 from the second electrode 340.

[0087] For example, refer to Figure 2 The isolation dielectric structure 360a includes a first isolation dielectric layer 361a, which surrounds a portion of the sidewall of the carbon nanotube. The first isolation dielectric layer 361a can not only be used to electrically isolate the gate 351 from the first electrode 330, but also to control the type and concentration of charge carriers in the CNT320, thereby reducing the contact resistance between the CNT320 and the first electrode 330, and making ohmic contact between the CNT320 and the first electrode 330 as much as possible, thus improving the performance of the CNTFET.

[0088] Furthermore, the isolation dielectric structure 360b includes a first isolation dielectric layer 361b, which surrounds a portion of the sidewall of the carbon nanotube. The first isolation dielectric layer 361b can not only be used to electrically isolate the gate 351 from the second electrode 340, but also to regulate the type and concentration of charge carriers in the CNT320, thereby reducing the contact resistance between the CNT320 and the second electrode 340, and maximizing the ohmic contact between the CNT320 and the second electrode 340 to improve the performance of the CNTFET.

[0089] Furthermore, in existing CNTFETs, to reduce the contact resistance between CNT320 and the first electrode 330 and the second electrode 340, a metal material with a specific work function is typically selected to form the first electrode 330 and the second electrode 340. This limits the flexibility in material selection for the first electrode 330 and the second electrode 340, thus restricting the design flexibility of the CNTFET. In this embodiment, by providing first isolation dielectric layers 361a and 361b, and by controlling the type and concentration of charge carriers in CNT320 through the first isolation dielectric layers 361a and 361b, the contact resistance between CNT320 and the first electrode 330 and the second electrode 340 can be reduced. Therefore, it is no longer necessary to additionally select a metal material with a specific work function to form the first electrode 330 and the second electrode 340. Instead, the range of materials for forming the first electrode 330 and the second electrode 340 can be broadened, further improving the design flexibility of the CNTFET.

[0090] In one embodiment of this application, reference is made to... Figure 2The first isolation dielectric layers 361a and 361b are in contact with the sidewalls of the CNT320, which can better electrically isolate the first electrode 330 and the second electrode 340 from the gate 351. Furthermore, the first isolation dielectric layers 361a and 361b can directly act on the CNT320, improving the precision of controlling the type and concentration of charge carriers in the CNT320.

[0091] In one embodiment of this application, reference is made to... Figure 2 The first isolation dielectric layers 361a and 361b are in contact with the substrate 310, which can better electrically isolate the first electrode 330 and the second electrode 340 from the gate 351. For example, when the substrate 310 includes a support layer 312, the first isolation dielectric layer 361a is in contact with the support layer 312.

[0092] In one embodiment of this application, reference is made to... Figure 2 The first isolation dielectric layers 361a and 361b are made of the same material, and the first isolation dielectric layers 361a and 361b can be formed in the same process, which reduces the difficulty of material selection, reduces process steps, and reduces costs.

[0093] Due to differences in deposition processes and the order in which the film layers are formed, the positions of the gate dielectric layer 352, the gate electrode 351, and the isolation dielectric structures 360a and 360b can differ. For example, refer to... Figure 2 The gate dielectric layer 352 is not only disposed between the gate 351 and CNT320, but also between the isolation dielectric structure 360a and the gate 351, between the isolation dielectric structure 360b and the gate 351, and between the gate 351 and the substrate 310.

[0094] In one embodiment of this application, the plurality of CNTFETs may include one or a combination of P-type CNTFETs and N-type CNTFETs. Exemplarily, the plurality of CNTFETs may all be either P-type or N-type CNTFETs, simplifying the fabrication process. Alternatively, the plurality may also include both P-type and N-type CNTFETs, allowing the P-type and N-type CNTFETs to form a complementary metal-oxide-semiconductor (CMOS) structure, thereby reducing leakage current in the CMOS structure and improving its performance.

[0095] Since the polarity of CNT320 is different in P-type CNTFET and N-type CNTFET, the contact form between CNT320 and the first electrode 330 and the second electrode 340 may also be different. Therefore, the material of the first isolation dielectric layer required is also different. Examples of P-type CNTFET and N-type CNTFET will be used for illustration below.

[0096] (1) When CNTFET includes P-type CNTFET: In P-type CNTFET, the materials of the first isolation dielectric layers 361a and 361b are first dielectric materials, and the work function of the first dielectric material is not less than 6eV. Therefore, the type of charge carriers of CNT320 can be controlled and the charge carrier concentration can be increased by the first isolation dielectric layers 361a and 361b with high work function, so that the energy band of CNT320 is bent, which is equivalent to the effect of forming P-type doping. This can reduce the Schottky barrier width between CNT320 and the first electrode 330 and the second electrode 340, making it easier for charge carriers to tunnel, thereby reducing the contact resistance between CNT320 and the first electrode 330 and the second electrode 340, realizing ohmic contact, which is suitable for the application scenarios of P-type CNTFET. When the first electrode 330 and the second electrode 340 are made of metal materials and the work function of the metal materials is high, the first electrode 330 and the second electrode 340 can be directly made to make ohmic contact with the CNT320. At this time, the carrier concentration is increased by the first isolation dielectric layers 361a and 361b, which can reduce the resistance of the CNT320 region surrounded by the first isolation dielectric layers 361a and 361b and increase the on-state current.

[0097] For example, the work function of the first dielectric material is not less than 6 eV or not less than 7 eV, further enabling the control of the type and concentration of charge carriers in the CNT320. For instance, the work function of the first dielectric material can be 6 eV, 6.6 eV, 7 eV, 7.6 eV, 8 eV, etc., and is not limited here. Furthermore, the work function of the first dielectric material can also be flexibly adjusted and controlled according to the design requirements of the actual application scenario, and is not limited here.

[0098] For example, the first dielectric material is a metal oxide. Therefore, the first dielectric material can be implemented using a metal oxide. Since metal oxides with a work function of not less than 6 eV are relatively mature, the implementation of the first dielectric material is relatively simple, thereby reducing the design difficulty of P-type CNTFETs and lowering production costs. As an example, the metal oxide includes, but is not limited to, one or a combination of tungsten oxide, vanadium oxide, molybdenum oxide, cobalt oxide, and ruthenium oxide. It is understood that in the actual fabrication process, the ratio of oxygen to metal elements may vary; therefore, the chemical formula of tungsten oxide can be WO3. y1 The chemical formula of vanadium oxide can be VO y2 The chemical formula of molybdenum oxide can be MoO y3 The chemical formula of cobalt oxide can be CoO y4 The chemical formula of ruthenium oxide can be RuO. y5Moreover, the values of y1 to y5 can be any numerical values, which can be flexibly designed according to the requirements of the actual application scenario and are not limited herein.

[0099] (2) When the CNTFET includes an N-type CNTFET: In the N-type CNTFET, the materials of the first isolation dielectric layers 361a and 361b are the second dielectric material, and the second dielectric material has positively charged defects. The positive charges carried by these defects have an electrostatic doping effect on the CNT 320, which can regulate the type of carriers in the CNT 320 and increase the carrier concentration, causing the energy band of the CNT 320 to bend, equivalent to forming the effect of N-type doping. Thus, the Schottky barrier width between the CNT 320 and the first electrode 330 and the second electrode 340 can be reduced, making it easier for carriers to achieve tunneling, and further reducing the contact resistance between the CNT 320 and the first electrode 330 and the second electrode 340, achieving ohmic contact, so as to be applicable to the application scenario of the N-type CNTFET. When the first electrode 330 and the second electrode 340 adopt a metal material and the work function of the metal material is relatively low, the first electrode 330 and the second electrode 340 can also directly achieve ohmic contact with the CNT 320. At this time, by increasing the carrier concentration through the first isolation dielectric layers 361a and 361b, the resistance of the CNT 320 region surrounded by the first isolation dielectric layers 361a and 361b can be reduced, and the on-state current can be increased.

[0100] Exemplarily, the second dielectric material includes one or a combination of: aluminum oxide, silicon oxide, aluminum nitride, silicon nitride, aluminum oxynitride, and silicon oxynitride. Thus, the implementation of the second dielectric material can be relatively simple, thereby reducing the design difficulty of the N-type CNTFET and the production cost.

[0101] As an example, the chemical formula of aluminum oxide is AlO x1 , 0 < x1 < 3 / 2, so that the first isolation dielectric layers 361a and 361b can have positively charged defects, equivalent to achieving N-type doping, so as to reduce the contact resistance between the CNT 320 and the first electrode 330 and the second electrode 340 and achieve ohmic contact.

[0102] As an example, the chemical formula of silicon oxide is SiO x2 [[ID=`16]]], 0 < x2 < 2, so that the first isolation dielectric layers 361a and 361b can have positively charged defects, equivalent to achieving N-type doping, so as to reduce the contact resistance between the CNT 320 and the first electrode 330 and the second electrode 340 and achieve ohmic contact.

[0103] As an example, the chemical formula of aluminum nitride is AlN x3, 0 < x3 < 1, such that there can be positively charged defects in the first isolation dielectric layers 361a and 361b, which is equivalent to achieving N-type doping to reduce the contact resistance between the CNT 320 and the first electrode 330 and the second electrode 340, and achieve ohmic contact.

[0104] As an example, the chemical formula of silicon nitride is SiN x4 , x4 > 4 / 3, such that there can be positively charged defects in the first isolation dielectric layers 361a and 361b, which is equivalent to achieving N-type doping to reduce the contact resistance between the CNT 320 and the first electrode 330 and the second electrode 340, and achieve ohmic contact.

[0105] It can be understood that for aluminum oxynitride, the component ratios of aluminum, nitrogen, and oxygen can be flexibly designed based on the adjustment of the positively charged defects in the formed material to achieve ohmic contact. Similarly, for silicon oxynitride, the component ratios of silicon, nitrogen, and oxygen can be flexibly designed based on the adjustment of the positively charged defects in the formed material to achieve ohmic contact.

[0106] Figure 3 Another structural schematic diagram of the chip in the embodiment of the present application, refer to Figure 3 , this embodiment is a deformation of the implementation manner in the Figure 2 illustrated embodiment. The same parts will not be elaborated here. The differences will be described below.

[0107] Exemplarily, refer to Figure 3 , the end face S1a of the first end DA1 of the CNT 320 facing away from the second end DA2 is embedded in the first electrode 330, and the end face S1b of the second end DA2 of the CNT 320 facing away from the first end DA1 is embedded in the second electrode 340. With this setting, the first electrode 330 and the second electrode 340 can also surround part of the side wall of the CNT 320, so that the first electrode 330 and the second electrode 340 can contact the side wall of the CNT 320. Thus, on the basis of the covalent bond contact between the CNT 320 and the first electrode 330 and the second electrode 340, the CNT 320 can further form van der Waals force contact with the first electrode 330 and the second electrode 340 respectively. Combining the covalent bond contact and the van der Waals force contact can further improve the conductivity between the CNT 320 and the first electrode 330 and the second electrode 340. In addition, during the process preparation, by etching back the isolation dielectric structures 360a and 360b, part of the regions of the first end DA1 and the second end DA2 of the CNT 320 can be exposed. After depositing and forming the first electrode 330 and the second electrode 340, the end face S1a of the CNT 320 can be embedded in the first electrode 330, and the end face S1b of the CNT 320 can be embedded in the second electrode 340.

[0108] Figure 4A and Figure 4B These are schematic diagrams illustrating yet another structural configuration of the chip in the embodiments of this application, wherein, Figure 4A The illustrated embodiments are for Figure 2 The embodiments shown have been modified. Figure 4B The illustrated embodiments are for Figure 3 The embodiments shown have been modified, and the similarities will not be repeated here. The differences will be explained below.

[0109] For example, refer to Figure 4A and Figure 4B The CNTFET features multiple layers of carbon nanotubes stacked and spaced apart. Each carbon nanotube layer contains one or more CNT320s, with a gate 351 surrounding each CNT320 and a gate dielectric layer 352 located between the gate 351 and each CNT320. This increases the effective channel area of ​​the CNTFET, improves its turn-on current, and thus enhances its performance and efficiency. Furthermore, the stacked design of the multilayer carbon nanotubes optimizes space utilization, allowing more CNTFETs to be accommodated within the same chip area, thereby increasing integration density.

[0110] Figure 5 This is another schematic diagram of the chip structure in the embodiments of this application, referring to... Figure 5 This embodiment is for Figure 2 The embodiments shown have been modified, and the similarities will not be repeated here. The differences will be explained below.

[0111] For example, refer to Figure 5 The isolation dielectric structure 360a further includes second isolation dielectric layers 362a1, 362a2, and 362a3, and the isolation dielectric structure 360b further includes second isolation dielectric layers 362b1, 362b2, and 362b3. Furthermore, in the same isolation dielectric structure 360a, the second isolation dielectric layers 362a1 to 362a3 are located between the first isolation dielectric layer 361a and the gate 351, and surround a portion of the sidewall of the CNT 320. In the same isolation dielectric structure 360b, the second isolation dielectric layers 362b1 to 362b3 are located between the first isolation dielectric layer 361b and the gate 351, and surround a portion of the sidewall of the CNT 320. Therefore, the second isolation dielectric layers 362a1 to 362a3 can be used to further electrically isolate the gate 351 from the first electrode 330, and the second isolation dielectric layers 362b1 to 362b3 can be used to electrically isolate the gate 351 from the second electrode 340, thereby improving electrical isolation performance.

[0112] For example, refer to Figure 5 The second isolation dielectric layers 362a1~362a3 and 362b1~362b3 are in contact with the sidewall of CNT320, which can better electrically isolate the first electrode 330 and the second electrode 340 from the gate 351.

[0113] For example, refer to Figure 5 The second isolation dielectric layers 362a1-362a3 and 362b1-362b3 are in contact with the substrate 310, which can better electrically isolate the first electrode 330 and the second electrode 340 from the gate 351. For example, when the substrate 310 includes a support layer 312, the second isolation dielectric layers 362a1-362a3 and 362b1-362b3 are in contact with the support layer 312.

[0114] For example, the materials of the second isolation dielectric layers 362a1 to 362a3 and 362b1 to 362b3 can be the aforementioned metal oxides, or the materials of the second isolation dielectric layers 362a1 to 362a3 and 362b1 to 362b3 can also be other common dielectric materials, such as alumina, silicon oxide, silicon nitride, etc., which are not limited here.

[0115] Understandably, in order to clearly demonstrate the structure of the CNTFET in the embodiments of this application, Figure 5 The illustration is given using the contact between end face S1a and surface S2a, and the contact between end face S1b and surface S2b of CNT320 in a CNTFET. In other embodiments of this application, it can also be combined with... Figure 3 The structure shown embeds end face S1a into the first electrode 330 and end face S1b into the second electrode 340, but the specific details are not limited here.

[0116] Furthermore, in order to clearly demonstrate the structure of the CNTFET in the embodiments of this application, Figure 5 The illustration takes the formation of CNT320 as a single-layer carbon nanotube layer in a CNTFET as an example. In other embodiments of this application, it can also be combined with... Figure 4A and Figure 4B The structure shown contains multiple layers of carbon nanotubes in the CNTFET, but the specific details are not limited here.

[0117] In one embodiment of this application, in any CNTFET, within the same isolation dielectric structure, the relative permittivity of the second isolation dielectric layer is less than that of the first isolation dielectric layer, thereby reducing the parasitic capacitance between the gate 351 and the first electrode 330 and the second electrode 340. For example, refer to... Figure 5In any CNTFET, within the same isolation dielectric structure 360a, the relative permittivity of the second isolation dielectric layers 362a1 to 362a3 is lower than that of the first isolation dielectric layer 361a, which reduces the parasitic capacitance between the gate 351 and the first electrode 330. Furthermore, within the same isolation dielectric structure 360b, the relative permittivity of the second isolation dielectric layers 362b1 to 362b3 is lower than that of the first isolation dielectric layer 361b, which reduces the parasitic capacitance between the gate 351 and the second electrode 340. In other words, whether it is an N-type or P-type CNTFET, the parasitic capacitance between the gate 351 and the first electrode 330 and the second electrode 340 can be reduced by setting the second isolation dielectric layers 362a1 to 362a3 and 362b1 to 362b3.

[0118] For example, the relative permittivity of at least one of the second isolation dielectric layers 362a1 to 362a3 is not greater than 4, further reducing the parasitic capacitance between the gate 351 and the first electrode 330. For instance, the relative permittivity of any one of the second isolation dielectric layers 362a1 to 362a3 is not greater than 4, further reducing the parasitic capacitance between the gate 351 and the first electrode 330. For example, the relative permittivity of any one of the second isolation dielectric layers 362a1 to 362a3 can be 4, 3.9, 3.8, 3.7, 3.6, 3.5, 3.4, 3.3, etc., and is not limited here. Furthermore, the relative permittivity of the second isolation dielectric layers 362a1 to 362a3 is not limited to a value not greater than 4, and can be flexibly adjusted and controlled according to the design requirements of the actual application scenario, and is not limited here.

[0119] For example, the relative permittivity of at least one of the second isolation dielectric layers 362b1 to 362b3 is not greater than 4, further reducing the parasitic capacitance between the gate 351 and the first electrode 330. For instance, the relative permittivity of any one of the second isolation dielectric layers 362b1 to 362b3 is not greater than 4, further reducing the parasitic capacitance between the gate 351 and the first electrode 330. For example, the relative permittivity of any one of the second isolation dielectric layers 362b1 to 362b3 can be 4, 3.9, 3.8, 3.7, 3.6, 3.5, 3.4, 3.3, etc., and is not limited here. Furthermore, the relative permittivity of the second isolation dielectric layers 362b1 to 362b3 is not limited to a value not greater than 4, and can be flexibly adjusted and controlled according to the design requirements of the actual application scenario, and is not limited here.

[0120] For example, in any CNTFET, within the same isolation dielectric structure, the relative permittivity of the second isolation dielectric layer farther from the gate 351 is either larger or smaller. This allows the relative permittivity of the second isolation dielectric layer within the same isolation dielectric structure to be set in a gradient form, satisfying the design requirements for relative permittivity in some application scenarios. For instance, the relative permittivity of the second isolation dielectric layers 362a1 to 362a3 is successively larger or smaller, and the relative permittivity of the second isolation dielectric layers 362b1 to 362b3 is successively larger or smaller.

[0121] For example, in any CNTFET, in the two isolation dielectric structures, the relative permittivity of the second isolation dielectric layers that are in the same order from the gate 351 is the same. For example, the second isolation dielectric layers 362a1 and 362b1 are in the same order from the gate 351 and have the same relative permittivity; the second isolation dielectric layers 362a2 and 362b2 are in the same order from the gate 351 and have the same relative permittivity; and the second isolation dielectric layers 362a3 and 362b3 are in the same order from the gate 351 and have the same relative permittivity.

[0122] For example, in any CNTFET, in the two isolation dielectric structures, the second isolation dielectric layers with the same order of distance from the gate 351 are made of the same material. These second isolation dielectric layers with the same order of distance from the gate 351 can be formed in the same process, reducing the difficulty of material selection, reducing process steps, and lowering costs. For instance, if the second isolation dielectric layers 362a1 and 362b1 have the same order of distance from the gate 351 and are made of the same material, they can be formed in the same process, reducing the difficulty of material selection, reducing process steps, and lowering costs. Similarly, if the second isolation dielectric layers 362a2 and 362b2 have the same order of distance from the gate 351 and are made of the same material, they can be formed in the same process, reducing the difficulty of material selection, reducing process steps, and lowering costs. The second isolation dielectric layers 362a3 and 362b3 are in the same order from the gate 351 and are made of the same material. Therefore, the second isolation dielectric layers 362a3 and 362b3 can be formed in the same process, which reduces the difficulty of material selection, reduces process steps, and reduces costs.

[0123] It is understood that the structure described in this embodiment can be applied to any CNTFET, that is, whether it is a P-type CNTFET or an N-type CNTFET. However, since the methods for controlling the type and concentration of charge carriers in CNT320 are different in P-type CNTFETs and N-type CNTFETs, examples are given below for each.

[0124] In a P-type CNTFET, by using the first isolation dielectric layers 361a and 361b as the first dielectric material, and ensuring that the work function of the first dielectric material is not less than 6 eV, the carrier concentration of the CNT320 can be increased. However, when the carrier concentration of the CNT320 is high, BTBT leakage during the off-state is prone to occur. Therefore, in this embodiment of the application, by adjusting the work function of the second isolation dielectric layers 362a1-362a3 and 362b1-362b3 in the P-type CNTFET, the problem of BTBT leakage during the off-state can be reduced. For example, in a P-type CNTFET, within the same isolation dielectric structure 360a, by making the work function of the second isolation dielectric layers 362a1 to 362a3 smaller than the work function of the first isolation dielectric layer 361a, the carrier concentration in the portion B2a of the CNT 320 surrounded by the isolation dielectric structure 360a gradually changes in the direction towards the first terminal DA1. This allows for the control of the band bending degree, thereby reducing the BTBT leakage problem in the off-state. Similarly, within the same isolation dielectric structure 360b, by making the work function of the second isolation dielectric layers 362b1 to 362b3 smaller than the work function of the first isolation dielectric layer 361b, the carrier concentration in the portion B2b of the CNT 320 surrounded by the isolation dielectric structure 360b gradually changes in the direction towards the second terminal DA2. This allows for the control of the band bending degree, thereby reducing the BTBT leakage problem in the off-state.

[0125] For example, in a P-type CNTFET, within the same isolation dielectric structure 360a, the work function of the second isolation dielectric layer farther from the gate 351 can be increased. For instance, the work function of the second isolation dielectric layers 362a1 to 362a3 increases sequentially, thereby gradually increasing the carrier concentration of the CNT320 portion B2a in the direction toward the first terminal DA1, further improving the band bending degree and further reducing the BTBT leakage problem in the off-state.

[0126] Furthermore, in the P-type CNTFET, within the same isolation dielectric structure 360b, the work function of the second isolation dielectric layer farther from the gate 351 can be increased. For example, the work function of the second isolation dielectric layers 362b1 to 362b3 increases sequentially, thereby gradually increasing the carrier concentration of the B2b portion of CNT320 in the direction toward the second terminal DA2, further improving the band bending degree and further reducing the BTBT leakage problem in the off-state.

[0127] For example, in a P-type CNTFET, in two isolation dielectric structures, the work functions of the second isolation dielectric layers that are in the same order from the gate 351 are the same. For example, the work functions of the second isolation dielectric layers 362a1 and 362b1 are the same, the work functions of the second isolation dielectric layers 362a2 and 362b2 are the same, and the work functions of the second isolation dielectric layers 362a3 and 362b3 are the same.

[0128] Understandably, in a P-type CNTFET, the relative permittivity of the second isolation dielectric layers 362a1-362a3 and 362b1-362b3 can be adjusted based on the work function of the second isolation dielectric layers 362a1-362a3 and 362b1-362b3. This not only reduces BTBT leakage current but also reduces the parasitic capacitance between the gate 351 and the first electrode 330 and the second electrode 340.

[0129] In an N-type CNTFET, by using the material of the first isolation dielectric layers 361a and 361b as the second dielectric material, and by ensuring that the second dielectric material has positively charged defects, the carrier concentration of the CNT320 can be increased. However, when the carrier concentration of the CNT320 is high, BTBT leakage during the off-state is prone to occur. Therefore, in this embodiment of the application, in the N-type CNTFET, the material of the second isolation dielectric layers 362a1-362a3 and 362b1-362b3 is a third dielectric material, and this third dielectric material has positively charged defects. Furthermore, in the same isolation dielectric structure 360a, the concentration of positive charge from defects in the second isolation dielectric layers 362a1 to 362a3 is less than the concentration of positive charge from defects in the first isolation dielectric layer 361a. This allows for a gradual change in carrier concentration in the portion B2a of the CNT320 surrounded by the isolation dielectric structure 360a in the direction towards the first end DA1, thereby controlling the degree of band bending and reducing BTBT leakage in the off-state. Similarly, in the same isolation dielectric structure 360b, by making the concentration of positive charge from defects in the second isolation dielectric layers 362b1 to 362b3 less than the concentration of positive charge from defects in the first isolation dielectric layer 361b, the concentration of carrier concentration in the portion B2b of the CNT320 surrounded by the isolation dielectric structure 360b in the direction towards the second end DA2 is gradually changed, thereby controlling the degree of band bending and reducing BTBT leakage in the off-state.

[0130] It is understood that, in the embodiments of this application, the concentration of positive charge of a defect may refer to the number of positive charges of a defect per unit volume or unit area.

[0131] For example, in an N-type CNTFET, within the same isolation dielectric structure 360a, the concentration of positive charge of defects in the second isolation dielectric layer farther from the gate 351 can be increased. For instance, the concentration of positive charge of defects in the second isolation dielectric layers 362a1 to 362a3 increases sequentially, thereby gradually increasing the carrier concentration of the CNT320 portion B2a in the direction toward the first terminal DA1, further improving the band bending degree and further reducing the BTBT leakage problem in the off-state.

[0132] Furthermore, in the N-type CNTFET, within the same isolation dielectric structure 360b, the concentration of positive charge of defects in the second isolation dielectric layer farther from the gate 351 can be increased. For example, the concentration of positive charge of defects in the second isolation dielectric layers 362b1 to 362b3 increases sequentially. This allows the carrier concentration in the B2b portion of the CNT320 to gradually increase in the direction toward the second terminal DA2, further improving the band bending degree and further reducing the BTBT leakage problem in the off-state.

[0133] For example, in an N-type CNTFET, in two isolation dielectric structures, the concentration of positive charge of defects in the second isolation dielectric layer that is in the same order from the gate 351 is the same. For example, the concentration of positive charge of defects in the second isolation dielectric layers 362a1 and 362b1 is the same, the concentration of positive charge of defects in the second isolation dielectric layers 362a2 and 362b2 is the same, and the concentration of positive charge of defects in the second isolation dielectric layers 362a3 and 362b3 is the same.

[0134] Understandably, in an N-type CNTFET, the relative permittivity of the second isolation dielectric layers 362a1-362a3 and 362b1-362b3 can be adjusted by adjusting the concentration of positive charge of defects in the second isolation dielectric layers 362a1-362a3 and 362b1-362b3. This not only reduces BTBT leakage current but also reduces the parasitic capacitance between the gate 351 and the first electrode 330 and the second electrode 340.

[0135] For example, the third dielectric material includes one or a combination of aluminum oxide, silicon oxide, aluminum nitride, silicon nitride, aluminum oxide nitride, and silicon oxide nitride. This makes the implementation of the third dielectric material relatively simple, thereby reducing the design complexity of N-type CNTFETs and lowering production costs.

[0136] As an example, the chemical formula of the aluminum oxide in the third dielectric material is AlO. z1, 0 < z1 < 3 / 2, such that the second isolation dielectric layers 362a1 - 362a3, 362b1 - 362b3 can have positively charged defects, which is equivalent to achieving N-type doping to reduce the contact resistance between the CNT 320 and the first electrode 330 and the second electrode 340, and achieve ohmic contact. Exemplarily, when both the second dielectric material and the third dielectric material are oxides of aluminum, z1 can be made different from x1. For example, z1 < x1 can be set to achieve a concentration difference of positive charges.

[0137] As an example, the chemical formula of the oxide of silicon in the third dielectric material is SiO z2 , 0 < z2 < 2, such that the second isolation dielectric layers 362a1 - 362a3, 362b1 - 362b3 can have positively charged defects, which is equivalent to achieving N-type doping to reduce the contact resistance between the CNT 320 and the first electrode 330 and the second electrode 340, and achieve ohmic contact. Exemplarily, when both the second dielectric material and the third dielectric material are oxides of silicon, z2 can be made different from x2. For example, z2 < x2 can be set to achieve a concentration difference of positive charges.

[0138] As an example, the chemical formula of the nitride of aluminum in the third dielectric material is AlN z3 , 0 < z3 < 1, such that the second isolation dielectric layers 362a1 - 362a3, 362b1 - 362b3 can have positively charged defects, which is equivalent to achieving N-type doping to reduce the contact resistance between the CNT 320 and the first electrode 330 and the second electrode 340, and achieve ohmic contact. Exemplarily, when both the second dielectric material and the third dielectric material are nitrides of aluminum, z3 can be made different from x3. For example, z3 < x3 can be set to achieve a concentration difference of positive charges.

[0139] As an example, the chemical formula of the nitride of silicon in the third dielectric material is SiN z4 , z4 > 4 / 3, such that the second isolation dielectric layers 362a1 - 362a3, 362b1 - 362b3 can have positively charged defects, which is equivalent to achieving N-type doping to reduce the contact resistance between the CNT 320 and the first electrode 330 and the second electrode 340, and achieve ohmic contact. Exemplarily, when both the second dielectric material and the third dielectric material are nitrides of silicon, z4 can be made different from x4. For example, z4 < x4 can be set to achieve a concentration difference of positive charges.

[0140] Figure 6 This is another schematic structural diagram of the chip in the embodiment of the present application. Refer to Figure 6 , this embodiment is directed to Figure 5The embodiments shown have been modified, and the similarities will not be repeated here. The differences will be explained below.

[0141] For example, refer to Figure 6 In any CNTFET, whether it is an N-type or P-type CNTFET, within the same isolation dielectric structure 360a, the first isolation dielectric layer 361a is located between the second isolation dielectric layers 362a1-362a3 and the sidewall of the CNT320. Furthermore, in the same isolation dielectric structure 360b, the first isolation dielectric layer 361b is located between the second isolation dielectric layers 362b1-362b3 and the sidewall of the CNT320, further enabling the control of the type and concentration of charge carriers in the CNT320.

[0142] For example, refer to Figure 6 In any CNTFET, whether it is an N-type or P-type CNTFET, within the same isolation dielectric structure 360a, the first isolation dielectric layer 361a is also located between the second isolation dielectric layers 362a1 to 362a3 and the substrate 310. Furthermore, in the same isolation dielectric structure 360b, the first isolation dielectric layer 361b is also located between the second isolation dielectric layers 362b1 to 362b3 and the substrate 310.

[0143] Figure 7 This is another schematic diagram of the chip structure in the embodiments of this application, referring to... Figure 7 This embodiment is for Figure 6 The embodiments shown have been modified, and the similarities will not be repeated here. The differences will be explained below.

[0144] In one embodiment of this application, each isolation dielectric structure includes a plurality of second isolation dielectric layers, including an m-th second isolation dielectric layer and an (m+1)-th second isolation dielectric layer. The (m+1)-th second isolation dielectric layer is located between the m-th second isolation dielectric layer and the gate 351, where m is a positive integer. The value of m can be selected from 1 to M-1, where M is the total number of second isolation dielectric layers in the same isolation dielectric structure. For example, referring to… Figure 6The isolation dielectric structure 360a has second isolation dielectric layers 362a1 to 362a3. When m = 1, the second isolation dielectric layer 362a1 can be used as the first second isolation dielectric layer, and the second isolation dielectric layer 362a2 can be used as the second second isolation dielectric layer. In this case, the second isolation dielectric layer 362a2 is located between the second isolation dielectric layer 362a1 and the gate 351. When m = 2, the second isolation dielectric layer 362a2 can be used as the second second isolation dielectric layer, and the second isolation dielectric layer 362a3 can be used as the third second isolation dielectric layer. In this case, the second isolation dielectric layer 362a3 is located between the second isolation dielectric layer 362a2 and the gate 351. Similarly, the isolation dielectric structure 360b has second isolation dielectric layers 362b1 to 362b3. When m = 1, the second isolation dielectric layer 362b1 can be used as the first second isolation dielectric layer, and the second isolation dielectric layer 362b2 can be used as the second second isolation dielectric layer. In this case, the second isolation dielectric layer 362b2 is located between the second isolation dielectric layer 362b1 and the gate 351. When m = 2, the second isolation dielectric layer 362b2 can be used as the second second isolation dielectric layer, and the second isolation dielectric layer 362b3 can be used as the third second isolation dielectric layer. In this case, the second isolation dielectric layer 362b3 is located between the second isolation dielectric layer 362b2 and the gate 351.

[0145] In one embodiment of this application, in the same isolation medium structure, the (m+1)th second isolation medium layer is further provided between the m-th second isolation medium layer and the sidewall of CNT320. For example, refer to... Figure 6 In the isolation dielectric structure 360a, when m=1, a second isolation dielectric layer 362a1 is also present between the second isolation dielectric layer 362a2 and the sidewall of the CNT320. When m=2, a second isolation dielectric layer 362a2 is also present between the second isolation dielectric layer 362a3 and the sidewall of the CNT320. Similarly, in the isolation dielectric structure 360b, when m=1, a second isolation dielectric layer 362b1 is also present between the second isolation dielectric layer 362b2 and the sidewall of the CNT320. When m=2, a second isolation dielectric layer 362b2 is also present between the second isolation dielectric layer 362b3 and the sidewall of the CNT320.

[0146] In one embodiment of this application, in the same isolation dielectric structure, the (m+1)th second isolation dielectric layer is further provided between the substrate 310 and the second second isolation dielectric layer. For example, referring to... Figure 6In the isolation dielectric structure 360a, when m=1, a second isolation dielectric layer 362a1 is also present between the second isolation dielectric layer 362a2 and the substrate 310. When m=2, a second isolation dielectric layer 362a2 is also present between the second isolation dielectric layer 362a3 and the substrate 310. Similarly, in the isolation dielectric structure 360b, when m=1, a second isolation dielectric layer 362b1 is also present between the second isolation dielectric layer 362b2 and the substrate 310. When m=2, a second isolation dielectric layer 362b3 is also present between the second isolation dielectric layer 362b2 and the substrate 310.

[0147] In one embodiment of this application, in any CNTFET, within the same isolation dielectric structure, the relative permittivity of the m-th second isolation dielectric layer is greater than the relative permittivity of the (m+1)-th second isolation dielectric layer. For example, refer to... Figure 6 In the isolation dielectric structure 360a, when m=1, the relative permittivity of the second isolation dielectric layer 362a1 is greater than that of the second isolation dielectric layer 362a2. When m=2, the relative permittivity of the second isolation dielectric layer 362a2 is greater than that of the second isolation dielectric layer 362a3. Similarly, in the isolation dielectric structure 360b, when m=1, the relative permittivity of the second isolation dielectric layer 362b1 is greater than that of the second isolation dielectric layer 362b2. When m=2, the relative permittivity of the second isolation dielectric layer 362b2 is greater than that of the second isolation dielectric layer 362b3. Therefore, the relative permittivity of multiple second isolation dielectric layers in the same isolation dielectric structure can be gradually varied, improving structural stability.

[0148] It is understood that the structure described in this embodiment can be applied to any CNTFET, that is, whether it is a P-type CNTFET or an N-type CNTFET. However, since the methods for controlling the type and concentration of charge carriers in CNT320 are different in P-type CNTFETs and N-type CNTFETs, examples are given below for each.

[0149] In a P-type CNTFET, within the same isolation dielectric structure, the work function of the m-th second isolation dielectric layer is greater than the work function of the (m+1)-th second isolation dielectric layer. For example, refer to... Figure 6In the isolation dielectric structure 360a, when m=1, the work function of the second isolation dielectric layer 362a1 is greater than that of the second isolation dielectric layer 362a2. When m=2, the work function of the second isolation dielectric layer 362a2 is greater than that of the second isolation dielectric layer 362a3. Similarly, in the isolation dielectric structure 360b, when m=1, the work function of the second isolation dielectric layer 362b1 is greater than that of the second isolation dielectric layer 362b2. When m=2, the work function of the second isolation dielectric layer 362b2 is greater than that of the second isolation dielectric layer 362b3. Therefore, the work functions of multiple second isolation dielectric layers in the same isolation dielectric structure can be gradually varied, improving structural stability.

[0150] For example, in a P-type CNTFET, the work function of the m-th second isolation dielectric layer is the same in both isolation dielectric structures. For instance, the work functions of second isolation dielectric layers 362a1 and 362b1 are the same, the work functions of second isolation dielectric layers 362a2 and 362b2 are the same, and the work functions of second isolation dielectric layers 362a3 and 362b3 are the same. This allows the gradient of the work function to be symmetrically set, thus ensuring a symmetrical gradient in the carrier concentration of the CNT320.

[0151] For example, in a P-type CNTFET, the work function of the m-th second isolation dielectric layer in two isolation dielectric structures is made of the same material, so that the m-th second isolation dielectric layer in both isolation dielectric structures can be formed in the same process, reducing the difficulty of material selection, reducing process steps, and reducing costs. For example, the second isolation dielectric layers 362a1 and 362b1 are made of the same material, so that the second isolation dielectric layers 362a2 and 362b2 are made of the same material, so that the second isolation dielectric layers 362a3 and 362b3 are made of the same material, so that the second isolation dielectric layers 362a3 and 362b3 are formed in the same process.

[0152] In an N-type CNTFET, within the same isolation dielectric structure, the concentration of positive charge from defects in the m-th second isolation dielectric layer is greater than the concentration of positive charge from defects in the (m+1)-th second isolation dielectric layer. For example, refer to... Figure 6In the isolation dielectric structure 360a, when m=1, the concentration of positive charge of defects in the second isolation dielectric layer 362a1 is greater than that in the second isolation dielectric layer 362a2. When m=2, the concentration of positive charge of defects in the second isolation dielectric layer 362a2 is greater than that in the second isolation dielectric layer 362a3. Similarly, in the isolation dielectric structure 360b, when m=1, the concentration of positive charge of defects in the second isolation dielectric layer 362b1 is greater than that in the second isolation dielectric layer 362b2. When m=2, the concentration of positive charge of defects in the second isolation dielectric layer 362b2 is greater than that in the second isolation dielectric layer 362b3. Therefore, the concentration of positive charge of defects in multiple second isolation dielectric layers within the same isolation dielectric structure can be gradually varied, improving structural stability.

[0153] For example, in an N-type CNTFET, in two isolation dielectric structures, the concentration of positive charge of defects in the m-th second isolation dielectric layer is the same. For instance, the concentration of positive charge of defects in second isolation dielectric layers 362a1 and 362b1 is the same, the concentration of positive charge of defects in second isolation dielectric layers 362a2 and 362b2 is the same, and the concentration of positive charge of defects in second isolation dielectric layers 362a3 and 362b3 is the same. This allows the gradient of the positive charge concentration of defects in the m-th second isolation dielectric layer to be symmetrically set, so that the gradient of the carrier concentration of CNT320 can also be symmetrical.

[0154] For example, in an N-type CNTFET, the materials used for the concentration of positive charge on defects in the m-th second isolation dielectric layer are the same in both isolation dielectric structures. This allows the m-th second isolation dielectric layer in both structures to be formed using the same process, reducing the difficulty of material selection, minimizing process steps, and lowering costs. For instance, second isolation dielectric layers 362a1 and 362b1 are made of the same material, allowing them to be formed using the same process. Similarly, second isolation dielectric layers 362a2 and 362b2 are made of the same material, allowing them to be formed using the same process. Likewise, second isolation dielectric layers 362a3 and 362b3 are made of the same material, allowing them to be formed using the same process.

[0155] Figure 8 This is another schematic diagram of the chip structure in the embodiments of this application, referring to... Figure 8 This embodiment is for Figure 7 The embodiments shown have been modified, and the similarities will not be repeated here. The differences will be explained below.

[0156] For example, refer to Figure 8The isolation dielectric structure 360a further includes a third isolation dielectric layer 363a, which surrounds a portion of the sidewall of the CNT 320. In the same isolation dielectric structure 360a, the third isolation dielectric layer 363a is located on the side of the first isolation dielectric layer 361a facing away from the gate 351, and between the first isolation dielectric layer 361a and the sidewall of the CNT 320. Furthermore, the isolation dielectric structure 360b also includes a third isolation dielectric layer 363b, which surrounds a portion of the sidewall of the CNT 320. In the same isolation dielectric structure 360b, the third isolation dielectric layer 363b is located on the side of the first isolation dielectric layer 361b facing away from the gate 351, and between the first isolation dielectric layer 361b and the sidewall of the CNT 320. Therefore, the gate 351 can be further electrically isolated from the first electrode 330 and the second electrode 340, improving electrical isolation performance.

[0157] For example, the third isolation dielectric layer 363a is also located between the first isolation dielectric layer 361a and the substrate 310, and the third isolation dielectric layer 363b is also located between the first isolation dielectric layer 361b and the substrate 310.

[0158] For example, the relative permittivity of the third isolation dielectric layer 363a is less than that of the first isolation dielectric layer 361a, and the relative permittivity of the third isolation dielectric layer 363b is less than that of the first isolation dielectric layer 361b.

[0159] For example, the third isolation dielectric layers 363a and 363b have the same relative permittivity.

[0160] For example, the third isolation dielectric layer 363a and 363b are made of the same material, so that the third isolation dielectric layer 363a and 363b can be formed in the same process, reducing the difficulty of material selection, reducing process steps, and reducing costs.

[0161] In addition, the isolation medium structure 360a also includes a second isolation medium layer 362a1 to 362a2, and the isolation medium structure 360b also includes a second isolation medium layer 362b1 to 362b2. For the implementation of the second isolation medium layers 362a1 to 362a2 and 362b1 to 362b2, please refer to the description in the above embodiments, and the specific details will not be repeated here.

[0162] It is understood that the structure described in this embodiment can be applied to any CNTFET, that is, whether it is a P-type CNTFET or an N-type CNTFET. However, since the methods for controlling the type and concentration of charge carriers in CNT320 are different in P-type CNTFETs and N-type CNTFETs, examples are given below for each.

[0163] In a P-type CNTFET, within the same isolation dielectric structure 360a, the work function of the third isolation dielectric layer 363a is less than that of the first isolation dielectric layer 361a. Therefore, the distance between the first isolation dielectric layer 361a and the sidewalls of the CNT 320 can be controlled by adjusting the thickness of the third isolation dielectric layer 363a, thereby controlling the type and concentration of charge carriers in the CNT 320 affected by the first isolation dielectric layer 361a. Similarly, within the same isolation dielectric structure 360b, the work function of the third isolation dielectric layer 363b is less than that of the first isolation dielectric layer 361b. Therefore, the distance between the first isolation dielectric layer 361b and the sidewalls of the CNT 320 can be controlled by adjusting the thickness of the third isolation dielectric layer 363b, thereby controlling the type and concentration of charge carriers in the CNT 320 affected by the first isolation dielectric layer 361b.

[0164] For example, in a P-type CNTFET, the third isolation dielectric layer 363a and 363b have the same work function.

[0165] For example, in a P-type CNTFET, the materials of the third isolation dielectric layers 363a and 363b can be the aforementioned metal oxides, or the materials of the third isolation dielectric layers 363a and 363b can also be other common dielectric materials, such as alumina, silicon oxide, silicon nitride, etc., without limitation.

[0166] In an N-type CNTFET, within the same isolation dielectric structure 360a, the concentration of positive charge from defects in the third isolation dielectric layer 363a is less than the concentration of positive charge from defects in the first isolation dielectric layer 361a. Therefore, the distance between the first isolation dielectric layer 361a and the sidewalls of the CNT 320 can be controlled by adjusting the thickness of the third isolation dielectric layer 363a, thereby controlling the type and concentration of charge carriers in the CNT 320 from the first isolation dielectric layer 361a. Similarly, within the same isolation dielectric structure 360b, the concentration of positive charge from defects in the third isolation dielectric layer 363b is less than the concentration of positive charge from defects in the first isolation dielectric layer 361b. Therefore, the distance between the first isolation dielectric layer 361b and the sidewalls of the CNT 320 can be controlled by adjusting the thickness of the third isolation dielectric layer 363b, thereby controlling the type and concentration of charge carriers in the CNT 320 from the first isolation dielectric layer 361b.

[0167] For example, in an N-type CNTFET, the concentration of positive charge of defects in the third isolation dielectric layer 363a and 363b is the same.

[0168] For example, in an N-type CNTFET, the materials of the third isolation dielectric layers 363a and 363b can be the aforementioned third dielectric material, or the materials of the third isolation dielectric layers 363a and 363b can also be other common dielectric materials, which are not limited here.

[0169] Figure 9 This is another schematic diagram of the chip structure in the embodiments of this application, referring to... Figure 9 This embodiment is for Figure 2 The embodiments shown have been modified, and the similarities will not be repeated here. The differences will be explained below.

[0170] For example, refer to Figure 9 The isolation dielectric structure 360a further includes fifth isolation dielectric layers 365a1 and 365a2, which surround the first isolation dielectric layer 361a within the same isolation dielectric structure 360a. Furthermore, the relative permittivity of the fifth isolation dielectric layers 365a1 and 365a2 is lower than that of the first isolation dielectric layer 361a. Therefore, not only can the gate 351 and the first electrode 330 be electrically isolated, but the parasitic capacitance between the gate 351 and the first electrode 330 can also be reduced.

[0171] Furthermore, the isolation dielectric structure 360b also includes fifth isolation dielectric layers 365b1 and 365b2, which surround the first isolation dielectric layer 361b within the same isolation dielectric structure 360b. Moreover, the relative permittivity of the fifth isolation dielectric layers 365b1 and 365b2 is lower than that of the first isolation dielectric layer 361b. Therefore, not only can the gate 351 and the second electrode 340 be electrically isolated, but the parasitic capacitance between the gate 351 and the second electrode 340 can also be reduced.

[0172] For example, the relative permittivity of at least one of the fifth isolation dielectric layers 365a1 to 365a3 is not greater than 4, further reducing the parasitic capacitance between the gate 351 and the first electrode 330. For instance, the relative permittivity of any one of the fifth isolation dielectric layers 365a1 to 365a3 is not greater than 4, further reducing the parasitic capacitance between the gate 351 and the first electrode 330. For example, the relative permittivity of any one of the fifth isolation dielectric layers 365a1 to 365a3 can be 4, 3.9, 3.8, 3.7, 3.6, 3.5, 3.4, 3.3, etc., and is not limited here. Furthermore, the relative permittivity of the fifth isolation dielectric layers 365a1 to 365a3 is not limited to a value not greater than 4, and can be flexibly adjusted and controlled according to the design requirements of the actual application scenario, and is not limited here.

[0173] For example, the relative permittivity of at least one of the fifth isolation dielectric layers 365b1 to 365b3 is not greater than 4, further reducing the parasitic capacitance between the gate 351 and the first electrode 330. For instance, the relative permittivity of any one of the fifth isolation dielectric layers 365b1 to 365b3 is not greater than 4, further reducing the parasitic capacitance between the gate 351 and the first electrode 330. For example, the relative permittivity of any one of the fifth isolation dielectric layers 365b1 to 365b3 can be 4, 3.9, 3.8, 3.7, 3.6, 3.5, 3.4, 3.3, etc., and is not limited here. Furthermore, the relative permittivity of the fifth isolation dielectric layers 365b1 to 365b3 is not limited to a value not greater than 4, and can be flexibly adjusted and controlled according to the design requirements of the actual application scenario, and is not limited here.

[0174] For example, in any CNTFET, each isolation dielectric structure includes multiple fifth isolation dielectric layers. Within the same isolation dielectric structure, the relative permittivity of the fifth isolation dielectric layer farther away from CNT320 is either larger or smaller. This allows the relative permittivity of the fifth isolation dielectric layers within the same isolation dielectric structure to be set in a gradient form, meeting the design requirements for relative permittivity in some application scenarios. For instance, the relative permittivity of the fifth isolation dielectric layers 365a1 to 365a3 is successively larger or smaller, and the relative permittivity of the fifth isolation dielectric layers 365b1 to 365b3 is successively larger or smaller.

[0175] For example, in any CNTFET, in the two isolation dielectric structures, the fifth isolation dielectric layers that are in the same order from CNT320 have the same relative permittivity. For example, the fifth isolation dielectric layers 365a1 and 365b1 are in the same order from CNT320 and have the same relative permittivity; the fifth isolation dielectric layers 365a2 and 365b2 are in the same order from CNT320 and have the same relative permittivity; the fifth isolation dielectric layers 365a3 and 365b3 are in the same order from CNT320 and have the same relative permittivity.

[0176] For example, in any CNTFET, if the fifth isolation dielectric layers in the two isolation dielectric structures have the same material at the same distance from the gate 351, they can be formed in the same process, reducing the difficulty of material selection, reducing process steps, and reducing costs. For instance, if the fifth isolation dielectric layers 365a1 and 365b1 have the same distance from the CNT 320 and are made of the same material, they can be formed in the same process, reducing the difficulty of material selection, reducing process steps, and reducing costs. Similarly, if the fifth isolation dielectric layers 365a2 and 365b2 have the same distance from the CNT 320 and are made of the same material, they can be formed in the same process, reducing the difficulty of material selection, reducing process steps, and reducing costs. Since the fifth insulating dielectric layers 365a3 and 365b3 are in the same order from CNT320 and are made of the same material, they can be formed in the same process, which reduces the difficulty of material selection, reduces process steps, and reduces costs.

[0177] For example, the materials of the fifth isolation dielectric layers 365a1 to 365a3 and 365b1 to 365b3 can be the aforementioned metal oxides, or the materials of the fifth isolation dielectric layers 365a1 to 365a3 and 365b1 to 365b3 can also be other common dielectric materials, such as alumina, silicon oxide, silicon nitride, etc., which are not limited here.

[0178] For example, a first isolation dielectric layer 361a is further disposed between the fifth isolation dielectric layer 365a1 to 365a3 and the substrate 310, and a first isolation dielectric layer 361b is further disposed between the fifth isolation dielectric layer 365b1 to 365b3 and the substrate 310.

[0179] For example, the fifth isolation dielectric layers 365a1 to 365a3 of the CNT320 facing the substrate 310 are symmetrically arranged in the vertical direction, and the fifth isolation dielectric layers 365b1 to 365b3 of the CNT320 facing the substrate 310 are symmetrically arranged in the vertical direction, wherein the vertical direction is perpendicular to the substrate 310.

[0180] Understandably, in order to clearly demonstrate the structure of the CNTFET in the embodiments of this application, Figure 9 The illustration is given using the contact between end face S1a and surface S2a, and the contact between end face S1b and surface S2b of CNT320 in a CNTFET. In other embodiments of this application, it can also be combined with... Figure 3 The structure shown embeds end face S1a into the first electrode 330 and end face S1b into the second electrode 340, but the specific details are not limited here.

[0181] Furthermore, in order to clearly demonstrate the structure of the CNTFET in the embodiments of this application, Figure 9 The illustration takes the formation of CNT320 as a single-layer carbon nanotube layer in a CNTFET as an example. In other embodiments of this application, it can also be combined with... Figure 4A and Figure 4B The structure shown contains multiple layers of carbon nanotubes in the CNTFET, but the specific details are not limited here.

[0182] It is understood that the structure described in this embodiment can be applied to any CNTFET, that is, whether it is a P-type CNTFET or an N-type CNTFET. However, since the methods for controlling the type and concentration of charge carriers in CNT320 are different in P-type CNTFETs and N-type CNTFETs, examples are given below for each.

[0183] In a P-type CNTFET, within the same isolation dielectric structure 360a, the work function of the fifth isolation dielectric layers 365a1 to 365a3 is less than the work function of the first isolation dielectric layer 361a. Furthermore, within the same isolation dielectric structure 360b, the work function of the fifth isolation dielectric layers 365b1 to 365b3 is less than the work function of the first isolation dielectric layer 361b.

[0184] For example, in a P-type CNTFET, the work function of the fifth isolation dielectric layers 365a1 to 365a3 in the same isolation dielectric structure 360a can be increased or decreased sequentially. Furthermore, in the same isolation dielectric structure 360b, the work function of the fifth isolation dielectric layers 365b1 to 365b3 can be increased or decreased sequentially.

[0185] For example, in a P-type CNTFET, in two isolation dielectric structures, the work function of the fifth isolation dielectric layer, which is at the same distance from CNT320 in the order, is the same. For example, refer to... Figure 9 The fifth isolation dielectric layers 365a1 and 365b1 have the same distance from CNT320 and therefore the same work function. The fifth isolation dielectric layers 365a2 and 365b2 also have the same distance from CNT320 and therefore the same work function. The fifth isolation dielectric layers 365a3 and 365b3 also have the same distance from CNT320 and therefore the same work function.

[0186] In an N-type CNTFET, within the same isolation dielectric structure 360a, the concentration of positive charge from defects in the fifth isolation dielectric layers 365a1 to 365a3 is less than the concentration of positive charge from defects in the first isolation dielectric layer 361a. Furthermore, within the same isolation dielectric structure 360b, the concentration of positive charge from defects in the fifth isolation dielectric layers 365b1 to 365b3 is less than the concentration of positive charge from defects in the first isolation dielectric layer 361b.

[0187] For example, in an N-type CNTFET, within the same isolation dielectric structure 360a, the concentration of positive charge of defects in the fifth isolation dielectric layers 365a1 to 365a3 can sequentially increase or decrease. Furthermore, within the same isolation dielectric structure 360b, the concentration of positive charge of defects in the fifth isolation dielectric layers 365b1 to 365b3 can sequentially increase or decrease.

[0188] For example, in an N-type CNTFET, in two isolation dielectric structures, the concentration of positive charge on defects in the fifth isolation dielectric layer, which is at the same distance from the CNT320 order, is the same. For example, refer to... Figure 9 The fifth insulating dielectric layers 365a1 and 365b1 have the same distance from CNT320, and their defects have the same concentration of positive charge. The fifth insulating dielectric layers 365a2 and 365b2 have the same distance from CNT320, and their defects have the same concentration of positive charge. The fifth insulating dielectric layers 365a3 and 365b3 have the same distance from CNT320, and their defects have the same concentration of positive charge.

[0189] Figure 10 This is another schematic diagram of the chip structure in the embodiments of this application, referring to... Figure 10 This embodiment is for Figure 9 The embodiments shown have been modified, and the similarities will not be repeated here. The differences will be explained below.

[0190] For example, refer to Figure 10 The isolation dielectric structure 360a also includes a fourth isolation dielectric layer 364a, which is located between the first isolation dielectric layer 361a and the CNT 320. Furthermore, the relative permittivity of the fourth isolation dielectric layer 364a is lower than that of the first isolation dielectric layer 361a. Therefore, not only can the gate 351 and the first electrode 330 be electrically isolated, but the parasitic capacitance between the gate 351 and the first electrode 330 can also be reduced.

[0191] Furthermore, the isolation dielectric structure 360b also includes a fourth isolation dielectric layer 364b, which is located between the first isolation dielectric layer 361b and the CNT 320. The relative permittivity of the fourth isolation dielectric layer 364b is lower than that of the first isolation dielectric layer 361b. Therefore, not only can the gate 351 and the second electrode 340 be electrically isolated, but the parasitic capacitance between the gate 351 and the second electrode 340 can also be reduced.

[0192] For example, the relative permittivity of the fourth isolation dielectric layers 364a and 364b is no greater than 4, further reducing parasitic capacitance. For instance, the relative permittivity of the fourth isolation dielectric layers 364a and 364b can be 4, 3.9, 3.8, 3.7, 3.6, 3.5, 3.4, 3.3, etc., and is not limited here. Furthermore, the relative permittivity of the fourth isolation dielectric layers 364a and 364b is not limited to a value no greater than 4, and can be flexibly adjusted and controlled according to the design requirements of the actual application scenario, and is not limited here.

[0193] For example, in any CNTFET, each isolation dielectric structure includes multiple fourth isolation dielectric layers. Within the same isolation dielectric structure, the relative permittivity of the fourth isolation dielectric layer farther from CNT320 is either larger or smaller. This allows the relative permittivity of the fourth isolation dielectric layers within the same isolation dielectric structure to be set in a gradient form, meeting the design requirements for relative permittivity in some application scenarios. For example, in any CNTFET, in two isolation dielectric structures, the relative permittivity of the fourth isolation dielectric layers with the same order from CNT320 is the same.

[0194] For example, a fourth isolation dielectric layer 364a is further disposed between the first isolation dielectric layer 361a and the substrate 310, and a fourth isolation dielectric layer 364b is further disposed between the first isolation dielectric layer 361b and the substrate 310.

[0195] For example, the fourth isolation dielectric layers 364a and 364b are made of the same material, and can be formed in the same process, which reduces the difficulty of material selection, reduces process steps, and reduces costs.

[0196] In addition, the isolation medium structure 360a also includes a fifth isolation medium layer 365a1 to 365a2, and the isolation medium structure 360b also includes a fifth isolation medium layer 365b1 to 365b2. For the implementation of the fifth isolation medium layers 365a1 to 365a2 and 365b1 to 365b2, please refer to the description in the above embodiments, and the specific details will not be repeated here.

[0197] It is understood that the structure described in this embodiment can be applied to any CNTFET, that is, whether it is a P-type CNTFET or an N-type CNTFET. However, since the methods for controlling the type and concentration of charge carriers in CNT320 are different in P-type CNTFETs and N-type CNTFETs, examples are given below for each.

[0198] In a P-type CNTFET, within the same isolation dielectric structure 360a, the work function of the fourth isolation dielectric layer 364a is less than the work function of the first isolation dielectric layer 361a. Furthermore, within the same isolation dielectric structure 360b, the work function of the fourth isolation dielectric layer 364b is less than the work function of the first isolation dielectric layer 361b. Exemplarily, in a P-type CNTFET, the work functions of the fourth isolation dielectric layers 364a and 364b are the same.

[0199] In an N-type CNTFET, within the same isolation dielectric structure 360a, the concentration of positive charge from defects in the fourth isolation dielectric layer 364a is less than the concentration of positive charge from defects in the first isolation dielectric layer 361a. Furthermore, within the same isolation dielectric structure 360b, the concentration of positive charge from defects in the fourth isolation dielectric layer 364b is less than the concentration of positive charge from defects in the first isolation dielectric layer 361b. Exemplarily, in an N-type CNTFET, the concentration of positive charge from defects in the fourth isolation dielectric layers 364a and 364b is the same.

[0200] Figure 11 This is another schematic diagram of the chip structure in the embodiments of this application, referring to... Figure 11 This embodiment is for Figure 9 The embodiments shown have been modified; their similarities will not be repeated here, but their differences will be explained below. For example, refer to... Figure 11 The isolation medium structure 360a includes a first isolation medium layer 361a and a fourth isolation medium layer 364a, but does not have a fifth isolation medium layer. Similarly, the isolation medium structure 360b includes a first isolation medium layer 361b and a fourth isolation medium layer 364b, but does not have a fifth isolation medium layer.

[0201] Figure 12 This is another schematic diagram of the chip structure in the embodiments of this application, referring to... Figure 12 This embodiment is for Figure 2 The embodiments shown have been modified; their similarities will not be repeated here, but their differences will be explained below. For example, refer to... Figure 12 The gate dielectric layer 352 can also be disposed between the isolation dielectric structure 360a and the first electrode 330, and the gate dielectric layer 352 can also be disposed between the isolation dielectric structure 360b and the second electrode 340. This further provides electrical isolation between the gate and the first electrode 330 and the second electrode 340.

[0202] For example, the gate dielectric layer 352 may also be disposed between the isolation dielectric structure 360a and the CNT 320, and the gate dielectric layer 352 may also be disposed between the isolation dielectric structure 360b and the CNT 320.

[0203] It is understood that the structure described in this embodiment can be applied to any CNTFET, that is, whether it is a P-type CNTFET or an N-type CNTFET, the structure described in this embodiment is applicable.

[0204] It is understood that any modifications to the structure described in this embodiment in conjunction with the structure shown in the above embodiments are all within the protection scope of this application.

[0205] The above description is only a specific implementation of this application, but the protection scope of this application is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the protection scope of this application.

Claims

1. A chip, characterized in that, include: A substrate and a plurality of carbon nanotube field-effect transistors (CNTFETs) located on the substrate; The CNTFET includes: a carbon nanotube, a first electrode, a second electrode, a gate, and two isolation dielectric structures; The carbon nanotubes extend along a first direction, and the first electrode and the second electrode are located at the two ends of the carbon nanotubes in the first direction, the first direction being parallel to the layer containing the substrate. The gate is located between the first electrode and the second electrode and surrounds part of the sidewall of the carbon nanotube. A gate dielectric layer is also disposed between the gate and the carbon nanotube. Of the two isolation dielectric structures, one isolation dielectric structure is located between the gate and the first electrode, and the other isolation dielectric structure is located between the gate and the second electrode; Each of the isolation medium structures includes a first isolation medium layer, which surrounds a portion of the sidewall of the carbon nanotube. The plurality of CNTFETs includes one or a combination of P-type CNTFETs and N-type CNTFETs; In the P-type CNTFET, the material of the first isolation dielectric layer is a first dielectric material, and the work function of the first dielectric material is not less than 6eV; In the N-type CNTFET, the material of the first isolation dielectric layer is a second dielectric material, and the second dielectric material has positively charged defects.

2. The chip according to claim 1, characterized in that, The carbon nanotube has a first end and a second end opposite to each other in the first direction. The first electrode is located at the first end of the carbon nanotube and covers the end face of the first end facing away from the second end. The second electrode is located at the second end of the carbon nanotube and covers the end face of the second end facing away from the first end.

3. The chip according to claim 2, characterized in that, The end face of the first end of the carbon nanotube facing away from the second end is in contact with the surface of the first electrode facing the gate, and the end face of the second end of the carbon nanotube facing away from the first end is in contact with the surface of the second electrode facing the gate; or, The first end of the carbon nanotube, facing away from the second end, is embedded in the first electrode, and the second end of the carbon nanotube, facing away from the first end, is embedded in the second electrode.

4. The chip according to any one of claims 1-3, characterized in that, The first dielectric material is a metal oxide.

5. The chip according to claim 4, characterized in that, The metal oxides include one or a combination of oxides of tungsten, vanadium, molybdenum, cobalt, and ruthenium.

6. The chip according to any one of claims 1-3, characterized in that, The second dielectric material includes one or a combination of aluminum oxide, silicon oxide, aluminum nitride, silicon nitride, aluminum oxynitride, and silicon oxynitride.

7. The chip according to claim 6, characterized in that, The chemical formula of the aluminum oxide is AlO x1 , 0 < x1 < 3 / 2; or, The chemical formula of the oxide of silicon is SiO x2 , 0 < x2 < 2; or, The chemical formula of the aluminum nitride is AlN x3 , 0 < x3 < 1; or, The chemical formula of the silicon nitride is SiN. x4 x4 > 4 / 3.

8. The chip according to any one of claims 1-7, characterized in that, Each of the isolation dielectric structures further includes a second isolation dielectric layer, wherein in the same isolation dielectric structure, the second isolation dielectric layer is located between the first isolation dielectric layer and the gate, and surrounds a portion of the sidewall of the carbon nanotube; In any of the CNTFETs, within the same isolation dielectric structure, the relative permittivity of the second isolation dielectric layer is less than the relative permittivity of the first isolation dielectric layer; or, In the P-type CNTFET, within the same isolation dielectric structure, the work function of the second isolation dielectric layer is less than the work function of the first isolation dielectric layer; or, In the N-type CNTFET, the material of the second isolation dielectric layer is a third dielectric material, and the third dielectric material has positively charged defects. In the same isolation dielectric structure, the concentration of positive charge of the defects in the second isolation dielectric layer is less than the concentration of positive charge of the defects in the first isolation dielectric layer.

9. The chip according to claim 8, characterized in that, The second isolation medium layer is in contact with the sidewall of the carbon nanotube; and / or, the second isolation medium layer is in contact with the substrate.

10. The chip according to claim 9, characterized in that, Each of the isolation medium structures includes a plurality of second isolation medium layers; In the P-type CNTFET, within the same isolation dielectric structure, the work function of the second isolation dielectric layer farther from the gate is larger; or... In the N-type CNTFET, within the same isolation dielectric structure, the concentration of positive charge of the defect is greater in the second isolation dielectric layer that is farther away from the gate.

11. The chip according to claim 8, characterized in that, In the same isolation medium structure, the first isolation medium layer is also located between the second isolation medium layer and the sidewall of the carbon nanotube; and / or, In the same isolation medium structure, the first isolation medium layer is also located between the second isolation medium layer and the substrate.

12. The chip according to claim 11, characterized in that, Each of the isolation dielectric structures includes a plurality of second isolation dielectric layers, the plurality of second isolation dielectric layers including an m-th second isolation dielectric layer and an (m+1)-th second isolation dielectric layer, the (m+1)-th second isolation dielectric layer being located between the m-th second isolation dielectric layer and the gate, where m is a positive integer; In the same isolation medium structure, the (m+1)th second isolation medium layer is further provided between the mth second isolation medium layer and the sidewall of the carbon nanotube; or, In the same isolation medium structure, the (m+1)th second isolation medium layer is further provided between the substrate and the mth second isolation medium layer.

13. The chip according to claim 12, characterized in that, In any CNTFET, within the same isolation dielectric structure, the relative permittivity of the m-th second isolation dielectric layer is greater than the relative permittivity of the (m+1)-th second isolation dielectric layer; or, In the P-type CNTFET, within the same isolation dielectric structure, the work function of the m-th second isolation dielectric layer is greater than the work function of the (m+1)-th second isolation dielectric layer; or, In the N-type CNTFET, within the same isolation dielectric structure, the concentration of the positive charge of the defect in the m-th second isolation dielectric layer is greater than the concentration of the positive charge of the defect in the (m+1)-th second isolation dielectric layer.

14. The chip according to any one of claims 11-13, characterized in that, Each of the isolation dielectric structures further includes a third isolation dielectric layer that surrounds a portion of the sidewall of the carbon nanotube. In the same isolation dielectric structure, the third isolation dielectric layer is located on the side of the first isolation dielectric layer facing away from the gate and between the first isolation dielectric layer and the sidewall of the carbon nanotube. In the P-type CNTFET, within the same isolation dielectric structure, the work function of the third isolation dielectric layer is less than the work function of the first isolation dielectric layer; or, In the N-type CNTFET, within the same isolation dielectric structure, the concentration of the positive charge of the defect in the third isolation dielectric layer is less than the concentration of the positive charge of the defect in the first isolation dielectric layer.

15. The chip according to any one of claims 1-7, characterized in that, Each of the isolation media structures further includes a fourth isolation media layer, wherein in the same isolation media structure, the fourth isolation media layer is located between the first isolation media layer and the carbon nanotube; The relative permittivity of the fourth isolation dielectric layer is less than that of the first isolation dielectric layer.

16. The chip according to any one of claims 1-7, 15, characterized in that, Each of the isolation medium structures further includes a fifth isolation medium layer, wherein in the same isolation medium structure, the fifth isolation medium layer surrounds the first isolation medium layer; The relative permittivity of the fifth isolation dielectric layer is less than that of the first isolation dielectric layer.

17. The chip according to claim 16, characterized in that, Each of the isolation dielectric structures includes multiple fifth isolation dielectric layers. Within the same isolation dielectric structure, the relative permittivity of the fifth isolation dielectric layer that is farther away from the carbon nanotube is smaller or larger.

18. The chip according to any one of claims 8-13, 15-17, characterized in that, The first isolation medium layer is in contact with the sidewall of the carbon nanotube; and / or, the first isolation medium layer is in contact with the substrate.

19. A semiconductor packaging structure, characterized in that, It includes a packaging substrate and a chip as described in any one of claims 1-18, wherein the chip is packaged on the packaging substrate.

20. An electronic device, characterized in that, include: The circuit board and the semiconductor package structure as described in claim 19, wherein the semiconductor package structure is disposed on the circuit board.

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