Method for manufacturing mother substrate and display device mother substrate

Abstract

This invention provides a method for manufacturing a mother substrate and a mother substrate for a display device. The method for manufacturing the mother substrate includes: forming a lower electrode in a display area; forming a rib layer covering a panel portion and a blank area; forming a first partition wall including a lower portion and an upper portion in the display area; forming a second partition wall including a lower portion and an upper portion in the blank area; forming a first laminated film including a first color organic layer and a first sealing layer covering the first laminated film in the panel portion and the blank area; performing an etching process to remove the first laminated film and the first sealing layer formed in the first laminated film and the first sealing layer formed in the panel portion and the blank area, except for the target area where the first color organic layer is disposed; in the target area of ​​the blank area, the portions of the first laminated film and the first sealing layer formed in the blank area, except for the first laminated film and the first sealing layer formed on the second partition wall and the first laminated film and the first sealing layer formed on the side of the second partition wall, are removed.

Description

[0001] This application is based on Japanese Patent Application 2025-019876 (filed on February 10, 2025), and enjoys priority based on that application. The entire contents of that application are incorporated herein by reference. Technical Field

[0002] The embodiments of the present invention relate to a method for manufacturing a mother substrate and a mother substrate for a display device. Background Technology

[0003] In recent years, display devices using organic light-emitting diodes (OLEDs) as display elements have become practical. During the manufacturing of such display devices, inspections are performed to verify that the elements on the substrate are formed according to the design. Technologies for performing this inspection efficiently or with high precision are needed. Summary of the Invention

[0004] One of the objectives of this invention is to provide a method for manufacturing a mother substrate capable of efficiently or with high precision performing inspections during the manufacturing of a display device, and a mother substrate for a display device.

[0005] In general, according to the embodiments, the method for manufacturing a mother substrate includes: preparing a substrate comprising a panel portion and a surrounding blank area, the panel portion comprising a display area and a surrounding peripheral area; forming a lower electrode in the display area; forming a rib layer covering the panel portion and the blank area; forming a first partition wall in the display area, the first partition wall comprising a lower portion and an upper portion having an end portion protruding from the side of the lower portion; forming a second partition wall comprising the lower portion and the upper portion in the blank area; and forming an organic layer comprising at least a first color in the panel portion and the blank area. The first laminated film and the first sealing layer covering the first laminated film; and an etching process is performed in which the first laminated film and the first sealing layer formed in the panel portion and the blank area are removed from the object area where the organic layer of the first color is disposed; and in the object area of ​​the blank area, the portion of the first laminated film and the first sealing layer formed in the blank area other than the first laminated film and the first sealing layer formed on the second partition wall and the first laminated film and the first sealing layer formed on the side of the second partition wall is removed.

[0006] Furthermore, according to an embodiment, the mother substrate for a display device includes: a plurality of panel portions, each including a display area and a peripheral area surrounding the display area; a blank area surrounding the plurality of panel portions; a lower electrode disposed in the display area; a rib layer disposed in the plurality of panel portions and the blank area; a first partition wall disposed in the display area; a first laminated film including an organic layer of a first color, disposed in the first area respectively included in the plurality of panel portions and the blank area; a first sealing layer covering the first laminated film; a second laminated film including an organic layer of a second color, disposed in the second area respectively included in the plurality of panel portions and the blank area; a second sealing layer covering the second laminated film; and a plurality of second partition walls, respectively disposed in the first area and the second area included in the blank area. The first partition wall and the second partition wall each include a lower portion and an upper portion having an end portion protruding from the side of the lower portion. The first laminated film is disposed on the upper portion of the second partition wall disposed in the first area. A first sealing layer, bonded to the second partition wall, is disposed around the second partition wall in the first region. A second laminated film is disposed on top of the second partition wall in the second region. A second sealing layer, bonded to the second partition wall, is disposed around the second partition wall in the second region.

[0007] Furthermore, according to an embodiment, the mother substrate for a display device includes: a plurality of panel portions each including a display area and a peripheral area surrounding the display area; a blank area surrounding the plurality of panel portions; a lower electrode disposed in the display area; a rib layer disposed in the plurality of panel portions and the blank area; a first partition wall disposed in the display area; a first laminated film including an organic layer of a first color disposed in the first area respectively included in the plurality of panel portions and the blank area; a first sealing layer covering the first laminated film; a second laminated film including an organic layer of a second color disposed in the second area respectively included in the plurality of panel portions and the blank area; a second sealing layer covering the second laminated film; and a plurality of second partition walls respectively disposed at positions overlapping with the first area and the second area included in the blank area when viewed from above. The first partition wall and the second partition wall each include a lower portion and an upper portion having an end portion protruding from the side of the lower portion. The second partition wall has an opening in the center. The first laminated film is disposed in an opening in the second partition wall at a location overlapping the first region. A first sealing layer, bonded to the second partition wall, is disposed around the opening in the second partition wall at a location overlapping the first region. The second laminated film is disposed in an opening in the second partition wall at a location overlapping the second region. A second sealing layer, bonded to the second partition wall, is disposed around the opening in the second partition wall at a location overlapping the second region. Attached Figure Description

[0008] Figure 1 This is a diagram illustrating an example configuration of a display device according to one embodiment.

[0009] Figure 2 A schematic top view of an example of a layout that generates subpixels.

[0010] Figure 3 It is along Figure 2 A schematic cross-sectional view of the display panel along line III-III.

[0011] Figure 4 This is a schematic top view of the mother substrate in one embodiment.

[0012] Figure 5 This is a schematic top view of a portion of the mother substrate in one embodiment.

[0013] Figure 6 This is a schematic top view illustrating an example of the configuration of a test pattern applicable to one embodiment.

[0014] Figure 7 It is along Figure 6 A schematic cross-sectional view of the mother substrate along line VII-VII.

[0015] Figure 8A This is a schematic top view illustrating an example of the configuration of a test pattern applicable to one embodiment.

[0016] Figure 8B This is a schematic top view illustrating an example of the configuration of a test pattern applicable to one embodiment.

[0017] Figure 9 This is a schematic top view illustrating an example of the configuration of a test pattern applicable to one embodiment.

[0018] Figure 10 It is along Figure 9 A schematic cross-sectional view of the mother substrate of the XX line.

[0019] Figure 11 This is a schematic top view illustrating an example of the configuration of a test pattern applicable to one embodiment.

[0020] Figure 12 This is a schematic top view illustrating an example of the configuration of a test pattern applicable to one embodiment.

[0021] Figure 13 It is along Figure 12 A schematic cross-sectional view of the mother substrate along line XIII-XIII.

[0022] Figure 14 This is a schematic top view illustrating an example of the configuration of a test pattern applicable to one embodiment.

[0023] Figure 15 This is a schematic top view illustrating an example of the configuration of a test pattern applicable to one embodiment.

[0024] Figure 16 It is along Figure 15 A schematic cross-sectional view of the mother substrate of the XVI-XVI line.

[0025] Figure 17 This is a schematic top view illustrating an example of the configuration of a test pattern applicable to one embodiment.

[0026] Figure 18 This is a flowchart illustrating an example of a method for manufacturing a display device according to one embodiment.

[0027] Figure 19A This is a schematic cross-sectional view showing the process of forming a panel portion on a mother substrate in one embodiment.

[0028] Figure 19B It shows the next step. Figure 19A A rough cross-sectional view of the process.

[0029] Figure 19C It shows the next step. Figure 19B A rough cross-sectional view of the process.

[0030] Figure 19D It shows the next step. Figure 19C A rough cross-sectional view of the process.

[0031] Figure 19E It shows the next step. Figure 19D A rough cross-sectional view of the process.

[0032] Figure 19F It shows the next step. Figure 19E A rough cross-sectional view of the process.

[0033] Figure 19G It shows the next step. Figure 19F A rough cross-sectional view of the process.

[0034] Figure 19H It shows the next step. Figure 19G A rough cross-sectional view of the process.

[0035] Figure 19I It shows the next step. Figure 19H A rough cross-sectional view of the process.

[0036] Figure 19J It shows the next step. Figure 19I A rough cross-sectional view of the process.

[0037] Figure 20A This is a schematic cross-sectional view showing the process of removing the rib layer in the terminal section.

[0038] Figure 20B It shows the next step. Figure 20A A rough cross-sectional view of the process.

[0039] Figure 21A This is a schematic cross-sectional view illustrating one embodiment of the process of forming elements constituting a display element in a test pattern.

[0040] Figure 21B It shows the next step. Figure 21A A rough cross-sectional view of the process.

[0041] Figure 21C It shows the next step. Figure 21B A rough cross-sectional view of the process.

[0042] Figure 21D It shows the next step. Figure 21C A rough cross-sectional view of the process.

[0043] Figure 22AThis is a schematic cross-sectional view illustrating an example of the measurement process of one embodiment.

[0044] Figure 22B This is a schematic cross-sectional view illustrating an example of the measurement process of one embodiment.

[0045] Figure 22C This is a schematic cross-sectional view illustrating an example of the measurement process of one embodiment.

[0046] Figure 22D This is a schematic cross-sectional view illustrating an example of the measurement process of one embodiment. Detailed Implementation

[0047] Several embodiments are described with reference to the accompanying drawings.

[0048] The disclosure is merely one example, and appropriate modifications that can be readily conceived by those skilled in the art while maintaining the spirit of the invention are naturally included within the scope of this invention. Furthermore, to make the description clearer, the width, thickness, shape, etc., of various parts in the drawings are sometimes shown schematically compared to the actual form, but this is merely an example and not a limitation on the interpretation of the invention. Additionally, in this specification and the figures, components that perform the same or similar function as the components previously described with respect to the existing figures are labeled with the same reference numerals, and sometimes repeated detailed descriptions are appropriately omitted.

[0049] It should be noted that, for ease of understanding, the accompanying diagrams show the mutually orthogonal X-axis, Y-axis, and Z-axis. The direction along the X-axis is called the X-direction, the direction along the Y-axis is called the Y-direction, and the direction along the Z-axis is called the Z-direction. The Z-direction is the normal direction of the plane that includes the X and Y directions. Furthermore, observing various elements parallel to the Z-direction is called a top-down view.

[0050] The display device in each embodiment is an organic electroluminescent display device that uses organic light-emitting diodes (OLEDs) as display elements, and can be mounted on various electronic devices such as televisions, personal computers, in-vehicle devices, tablet computers, smartphones, mobile phone terminals, and wearable terminals.

[0051] Figure 1 This diagram illustrates a configuration example of a display device DSP according to one embodiment. The display device DSP includes a display panel PNL comprising an insulating substrate 10. The display panel PNL has a display area DA for displaying an image and a peripheral area SA surrounding the display area DA. The substrate 10 may be glass or a flexible resin film.

[0052] In this embodiment, the substrate 10 is rectangular when viewed from above. However, the shape of the substrate 10 when viewed from above is not limited to a rectangle, and may also be other shapes such as a square, a circle, or an ellipse.

[0053] The display area DA has a plurality of pixels PX arranged in a matrix in the X and Y directions. Each pixel PX contains a plurality of sub-pixels SP that display different colors. In this embodiment, it is envisioned that the pixel PX contains a blue sub-pixel SP1, a green sub-pixel SP2, and a red sub-pixel SP3. However, the pixel PX may also contain sub-pixels SP of other colors, such as white, which may be present along with or replace any of the sub-pixels SP1, SP2, and SP3.

[0054] The sub-pixel SP includes a pixel circuit 1 and a display element DE driven by the pixel circuit 1. The pixel circuit 1 includes a pixel switch 2, a driving transistor 3, and a capacitor 4. The pixel switch 2 and the driving transistor 3 are switching elements, for example, made of thin-film transistors.

[0055] The display area DA is configured with multiple scan lines GL that supply scan signals to the pixel circuit 1 of each sub-pixel SP, multiple signal lines SL that supply image signals to the pixel circuit 1 of each sub-pixel SP, and multiple power lines PL. Figure 1 In the example, the scan line GL and the power line PL extend along the X direction, and the signal line SL extends along the Y direction.

[0056] The gate electrode of pixel switch 2 is connected to scan line GL. One of the source and drain electrodes of pixel switch 2 is connected to signal line SL, and the other is connected to the gate electrode of driving transistor 3 and capacitor 4. In driving transistor 3, one of the source and drain electrodes is connected to power line PL and capacitor 4, and the other is connected to display element DE.

[0057] It should be noted that the configuration of pixel circuit 1 is not limited to the example shown in the figure. For example, pixel circuit 1 may also have more thin-film transistors and capacitors.

[0058] The display device DSP also includes a terminal section T disposed in the peripheral area SA. The terminal section T is connected, for example, to a flexible circuit board. Signals or voltages for driving the pixel circuit 1 are input to the display device DSP via the flexible circuit board and the terminal section T.

[0059] Figure 2 This is a schematic top view showing an example of the layout of subpixels SP1, SP2, and SP3. Figure 2 In the example, subpixels SP2 and SP3 are arranged in the X direction along with subpixel SP1. Furthermore, subpixels SP2 and SP3 are arranged in the Y direction.

[0060] With sub-pixels SP1, SP2, and SP3 arranged in this layout, the display area DA contains columns of sub-pixels SP2 and SP3 arranged alternately in the Y direction, and multiple columns of sub-pixels SP1 arranged repeatedly in the Y direction. These columns are arranged alternately in the X direction. It should be noted that the layout of sub-pixels SP1, SP2, and SP3 is not limited to this. Figure 2 Examples.

[0061] A rib layer 5 is configured in the display area DA. Rib layer 5 has pixel openings AP1, AP2, and AP3 in sub-pixels SP1, SP2, and SP3, respectively. Figure 2 In the example, pixel aperture AP1 is larger than pixel aperture AP2, and pixel aperture AP2 is larger than pixel aperture AP3. That is, among sub-pixels SP1, SP2, and SP3, sub-pixel SP1 has the largest aperture ratio, and sub-pixel SP3 has the smallest aperture ratio.

[0062] Sub-pixel SP1 has a lower electrode LE1, an upper electrode UE1, and an organic layer OR1 that overlap with pixel opening AP1. Sub-pixel SP2 has a lower electrode LE2, an upper electrode UE2, and an organic layer OR2 that overlap with pixel opening AP2. Sub-pixel SP3 has a lower electrode LE3, an upper electrode UE3, and an organic layer OR3 that overlap with pixel opening AP3.

[0063] The portion of the lower electrode LE1, the upper electrode UE1, and the portion of the organic layer OR1 overlapping with the pixel opening AP1 constitutes the display element DE1 of sub-pixel SP1. The portion of the lower electrode LE2, the upper electrode UE2, and the portion of the organic layer OR2 overlapping with the pixel opening AP2 constitutes the display element DE2 of sub-pixel SP2. The portion of the lower electrode LE3, the upper electrode UE3, and the portion of the organic layer OR3 overlapping with the pixel opening AP3 constitutes the display element DE3 of sub-pixel SP3. Display elements DE1, DE2, and DE3 may also include a capping layer described later. Rib layer 5 surrounds each of these display elements DE1, DE2, and DE3.

[0064] A conductive partition 6 (first partition) is disposed above the rib layer 5. The partition 6 serves as a wiring to supply a common voltage to the upward electrodes UE1, UE2, and UE3. The partition 6 overlaps the rib layer 5 entirely and has the same planar shape as the rib layer 5.

[0065] Specifically, partition 6 has partition opening 601 in sub-pixel SP1, partition opening 602 in sub-pixel SP2, and partition opening 603 in sub-pixel SP3. Partition openings 601, 602, and 603 are larger than pixel openings AP1, AP2, and AP3, respectively. Partition openings 601, 602, and 603 overlap with the entire display elements DE1, DE2, and DE3, respectively. That is, partition 6 surrounds display elements DE1, DE2, and DE3.

[0066] Figure 3 It is along Figure 2 A schematic cross-sectional view of the display panel PNL with line III-III. A circuit layer 11 (conductive layer) is disposed on the substrate 10 described above. The circuit layer 11 includes... Figure 1 The diagram shows various circuits and wiring, including pixel circuit 1, scan line GL, signal line SL, and power line PL. Circuit layer 11 is covered by organic insulating layer 12. Organic insulating layer 12 functions as a planarization film to flatten the unevenness generated by circuit layer 11.

[0067] Lower electrodes LE1, LE2, and LE3 are disposed on the organic insulating layer 12. Rib layer 5 is disposed on the organic insulating layer 12 and the lower electrodes LE1, LE2, and LE3. The ends of the lower electrodes LE1, LE2, and LE3 are covered by rib layer 5. Figure 3 The cross-section is not shown. The lower electrodes LE1, LE2, and LE3 are connected to the pixel circuit 1 of the circuit layer 11 through contact holes provided in the organic insulating layer 12.

[0068] The partition 6 includes a conductive lower portion 61 disposed on the rib layer 5 and an upper portion 62 disposed on the lower portion 61. The upper portion 62 has a wider width than the lower portion 61. As a result, both ends of the upper portion 62 protrude beyond the sides of the lower portion 61. This shape of the partition 6 is also referred to as a cantilever shape.

[0069] exist Figure 3 In this example, the lower part 61 includes a bottom layer 63 disposed above the rib layer 5 and a shaft layer 64 disposed above the bottom layer 63. For example, the bottom layer 63 is formed thinner than the shaft layer 64. Additionally, in Figure 3 In the example, the two ends of the bottom layer 63 protrude from the sides of the shaft layer 64.

[0070] In addition, Figure 3 In this example, the upper part 62 includes a first top layer 65 and a second top layer 66 disposed above the first top layer 65. For example, the width of the second top layer 66 is slightly smaller than the width of the first top layer 65. However, it is not limited to this; the first top layer 65 and the second top layer 66 may also have the same width.

[0071] Organic layer OR1 covers lower electrode LE1 through pixel opening AP1. Upper electrode UE1 covers organic layer OR1 and is opposite to lower electrode LE1. Organic layer OR2 covers lower electrode LE2 through pixel opening AP2. Upper electrode UE2 covers organic layer OR2 and is opposite to lower electrode LE2. Organic layer OR3 covers lower electrode LE3 through pixel opening AP3. Upper electrode UE3 covers organic layer OR3 and is opposite to lower electrode LE3. Upper electrodes UE1, UE2, and UE3 are in contact with the lower part 61 of partition 6.

[0072] Display element DE1 includes a capping layer CP1 covering the upper electrode UE1. Display element DE2 includes a capping layer CP2 covering the upper electrode UE2. Display element DE3 includes a capping layer CP3 covering the upper electrode UE3. Capping layers CP1, CP2, and CP3 respectively serve as optical adjustment layers to improve the light extraction efficiency emitted by organic layers OR1, OR2, and OR3.

[0073] In the following description, the multilayer containing organic layer OR1, upper electrode UE1 and capping layer CP1 is referred to as laminated film FL1, the multilayer containing organic layer OR2, upper electrode UE2 and capping layer CP2 is referred to as laminated film FL2, and the multilayer containing organic layer OR3, upper electrode UE3 and capping layer CP3 is referred to as laminated film FL3.

[0074] Subpixels SP1, SP2, and SP3 are respectively equipped with sealing layers SE11, SE12, and SE13. Sealing layer SE11 continuously covers the stacked film FL1 and the partition wall 6 surrounding subpixel SP1. Sealing layer SE12 continuously covers the stacked film FL2 and the partition wall 6 surrounding subpixel SP2. Sealing layer SE13 continuously covers the stacked film FL3 and the partition wall 6 surrounding subpixel SP3.

[0075] exist Figure 3 In the example, the sealing layer SE11 on the partition 6 between sub-pixels SP1 and SP2 is separated from the sealing layer SE12 on the same partition 6. Additionally, the sealing layer SE11 on the partition 6 between sub-pixels SP1 and SP3 is separated from the sealing layer SE13 on the same partition 6. As another example, the ends of sealing layer SE11 and SE12 may overlap on the partition 6. Similarly, the ends of sealing layer SE11 and SE13 may overlap on the partition 6.

[0076] Sealing layers SE11, SE12, and SE13 are covered by resin layer RS1. Resin layer RS1 is covered by sealing layer SE2. Sealing layer SE2 is covered by resin layer RS2. Resin layers RS1, RS2, and sealing layer SE2 are continuously disposed throughout the entire display area DA, and a portion of them also extends to the peripheral area SA.

[0077] Polarizing films, touch panels, protective films, or cover glass can also be further disposed above the resin layer RS2. Such cover components can also be bonded to the resin layer RS2, for example, using an adhesive layer such as OCA (Optical Clear Adhesive).

[0078] The organic insulating layer 12 is formed of an organic insulating material such as polyimide. The rib layer 5 and the sealing layers SE11, SE12, SE13, and SE2 are formed of inorganic insulating materials such as silicon nitride (SiNx), silicon oxide (SiOx), or silicon oxynitride (SiON). In one example, the rib layer 5 is formed of silicon oxynitride, and the sealing layers SE11, SE12, SE13, and SE2 are formed of silicon nitride. The resin layers RS1 and RS2 are formed, for example, of resin materials (organic insulating materials) such as epoxy resin or acrylic resin.

[0079] The lower electrodes LE1, LE2, and LE3 have, for example, a reflective layer formed of silver and a pair of conductive oxide layers covering the upper and lower surfaces of the reflective layer, respectively. Each conductive oxide layer can be formed, for example, a transparent conductive oxide such as ITO (Indium Tin Oxide), IZO (Indium Zinc Oxide), or IGZO (Indium Gallium Zinc Oxide).

[0080] The upper electrodes UE1, UE2, and UE3 are formed, for example, of a metallic material such as an alloy of magnesium and silver (MgAg). For example, the lower electrodes LE1, LE2, and LE3 correspond to the positive electrode, and the upper electrodes UE1, UE2, and UE3 correspond to the negative electrode.

[0081] Organic layers OR1, OR2, and OR3 are composed of multiple thin films including light-emitting layers. In one example, organic layers OR1, OR2, and OR3 have a structure in which a hole injection layer, a hole transport layer, an electron blocking layer, a light-emitting layer, a hole blocking layer, an electron transport layer, and an electron injection layer are sequentially stacked in the Z direction. However, organic layers OR1, OR2, and OR3 may also have other structures, such as a so-called tandem structure containing multiple light-emitting layers.

[0082] The capping layers CP1, CP2, and CP3, for example, have a stacked structure with multiple overlapping transparent layers. These transparent layers can include layers formed of inorganic materials and layers formed of organic materials. Furthermore, these transparent layers have different refractive indices. For example, the refractive indices of these transparent layers differ from the refractive indices of the upper electrodes UE1, UE2, and UE3, and the refractive indices of the sealing layers SE11, SE12, and SE13. It should be noted that at least one of the capping layers CP1, CP2, and CP3 may be omitted.

[0083] The bottom layer 63 and the axial layer 64 of the lower part 64 of the partition 6 are formed of, for example, metallic materials. For example, molybdenum, titanium, titanium nitride (TiN), molybdenum-tungsten alloy (MoW), or molybdenum-niobium alloy (MoNb) can be used as the metallic material for the bottom layer 63. For example, aluminum, aluminum-neodymium alloy (AlNd), aluminum-yttrium alloy (AlY), or aluminum-silicon alloy (AlSi) can be used as the metallic material for the axial layer 64. It should be noted that the axial layer 64 can also be formed of an insulating material. Furthermore, the lower part 64 can also be formed of a single layer.

[0084] The first top layer 65 of the partition 6 is formed, for example, of a metallic material. The second top layer 66 of the partition 6 is formed, for example, of a conductive oxide. As the metallic material forming the first top layer 65, titanium, titanium nitride, molybdenum, tungsten, a molybdenum-tungsten alloy, or a molybdenum-niobium alloy can be used, for example. As the conductive oxide forming the second top layer 66, ITO or IZO can be used, for example. It should be noted that the upper part 62 may have three or more layers, or it may be formed from a single layer. Furthermore, the upper part 62 may also include a layer formed of an insulating material.

[0085] A common voltage is supplied to the adjacent 6. This common voltage is supplied to the upper electrodes UE1, UE2, and UE3, which are in contact with the lower part 61. The pixel circuits 1 of the sub-pixels SP1, SP2, and SP3 respectively supply the pixel voltages corresponding to the image signals of the signal line SL to the lower electrodes LE1, LE2, and LE3.

[0086] Organic layers OR1, OR2, and OR3 emit light in response to the application of voltage. Specifically, when a potential difference is established between the lower electrode LE1 and the upper electrode UE1, the light-emitting layer of organic layer OR1 emits light in the blue wavelength range. When a potential difference is established between the lower electrode LE2 and the upper electrode UE2, the light-emitting layer of organic layer OR2 emits light in the green wavelength range. When a potential difference is established between the lower electrode LE3 and the upper electrode UE3, the light-emitting layer of organic layer OR3 emits light in the red wavelength range.

[0087] As another example, the light-emitting layers of organic layers OR1, OR2, and OR3 can also emit light of the same color (e.g., white). In this case, the display device DSP can also include a color filter that converts the light emitted by the light-emitting layers into light corresponding to the colors of sub-pixels SP1, SP2, and SP3. Alternatively, the display device DSP can also include a layer containing quantum dots that generate light of the colors corresponding to the colors of sub-pixels SP1, SP2, and SP3 when excited by the light emitted by the light-emitting layers.

[0088] In manufacturing a display device DSP, a large mother substrate is made, each having multiple regions (panel sections) corresponding to the display panel PNL. The following describes the configuration applicable to this mother substrate.

[0089] Figure 4 This is a schematic top view of the mother substrate MB (mother substrate for display device) in this embodiment. The mother substrate MB is rectangular, as shown in the figure, but it can also be other shapes such as circles.

[0090] The mother substrate MB has multiple panel portions PP arranged in a matrix and surrounding blank areas BA of these panel portions PP. Figure 4 In the example, the panel portions PP are arranged with a blank area BA between them in the X and Y directions. However, at least two of the multiple panel portions PP of the mother substrate MB can also be adjacent to each other without being separated by a blank area BA.

[0091] The mother substrate (MB) also has at least one test pattern (TEG). Figure 4 In the example, multiple test pattern TEGs are arranged in the blank area BA. The arrangement position and number of these test pattern TEGs are not particularly limited, but in one example, it is preferred that the test pattern TEGs are distributed in various places such as near the end and center of the mother substrate MB.

[0092] Figure 5 This is a schematic top view of a portion of the mother substrate MB. The focus of this view is on a panel portion PP. The shape of the panel portion PP corresponds to the cutting line CL1 used to cut the panel portion PP from the mother substrate MB.

[0093] Each panel PP has the aforementioned display area DA and peripheral area SA. Furthermore, the peripheral area SA includes an inspection area TA. The inspection area TA contains inspection pads and the like for inspecting the operation of the display panel PNL.

[0094] A cutting line CL2 is formed on each panel portion PP. The panel portion PP is divided into a portion containing the display area DA and a portion containing the inspection area TA by the cutting line CL2.

[0095] When manufacturing the display device DSP, the panel portion PP is first cut from the mother substrate MB along the cutting line CL1. Furthermore, the cut panel portion PP is inspected using the aforementioned inspection pads. After this inspection, the inspection area TA is removed from the panel portion PP along the cutting line CL2.

[0096] Figure 4 The test pattern TEG shown can be configured not only in the blank area BA, but also in the surrounding area SA. For example, the test pattern TEG can be configured in the inspection area TA. In this case, no test pattern TEG remains on the panel portion PP after the inspection area TA is cut off along the cutting line CL2. Figure 4 As shown, when the test pattern TEG is configured in the blank area BA, no test pattern TEG remains on the panel PP after the inspection area TA is cut off along the cutting line CL2.

[0097] As another example, the test pattern TEG can also be configured in the peripheral area SA, excluding the inspection area TA. In this case, the test pattern TEG remains in the panel portion PP after the inspection area TA has been removed along the cutting line CL2.

[0098] Figure 6 This is a schematic top view showing an example of the configuration that can be applied to the test pattern TEG. Figure 7 It is along Figure 6 A schematic cross-sectional view of the mother substrate MB containing the test pattern TEG along lines VII-VII. Figure 7 In the text, elements below the organic insulating layer 12 are omitted. Figure 6 and Figure 7 The configuration shown is, for example, a configuration that can be applied in the test pattern TEG used to confirm the misalignment of the partition 6 and the elements constituting the display element DE.

[0099] like Figure 6 As shown, the test pattern TEG consists of rib layer 5, septum 7A (third septum) and multiple septum 7B (second septum, protrusion).

[0100] Rib layer 5 is configured in Figure 4 Within the area of ​​the panel portion PP and the remaining white area BA shown.

[0101] Adjacent partition 7A is positioned within the remaining blank area BA. Like adjacent partition 6, partition 7A extends along both the X and Y directions, forming a grid pattern. Figure 6 In the example, partition 7A has partition openings 701, 702, and 703. For example, the shape and layout of partition openings 701, 702, and 703 are similar to... Figure 2 The partition openings 601, 602, and 603 shown have the same shape and layout. That is, partition opening 701 is the partition opening corresponding to sub-pixel SP1, partition opening 702 is the partition opening corresponding to sub-pixel SP2, and partition opening 703 is the partition opening corresponding to sub-pixel SP3.

[0102] The partition 7B (see below), surrounded by the partition opening 701, and the area overlapping with the partition opening 701 when viewed from above, are the areas for arranging elements constituting display element DE1 (object area, first area). The partition 7B (see below), surrounded by the partition opening 702, and the area overlapping with the partition opening 702 when viewed from above, are the areas for arranging elements constituting display element DE2 (object area, second area). The partition 7B (see below), surrounded by the partition opening 703, and the area overlapping with the partition opening 703 when viewed from above, are the areas for arranging elements constituting display element DE3 (object area).

[0103] It should be noted that the shape and layout of the partition openings 701, 702, and 703 shown here are similar to those shown in the original text. Figure 2 The partition openings 601, 602, and 603 shown are identical in shape and layout, but partition 7A, for example, Figure 8A As shown, it may also have one or more partition openings with shapes different from partition openings 601, 602, and 603. Figure 8A In the example shown below, in addition to the partition openings 701, 702, and 703 corresponding to sub-pixels SP1, SP2, and SP3, partition 7A also has a partition opening 704 corresponding to sub-pixels SP of other colors such as white, and the partition openings 701, 702, 703, and 704 are square in shape.

[0104] In addition, such as Figure 8B As shown, it can also be constructed as follows: It is equipped with multiple partitions 7A, the shape and layout of which are respectively similar to... Figure 2 The partition openings 601, 602, and 603 shown have the same shape and layout, and the partition 7A has partition openings 701', 702', and 703' respectively.

[0105] exist Figure 6 In the example, multiple partitions 7B are respectively arranged in the center of partition openings 701, 702, and 703, and are surrounded by partition openings 701, 702, and 703. Here, the case where the length of each side of partition 7B is less than the width of partition 7A is shown, but the length of each side of partition 7B can also be the same as the width of partition 7A.

[0106] like Figure 6 and Figure 7 As shown, partitions 7A and 7B, like partition 6, each comprise lower parts 71A and 71B (bottom layers 73A and 73B and axial layers 74A and 74B) and upper parts 72A and 72B (first top layer 75A and 75B and second top layer 76A and 76B). Furthermore, like partition 6, the bottom layers 73A and 73B of partitions 7A and 7B protrude from the sides of axial layers 74A and 74B.

[0107] The lower portions 71A and 71B of partitions 7A and 7B are formed of the same material as the lower portion 61 of partition 6. Specifically, the bottom layers 73A and 73B and the axial layers 74A and 74B are formed of the same material as the bottom layer 63 and axial layer 64 of partition 6, respectively. The thickness of the bottom layers 73A and 73B is the same as the thickness of the bottom layer 63 of partition 6. In addition, the thickness of the axial layers 74A and 74B is the same as the thickness of the axial layer 64 of partition 6.

[0108] The upper portions 72A and 72B of partitions 7A and 7B are formed of the same material as the upper portion 62 of partition 6. Specifically, the first top layer 75A and 75B and the second top layer 76A and 76B are formed of the same material as the first top layer 65 and the second top layer 66 of partition 6, respectively. The thickness of the first top layer 75A and 75B is the same as the thickness of the first top layer 65 of partition 6. In addition, the thickness of the second top layer 76A and 76B is the same as the thickness of the second top layer 66 of partition 6.

[0109] Figure 9 This is a schematic top view showing other examples of the configuration that can be applied to the test pattern TEG. Figure 10 It is along Figure 9 A schematic cross-sectional view of the mother substrate MB containing the test pattern TEG along the XX line. Figure 10 In the text, elements below the organic insulating layer 12 are omitted. Figure 9 and Figure 10 The structure shown is Figure 6 and Figure 7 Similarly, the configuration shown is, for example, a configuration that can be applied in the test pattern TEG used to confirm the misalignment of the partition 6 and the elements constituting the display element DE.

[0110] like Figure 9 As shown, the test pattern TEG consists of rib layer 5 and multiple septa 7C (second septa).

[0111] Rib layer 5 is configured in Figure 4 Within the area of ​​the panel portion PP and the remaining white area BA shown.

[0112] Multiple adjacent 7C units are configured within the remaining white space BA. For example, the shape and layout of the adjacent 7C units are similar to... Figure 2 The partition openings 601, 602, and 603 shown have the same shape and layout.

[0113] exist Figure 9 In the example, multiple partitions 7C each have partition openings 711, 712, and 713 (recesses) in the center. A portion of the partition 7C with partition opening 711 and the area overlapping with partition opening 711 when viewed from above constitutes the area for arranging elements constituting display element DE1 (object area, first area). A portion of the partition 7C with partition opening 712 and the area overlapping with partition opening 712 when viewed from above constitutes the area for arranging elements constituting display element DE2 (object area, second area). A portion of the partition 7C with partition opening 713 and the area overlapping with partition opening 713 when viewed from above constitutes the area for arranging elements constituting display element DE3 (object area).

[0114] It should be noted that the appearance and layout of the adjacent 7C are shown here. Figure 2The partition openings 601, 602, and 603 shown are identical in shape and layout, but partition 7C, for example, Figure 11 As shown, it can also be configured with a different shape and layout than the adjacent openings 601, 602, and 603. Figure 11 The following example is shown: the partition 7C is configured with a different shape and layout than the partition openings 601, 602, and 603. In addition to the three partitions 7C having partition openings 711, 712, and 713 corresponding to sub-pixels SP1, SP2, and SP3, a partition 7C having a partition opening 714 corresponding to sub-pixels SP of other colors such as white is also configured. The shape of the partition 7C is square.

[0115] like Figure 9 and Figure 10 As shown, partition 7C, like partition 6, includes a lower part 71C (bottom layer 73C and axial layer 74C) and an upper part 72C (first top layer 75C and second top layer 76C). In addition, like partition 6, the two ends of the bottom layer 73C protrude from the side of the axial layer 74C.

[0116] The lower portion 71C of partition 7C is formed of the same material as the lower portion 61 of partition 6. Specifically, the bottom layer 73C and the axial layer 74C are formed of the same material as the bottom layer 63 and axial layer 64 of partition 6, respectively. The thickness of the bottom layer 73C is the same as the thickness of the bottom layer 63 of partition 6. In addition, the thickness of the axial layer 74C is the same as the thickness of the axial layer 64 of partition 6.

[0117] The upper part 72C of partition 7C is formed of the same material as the upper part 62 of partition 6. Specifically, the first top layer 75C and the second top layer 76C are formed of the same material as the first top layer 65 and the second top layer 66 of partition 6, respectively. The thickness of the first top layer 75C is the same as the thickness of the first top layer 65 of partition 6. In addition, the thickness of the second top layer 76C is the same as the thickness of the second top layer 66 of partition 6.

[0118] Figure 12 This is a schematic top view showing yet another example of the configuration that can be applied to the test pattern TEG. Figure 13 It is along Figure 12 A schematic cross-sectional view of the mother substrate MB containing the test pattern TEG along the XIII-XIII line. Figure 12 and Figure 13 The configuration shown is, for example, a configuration that can be applied in a test pattern TEG used to confirm the misalignment of metal lines (e.g., signal lines SL, etc.) contained in circuit layer 11 with elements constituting display element DE.

[0119] like Figure 12 As shown, the test pattern TEG consists of rib 5, septum 7D (third septum) and multiple septum 7E (second septum, protrusion).

[0120] Rib layer 5 is configured in Figure 4 Within the area of ​​the panel portion PP and the remaining white area BA shown.

[0121] Adjacent to 7D is positioned within the blank area BA. Like adjacent to 6, adjacent to 7D extends along the X and Y directions to form a grid pattern. Figure 12 In the example, partition 7D has partition openings 721, 722, and 723. For example, the shape and layout of partition openings 721, 722, and 723 are similar to... Figure 2 The partition openings 601, 602, and 603 shown have the same shape and layout. The partition 7E (see below), surrounded by partition opening 721, and the area overlapping with partition opening 721 when viewed from above, constitute the area for arranging elements constituting display element DE1 (object area, first area). The partition 7E (see below), surrounded by partition opening 722, and the area overlapping with partition opening 722 when viewed from above, constitute the area for arranging elements constituting display element DE2 (object area, second area). The partition 7E (see below), surrounded by partition opening 723, and the area overlapping with partition opening 723 when viewed from above, constitute the area for arranging elements constituting display element DE3 (object area).

[0122] It should be noted that the shape and layout of the partition openings 721, 722, and 723 shown here are similar to those shown in the original text. Figure 2 The partition openings 601, 602, and 603 shown are identical in shape and layout, but partition 7D, for example, Figure 14 As shown, it may also have one or more partition openings with shapes different from partition openings 601, 602, and 603. Figure 14 The following example is shown: In addition to the partition openings 721, 722, and 723 corresponding to the sub-pixels SP1, SP2, and SP3, the partition 7D also has a partition opening 724 corresponding to the sub-pixels SP of other colors such as white. The partition openings 721, 722, 723, and 724 are square in shape.

[0123] exist Figure 12 In this example, multiple partitions 7E are arranged to overlap with the metal lines ML included in the circuit layer 11, and are positioned at the center of partition openings 721, 722, and 723. Each partition 7E is surrounded by partition openings 721, 722, and 723. The length of each side of partition 7E is less than the length of each side of the metal line ML. Additionally, the length of each side of partition 7E is less than the width of partition 7D. However, the length of each side of partition 7E can also be the same as the width of partition 7D.

[0124] like Figure 12 and Figure 13As shown, partitions 7D and 7E, like partition 6, respectively comprise lower parts 71D and 71E (bottom layers 73D and 73E and axial layers 74D and 74E) and upper parts 72D and 72E (first top layer 75D and 75E and second top layer 76D and 76E). Furthermore, similar to partition 6, the bottom layers 73D and 73E of partitions 7D and 7E protrude from the sides of axial layers 74D and 74E.

[0125] The lower portions 71D and 71E of partitions 7D and 7E are formed of the same material as the lower portion 61 of partition 6. Specifically, the bottom layers 73D and 73E and the axial layers 74D and 74E are formed of the same material as the bottom layer 63 and axial layer 64 of partition 6, respectively. The thickness of the bottom layers 73D and 73E is the same as the thickness of the bottom layer 63 of partition 6. In addition, the thickness of the axial layers 74D and 74E is the same as the thickness of the axial layer 64 of partition 6.

[0126] The upper parts 72D and 72E of partitions 7D and 7E are formed of the same material as the upper part 62 of partition 6. Specifically, the first top layer 75D and 75E and the second top layer 76D and 76E are formed of the same material as the first top layer 65 and the second top layer 66 of partition 6, respectively. The thickness of the first top layer 75D and 75E is the same as the thickness of the first top layer 65 of partition 6. In addition, the thickness of the second top layer 76D and 76E is the same as the thickness of the second top layer 66 of partition 6.

[0127] Figure 15 This is a schematic top view showing yet another example of the configuration that can be applied to the test pattern TEG. Figure 16 It is along Figure 15 A schematic cross-sectional view of the mother substrate MB of the XVI-XVI line. Figure 15 and Figure 16 The structure shown is Figure 12 and Figure 13 Similarly, the configuration shown is, for example, a configuration that can be applied in a test pattern TEG used to confirm the misalignment of metal lines (e.g., signal lines SL, etc.) contained in circuit layer 11 with elements constituting display element DE.

[0128] like Figure 15 As shown, the test pattern TEG consists of rib layer 5 and multiple septa 7F (second septa, protrusions).

[0129] Rib layer 5 is configured in Figure 4 Within the area of ​​the panel portion PP and the remaining white area BA shown.

[0130] Multiple adjacent 7F units are configured in the remaining blank area (BA). Figure 15In this example, the three partitions 7F are respectively positioned to overlap with the center of the metal lines ML included in the circuit layer 11. The length of each side of the partition 7F is less than the length of each side of the metal lines ML. When viewed from above, the area overlapping with the three metal lines ML is the area for arranging the elements constituting the display element DE (object area, first area, second area). It should be noted that the shape and layout of the metal lines ML shown here are similar to... Figure 2 The partition 7F is configured with the same shape and layout as the partition openings 601, 602, and 603 shown, while the shape and layout of the metal line ML are different. Figure 17 In the case of the shape and layout shown, the four partitions 7F are arranged in the test pattern TEG at a position that overlaps with the center of the metal line ML.

[0131] like Figure 15 and Figure 16 As shown, partition 7F, like partition 6, includes a lower part 71F (bottom layer 73F and axial layer 74F) and an upper part 72F (first top layer 75F and second top layer 76F). In addition, like partition 6, the two ends of the bottom layer 73F of partition 7F protrude from the side of the axial layer 74F.

[0132] The lower portion 71F of partition 7F is formed of the same material as the lower portion 61 of partition 6. Specifically, the bottom layer 73F and the axial layer 74F are formed of the same material as the bottom layer 63 and axial layer 64 of partition 6, respectively. The thickness of the bottom layer 73F is the same as the thickness of the bottom layer 63 of partition 6. In addition, the thickness of the axial layer 74F is the same as the thickness of the axial layer 64 of partition 6.

[0133] The upper part 72F of partition 7F is formed of the same material as the upper part 62 of partition 6. Specifically, the first top layer 75F and the second top layer 76F are formed of the same material as the first top layer 65 and the second top layer 66 of partition 6, respectively. The thickness of the first top layer 75F is the same as the thickness of the first top layer 65 of partition 6. In addition, the thickness of the second top layer 76F is the same as the thickness of the second top layer 66 of partition 6.

[0134] The following describes an example of a manufacturing method for a display device DSP. Figure 18 This is a flowchart illustrating an example of a manufacturing method for a display device DSP. Figures 19A to 19J This is a schematic cross-sectional view showing the process of forming the panel portion PP on the mother substrate MB. Figures 19A to 19J In this section, the focus is primarily on the display area DA, and elements below the organic insulating layer 12 are omitted.

[0135] When forming the panel portion PP, a circuit layer 11 and an organic insulating layer 12 are first formed on the substrate 10 of the mother substrate MB. Figure 18 The next step is as follows (PR1). Figure 19AAs shown, lower electrodes LE1, LE2, and LE3 are formed on the organic insulating layer 12. Figure 18 Process PR2).

[0136] Next, as Figure 19B As shown, the rib layer 5 covering the lower electrodes LE1, LE2, and LE3 is formed on the entire mother substrate MB. Figure 18 (Process PR3). At this time, the rib layer 5 does not have pixel openings AP1, AP2, and AP3. The rib layer 5 can be formed by CVD (Chemical Vapor Deposition).

[0137] After the rib layer 5 is formed, the process for forming the partition wall 6 is carried out. Figure 18 (Processes PR4 and PR5). In process PR4, such as... Figure 19C As shown, a first layer L1 for processing as a bottom layer 63, a second layer L2 for processing as a shaft layer 64, a third layer L3 for processing as a first top layer 65, and a fourth layer L4 for processing as a second top layer 66 are sequentially formed on the entire mother substrate MB. Furthermore, a photoresist R1 is disposed on the fourth layer L4. The photoresist R1 is patterned into the shape of a partition 6. The first layer L1, the second layer L2, the third layer L3, and the fourth layer L4 can be formed, for example, by sputtering.

[0138] In the subsequent process PR5, the photoresist R1 is used as a mask to pattern the first layer L1, the second layer L2, the third layer L3, and the fourth layer L4. In one example, the first layer L1 is formed of titanium nitride, the second layer L2 is formed of aluminum, the third layer L3 is formed of titanium, and the fourth layer L4 is formed of ITO. In this case, process PR5 can include wet etching to remove the portion of the fourth layer L4 exposed from the photoresist R1, dry etching to remove the portions of the first layer L1, the second layer L2, and the third layer L3 exposed from the photoresist R1, and wet etching to reduce the width of the second layer L2. It should be noted that the etching performed in process PR5 is appropriately selected according to the structure and material of the partition 6.

[0139] When passing through process PR5, such as Figure 19D As shown, a partition 6 is formed in the display area DA. After the partition 6 is formed, the resist R1 is removed (stripped off). In the wet etching process described above, which reduces the width of the second layer L2, the second top layer 66 (the fourth layer L4) may also be slightly etched. In the case of this etch, the width of the second top layer 66 is smaller than the width of the first top layer 65.

[0140] Next, the process of setting pixel apertures AP1, AP2, and AP3 is carried out. Figure 18 Process PR6). In process PR6, such as Figure 19EAs shown, a photoresist R2 is formed covering the partition 6. Furthermore, using the photoresist R2 as a mask, dry etching is performed on the rib layer 5. Thus, as... Figure 19F As shown, pixel openings AP1, AP2, and AP3 are formed on the rib layer 5 to expose the lower electrodes LE1, LE2, and LE3. After the above dry etching, the resist R2 is removed (stripped off).

[0141] After process PR6, implement the process for... Figure 1 The process of removing the rib layer 5 in the terminal part T shown ( Figure 18 Process PR7).

[0142] Figure 20A and Figure 20B These are schematic cross-sectional views of the terminal portion T used to illustrate process PR7. As shown in these figures, the terminal portion T has conductive pads PD. The pads PD are disposed on an insulating layer 110, for example, formed of an inorganic insulating material. The pads PD and the insulating layer 110 are, for example, included in... Figure 3 In the circuit layer 11 shown, for example, the periphery of the pad PD is covered by an organic insulating layer 12.

[0143] At the time point when process PR6 is completed, such as Figure 20A As shown, the pad PD is covered by rib layer 5. In process PR7, a photoresist R3 with an opening shape above the pad PD is disposed on rib layer 5. Furthermore, the photoresist R3 is used as a mask to perform dry etching on rib layer 5. Thus, as Figure 20B As shown, terminal openings APt are formed on rib layer 5 to expose pad PD. After the above dry etching, resist R3 is removed (stripped).

[0144] After process PR7, a process for forming display element DE1 is performed. Figure 18 Process PR8). When forming the display element DE1, first as follows: Figure 19G The laminated film FL1 and the sealing layer SE11 are shown. The laminated film FL1 is as follows... Figure 3 The diagram shows an organic layer OR1 that contacts the lower electrode LE1 through a pixel opening AP1, an upper electrode UE1 covering the organic layer OR1, and a capping layer CP1 covering the upper electrode UE1. The organic layer OR1, the upper electrode UE1, and the capping layer CP1 can be formed, for example, by vapor deposition. Additionally, the sealing layer SE11 can be formed, for example, by CVD.

[0145] The laminated film FL1 and the sealing layer SE11 are formed not only in the display area DA of each panel portion PP, but also on the entire mother substrate MB, including the peripheral area SA and the blank area BA. The laminated film FL1 is divided into multiple parts by overhanging partitions 6. The sealing layer SE11 continuously covers each of the divided parts of the laminated film FL1 and the partitions 6.

[0146] Next, the laminated film FL1 and the sealing layer SE11 are patterned. In this patterning, as... Figure 19G As shown, resist R4 is disposed on top of the sealing layer SE11. Resist R4 covers a portion of the sub-pixel SP1 and its surrounding partition 6.

[0147] Next, an etching process is performed using resist R4 as a mask. Thus, as... Figure 19H As shown, the portions of the laminated film FL1 and the sealing layer SE11 exposed from the resist R4 are removed. In other words, the portions of the laminated film FL1 and the sealing layer SE11 that overlap with the lower electrode LE1 are retained, while the remaining portions are removed. Thus, the display element DE1 is formed in the sub-pixel SP1. For example, in the peripheral region SA and the blank region BA, the laminated film FL1 and the sealing layer SE11 are removed by this etching process. This etching process can include wet etching and dry etching performed sequentially on the sealing layer SE11, the capping layer CP1, the upper electrode UE1, and the organic layer OR1. After these etchings, the resist R4 is removed (stripped off).

[0148] After process PR8, a process for forming display element DE2 is performed. Figure 18 The process PR9). Display element DE2 can be formed using the same steps as display element DE1. That is, when forming display element DE2, the laminated film FL2 and the sealing layer SE12 are formed on the entire mother substrate MB. Figure 3 As shown, the laminated film FL2 includes an organic layer OR2 that is in contact with the lower electrode LE2 through the pixel opening AP2, an upper electrode UE2 covering the organic layer OR2, and a capping layer CP2 covering the upper electrode UE2.

[0149] The organic layer OR2, the upper electrode UE2, and the capping layer CP2 can be formed, for example, by vapor deposition. Additionally, the sealing layer SE12 can be formed, for example, by CVD. The laminated film FL2 is divided into multiple portions by cantilevered partitions 6. The sealing layer SE12 continuously covers each of the divided portions of the laminated film FL2 and the partitions 6. By patterning this laminated film FL2 and the sealing layer SE2, as shown... Figure 19I As shown, display element DE2 is formed in sub-pixel SP2. For example, in the peripheral area SA and the blank area BA, the laminated film FL2 and the sealing layer SE12 are removed by etching during this patterning.

[0150] After process PR9, a process for forming display element DE3 is performed. Figure 18 The process PR10). Display element DE3 can be formed using the same steps as display elements DE1 and DE2. That is, when forming display element DE3, the laminated film FL3 and the sealing layer SE13 are formed on the entire mother substrate MB. Figure 3 As shown, the laminated film FL3 includes an organic layer OR3 that is in contact with the lower electrode LE3 through the pixel opening AP3, an upper electrode UE3 covering the organic layer OR3, and a capping layer CP3 covering the upper electrode UE3.

[0151] The organic layer OR3, the upper electrode UE3, and the capping layer CP3 can be formed, for example, by vapor deposition. Additionally, the sealing layer SE13 can be formed, for example, by CVD. The laminated film FL3 is divided into multiple portions by cantilevered partitions 6. The sealing layer SE13 continuously covers each of the divided portions of the laminated film FL3 and the partitions 6. By patterning this laminated film FL3 and the sealing layer SE13, as... Figure 19J As shown, a display element DE3 is formed in sub-pixel SP3. For example, in the peripheral area SA and the blank area BA, the laminated film FL3 and the sealing layer SE13 are removed by etching during this patterning process.

[0152] It should be noted that this is an assumption that display elements DE1, DE2, and DE3 are formed in sequence, but display elements DE1, DE2, and DE3 can also be formed in other orders.

[0153] After forming display elements DE1, DE2, and DE3, they are formed sequentially. Figure 3 The resin layer RS1, sealing layer SE2, and resin layer RS2 shown are shown. Figure 18 Process PR11). Furthermore, each panel portion PP is cut from the mother substrate MB along the cutting line CL1. Figure 18 Process PR12).

[0154] Afterwards, an inspection of each panel PP was carried out. Figure 18 The process PR13). This inspection includes lighting checks of each display element DE1, DE2, and DE3 using inspection pads configured in the inspection area TA. After the inspection, the inspection area TA is interrupted along the cut line CL2 ( Figure 18 (Process PR14). Thus, the display panel PNL is completed.

[0155] Partitions 7A to 7F are formed in the same way as partition 6 through processes PR4 and PR5. That is, through processes PR4 and PR5, bottom layers 73A to 73F are formed on the rib layer 5, shaft layers 74A to 74F are formed on the bottom layers 73A to 73F, the first top layers 75A to 75F are formed on the shaft layers 74A to 74F, and the second top layers 76A to 76F are formed on the first top layers 75A to 75F.

[0156] Figures 21A to 21D Yes Figure 6 and Figure 7The diagram shows a schematic cross-sectional view of the test pattern TEG being implemented in process PR8 for forming the display element DE1. This cross-section shows... Figure 7 For the same location, elements below the organic insulating layer 12 are omitted.

[0157] Through process PR8, such as Figure 21A As shown, a laminated film FL1 and a sealing layer SE11 are formed in the partition wall opening 701. A layer is formed on top of the laminated film FL1 and the sealing layer SE11... Figure 19H The resist R4 shown is equivalent to resist R. Furthermore, as indicated by the multiple arrows, a mask MK is used to expose resist R. The mask MK has an opening above the partition 7B. Resist R is, for example, positive. Therefore, as... Figure 21B As shown, the exposed portion of the resist R is removed during the developing process.

[0158] Next, an etching process is performed using resist R as a mask. Thus, as... Figure 21C As shown, the portions of the laminated film FL1 and the sealing layer SE11 exposed from the resist R are removed. Since the laminated film FL1 and the sealing layer SE11 disposed on the partition wall 7B and the laminated film FL1 and the sealing layer SE11 disposed on the sides of the partition wall 7B are covered by the resist R, they are not removed by this etching process. The sealing layer SE11 disposed around the partition wall 7B is strongly bonded to the partition wall 7B and is not peeled off along with the resist R when it is removed (peeled off) after this process. Therefore, as... Figure 21D As shown, in the test pattern TEG after the resist R is removed, the sealing layer SE11 surrounding the partition 7B and the laminated film FL1 disposed on the partition 7B remain. However, the laminated film FL1 disposed on the side of the partition 7B is removed by interfacial erosion of the stripping solution used to remove the resist R or by a subsequent etching process.

[0159] In process PR9, the partition opening 702 is also subjected to the same process. Figures 21A to 21D The same process as shown. Additionally, in process PR10, the same process is performed on the partition opening 703. Figures 21A to 21D The process shown is the same as the process described. In any process, the sealing layers SE12 and SE13 disposed around the partition 7B are also strongly bonded to the partition 7B and are not peeled off together with the resist R when they are peeled off after these processes.

[0160] It should be noted that this explanation pertains to... Figure 6 and Figure 7 The test pattern shown is the result of TEG performing processes PR8, PR9, and PR10, while for... Figure 9 and Figure 10Similarly, in the case of the TEG implementation processes PR8, PR9, and PR10 with the test pattern shown, the partition openings 711, 712, and 713 formed on the partition 7C and the sealing layers SE11, SE12, and SE13 disposed around the partition openings 711, 712, and 713 are strongly bonded to the partition 7C and are not peeled off along with the resist R when it is peeled off after the etching process. However, the laminated films FL1, FL2, and FL3 disposed on the partition 7C (the case where the laminated film FL1 is disposed on the partition 7C is described later) Figure 22B It is removed by interfacial erosion of the stripping solution used to strip the resist R or by a subsequent etching process.

[0161] In addition, in the case of Figure 12 and Figure 13 Similarly, in the case of the TEG implementation processes PR8, PR9, and PR10 with the test pattern shown, the sealing layers SE11, SE12, and SE13 disposed around the partition 7E are strongly bonded to the partition 7E and are not peeled off along with the resist R when it is peeled off after the etching process. However, the laminated films FL1, FL2, and FL3 disposed on the side of the partition 7E (see later description for the case where the laminated film FL1 is disposed on the side of the partition 7E) Figure 22C It is removed by interfacial erosion of the stripping solution used to strip the resist R or by a subsequent etching process.

[0162] In addition, in the context of Figure 15 and Figure 16 Similarly, in the case of the TEG implementation processes PR8, PR9, and PR10 with the test pattern shown, the sealing layers SE11, SE12, and SE13 surrounding the partition 7F are strongly bonded to the partition 7F and are not peeled off along with the resist R when it is removed after the etching process. However, the laminated films FL1, FL2, and FL3 disposed on the side of the partition 7F (see later description for the case where laminated film FL1 is disposed on the side of the partition 7F) Figure 22D It is removed by interfacial erosion of the stripping solution used to strip the resist R or by a subsequent etching process.

[0163] Next, the measurement process for the test pattern TEG according to this embodiment will be described. For example, in the measurement process of the test pattern TEG according to this embodiment, a mask MK is used in step PR8 to measure the TEG... Figure 19H The resist R4 shown is equivalent to the resist R after exposure.

[0164] Figures 22A to 22D This is a schematic cross-sectional view showing an example of a measurement process. Figure 22A Showing targets Figure 6 and Figure 7The test pattern shown is an example of the TEG measurement procedure. Figure 22B Showing targets Figure 9 and Figure 10 The test pattern shown is an example of the TEG measurement procedure. Figure 22C Showing targets Figure 12 and Figure 13 The test pattern shown is an example of a TEG measurement procedure. Figure 22D Showing targets Figure 15 and Figure 16 The test pattern shown is an example of a TEG measurement procedure.

[0165] In response to Figure 6 and Figure 7 In the TEG measurement process of the test pattern shown, as indicated, Figure 22A As shown, the linewidth W1 of the resist R is measured from one end e of the resist R. r1 to the upper part 72A of the partition 7A, end e 72A1 The length (width) W2 up to the end and the other end e from the resist R r2 to the upper part 72A of the partition 7A, end e 72A2 The length (width) W3 up to this point. Widths W1, W2, and W3 can be measured, for example, using an atomic force microscope (AFM) or a white interference microscope. Alternatively, widths W1, W2, and W3 can also be determined by analyzing an image obtained from a top-view photograph of the test pattern TEG. It should be noted that, here, the description refers to... Figure 22A The XZ section measures the widths W1, W2, and W3 in the X direction, but the width in the Y direction is also measured in the same way.

[0166] In response to Figure 9 and Figure 10 In the TEG measurement process of the test pattern shown, as indicated, Figure 22B As shown, the linewidth W11 of the resist R is measured from one end e of the resist R. r11 One end e of the partition opening 711 on the upper part 72C of the partition 7C 72C1 The length (width) W12 up to the end and the other end e from the resist R r12 The other end e of the partition opening 711 on the upper part 72C of partition 7C 72C2 The length (width) W13 up to this point. Widths W11, W12, and W13 can be measured, for example, using an atomic force microscope (AFM) or a white interference microscope. Alternatively, widths W11, W12, and W13 can also be determined by analyzing an image obtained from a top-view photograph of the test pattern TEG. It should be noted that, here, refer to... Figure 22BThe XZ section illustrates the measurement of the widths W11, W12, and W13 in the X direction, but the width in the Y direction is also measured in the same way.

[0167] In response to Figure 12 and Figure 13 In the TEG measurement process of the test pattern shown, as indicated, Figure 22C As shown, the linewidth W21 of the resist R is measured from one end e of the resist R. r21 to one end e of the metal wire ML ML1 The length (width) W22 up to the end and the other end e from the resist R r22 to the other end of the metal wire ML e ML2 The length (width) W23 up to this point. Widths W21, W22, and W23 can be measured, for example, using an atomic force microscope (AFM) or a white interference microscope. Alternatively, widths W21, W22, and W23 can also be determined by analyzing an image obtained from a top-view photograph of the test pattern TEG. It should be noted that, here, refer to... Figure 22C The XZ cross section is used to illustrate the measurement of the widths W21, W22, and W23 in the X direction, but the width in the Y direction is also measured in the same way.

[0168] In response to Figure 15 and Figure 16 In the TEG measurement process of the test pattern shown, as indicated, Figure 22D As shown, the linewidth W31 of the resist R is measured from one end e of the resist R. r31 to one end e of the metal wire ML ML11 The length (width) W32 up to the end and the other end e from the resist R r32 to the other end of the metal wire ML e ML12 The length (width) up to that point is W33. Widths W31, W32, and W33 can be measured, for example, using an atomic force microscope (AFM) or a white interference microscope. Alternatively, widths W31, W32, and W33 can also be determined by analyzing an image obtained from a top-view photograph of the test pattern TEG. It should be noted that, here, refer to... Figure 22D The XZ cross section is used to illustrate the measurement of the widths W31, W32, and W33 in the X direction, but the width in the Y direction is also measured in the same way.

[0169] Based on these measurement steps, misalignment between the partition wall 6 and the elements constituting the display element DE, and misalignment between the metal line ML, which functions as a reference layer, and the elements constituting the display element DE can be confirmed before the etching process. Additionally, it can be confirmed whether the resist R is applied in the correct position. For example, if at least one of the widths deviates from a predetermined allowable range, the manufacturing process after the measurement step can be suspended. Alternatively, the position of the resist R can be adjusted (specifically, after the resist R has been peeled off once, it is reapplied, and the position of the resist R is adjusted by adjusting the position of the mask MK and performing a development process again to adjust the position of the resist R), thus advancing the manufacturing process.

[0170] It should be noted that the measurement process for the test pattern TEG is also performed after the photoresist R is exposed using a mask MK in processes PR9 and PR10.

[0171] Alternatively, the measurement process for the test pattern TEG can be performed again after the resist R has been peeled off in processes PR8, PR9, and PR10. In this case, the measurement process for the test pattern TEG is performed with respect to the sealing layers SE11, SE12, and SE13 instead of the resist R.

[0172] For example, the measurement process performed after stripping the resist R in process PR8 (for... Figure 6 and Figure 7 In the measurement process of the test pattern TEG shown, the line width replacing the resist R is measured. Figure 21D The linewidth of the sealing layer SE11 is shown, and the length from one end of the sealing layer SE11 to the end of the upper part 72A of the partition wall 7A and the length from the other end of the sealing layer SE11 to the end of the upper part 72A of the partition wall 7A are measured.

[0173] Here, as a comparative example, consider a test pattern in which the partition wall 7B is not positioned in the center of the partition wall opening 701. In such a test pattern, for example, after the resist R is peeled off in process PR8, even if the above-described measurement process focusing on the sealing layer SE11 is to be performed, the laminated film FL1 is peeled off from the rib layer 5 due to interfacial erosion by the stripping liquid used to peel off the resist R. As a result, since the sealing layer SE11 disposed on the laminated film FL1 is also removed along with the resist R, the above-described measurement process focusing on the sealing layer SE11 cannot be performed. In contrast, according to the test pattern TEG of this embodiment, since the partition wall 7B is positioned in the center of the partition wall opening 701, the sealing layer SE11 is bonded to the partition wall 7B, preventing the sealing layer SE11 from being removed along with the resist R when it is peeled off, and the above-described measurement process focusing on the sealing layer SE11 can be performed.

[0174] It should be noted that this description refers to the process performed after the resist R is stripped in process PR8, specifically targeting... Figure 6 and Figure 7 The measurement procedure for the TEG test pattern shown is also performed in steps PR9 and PR10 after the resist R is removed, targeting... Figure 6 and Figure 7 The measurement process for the TEG test pattern shown is as follows. Additionally, measurement processes for other TEG test patterns, performed after the resist R is removed in processes PR8, PR9, and PR10, are also performed in the same manner.

[0175] The measurement procedures described above are as follows: Figure 4 The measurement process can also be performed on each of the multiple test pattern TEGs dispersed on the mother substrate MB. In this case, non-uniformity in the measurement corresponding to the position of the mother substrate MB can be suppressed. As another example, the measurement process can also be performed on a portion of the multiple test pattern TEGs.

[0176] As explained above, regarding the test pattern TEG of this embodiment, regardless of whether the test pattern TEG is Figure 6 and Figure 7 The structure shown Figure 9 and Figure 10 The structure shown Figure 12 and Figure 13 The structure shown and Figure 15 and Figure 16 As described above, in any of the configurations shown, since the resist R is stripped in processes PR8, PR9, and PR10, the sealing layers SE11, SE12, and SE13 can still be retained in the test pattern TEG, a measurement process focusing on the sealing layers SE11, SE12, and SE13 can be performed.

[0177] On the other hand, in order to reliably measure the aforementioned widths, it is important that the TEG test pattern is free of contaminants during the measurement process. Therefore, when targeting... Figure 6 and Figure 7 The test pattern TEG shown is configured as follows. Figure 9 and Figure 10 The test pattern TEG shown is configured as follows. Figure 12 and Figure 13 The test pattern TEG and shown are constructed Figure 15 and Figure 16 When TEG tests using the pattern shown to evaluate the degree of adhering dirt, the inventors' research has determined that... Figure 9 and Figure 10The test pattern shown is the least prone to TEG contamination. Therefore, from the viewpoint that it is possible to perform the measurement process focusing on the sealing layers SE11, SE12, and SE13, and to perform the measurement process stably, it is preferred. Figure 9 and Figure 10 The test pattern TEG shown is a test pattern TEG in which multiple partitions 7C arranged in the blank area BA each form a partition opening (recess).

[0178] As explained above, this embodiment enables efficient and high-precision inspection during the manufacturing process of the display device DSP. In addition to the effects described herein, various other beneficial effects can be obtained from this embodiment.

[0179] Based on the display devices, mother substrates, and manufacturing methods disclosed in the above embodiments, all display devices, mother substrates, and manufacturing methods that can be appropriately designed, modified, and implemented by those skilled in the art as long as they contain the spirit of the present invention also fall within the scope of the present invention.

[0180] Within the scope of this invention, various modifications will be conceived by those skilled in the art, and these modifications should also be understood to fall within the scope of this invention. For example, as long as the spirit of this invention is present, any appropriate additions, deletions, design changes, or additions, omissions, or conditional changes to the constituent elements or processes described above in relation to the embodiments are also included within the scope of this invention.

[0181] Furthermore, any other effects resulting from the methods described in the above embodiments should be understood as effects that are known from the description in this specification or that can be reasonably conceived by those skilled in the art.

Claims

1. A method of manufacturing a mother substrate, characterized by, include: Prepare a substrate comprising a panel portion and a surrounding blank area of ​​the panel portion, wherein the panel portion comprises a display area and a surrounding peripheral area of ​​the display area; A lower electrode is formed in the display area; A rib layer is formed to cover the panel portion and the remaining blank area; A first partition is formed in the display area, the first partition comprising a lower portion and an upper portion having an end portion protruding from the side of the lower portion; A second partition wall comprising the lower part and the upper part is formed in the remaining blank area; A first laminated film comprising at least a first color organic layer and a first sealing layer covering the first laminated film are formed in the panel portion and the remaining blank area; and An etching process is performed, in which the first laminated film and the first sealing layer formed on the panel portion and the blank area, excluding the target area where the organic layer of the first color is disposed, are removed. In the object area of ​​the blank area, portions of the first laminated film and the first sealing layer formed in the blank area, excluding the first laminated film and the first sealing layer formed on the second partition wall and the first laminated film and the first sealing layer formed on the side of the second partition wall, are removed.

2. The method for manufacturing a mother substrate according to claim 1, characterized in that, Prior to the etching process, a resist is applied to expose the portion outside the target area. By performing the etching process with the resist in place, portions of the first laminated film and first sealing layer formed in the blank area, excluding the first laminated film and first sealing layer formed on the second partition wall and the first laminated film and first sealing layer formed on the side of the second partition wall, are removed from the target area in the blank area.

3. The method for manufacturing a mother substrate according to claim 2, characterized in that, Before the process of forming the first laminated film and the first sealing layer, a third partition wall is formed that includes the lower part and the upper part and surrounds the blank area of ​​the target area. The second partition is located in the center of the object area surrounded by the third partition.

4. The method for manufacturing a mother substrate according to claim 3, characterized in that, The resist is removed after the etching process. In the object area of ​​the blank area, the portion other than the first laminated film formed on the second partition wall and the first sealing layer adhered to the second partition wall is removed.

5. The method for manufacturing a mother substrate according to claim 3, characterized in that, Between the etching process and the process of removing the resist, the width of the resist and its length from the end of the resist to the end of the upper portion contained in the third partition are measured.

6. The method for manufacturing a mother substrate according to claim 3, characterized in that, After the process of removing the resist, the width of the first sealing layer bonded to the second partition wall and the length from the end of the first sealing layer bonded to the second partition wall to the end of the upper part included in the third partition wall are measured.

7. The method for manufacturing a mother substrate according to claim 2, characterized in that, The second partition has an opening in the center. The opening overlaps with the object area in the blank space when viewed from above.

8. The method for manufacturing a mother substrate according to claim 7, characterized in that, The resist is removed after the etching process. In the object area of ​​the blank area, the portion other than the first laminated film formed at the opening and the first sealing layer adhered to the second partition wall is removed.

9. The method for manufacturing a mother substrate according to claim 7, characterized in that, Between the etching process and the process of removing the resist, the width of the resist and the length from the end of the resist to the end of the opening side of the upper part included in the second partition are measured.

10. The method for manufacturing a mother substrate according to claim 7, characterized in that, After the process of removing the resist, the width of the first sealing layer bonded to the second partition wall and the length from the end of the first sealing layer bonded to the second partition wall to the end of the opening side of the upper part included in the second partition wall are measured.

11. The method for manufacturing a mother substrate according to claim 2, characterized in that, Before the process of forming the rib layer, a conductive layer is formed on the panel portion and the remaining blank area. In the object region of the blank area, the second partition is formed at a position overlapping the conductive layer.

12. The method for manufacturing a mother substrate according to claim 11, characterized in that, The resist is removed after the etching process. In the object area of ​​the blank area, the portion other than the first laminated film formed on the second partition wall and the first sealing layer adhered to the second partition wall is removed.

13. The method for manufacturing a mother substrate according to claim 11, characterized in that, Between the etching process and the process of removing the resist, the width of the resist and the length from the end of the resist to the end of the conductive layer are measured.

14. The method for manufacturing a mother substrate according to claim 11, characterized in that, After the process of removing the resist, the width of the first sealing layer bonded to the second partition wall and the length from the end of the first sealing layer bonded to the second partition wall to the end of the conductive layer are measured.

15. A mother substrate for a display device, characterized by comprising: include: Each panel includes a display area and a surrounding area of ​​the display area; The blank area around the plurality of panels; The lower electrode is configured in the display area; Rib layers are disposed in the plurality of panel portions and the blank areas; Configured in the first partition of the display area; A first laminate containing an organic layer of a first color is disposed in the first region included in the plurality of panel portions and the white space region, respectively; A first sealing layer covering the first layer of the laminated film; A second laminate containing an organic layer of a second color is disposed in the second region included in the plurality of panel portions and the remaining white area, respectively; The second sealing layer covering the second layer of the laminated film; and Multiple second partitions are respectively disposed in the first region and the second region included in the blank area. The first partition and the second partition each include a lower portion and an upper portion having an end protruding from the side of the lower portion. The first laminated film is disposed on the upper part of the second partition wall in the first region. The first sealing layer is disposed around the second partition wall in the first region, and is bonded to the second partition wall. The second laminated film is disposed on the upper part of the second partition wall in the second region. The second sealing layer is disposed around the second partition wall in the second region and is bonded to the second partition wall.

16. The mother substrate for a display device according to claim 15, characterized in that, The second partition wall, configured in the first region, is located in the center of the first region. The second partition wall, which is located in the second region, is located in the center of the second region.

17. The mother substrate for a display device according to claim 15, characterized in that, It also includes a third partition, which comprises the upper part and the lower part and surrounds the first region and the second region.

18. The mother substrate for a display device according to claim 15, characterized in that, It also has a conductive layer disposed below the rib layer. The second partition wall overlaps with the conductive layer when viewed from above.

19. The mother substrate for a display device according to claim 17, characterized in that, In each of the first, second, and third partitions, the lower portion is disposed above the rib layer.

20. The mother substrate for a display device according to claim 17, characterized in that, The lower portions of each of the first, second, and third partition walls are formed of the same material. The upper portion of each of the first, second, and third partitions is formed of the same material.

21. A mother substrate for a display device, characterized by comprising: include: Each panel includes a display area and a surrounding area of ​​the display area; The blank area around the plurality of panels; The lower electrode is configured in the display area; Rib layers are disposed in the plurality of panel portions and the blank areas; Configured in the first partition of the display area; A first laminate containing an organic layer of a first color is disposed in the first region included in the plurality of panel portions and the white space region, respectively; The first sealing layer covering the first layer of the laminated film; A second laminate containing an organic layer of a second color is disposed in the second region included in the plurality of panel portions and the white space region, respectively; The second sealing layer covering the second layer of the laminated film; and Multiple second partitions are respectively positioned at locations that overlap with the first and second regions included in the blank area when viewed from above. The first partition and the second partition each include a lower portion and an upper portion having an end protruding from the side of the lower portion. The second partition has an opening in the center. The first laminated film is disposed in an opening in the second partition wall at a position overlapping with the first region. The first sealing layer, in an adhesive state, is disposed around the opening in the second partition wall at a location overlapping with the first region. The second laminated film is disposed in an opening at a position overlapping with the second region in the second partition wall. The second sealing layer is disposed around the opening at a location overlapping the second region in the second partition wall, and is in a state of being bonded to the second partition wall.

22. The mother substrate for a display device according to claim 21, characterized in that, The opening in the second partition wall in the first region is located in the center of the first region. The opening in the second partition wall configured in the second region is located in the center of the second region.

23. The mother substrate for a display device according to claim 21, characterized in that, In each of the first and second partitions, the lower portion is disposed above the rib layer.

24. The mother substrate for a display device according to claim 21, characterized in that, The lower portions of both the first and second partition walls are formed of the same material. The upper portion of each of the first and second partitions is formed of the same material.

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