Display device and electronic device

Abstract

A display device and an electronic device are provided. The display device includes: a substrate; a transistor layer including a first transistor and a second transistor; and a sub-pixel including a first type of light-emitting element and a second type of light-emitting element, the first type of light-emitting element being configured to be driven by the first transistor, the second type of light-emitting element being configured to be driven by the second transistor and including a first reflective pattern, the first reflective pattern having a triangular cross-section at the lower portion of the second type of light-emitting element and including a reflective surface inclined toward the center of the lower portion.

Description

[0001] This application claims priority and benefit to Korean Patent Application No. 10-2025-0016782, filed on February 10, 2025, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference. Technical Field

[0002] This disclosure relates to a display device and an electronic device. Background Technology

[0003] With the development of the information society, the demand for display devices for displaying images is increasing in various forms. Display devices can be flat panel displays such as liquid crystal displays, field emission displays, and light-emitting displays.

[0004] Light-emitting display devices can include organic light-emitting display devices that incorporate organic light-emitting diode (OLED) elements as light-emitting elements and micro light-emitting display devices that incorporate micro light-emitting diode elements (hereinafter referred to as micro light-emitting elements) as light-emitting elements. Because micro light-emitting diode elements are made of inorganic materials, they have a longer lifespan compared to organic light-emitting diode (OLED) elements due to fewer degradation problems.

[0005] The viewing angle characteristics of these display devices can be considered important. For example, even over a wide viewing angle range, display devices can be expected to achieve clear and distortion-free image quality. Therefore, wide viewing angle technologies are constantly being developed.

[0006] However, in addition to the wide-view mode (normal mode), there is also a narrow-view mode (privacy mode) for privacy, which is suitable for handling confidential documents or performing tasks that require security by allowing only the person sitting in front of the screen to see the image on the screen. Summary of the Invention

[0007] An embodiment of the present disclosure provides a display device having an effective narrow viewing angle mode in a display device that provides both narrow and wide viewing angle modes, and a method for manufacturing the display device.

[0008] However, this disclosure is not limited to what is set forth herein. The above and other embodiments of this disclosure will become more apparent to those skilled in the art from the following detailed description of the disclosure.

[0009] According to one or more embodiments of the present disclosure, a display device includes: a substrate; a transistor layer including a first transistor and a second transistor; and a sub-pixel including a first type of light-emitting element and a second type of light-emitting element, the first type of light-emitting element being configured to be driven by the first transistor, the second type of light-emitting element being configured to be driven by the second transistor and including a first reflective pattern, the first reflective pattern having a triangular cross-section at the lower portion of the second type of light-emitting element and including a reflective surface inclined toward the center of the lower portion.

[0010] Multiple first reflective patterns can be configured, wherein the first reflective patterns are on opposite sides of the second type of light-emitting element, such that the reflective surfaces face each other.

[0011] The second type of light-emitting element may include: a semiconductor layer; a reflective film on the side and top surfaces of the semiconductor layer and defining openings; a first protective film between the semiconductor layer and the reflective film; and a second protective film on the outside of the reflective film.

[0012] The first reflective pattern can be separated from the area overlapping the opening.

[0013] The display device may further include: a partition wall on the transistor layer and surrounding the first type of light-emitting element and the second type of light-emitting element in a plan view; and at least one second reflective pattern having a triangular cross-section adjacent to the upper part of the partition wall and surrounding the second type of light-emitting element in a plan view.

[0014] At least one second reflective pattern may include a first surface that protrudes from the partition wall at an angle, a second surface that is in full contact with the partition wall, and a third surface that is below the first surface and extends from the first surface to the second surface.

[0015] The angle can be approximately 90 degrees or greater.

[0016] The second reflective pattern can be positioned horizontally above the second type of light-emitting element.

[0017] The partition wall can have a tapered shape that narrows in the upward direction.

[0018] The first and second reflective patterns may include at least one of aluminum and silver.

[0019] The display device may also include a first optical pattern contained in a concave lens above a second type of light-emitting element.

[0020] The display device may also include a second optical pattern comprising an upwardly convex lens above the first type of light-emitting element.

[0021] The first transistor can be configured to operate in a wide-viewing-angle mode, while the second transistor is configured to operate in a narrow-viewing-angle mode.

[0022] The display device may further include: a wavelength conversion layer in the space defined by the partition wall; and a cover layer, an outer coating layer and a color filter layer, which are sequentially arranged above the partition wall.

[0023] According to one or more embodiments of the present disclosure, a display device includes: a substrate; a transistor layer above the substrate; a pixel electrode layer above the transistor layer; a light-emitting element above the pixel electrode layer, having a first reflective pattern with a triangular cross-section, the first reflective pattern being located at the lower portion of the light-emitting element and inclined toward the center of the light-emitting element; and a partition wall surrounding the light-emitting element in a plan view.

[0024] The light-emitting element may include: a semiconductor layer; a reflective film defined on the side and top surfaces of the semiconductor layer and defined in an opening separated from the first reflective pattern in a plan view; a first protective film between the semiconductor layer and the reflective film; and a second protective film on the outside of the reflective film.

[0025] The display device may also include one or more triangular second reflective patterns, which are located on the side adjacent to the upper part of the partition wall and surround the light-emitting element in a plan view, and include a first surface protruding from the partition wall at an angle, a second surface in full contact with one side of the partition wall, and a third surface below the first surface and extending from the first surface to the second surface.

[0026] One or more triangular secondary reflective patterns may be positioned horizontally above the light-emitting element.

[0027] The display device may also include an optical pattern contained in a concave lens above the light-emitting element.

[0028] According to one or more embodiments of the present disclosure, an electronic device includes: a display panel for displaying images, and includes a substrate, a transistor layer comprising a first transistor and a second transistor, and subpixels comprising a first type of light-emitting element and a second type of light-emitting element, the first type of light-emitting element being configured to be driven by the first transistor, the second type of light-emitting element being configured to be driven by the second transistor and including a first reflective pattern, the first reflective pattern having a triangular cross-section at the lower portion of the second type of light-emitting element and including a reflective surface inclined toward the center of a surface of the second type of light-emitting element.

[0029] According to the display device and manufacturing method thereof according to the embodiments, an effective narrow viewing angle can be provided in the display device that provides a wide viewing angle mode and a narrow viewing angle mode.

[0030] However, the aspects of this disclosure are not limited to those described above, and various other aspects are included in this specification. Attached Figure Description

[0031] Figure 1 This is a perspective view showing a display device according to one or more embodiments.

[0032] Figure 2 yes Figure 1 A magnified view of region A.

[0033] Figure 3 This is a block diagram illustrating a display device according to one or more embodiments.

[0034] Figure 4 It is shown that it includes Figure 3 The circuit diagram of the first sub-pixel in the display device.

[0035] Figure 5 It is shown that it includes Figure 1 A layout diagram of the pixels in the display area of ​​a display device.

[0036] Figure 6 It is along Figure 5 A sectional view taken by line I-I'.

[0037] Figure 7 yes Figure 6 A magnified view of region A1.

[0038] Figure 8 Is as Figure 7 Enlarged view of an example of a second type of light-emitting element, 2-1.

[0039] Figure 9 Is as Figure 7 Enlarged view of another example of the second type of light-emitting element, 2-1.

[0040] Figure 10 According to one or more other embodiments Figure 6 A magnified view of region A1.

[0041] Figure 11 yes Figure 10 A magnified view of region B.

[0042] Figure 12 According to one or more other embodiments Figure 10 A magnified view of region B.

[0043] Figure 13 This illustrates the display panel along one or more other embodiments. Figure 5 An example of a cross-sectional view taken by line I-I'.

[0044] Figure 14 It is shown in detail Figure 13A cross-sectional view of the example area A2.

[0045] Figure 15 It shows the display panel and Figure 5 A cross-sectional view of an example of the section corresponding to line II-II'.

[0046] Figure 16 It is shown in detail Figure 15 A cross-sectional view of an example of the first type of light-emitting element.

[0047] Figure 17 This illustrates a display panel according to one or more other embodiments. Figure 5 A cross-sectional view of an example of the section corresponding to line II-II'.

[0048] Figure 18 It is a layout diagram showing the pixels of a display area according to one or more embodiments.

[0049] Figure 19 It shows the display panel and Figure 18 A cross-sectional view of an example of the section corresponding to line I1-I1'.

[0050] Figure 20 It is shown in detail Figure 19 A cross-sectional view of the example area A2.

[0051] Figure 21 Is as Figure 20 Enlarged view of an example of a second type of light-emitting element, 2-1.

[0052] Figure 22 Is as Figure 20 Enlarged view of another example of the second type of light-emitting element, 2-1.

[0053] Figure 23 This illustrates the display panel along one or more other embodiments. Figure 18 An example sectional view of the section cut by line II1-II1'.

[0054] Figure 24 It is shown in detail Figure 23 A cross-sectional view of an example of the first type of light-emitting element.

[0055] Figure 25 This illustrates the display panel along one or more other embodiments. Figure 18 An example sectional view of the section cut by line II1-II1'.

[0056] Figure 26 It is along one or more other embodiments Figure 5 A sectional view taken by line I-I'.

[0057] Figure 27 yes Figure 26 A magnified view of region B1.

[0058] Figure 28 This illustrates the display panel along one or more other embodiments. Figure 5 An example sectional view of the section cut by line II-II'.

[0059] Figure 29 and Figure 30 This is a diagram illustrating a smartwatch including a display device according to one or more embodiments.

[0060] Figure 31 This is an exploded perspective view of a smartwatch including a display device according to one or more embodiments.

[0061] Figure 32 This is an example view of a virtual reality (VR) device including a display device according to one or more embodiments.

[0062] Figure 33 This is an example view of a VR device including a display device according to one or more embodiments.

[0063] Figure 34 This is an example view showing a vehicle dashboard and central instrument panel including a display device according to one or more embodiments.

[0064] Figure 35 This is an example view of a transparent display device including a display apparatus according to one or more embodiments. Detailed Implementation

[0065] Aspects of some embodiments of this disclosure and methods of implementing them can be more readily understood by referring to the detailed description and accompanying drawings of the embodiments. The described embodiments are provided as examples so that this disclosure will be thorough and complete, and will fully convey aspects of this disclosure to those skilled in the art. Therefore, redundant processes, elements, and techniques that are irrelevant or unrelated to the description of the embodiments, or that are unnecessary for those skilled in the art to fully understand aspects of this disclosure, may be omitted. Unless otherwise stated, the same reference numerals, symbols, or combinations thereof denote the same elements throughout the drawings and written description, and therefore, their repeated description may be omitted.

[0066] The described embodiments may have various modifications and may be embodied in different forms, and should not be construed as being limited to the embodiments shown herein. In describing embodiments, the use of "may," "may," or "may not" corresponds to one or more embodiments of this disclosure.

[0067] In view of the entire disclosure, those skilled in the art will understand that each suitable feature of the various embodiments of the present disclosure may be combined in part or in whole, or combined with one another, and may be technically interlocked and operated in a variety of suitable ways, and unless otherwise stated or implied, each embodiment may be implemented independently of one another or in any suitable combination with one another.

[0068] In the accompanying drawings, the relative dimensions of elements, layers, and regions may be exaggerated for clarity and / or descriptive purposes. In other words, the disclosure is not limited thereto because the dimensions and thicknesses of the elements in the drawings are arbitrarily shown for ease of description. Additionally, the use of crosshairs and / or shading typically provided in the drawings is to clarify the boundaries between adjacent elements. Thus, unless otherwise stated, the presence or absence of crosshairs or shading does not convey or indicate any preference or requirement for the specific material, material properties, dimensions, scale, commonalities between the elements shown, and / or any other characteristics, properties, etc.

[0069] Various embodiments are described herein with reference to cross-sectional views shown as schematic illustrations and / or intermediate structures. Thus, variations in the shape of the illustrations due to, for example, manufacturing techniques and / or tolerances will be expected. Furthermore, the specific structural or functional descriptions disclosed herein are illustrative only for the purpose of describing embodiments according to the concept of this disclosure. Therefore, the embodiments disclosed herein should not be construed as limited to the illustrated shapes of elements, layers, or regions, but will include deviations in shape due to, for example, manufacturing processes.

[0070] For example, an injection region shown as rectangular will typically have chamfered or curved features at its edges and / or a gradient of injection concentration, rather than a binary variation from the injection region to the non-injection region. Similarly, the embedded region formed by injection can induce some injection in the region between the embedded region and the surface through which the injection occurs.

[0071] For ease of explanation, spatial relative terms such as “below,” “under,” “lower,” “lower side,” “below,” “above,” “upper,” “above,” “higher,” “upper side,” and “side” (e.g., as in “sidewall”) are used herein to describe the relationship between one element or feature as shown in the accompanying drawings and another element or feature (or other elements or features). It will be understood that, in addition to the orientations depicted in the accompanying drawings, the spatial relative terms are also intended to cover different orientations of the device in use or operation. For example, if the device in the accompanying drawings is flipped, an element described as “below,” “under,” or “below” other elements or features will subsequently be oriented “above” said other elements or features. Thus, the example terms “below” and “below” can cover both above and below orientations. The device may be oriented in other ways (e.g., rotated 90 degrees or in other orientations), and the spatial relative descriptive terms used herein should be interpreted accordingly. Similarly, when the first part is described as being arranged "on" the second part, this means that the first part is arranged on the upper or lower side of the second part, but not limited to the upper side of the second part based on the direction of gravity.

[0072] Furthermore, the phrase "in a plan view" means when viewing a portion of the object from above, and the phrase "in a schematic sectional view" means when viewing a schematic section taken by vertically cutting the portion of the object from the side. The terms "overlapping with" or "overlapping" mean that the first object may be above, below, or to the side of the second object, or vice versa. Additionally, the term "overlapping with" can include stacking, facing or confronting, extending over (overlapping), covering or partially covering, or any other suitable term as will be understood and appreciated by one of ordinary skill in the art. The expression "not overlapping" can include meanings such as "separated," "offset," or "deviation," and any other suitable equivalent as will be understood and appreciated by one of ordinary skill in the art. The terms "facing" and "confronting" can mean that the first object may be directly or indirectly opposite the second object. Where a third object is located between the first and second objects, although the first and second objects still face each other, they can be understood as being indirectly opposite each other.

[0073] It will be understood that when a component, layer, region, or assembly (e.g., device, apparatus, circuit, wiring, electrode, terminal, conductive film, etc.) is referred to as "formed on," "on," "connected to," or "(operably, functionally, or communicatively) incorporated into" another component, layer, region, or assembly, it can be directly formed on, directly on, directly connected to, or directly incorporated into the other component, layer, region, or assembly, or indirectly formed on, indirectly on, indirectly connected to, or indirectly incorporated into the other component, layer, region, or assembly, such that one or more intermediary components, layers, regions, or assemblies may exist. Furthermore, this can be collectively referred to as direct or indirect incorporation or connection, and integral or non-integral incorporation or connection. For example, when a layer, region, or component is referred to as "electrically connected" or "electrically bonded" to another layer, region, or component, it can be directly electrically connected to or directly electrically bonded to said other layer, region, and / or component, or one or more intermediary layers, regions, or components may be present. One or more intermediary components may include switches, transistors, resistors, inductors, capacitors, and / or diodes, etc. Therefore, the connection is not limited to the connections shown in the accompanying drawings or detailed description, and may also include other types of connections. In describing embodiments, unless explicitly described as a direct connection, the expression for a connection indicates an electrical connection, and "directly connected / directly bonded" or "directly on..." means that one component is directly connected to or directly bonded to another component, or directly on another component, without an intermediary component.

[0074] Furthermore, in this specification, when a portion of a layer, film, region, plate, etc., is formed on another portion, the formation direction is not limited to the upward direction, but includes forming the portion on a side surface or in the downward direction. Conversely, when a portion of a layer, film, region, plate, etc., is formed "below" another portion, this includes not only the case where the portion is "directly below" the other portion, but also the case where there is another portion between the portion and the other portion. Similarly, other expressions describing the relationship between components, such as "between," "directly between," or "adjacent to," can be interpreted in a similar way. It will be understood that when an element or layer is referred to as "between" two elements or layers, it can be the only element or layer between the two elements or layers, or there may be one or more intervening elements or layers.

[0075] For the purposes of this disclosure, when expressions such as “at least one of…” or “any one of…” or “one or more of…” follow a list of elements, they modify the entire list of elements without modifying individual elements within the list. For example, “at least one of X, Y, and Z” and “at least one selected from the group consisting of X, Y, and Z” can be interpreted as any combination of only X, only Y, only Z, two or more of X, Y, and Z (such as XYZ, XY, YZ, and XZ) or any variations thereof. Similarly, the expression “at least one of A and B” can include A, B, or A and B. As used herein, “or” generally means “and / or”, and the term “and / or” includes any and all combinations of one or more of the associated listed items. For example, the expression “A and / or B” can include A, B, or A and B. Similarly, when expressions such as “at least one of…”, “multiple (species / beings)…”, “one of…”, and other prepositional phrases precede / follow a list of elements, they modify the entire list of elements without modifying individual elements within the list. When “C to D” is stated, unless otherwise specified, “C to D” means C or greater and D or less.

[0076] It will be understood that while the terms “first,” “second,” “third,” etc., may be used herein to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms do not correspond to a specific order, position, or priority, and are used only to distinguish one element, component, assembly, region, area, layer, segment, or part from another. Therefore, without departing from the spirit and scope of this disclosure, the first element, component, region, layer, or segment described below may be designated as a second element, component, region, layer, or segment. Describing an element as a “first” element does not require or imply the existence of a second element or other elements. The terms “first,” “second,” etc., may also be used herein to distinguish elements of different categories or groups. For the sake of brevity, the terms “first,” “second,” etc., may respectively represent “first category (or first group),” “second category (or second group),” etc.

[0077] In this example, the x-axis, y-axis, and / or z-axis are not limited to the three axes of a Cartesian coordinate system and can be interpreted in a broader sense. For example, the x-axis, y-axis, and z-axis can be perpendicular to each other, or they can represent different directions that are not perpendicular to each other. The same applies to the first direction DR1, the second direction DR2, and / or the third direction DR3.

[0078] The terminology used herein is for the purpose of describing embodiments only and is not intended to be limiting of this disclosure. As used herein, unless the context clearly indicates otherwise, the singular forms “a” and “an” are intended to include the plural forms, and the plural forms are intended to include the singular forms. It will also be understood that when the terms “comprising,” “having,” and “including,” and variations thereof are used in this specification, it indicates the presence of the stated features, integrals, steps, operations, elements, and / or components, but does not preclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof.

[0079] As used herein, the terms “substantially,” “about,” “approximately,” and similar terms are used as approximate terms rather than terms of degree and are intended to account for inherent deviations in measured or calculated values ​​that would be recognized by one of ordinary skill in the art. For example, “substantially” can include a range of + / - 5% of the corresponding value. As used herein, “about” or “approximately” includes the stated value and means within an acceptable range of deviations from the specific value as determined by one of ordinary skill in the art, taking into account the measurement in question and the errors associated with the measurement of the specific quantity (i.e., limitations of the measurement system). For example, “about” can mean within one or more standard deviations, or within ±30%, ±20%, ±10%, ±5% of the stated value. Furthermore, when describing embodiments of this disclosure, the use of “may” refers to “one or more embodiments of this disclosure.” Additionally, the expression “identical” can mean “substantially identical.” In other words, the expression “identical” can include a range acceptable to one of ordinary skill in the art. Other expressions may also be those from which “substantially” has been omitted.

[0080] In some embodiments, well-known structures and arrangements may be described in the accompanying drawings with respect to one or more functional blocks (e.g., block diagrams), units, and / or modules to avoid unnecessarily obscuring various embodiments. Those skilled in the art will understand that these blocks, units, and / or modules are physically implemented by logic circuitry, individual components, microprocessors, hardwired circuitry, memory elements, wiring connections, and other electronic circuitry. This can be formed using semiconductor-based manufacturing techniques or other manufacturing techniques. Blocks, units, and / or modules implemented by microprocessors or other similar hardware can be programmed and controlled using software to perform the various functions discussed herein, optionally driven by firmware and / or software. Additionally, each block, unit, and / or module may be implemented by dedicated hardware or a combination of dedicated hardware performing some functions and processors performing functions different from those of the dedicated hardware (e.g., one or more programmed microprocessors and associated circuitry). Furthermore, in some embodiments, blocks, units, and / or modules may be physically divided into two or more interacting separate blocks, units, and / or modules without departing from the scope of this disclosure. In addition, in some embodiments, without departing from the scope of this disclosure, blocks, units and / or modules may be physically combined into more complex blocks, units and / or modules.

[0081] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It will also be understood that terms (such as those defined in a general dictionary) shall be interpreted as having the same meaning as they have in the relevant field and / or in the context of this specification, and shall not be interpreted in an idealized or overly formal sense, unless expressly defined herein.

[0082] Figure 1 This is a perspective view showing a display device according to one or more embodiments. Figure 2 yes Figure 1 A magnified view of region A.

[0083] Reference Figure 1 The display device 10 is a device for displaying video or still images, such as portable electronic devices (such as mobile phones, smartphones, tablet PCs (TPCs), smartwatches, watch phones, mobile communication terminals, electronic notebooks, e-books, portable multimedia players (PMPs), navigators, and ultra-mobile PCs (UMPCs)) and display screens for various products including televisions, laptops, monitors, billboards, and Internet of Things (IoT) devices.

[0084] Display device 10 may be an organic light-emitting display device, such as an organic light-emitting display device using organic light-emitting diodes, a quantum dot light-emitting display device including a quantum dot light-emitting layer, an inorganic light-emitting display device including inorganic semiconductors, or an ultra-miniature light-emitting display device using ultra-miniature light-emitting diodes (micro-LEDs or nano-LEDs). Hereinafter, display device 10 will be primarily described as an ultra-miniature light-emitting display device, but this disclosure is not limited thereto. For ease of explanation, ultra-miniature light-emitting diodes will be described below as light-emitting elements.

[0085] The display device 10 according to one or more embodiments may include a display panel 100 comprising a display area DA and a non-display area NDA.

[0086] The display panel 100 may have a rectangular planar shape having a long side in the first direction DR1 and a short side in the second direction DR2. However, the planar shape of the display panel 100 is not limited to this, and the display panel 100 may have different shapes. For example, the display panel 100 may have a polygonal shape, a circular shape, an elliptical shape, or an irregular flat shape other than a rectangular shape.

[0087] The display area DA can be an area where an image is displayed, and the non-display area NDA can be an area where no image is displayed. In one or more embodiments, the flat shape of the display area DA can follow the flat shape of the display panel 100. Figure 1 In the diagram, the planar shape of the display area DA is shown as a rectangle. The display area DA can be arranged in the central area of ​​the display panel 100. The non-display area NDA can be arranged around the display area DA. For example, the non-display area NDA can surround the display area DA.

[0088] The display area DA may include pixels PX. Each pixel PX may include at least two light-emitting elements LE.

[0089] In one or more embodiments, each pixel PX may include three light-emitting elements LE. For example, each pixel PX may include a first light-emitting element LE1, a second light-emitting element LE2, and a third light-emitting element LE3. The number and / or type of light-emitting elements LE assigned to the pixel PX may vary depending on the embodiment.

[0090] In one or more embodiments, each pixel PX may include a light-emitting element LE that emits light of a different color. For example, a first light-emitting element LE1, a second light-emitting element LE2, and a third light-emitting element LE3 may emit light of correspondingly different colors.

[0091] The first light-emitting element LE1 can emit a first light. The first light can be red light. For example, the main peak wavelength (R peak) of the first light can be located at approximately 600 nm to approximately 750 nm, but the embodiments are not limited to this.

[0092] The second light-emitting element LE2 can emit a second light. The second light can be green light. For example, the main peak wavelength (G peak) of the second light can be located at approximately 480 nm to approximately 560 nm, but the embodiments are not limited to this.

[0093] The third light-emitting element LE3 can emit a third light. The third light can be blue light. For example, the main peak wavelength (B peak) of the third light can be located at approximately 370 nm to approximately 460 nm, but the embodiments are not limited to this.

[0094] In one or more other embodiments, the first light-emitting element LE1, the second light-emitting element LE2, and the third light-emitting element LE3 can emit light of the same color. Furthermore, a light conversion layer may be arranged including a light conversion element (e.g., a quantum dot) for converting the color (or corresponding wavelength) of light emitted from at least one of the first light-emitting element LE1, the second light-emitting element LE2, and the third light-emitting element LE3 into light of a different color (or corresponding wavelength).

[0095] In one or more embodiments, the first light-emitting element LE1, the second light-emitting element LE2, and the third light-emitting element LE3 of each pixel PX can be arranged sequentially in the first direction DR1. In one or more embodiments, the first light-emitting element LE1 can be arranged in the second direction DR2. The second light-emitting element LE2 can be arranged in the second direction DR2. The third light-emitting element LE3 can be arranged in the second direction DR2. For example, in each pixel column extending along the second direction DR2, the first light-emitting element LE1, the second light-emitting element LE2, or the third light-emitting element LE3 can be arranged. Furthermore, the arrangement structure of the pixel PX and the light-emitting elements LE disposed to the pixel PX can be varied according to embodiments.

[0096] In one or more embodiments, the light-emitting elements LE may be arranged at substantially the same intervals in the display area DA, but are not limited thereto. For example, the position and / or arrangement interval of the light-emitting elements LE may be varied according to the embodiments.

[0097] In one or more embodiments, the dimensions (e.g., area) of the light-emitting elements LE can be substantially the same. For example, the first light-emitting element LE1, the second light-emitting element LE2, and the third light-emitting element LE3 can have substantially the same dimensions. However, the embodiments are not limited thereto, and the dimensions of each of the light-emitting elements LE and / or the area of ​​the light-emitting region corresponding to the light-emitting element LE can be varied according to the embodiments.

[0098] In one or more embodiments, the light-emitting element LE may have a circular planar shape, but the embodiments are not limited thereto. For example, the light-emitting element LE may have a rectangular shape or other polygonal, elliptical, or irregular shapes. In addition, the light-emitting elements LE may have substantially the same planar shape, or may have different planar shapes for each group.

[0099] The non-display area NDA may include a first common voltage supply area CVA1, a second common voltage supply area CVA2, a first pad area PDA1, a second pad area PDA2, and a peripheral area PHA.

[0100] A first common voltage supply region CVA1 may be disposed between a first pad region PDA1 and a display region DA. A second common voltage supply region CVA2 may be disposed between a second pad region PDA2 and a display region DA. Each of the first common voltage supply region CVA1 and the second common voltage supply region CVA2 may include a connection to a common electrode (e.g., Figure 5 The common electrode (CE1, CE2, and CE3) is connected to a common electrode connector CVS. For example, the common electrode can extend from the display area DA to the first common voltage supply area CVA1 and the second common voltage supply area CVA2, and is electrically connected to the common electrode connector CVS. Common voltage can be supplied to the common electrode through the common electrode connector CVS.

[0101] The common electrode connector CVS can be disposed in the common voltage supply region (e.g., a first common voltage supply region CVA1 and / or a second common voltage supply region CVA2) of the non-display area NDA. The common electrode connector CVS may include a conductive material (e.g., a metallic material such as aluminum (Al)). Although Figure 1 and Figure 2 A display device 10 is shown with a common electrode connector CVS positioned in a non-display area NDA, but the embodiment is not limited thereto. For example, the common electrode connector CVS may be arranged in the display area DA. In one example, the common electrode connector CVS may be positioned in a pixel region or between pixel regions.

[0102] The common electrode connector CVS of the first common voltage supply region CVA1 can be electrically connected to one of the first pads PD1 of the first pad region PDA1. For example, the common electrode connector CVS of the first common voltage supply region CVA1 can receive common voltage from one of the first pads PD1 of the first pad region PDA1.

[0103] The first pad PD1 may be disposed in the first pad region PDA1. In one or more embodiments, the first pad PD1 may be connected to the circuit board via conductive connection members. For example, the first pad PD1 may be electrically connected to a circuit pad disposed on the circuit board via wiring.

[0104] The common electrode connector CVS of the second common voltage supply region CVA2 can be electrically connected to one of the second pads of the second pad region PDA2. For example, the common electrode connector CVS of the second common voltage supply region CVA2 can receive a common voltage from one of the second pads of the second pad region PDA2. In one or more embodiments, the display panel 100 may not include the second common voltage supply region CVA2.

[0105] The first pad region PDA1 can be arranged on one side (e.g., the top side) of the display panel 100. The first pad region PDA1 may include a first pad PD1 connected to an external circuit board.

[0106] The second pad region PDA2 may be disposed on the other side (e.g., the bottom side) of the display panel 100. The second pad region PDA2 may include a second pad connected to an external circuit board. In one or more embodiments, the display panel 100 may not include the second pad region PDA2.

[0107] The second pad can be disposed in the second pad region PDA2 of the non-display area NDA. In one or more embodiments, the second pad can be connected to the circuit board via conductive connection members. For example, the second pad can be electrically connected to a circuit pad disposed on the circuit board via wiring.

[0108] The peripheral area PHA can be the remaining area in the non-display area NDA, excluding the first common voltage supply area CVA1, the second common voltage supply area CVA2, the first pad area PDA1, and the second pad area PDA2. The peripheral area PHA can surround not only the display area DA, but also the first common voltage supply area CVA1, the second common voltage supply area CVA2, the first pad area PDA1, and the second pad area PDA2.

[0109] Figure 3 This is a block diagram illustrating a display device according to one or more embodiments.

[0110] Reference Figure 3 The display device 10 according to one or more embodiments of the present disclosure may include a display panel 100 and a display panel driving unit. The display panel driving unit may include a driving control unit 200, a gate driving unit 300, a gamma reference voltage generating unit 400, a data driving unit 500, and a light-emitting driving unit 600.

[0111] The display panel 100 may include a display area DA for displaying images and a non-display area NDA located around the display area DA.

[0112] The display panel 100 may include multiple gate lines GWL, GIL, and GBL, multiple data lines DL, multiple first light-emitting control lines EL1, multiple second light-emitting control lines EL2, and multiple sub-pixels. The sub-pixels may be electrically connected to each of the multiple gate lines GWL, GIL, and GBL, the multiple data lines DL, the multiple first light-emitting control lines EL1, and the multiple second light-emitting control lines EL2. For example, each of the multiple gate lines GWL, GIL, and GBL, the multiple first light-emitting control lines EL1, and the multiple second light-emitting control lines EL2 may extend in a first direction DR1 or a second direction DR2 opposite to the first direction DR1. Each of the multiple data lines DL may extend in a third direction DR3 intersecting the first direction DR1 and the second direction DR2.

[0113] The display panel 100 may also include initialization lines VIL that transmit initialization voltages to sub-pixels. For example, each of the initialization lines VIL may extend in a first direction DR1 or a second direction DR2.

[0114] In one or more embodiments, the drive control unit 200 may receive input image data IMG and input control signal CONT from an external device. For example, the input image data IMG may include red image data, green image data, and blue image data. The input image data IMG may include white image data. The input image data IMG may include magenta image data, yellow image data, and cyan image data. The input control signal CONT may include a master clock signal and a data enable signal. The input control signal CONT may also include a vertical synchronization signal and a horizontal synchronization signal.

[0115] The drive control unit 200 can generate a first control signal CONT1, a second control signal CONT2, a third control signal CONT3, a fourth control signal CONT4, and a data signal DATA based on the input image data IMG and the input control signal CONT.

[0116] The drive control unit 200 can generate a first control signal CONT1 for controlling the operation of the gate drive unit 300 based on the input control signal CONT. The drive control unit 200 can output the first control signal CONT1 to the gate drive unit 300. The first control signal CONT1 may include a vertical start signal and a gate clock signal.

[0117] The drive control unit 200 can generate a second control signal CONT2 for controlling the operation of the data drive unit 500 based on the input control signal CONT. The drive control unit 200 can output the second control signal CONT2 to the data drive unit 500. The second control signal CONT2 may include a horizontal start signal and a load signal.

[0118] The drive control unit 200 can generate a data signal DATA based on the input image data IMG. The drive control unit 200 can output the data signal DATA to the data drive unit 500.

[0119] The drive control unit 200 can generate a third control signal CONT3 based on the input control signal CONT for controlling the operation of the gamma reference voltage generation unit 400. The drive control unit 200 can output the third control signal CONT3 to the gamma reference voltage generation unit 400.

[0120] The drive control unit 200 can generate a fourth control signal CONT4 for controlling the operation of the light-emitting drive unit 600 based on the input control signal CONT. The drive control unit 200 can output the fourth control signal CONT4 to the light-emitting drive unit 600.

[0121] The gate driving unit 300 can generate gate signals for driving multiple gate lines GWL, GIL, and GBL in response to the first control signal CONT1 received from the drive control unit 200. The gate driving unit 300 can output the gate signals to the multiple gate lines GWL, GIL, and GBL.

[0122] The gate driving unit 300 can generate an initialization voltage for driving multiple initialization lines VIL in response to a first control signal CONT1 input from the drive control unit 200. The gate driving unit 300 can output the initialization voltage to the multiple initialization lines VIL.

[0123] The gamma reference voltage generation unit 400 can generate a gamma reference voltage VGREF in response to a third control signal CONT3 input from the drive control unit 200. The gamma reference voltage generation unit 400 can provide the gamma reference voltage VGREF to the data drive unit 500. The gamma reference voltage VGREF can have a value corresponding to each data signal DATA.

[0124] For example, the gamma reference voltage generation unit 400 may be arranged in the drive control unit 200 or in the data drive unit 500.

[0125] The data drive unit 500 can receive a second control signal CONT2 and a data signal DATA from the drive control unit 200, and can receive a gamma reference voltage VGREF from the gamma reference voltage generation unit 400. The data drive unit 500 can use the gamma reference voltage VGREF to convert the data signal DATA into an analog data voltage. The data drive unit 500 can output the analog data voltage to multiple data lines DL.

[0126] The light-emitting drive unit 600 can generate a light-emitting control signal for driving the first light-emitting control line EL1 and the second light-emitting control line EL2 in response to the fourth control signal CONT4 received from the drive control unit 200. The light-emitting drive unit 600 can output the light-emitting control signal to the first light-emitting control line EL1 and the second light-emitting control line EL2.

[0127] Figure 4 It is shown that it includes Figure 3 The circuit diagram of the first sub-pixel in the display device.

[0128] Reference Figure 3 and Figure 4 The first sub-pixel SPX1 included in the display panel 100 may include a first pixel circuit PC1, a 1-1 light-emitting element LE1-1, and a 2-1 light-emitting element LE2-1. The first pixel circuit PC1 can provide a first driving current to the 1-1 light-emitting element LE1-1 and the 2-1 light-emitting element LE2-1. The 1-1 light-emitting element LE1-1 and the 2-1 light-emitting element LE2-1 can emit light of the same color based on the first driving current.

[0129] Each of the first pixel circuits PC1 may include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor, a seventh transistor T7, an eighth transistor T8, a ninth transistor T9 and a tenth transistor T10, a first capacitor C1 and a second capacitor C2.

[0130] The first transistor T1 may include a gate electrode, a first electrode, and a second electrode. The gate electrode of the first transistor T1 may be connected to a second node N2. A drive voltage ELVDD may be applied to the first electrode of the first transistor T1. The second electrode of the first transistor T1 may be connected to a fourth node N4.

[0131] The second transistor T2 may include a gate electrode, a first electrode, and a second electrode. A first gate signal GW may be applied to the gate electrode of the second transistor T2. A data voltage VDATA may be applied to the first electrode of the second transistor T2. The second electrode of the second transistor T2 may be connected to the first node N1.

[0132] The third transistor T3 may include a gate electrode, a first electrode, and a second electrode. A second gate signal GC may be applied to the gate electrode of the third transistor T3. The first electrode of the third transistor T3 may be connected to a third node N3. The second electrode of the third transistor T3 may be connected to a fourth node N4.

[0133] The fourth transistor T4 may include a gate electrode, a first electrode, and a second electrode. A third gate signal GI may be applied to the gate electrode of the fourth transistor T4. A first initialization voltage VINT may be applied to the first electrode of the fourth transistor T4. The second electrode of the fourth transistor T4 may be connected to a third node N3.

[0134] The fifth transistor T5 may include a gate electrode, a first electrode, and a second electrode. A second gate signal GC may be applied to the gate electrode of the fifth transistor T5. A reference voltage VREF may be applied to the first electrode of the fifth transistor T5. The second electrode of the fifth transistor T5 may be connected to the first node N1.

[0135] The sixth transistor (not shown) may include a gate electrode, a first electrode, and a second electrode. The first electrode of the sixth transistor may be connected to the fifth node N5. The second electrode of the sixth transistor may be connected to the fourth node N4. In one or more embodiments, in the first pixel circuit PC1, a first light emission control signal may be applied to the gate electrode of the sixth transistor.

[0136] The seventh transistor T7 may include a gate electrode, a first electrode, and a second electrode. A fourth gate signal GS1 may be applied to the gate electrode of the seventh transistor T7. The first electrode of the seventh transistor T7 may be connected to the sixth node N6. The second electrode of the seventh transistor T7 may be connected to the fifth node N5.

[0137] The eighth transistor T8 may include a gate electrode, a first electrode, and a second electrode. A second initialization voltage VAINT may be applied to the first electrode of the eighth transistor T8. The second electrode of the eighth transistor T8 may be connected to the sixth node N6. In one or more embodiments, in the first pixel circuit PC1, a fifth gate signal GB may be applied to the gate electrode of the eighth transistor T8.

[0138] The ninth transistor T9 may include a gate electrode, a first electrode, and a second electrode. A sixth gate signal GS2 may be applied to the gate electrode of the ninth transistor T9. The first electrode of the ninth transistor T9 may be connected to the seventh node N7, and the second electrode may be connected to the fifth node N5.

[0139] The tenth transistor T10 may include a gate electrode, a first electrode, and a second electrode. A fifth gate signal GB may be applied to the gate electrode of the tenth transistor T10. A second initialization voltage VAINT may be applied to the first electrode of the tenth transistor T10. The second electrode of the tenth transistor T10 may be connected to the seventh node N7.

[0140] The first capacitor C1 may include a first electrode and a second electrode. A driving voltage ELVDD may be applied to the first electrode of the first capacitor C1. The second electrode of the first capacitor C1 may be connected to a first node N1. In one or more embodiments, the first capacitor C1 may be a storage capacitor.

[0141] The second capacitor C2 may include a first electrode and a second electrode. The first electrode of the second capacitor C2 may be connected to a first node N1. The second electrode of the second capacitor C2 may be connected to a second node N2. In one or more embodiments, the second capacitor C2 may be a holding capacitor.

[0142] Each of the 1-1 light-emitting element LE1-1 and the 2-1 light-emitting element LE2-1 may include a first electrode (e.g., a pixel electrode) and a second electrode (e.g., a common electrode). The first electrode of the 1-1 light-emitting element LE1-1 may be connected to a sixth node N6. A common voltage ELVSS may be applied to the second electrode of the 1-1 light-emitting element LE1-1. In one or more embodiments, the 1-1 light-emitting element LE1-1 may be controlled by a fourth gate signal GS1.

[0143] The 2-1 light-emitting element LE2-1 may include a first electrode (e.g., a pixel electrode) and a second electrode (e.g., a common electrode). The first electrode of the 2-1 light-emitting element LE2-1 may be connected to a seventh node N7. A common voltage ELVSS may be applied to the second electrode of the 2-1 light-emitting element LE2-1. In one or more embodiments, the 2-1 light-emitting element LE2-1 may be controlled by a sixth gate signal GS2.

[0144] For example, when the first light-emitting control signal has an active level and the fourth gate signal GS1 has an active level, the seventh transistor T7 and the eighth transistor T8 can be turned on. Furthermore, the first transistor T1 can also be turned on by the data voltage VDATA. In this case, in the first pixel circuit PC1, the first drive current can drive the 1-1 light-emitting element LE1-1 through the first transistor T1.

[0145] On the other hand, for example, when the first light-emitting control signal has an active level and the sixth gate signal GS2 has an active level, the ninth transistor T9 and the tenth transistor T10 can be turned on. Furthermore, the first transistor T1 can also be turned on by the data voltage VDATA. In this case, in the first pixel circuit PC1, the first drive current can drive the 2-1 light-emitting element LE2-1 through the first transistor T1.

[0146] For example, each of the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor, the seventh transistor T7, the eighth transistor T8, the ninth transistor T9, and the tenth transistor T10 may be a P-type thin-film transistor. Embodiments of this disclosure are not limited thereto.

[0147] However, in Figure 4 In the diagram, each of the first sub-pixels SPX1 is shown as comprising ten transistors, two capacitors, and two light-emitting elements, but the embodiments of this disclosure are not limited thereto.

[0148] Figure 5 It is shown that it includes Figure 1 A layout diagram of the pixels in the display area of ​​a display device.

[0149] Reference Figure 5 Each of the plurality of pixels PX in the display area DA may include three sub-pixels SPX1, SPX2, and SPX3, but embodiments of this disclosure are not limited thereto and may include four sub-pixels. When each of the plurality of pixels PX includes three sub-pixels SPX1, SPX2, and SPX3, it may include a first sub-pixel SPX1, a second sub-pixel SPX2, and a third sub-pixel SPX3.

[0150] Multiple pixels PX can be arranged in a matrix. In each of the multiple pixels PX, a first sub-pixel SPX1, a second sub-pixel SPX2, and a third sub-pixel SPX3 can be arranged in a first direction DR1.

[0151] When each of the multiple pixels PX comprises three sub-pixels SPX1, SPX2, and SPX3, the first sub-pixel SPX1 can emit light of a first color, the second sub-pixel SPX2 can emit light of a second color, and the third sub-pixel SPX3 can emit light of a third color. The first color of light can be light in the blue band, the second color of light can be light in the green band, and the third color of light can be light in the red band. For example, the blue band can refer to light with a dominant peak wavelength in the band approximately 370 μm to approximately 460 μm, the green band can refer to light with a dominant peak wavelength in the band approximately 480 μm to approximately 560 μm, and the red band can refer to light with a dominant peak wavelength in the band approximately 600 μm to approximately 750 μm.

[0152] Optionally, when each of the multiple pixels PX comprises four sub-pixels, the first sub-pixel can emit light of a first color, the second and fourth sub-pixels can emit light of a second color, and the third sub-pixel can emit light of a third color. Alternatively, the first sub-pixel can emit light of the first color, the second sub-pixel can emit light of the second color, the third sub-pixel can emit light of the third color, and the fourth sub-pixel can emit light of a fourth color. In this case, the fourth color can be white light.

[0153] Sub-pixels SPX1, SPX2, and SPX3 may include first-type light-emitting elements LE1-1, LE1-2, and LE1-3, and second-type light-emitting elements LE2-1, LE2-2, and LE2-3. For example, the first sub-pixel SPX1 may include a 1-1 light-emitting element LE1-1 as a first-type light-emitting element and a 2-1 light-emitting element LE2-1 as a second-type light-emitting element; the second sub-pixel SPX2 may include a 1-2 light-emitting element LE1-2 as a first-type light-emitting element and a 2-2 light-emitting element LE2-2 as a second-type light-emitting element; and the third sub-pixel SPX3 may include a 1-3 light-emitting element LE1-3 as a first-type light-emitting element and a 2-3 light-emitting element LE2-3 as a second-type light-emitting element.

[0154] The first type of light-emitting element is used to implement a wide-viewing-angle mode or a shared mode (normal mode), and the second type of light-emitting element is used to implement a narrow-viewing-angle mode or a privacy mode. A detailed description will be provided later.

[0155] Figure 6 It is along Figure 5 A sectional view taken by line I-I'. Figure 7 yes Figure 6 A magnified view of region A1. Figure 8 Is as Figure 7Enlarged view of an example of a second type of light-emitting element, 2-1.

[0156] Reference Figure 6 and Figure 7 The substrate SUB can be made of insulating materials such as glass or polymer resin. If the substrate SUB is made of polymer resin, it can be a flexible substrate that can be stretched. Polymer resins can be acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, etc.

[0157] The barrier film (BR) can be disposed on the substrate (SUB). The barrier film (BR) is a film that protects the transistors of the thin-film transistor layer (TFTL) from moisture that permeates through the moisture-sensitive substrate (SUB). The barrier film (BR) can be formed from multiple inorganic films stacked alternately.

[0158] The thin-film transistor TFT1 can be disposed on the barrier film BR. The thin-film transistor TFT1 may include a first active layer ACT1 and a first gate electrode G1. The thin-film transistor TFT1 connected to the first type of light-emitting element can be... Figure 4 The eighth transistor T8. The eighth transistor T8 can turn on the first type of light-emitting element in wide viewing angle mode.

[0159] Additionally, the thin-film transistor TFT1 connected to the second type of light-emitting element can be Figure 4 The tenth transistor T10. The tenth transistor T10 can turn on the second type of light-emitting element in narrow viewing angle mode.

[0160] The first active layer ACT1 of the thin-film transistor TFT1 can be disposed on the barrier film BR. The first active layer ACT1 of the thin-film transistor TFT1 may include polycrystalline silicon, monocrystalline silicon, low-temperature polycrystalline silicon, or amorphous silicon. Optionally, the first active layer ACT1 of the thin-film transistor TFT1 may include an oxide semiconductor comprising IGZO (indium (In), gallium (Ga), zinc (Zn), and oxygen (O)), IGZTO (indium (In), gallium (Ga), zinc (Zn), tin (Sn), and oxygen (O)) or IGTO (indium (In), gallium (Ga), tin (Sn), and oxygen (O)).

[0161] The first active layer ACT1 may include a first channel region CHA1, a first source region S1, and a first drain region D1. The first channel region CHA1 may be a region on the third direction DR3, which is the thickness direction of the substrate SUB, that is superimposed on the first gate electrode G1. The first source region S1 may be disposed on one side of the first channel region CHA1, and the first drain region D1 may be disposed on the other side of the first channel region CHA1. The first source region S1 and the first drain region D1 may be regions on the third direction DR3 that are not superimposed on the first gate electrode G1. The first source region S1 and the first drain region D1 may be conductive regions of a semiconductor material doped with ions.

[0162] The first gate insulating film 131 can be disposed on the first channel region CHA1, the first source region S1, and the first drain region D1 of the thin film transistor TFT1.

[0163] A first gate metal layer may be disposed on a first gate insulating film 131. The first gate metal layer may include a first gate electrode G1 and a first capacitor electrode CAE1 of a thin-film transistor TFT1. The first gate electrode G1 may be stacked on a third-direction DR3 with a first active layer ACT1. Although the first gate electrode G1 and the first capacitor electrode CAE1 are... Figure 6 The first gate electrode G1 and the first capacitor electrode CAE1 are shown to be arranged separately from each other, but the first gate electrode G1 and the first capacitor electrode CAE1 can be connected to each other.

[0164] The second gate insulating film 132 can be disposed on the first gate electrode G1 and the first capacitor electrode CAE1 of the thin film transistor TFT1.

[0165] A second gate metal layer can be disposed on the second gate insulating film 132. The second gate metal layer may include a second capacitor electrode CAE2. The second capacitor electrode CAE2 may be stacked on the third-direction DR3 with the first capacitor electrode CAE1. Because the second gate insulating film 132 has a dielectric constant (e.g., a predetermined dielectric constant), the capacitor ( Figure 4 The first capacitor C1 in the capacitor can be formed by a first capacitor electrode CAE1, a second capacitor electrode CAE2, and a second gate insulating film 132 disposed between them.

[0166] The interlayer insulating film 141 can be arranged on the second capacitor electrode CAE2.

[0167] The first data metal layer may be disposed on the interlayer insulating film 141. The first data metal layer may include a first source connection electrode PCE1. The first source connection electrode PCE1 may be connected to the first drain region D1 of the first active layer ACT1 through a first source contact hole PCT1 that penetrates the first gate insulating film 131, the second gate insulating film 132 and the interlayer insulating film 141.

[0168] The first planarization organic film 160 can be disposed on the first source connection electrode PCE1 to planarize the step caused by the thin film transistor TFT1.

[0169] The second data metal layer can be disposed on the first planarized organic film 160. The second data metal layer may include a second source connection electrode PCE2. The second source connection electrode PCE2 can be connected to the first source connection electrode PCE1 through a second pixel contact hole PCT2 penetrating the first planarized organic film 160.

[0170] The second planarized organic film 180 can be arranged on the second source connection electrode PCE2.

[0171] The barrier film BR, the first gate insulating film 131, the second gate insulating film 132, and the interlayer insulating film 141 can be made of materials such as silicon nitride (SiN). x ), silicon oxynitride (SiON), silicon oxide (SiO) x Titanium oxide (TiO) x ) or aluminum oxide (AlO x Inorganic membrane formation.

[0172] The first gate metal layer, the second gate metal layer, the first data metal layer, and the second data metal layer can be formed as a single layer or multiple layers of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu) or alloys thereof.

[0173] The first planarization organic membrane 160 and the second planarization organic membrane 180 can be formed from organic membranes such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, etc.

[0174] The light-emitting element layer can be disposed on the second planarized organic film 180. The light-emitting element layer may include pixel electrodes PXE1, PXE2 and PXE3 (or PXE1', PXE2' and PXE3'), light-emitting elements LE, and common electrodes CE1, CE2 and CE3 (or CE1', CE2' and CE3').

[0175] The pixel electrode layer, including pixel electrodes PXE1, PXE2 and PXE3 and common electrodes CE1, CE2 and CE3, can be arranged on the second planarized organic film 180.

[0176] Each of the first pixel electrode PXE1, the second pixel electrode PXE2, and the third pixel electrode PXE3 can be connected through a connection hole penetrating the second planarized organic film 180. Figure 5The connection holes CT1 / CT2 / CT3 in the image are connected to the second source connection electrode PCE2. Each of the pixel electrodes PXE1, PXE2, and PXE3 can be connected to the first source region S1 or the first drain region D1 of the thin-film transistor TFT1 via the first source connection electrode PCE1 and the second source connection electrode PCE2. Therefore, a voltage controlled by the thin-film transistor TFT1 can be applied to each of the pixel electrodes PXE1, PXE2, and PXE3.

[0177] Common electrodes CE1, CE2, and CE3 can be connected through a common connection hole ( Figure 5 The common connection holes CT4 / CT5 / CT6 in the middle are connected to the common voltage applied ( Figure 4 The wiring of the common voltage (ELVSS) in the system. Therefore, the common voltage (ELVSS) Figure 4 The common voltage (ELVSS) can be applied to each of the common electrodes CE1, CE2 and CE3.

[0178] The pixel electrode layer can be formed as a single layer or multiple layers of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or alloys thereof. For example, the pixel electrode layer can be made of copper (Cu) with low surface resistance to reduce the resistance of each of the pixel electrodes PXE1, PXE2, and PXE3.

[0179] Multiple light-emitting elements (LEs) can be arranged on each pixel electrode layer. Figure 6 and Figure 7 In the diagram, the light-emitting element LE is shown as a flip-chip microLED. A flip-chip microLED refers to an LED in which contact electrodes CTE1 and CTE2 are formed on one surface (e.g., the bottom surface) of the light-emitting element LE.

[0180] Each of the multiple light-emitting elements (LEs) can be formed from an inorganic material such as gallium nitride (GaN).

[0181] Each of the plurality of light-emitting elements (LEs) can be formed by growth on a semiconductor substrate such as a silicon substrate or a sapphire substrate. The plurality of light-emitting elements (LEs) can be transferred directly from the semiconductor substrate or via a relay substrate to the pixel electrode layer of the display panel 100. Alternatively, the plurality of light-emitting elements (LEs) can be transferred to the pixel electrodes PXE1, PXE2, and PXE3 of the display panel 100 by an electrostatic method using an electrostatic head or by an imprinting method using an elastic polymer material such as PDMS (polydimethylsiloxane) or silicon as a transfer substrate.

[0182] In one or more embodiments, the reflective film may be disposed on the top surface of the pixel electrode PXE1 and the common electrode CE1.

[0183] The reflective film can reflect light traveling downwards from the light-emitting element (LE) and project light onto the top surface of the LE. Therefore, by reducing light loss in the LE, the luminous efficiency of the LE can be increased.

[0184] The reflective film can be formed as a single layer of metal with high reflectivity, or as a multilayer such as titanium (Ti) / aluminum (Al) / titanium (Ti) or ITO / aluminum (Al) / ITO. Furthermore, the reflective film can be formed as a bilayer structure of organic films with different refractive indices. In this case, the organic film with the lower refractive index can be positioned closer to the light-emitting element (LE), and the organic film with the higher refractive index can be positioned further away from the LE.

[0185] consider Figure 6 and Figure 7 Reference Figure 8 The light-emitting element LE may include a first semiconductor layer SEM1, an active layer MQW, a second semiconductor layer SEM2, a first contact electrode CTE1, a second contact electrode CTE2, a first protective film (e.g., a first protective layer) INS1, a first reflective film RFL, a reflective pattern RFP (e.g., the first reflective pattern in the claim) and a second protective film (e.g., a second protective layer) INS2.

[0186] The first semiconductor layer SEM1 can be disposed on the contact electrode. The first semiconductor layer SEM1 can be formed from a semiconductor material layer (such as gallium nitride (GaN)) doped with a first conductive dopant (such as magnesium (Mg), zinc (Zn), calcium (Ca), strontium (Sr), barium (Ba) etc.).

[0187] The active layer MQW can be disposed on the first semiconductor layer SEM1. The active layer MQW can emit light by causing electron-hole pairs to recombine according to an electrical signal applied through the first semiconductor layer SEM1 and the second semiconductor layer SEM2.

[0188] The active layer MQW can include materials having a single quantum well structure or a multi-quantum well structure. When the active layer MQW includes a material with a multi-quantum well structure, it can have a structure in which multiple well layers and barrier layers are stacked alternately. In this case, the well layers can be formed of indium gallium nitride (InGaN), and the barrier layers can be formed of gallium nitride (GaN) or aluminum gallium nitride (AlGaN), but the embodiments disclosed herein are not limited thereto.

[0189] Optionally, the active layer MQW may have a structure in which semiconductor materials with high bandgap energy and semiconductor materials with low bandgap energy are stacked alternately, and may include other group 3 to group 5 semiconductor materials depending on the wavelength range of the emitted light.

[0190] In one or more embodiments, when the active layer MQW comprises InGaN, the color of the emitted light can vary depending on the indium (In) content. For example, as the indium (In) content increases, the wavelength of the light emitted by the active layer MQW can shift to the red band, and as the indium (In) content decreases, the wavelength of the light emitted by the active layer MQW can shift to the blue band. For example, the indium (In) content in the active layer MQW of a light-emitting element LE that emits a third light (light in the blue band) can be approximately 10 wt% to approximately 20 wt%.

[0191] The second semiconductor layer SEM2 can be disposed on the active layer MQW. The second semiconductor layer SEM2 can be a semiconductor material layer (e.g., gallium nitride (GaN)) doped with a second conductive dopant (such as silicon (Si), germanium (Ge), tin (Sn) etc.).

[0192] An electron blocking layer can be disposed between the first semiconductor layer SEM1 and the active layer MQW. The electron blocking layer can be a layer that suppresses, reduces, or prevents excessive electron inflow into the active layer MQW. For example, the electron blocking layer can be aluminum gallium nitride (AlGaN) or p-type aluminum gallium nitride (AlGaN) doped with p-type magnesium (Mg). The electron blocking layer can be omitted.

[0193] A superlattice layer can be disposed between the active layer MQW and the second semiconductor layer SEM2. The superlattice layer can be a layer used to alleviate stress between the second semiconductor layer SEM2 and the active layer MQW. For example, the superlattice layer can be aluminum gallium nitride (AlGaN) or p-type aluminum gallium nitride (AlGaN) doped with p-type magnesium (Mg). The superlattice layer can be omitted.

[0194] The first protective film INS1 can be a film used to protect the bottom and side surfaces of the light-emitting element LE and to reduce or prevent contact between the first reflective film RFL and the semiconductor layer. Therefore, the first protective film INS1 can be made of an inorganic film (such as silicon nitride (SiN)). x ), silicon oxynitride (SiON), silicon oxide (SiO) x Titanium oxide (TiO) x ) or aluminum oxide (AlO x (The insulating film) is formed.

[0195] The first protective film INS1 can be disposed on the bottom surface of the first semiconductor layer SEM1 and the side surfaces of the multiple semiconductor layers SEM1 and SEM2 and the active layer MQW. In addition, the first protective film INS1 can be disposed on the top surface of the second semiconductor layer SEM2, except for the first opening OP1 that exposes a portion of the top surface of the light-emitting element LE (e.g., the top surface of the second semiconductor layer SEM2).

[0196] A hole LEH can be formed by penetrating the first semiconductor layer SEM1 and the active layer MQW of the light-emitting element LE to expose the second semiconductor layer SEM2. The hole LEH can have a rectangular planar shape, but the embodiments of this disclosure are not limited thereto. For example, the hole LEH can have a polygonal planar shape such as a square, a circular planar shape, and an elliptical planar shape.

[0197] Furthermore, the first protective film INS1 can be disposed on the sidewalls of the first semiconductor layer SEM1 exposed by the via LEH and the active layer MQW exposed by the via LEH. The first protective film INS1 may not cover the second semiconductor layer SEM2 in the via LEH. Therefore, the second semiconductor layer SEM2 can be exposed without being covered by the first protective film INS1.

[0198] The first reflective film RFL may surround the side surface of the light-emitting element LE and cover a portion of the top surface of the light-emitting element LE. The first reflective film RFL may have an opening superimposed (e.g., in a plan view) with a first opening OP1 defined by the first protective film INS1. Therefore, the first reflective film RFL may be disposed on the top surface of the light-emitting element LE except for the first opening OP1. The upper surface of the second semiconductor layer SEM2 may still be exposed by the first opening OP1. The first opening OP1 includes the center of the light-emitting element LE and may be disposed in the central region of the top surface of the light-emitting element LE, but is not limited thereto.

[0199] As the first opening OP1 of the first reflective film RFL narrows, the flatness of the light-emitting element LE can be increased. However, since the luminous efficiency may decrease as the first opening OP1 of the first reflective film RFL narrows, the flatness and luminous efficiency of the light-emitting element LE should be considered when designing the area of ​​the first opening OP1.

[0200] The first reflective film RFL may include a metallic material with high reflectivity. For example, the first reflective film RFL may include aluminum or silver, and may also include alloys thereof.

[0201] Optionally, the first reflective film RFL may comprise M pairs of first and second layers (M being an integer greater than or equal to 2) with different refractive indices to function as a distributed Bragg reflector (DBR). In this case, the M first layers and M second layers can be arranged alternately. The first and second layers may be made of inorganic films (such as silicon nitride (SiN)). x ), silicon oxynitride (SiON), silicon oxide (SiO) x Titanium oxide (TiO) x ) or aluminum oxide (AlO x ))form.

[0202] The second protective film INS2 reduces or prevents electrical connections between the first reflective film RFL and other components, and also protects the first reflective film RFL. The second protective film INS2 is disposed on the outer surface of the first reflective film RFL, which is located on at least a portion of the side surface and top surface of the light-emitting element LE. Therefore, through the second protective film INS2, the first reflective film RFL is not electrically connected to the semiconductor layer of the light-emitting element LE or to the contact electrodes CTE1 and CTE2.

[0203] The reflective pattern RFP is arranged between the contact electrode of the light-emitting element LE and the first semiconductor layer SEM1, and is used to change the path of light incident on the reflective pattern RFP.

[0204] Light incident on the reflective pattern RFP may include light emitted downward from the light-emitting element LE, or light emitted from the side surface of the light-emitting element LE and reflected downward from the light-emitting element LE by the first reflective film RFL of the light-emitting element LE.

[0205] The reflective pattern RFP can be formed from multiple triangular shapes (e.g., triangles in cross-section). The cross-section of the reflective pattern RFP can be formed as at least one of right-angled triangles, equilateral triangles, and isosceles triangles. The hypotenuse of each triangle in the reflective pattern RFP can be a reflective surface. The hypotenuse of each triangle in the reflective pattern RFP has a slope (e.g., a predetermined slope) toward the center P of the bottom surface of the light-emitting element LE (e.g., one surface of the first semiconductor layer SEM1) (e.g., generally toward the center P of the bottom surface of the light-emitting element LE (e.g., one surface of the first semiconductor layer SEM1) or in a direction toward the center P of the bottom surface of the light-emitting element LE (e.g., one surface of the first semiconductor layer SEM1). Furthermore, because the first opening OP1 overlaps with the center P, the hypotenuse of the triangle can be inclined toward the first opening OP1 (as used herein, the term "hypotenuse" can more generally refer to the side of the triangle opposite to the angle or angle of the largest of the three angles / angles of the triangle, even if the largest angle / angle is not 90 degrees). The hypotenuses of the patterns arranged on either side of the center P can be arranged to face each other (e.g., facing upwards and towards each other). For example, the reflective pattern RFP may include a first pattern RFP1, a second pattern RFP2, and a third pattern RFP3 arranged to the left of the center P, and a fourth pattern RFP4 arranged to the right of the center P. The first pattern RFP1, the second pattern RFP2, and the third pattern RFP3 can be arranged sequentially from the outside towards the center P. The hypotenuses of the third pattern RFP3 and the fourth pattern RFP4 can face each other.

[0206] Reflective patterned RFPs can be formed from highly reflective metallic materials (such as aluminum (Al)) like reflective films, but are not limited to these. Reflective patterned RFPs can alter the path of light by using refractive index. For example, the reflective effect can be achieved by forming it with organic materials that have a low refractive index. Organic materials can include acrylic resins, epoxy resins, phenolic resins, polyamide resins, polyimide resins, etc.

[0207] The beveled surfaces of the reflective pattern RFP arranged on opposite sides of the center P of the first semiconductor layer SEM1 of the light-emitting element LE can be arranged to face each other.

[0208] The reflective pattern RFP may not be arranged in the area overlapping with the first opening OP1, or it may be omitted from the area overlapping with the first opening OP1.

[0209] The first contact electrode CTE1 and the second contact electrode CTE2 can be disposed on the bottom surface of the semiconductor layer, for example, on one side of the first semiconductor layer SEM1 (as used herein, "disposed on" can mean "below", "adjacent to the side of", and / or "above"). The first contact electrode CTE1 can be disposed on the exposed bottom surface of the first semiconductor layer SEM1 that is not covered by the protective films INS1 and INS2. Therefore, the first contact electrode CTE1 can be electrically connected to the first semiconductor layer SEM1.

[0210] The second contact electrode CTE2 can be disposed on at least one side of the first semiconductor layer SEM1 and at least one side and the bottom surface of the first protective film INS1. In this case, the first contact electrode CTE1 can be disposed on the first side of the semiconductor stack STC and the first side of the first protective film INS1, while the second contact electrode CTE2 can be disposed on the second side of the semiconductor stack STC and the second side of the first protective film INS1.

[0211] The second contact electrode CTE2 can be disposed on the first protective film INS1 disposed in the LEH and on the second semiconductor layer SEM2 exposed in the LEH but not covered by the first protective film INS1. Therefore, the second contact electrode CTE2 can be electrically connected to the second semiconductor layer SEM2 in the LEH.

[0212] The first contact electrode CTE1 and the second contact electrode CTE2 can be disposed on at least a portion of the side surfaces of the plurality of semiconductor layers SEM1 and SEM2 and the active layer MQW. The first contact electrode CTE1 and the second contact electrode CTE2 are separated from the top surface of the light-emitting element LE on the third-direction DR3. For example, among the side surfaces of the plurality of semiconductor layers SEM1 and SEM2 and the active layer MQW, at least the region adjacent to the top surface of the second semiconductor layer SEM2 can be exposed and not covered by the first contact electrode CTE1 and the second contact electrode CTE2. The first contact electrode CTE1 and the second contact electrode CTE2 can be formed below at least one end of the protective films INS1 and INS2.

[0213] The first contact electrode CTE1 and the second contact electrode CTE2 may include one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu). For example, the first contact electrode CTE1 and the second contact electrode CTE2 may be formed as a two-layer structure of chromium (Cr) and gold (Au), a three-layer structure of titanium (Ti), aluminum (Al), and titanium (Ti), or a three-layer structure of indium tin oxide (ITO), silver (Ag), and indium tin oxide (ITO) to increase reflectivity.

[0214] Each of the first contact electrode CTE1 and the second contact electrode CTE2 can be disposed on three side surfaces of the plurality of semiconductor layers SEM1 and SEM2 and the active layer MQW. For example, when the plurality of semiconductor layers SEM1 and SEM2 and the active layer MQW include a first side surface to a third side surface, the first contact electrode CTE1 can be disposed on the first side surface, the second side surface and the third side surface, and the second contact electrode CTE2 can be disposed on the second side surface and the third side surface.

[0215] The first bonding electrode BE1 and the second bonding electrode BE2 can be disposed between the contact electrodes CTE1 and CTE2 of the light-emitting element LE and the pixel electrode layer. For example, the first bonding electrode BE1 can be disposed between the pixel electrode PXE1 and the first contact electrode CTE1, and the second bonding electrode BE2 can be disposed between the common electrode CE1 and the second contact electrode CTE2. The first bonding electrode BE1 and the second bonding electrode BE2 serve as bonding metals for bonding the light-emitting element LE to the pixel electrode PXE1 and the common electrode CE1. The first bonding electrode BE1 and the second bonding electrode BE2 can include any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu).

[0216] On the second planarized organic film 180, separator walls BM can be further arranged to separate each sub-pixel SPX1, SPX2 and SPX3.

[0217] Because the partition wall BM includes light-blocking material to reduce or prevent light from the light-emitting element LE of the sub-pixel from propagating to the adjacent sub-pixel, the partition wall BM is also called a light-blocking layer.

[0218] The partition wall BM can extend across the entire display area DA and be formed in a grid pattern on a plane. The partition wall BM can be independent of multiple light-emitting elements LE on the third-direction DR3. The partition wall BM provides space for forming the first light conversion layer QDL1, the second light conversion layer QDL2, and the light transmission layer TPL. The partition wall BM can be formed of an organic insulating material such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, etc. In other embodiments, the first light conversion layer QDL1, the second light conversion layer QDL2, and the light transmission layer TPL can be omitted.

[0219] The partition wall BM can have a tapered shape that narrows towards the top, but is not limited to this.

[0220] In one or more embodiments, the partition wall BM is formed as a single layer, but is not limited thereto. For example, the partition wall BM may be formed as two layers to provide sufficient space for the first light conversion layer QDL1, the second light conversion layer QDL2, and the light transmission layer TPL to be formed.

[0221] The separator wall BM can include light-blocking materials as described above. For example, the separator wall BM can include inorganic black pigments (such as carbon black) or organic black pigments.

[0222] The second reflective film RF can be disposed inside the space formed by the partition wall BM. The second reflective film RF can be disposed on the side surface of the partition wall BM.

[0223] The second reflective film RF is used to reflect light traveling in the lateral direction from the first light conversion layer QDL1, the second light conversion layer QDL2, and the light transmission layer TPL.

[0224] The second reflective film RF can include a metallic material with high light reflectivity. For example, the second reflective film RF can include aluminum or silver, or an alloy thereof. Furthermore, the second reflective film RF can be formed as a bilayer structure of organic films with different refractive indices. In this case, the organic film with the lower refractive index can be positioned closer to the light-emitting element LE, and the organic film with the higher refractive index can be positioned further away from the light-emitting element LE.

[0225] In the first sub-pixel SPX1, the first light conversion layer QDL1 can be arranged between the separator BM and the separator BM. In the second sub-pixel SPX2, the second light conversion layer QDL2 can be arranged between the separator BM and the separator BM. In the third sub-pixel SPX3, the light transmission layer TPL can be arranged between the separator BM and the separator BM.

[0226] The first light conversion layer QDL1 can convert a portion of the third light (light in the blue band) incident from the light-emitting element LE into first light (light in the red band). The first light conversion layer QDL1 may include a first matrix resin BRS1 and first wavelength conversion particles WCP1. The first matrix resin BRS1 may include a light-transmitting organic material. The first wavelength conversion particles WCP1 can convert a portion of the third light (light in the blue band) incident from the light-emitting element LE into first light (light in the red band).

[0227] The second light conversion layer QDL2 can convert a portion of the third light (light in the blue band) incident from the light-emitting element LE into a second light (light in the green band). The second light conversion layer QDL2 may include a second matrix resin BRS2 and second wavelength conversion particles WCP2. The second matrix resin BRS2 may include a light-transmitting organic material. The second wavelength conversion particles WCP2 can convert a portion of the third light (light in the blue band) incident from the light-emitting element LE into the second light (light in the green band).

[0228] The light-transmitting layer (TPL) can include light-transmitting organic materials.

[0229] For example, the first matrix resin BRS1, the second matrix resin BRS2, ​​and the light-transmitting layer TPL may include epoxy resins, acrylic resins, cardo resins, or imide resins. The first wavelength conversion particle WCP1 and the second wavelength conversion particle WCP2 may be quantum dots (QDs), quantum rods, fluorescent materials, or phosphorescent materials.

[0230] The capping layer CAP can be arranged on the partition wall BM, the first optical conversion layer QDL1, the second optical conversion layer QDL2, and the optical transmission layer TPL.

[0231] The capping layer (CAP) can be made of materials such as silicon nitride (SiN). x ), silicon oxynitride (SiON), silicon oxide (SiO) x Titanium oxide (TiO) x ) or aluminum oxide (AlO x An inorganic film is formed. The first light conversion layer QDL1, the second light conversion layer QDL2, and the light transmission layer TPL can be encapsulated by a capping layer CAP.

[0232] A fourth organic membrane (or outer coating) 213 may be disposed on the capping layer CAP. Multiple color filters CF1, CF2, and CF3 may be disposed on the fourth organic membrane 213. The multiple color filters CF1, CF2, and CF3 may include a first color filter CF1, a second color filter CF2, and a third color filter CF3.

[0233] A first color filter CF1 disposed in the first sub-pixel SPX1 can transmit first light (light in the red band) and can absorb or block third light (light in the blue band). Therefore, the first color filter CF1 can transmit the first light (light in the red band) converted by the first light conversion layer QDL1 from the third light (light in the blue band) emitted from the light-emitting element LE, and absorb or block the third light (light in the blue band) that is not converted by the first light conversion layer QDL1. Therefore, the first sub-pixel SPX1 can emit first light (light in the red band).

[0234] The second color filter CF2, disposed in the second sub-pixel SPX2, can transmit second light (light in the green band) and absorb or block third light (light in the blue band). Therefore, the second color filter CF2 can transmit the second light (light in the green band) converted by the first light conversion layer QDL1 from the third light (light in the blue band) emitted from the light-emitting element LE, and absorb or block the third light (light in the blue band) that is not converted by the first light conversion layer QDL1. Thus, the second sub-pixel SPX2 can emit second light (light in the green band).

[0235] The third color filter CF3, arranged in the third sub-pixel SPX3, can transmit third light (light in the blue band). Therefore, the third color filter CF3 can transmit third light (light in the blue band) emitted from the light-emitting element LE that passes through the light-transmitting layer TPL. Therefore, the third sub-pixel SPX3 can emit third light (light in the blue band).

[0236] The first color filter CF1, the second color filter CF2, and the third color filter CF3, which are stacked on the third-direction DR3, can be stacked with the partition wall BM on the third-direction DR3.

[0237] In one or more other embodiments, the first color filter CF1, the second color filter CF2, and the third color filter CF3 may be omitted.

[0238] The fifth organic membrane 214 for planarization can be arranged on multiple color filters CF1, CF2 and CF3.

[0239] The fourth organic membrane 213 and the fifth organic membrane 214 can be formed from acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, etc.

[0240] Figure 9 Is as Figure 7 Enlarged view of another example of the second type of light-emitting element, 2-1.

[0241] Figure 9 and Figure 8 The difference in this embodiment is that the first protective film INS1, the first reflective film RFL, and the second protective film INS2 are not arranged on the upper part of the light-emitting element LE. Figure 9 In the middle, omission and Figure 8 The embodiments are described repeatedly, and the main description is consistent with... Figure 7 The differences between the embodiments.

[0242] The first protective film INS1 may surround the side surfaces of semiconductor layers SEM1 and SEM2, the active layer MQW, and a portion of the bottom surface of the first semiconductor layer SEM1. The first reflective film RFL may surround one side of the light-emitting element LE outside the first protective film INS1. The second protective film INS2 may surround one side of the light-emitting element LE on top of the first reflective film RFL. The second protective film INS2 may cover the end of the first reflective film RFL adjacent to the contact electrodes CTE1 and CTE2 to reduce or prevent contact between one end of the first reflective film RFL and the contact electrodes CTE1 and CTE2.

[0243] Figure 10 According to one or more other embodiments Figure 6 A magnified view of region A1. Figure 11 yes Figure 10 A magnified view of region B.

[0244] Figure 10 and Figure 7 The difference in this embodiment is that it has a second reflective pattern REP on the partition wall BM. Figure 10 In the middle, omission and Figure 7 The embodiments are described repeatedly, and the main description is consistent with... Figure 7 The differences between the embodiments.

[0245] For ease of explanation, the reflective pattern included in the light-emitting element LE is referred to as the first reflective pattern RFP.

[0246] Reference Figure 10 The second reflective pattern REP may be formed as one or more triangular hills (e.g., triangles in cross-section) on the side adjacent to the upper part of the partition wall BM. The cross-section of the second reflective pattern REP may be formed as at least one triangular shape among right-angled triangles, equilateral triangles, and isosceles triangles.

[0247] Each triangular hill of the second reflective pattern REP includes an inclined surface (e.g., a first surface) REPa formed by projecting at a corresponding angle from one side of the partition wall BM, and a side surface (e.g., a second surface) REPb that contacts the side of the partition wall BM (e.g., fully contacts one side of the partition wall BM). The second reflective pattern REP includes a bevel (e.g., a third surface) REPc formed along the angle of the tip formed by the inclined surface REPa and the side surface REPb. That is, the bevel REPc can extend from the end of the inclined surface REPa to the end of the side surface REPb. The inclined surface REPa can be positioned above the bevel REPc, and the bevel REPc can be arranged to face the light-emitting element LE. The opening defined by the partition wall BM can be narrowed by the inclined surface REPa. The angle θ formed by the inclined surface REPa and the side surface REPb can be about 90 degrees or greater.

[0248] The partition wall BM can be formed above the light-emitting element LE2-1, and the second reflective pattern REP can be arranged above the light-emitting element LE2-1. For example, the partition wall BM can be about twice or more the height of the light-emitting element LE2-1. The height of the light-emitting element LE2-1 can be about 5 μm or less, and the height of the partition wall BM can be about 10 μm or more. The second reflective pattern REP can be arranged in the height direction between about 5 μm and about 10 μm from the top of the partition wall BM.

[0249] The second reflective pattern REP can be formed from a highly reflective metallic material such as aluminum (Al), such as a reflective film, but is not limited to this.

[0250] The first reflective pattern RFP and the second reflective pattern REP can control the path of light emitted or reflected from the light-emitting element LE2-1 to limit the light-emitting area. Therefore, when the display device 10 employs the first reflective pattern RFP and the second reflective pattern REP, an effective narrow viewing angle mode can be provided.

[0251] Figure 12 According to one or more other embodiments Figure 10 A magnified view of region B.

[0252] Figure 12 and Figure 11 The difference in this embodiment is that it has a second reflective film RF on the outside of the separator wall BM. Figure 12 In the middle, omission and Figure 11 The embodiments are described repeatedly, and the main description is consistent with... Figure 11 The differences between the embodiments.

[0253] Reference Figure 12The second reflective film RF can be disposed inside the space formed by the partition wall BM. The second reflective film RF can be disposed on the side surface of the partition wall BM.

[0254] The second reflective film RF is used to reflect light that travels in the lateral direction in the first light conversion layer QDL1, the second light conversion layer QDL2, and the light transmission layer TPL.

[0255] The second reflective film RF may include a metallic material with high light reflectivity. For example, the second reflective film RF may include aluminum or silver, or may include an alloy of aluminum or silver.

[0256] The second reflective pattern REP can be formed into one or more triangular mountain shapes on the outer side of the second reflective film RF, adjacent to the upper part of the separator wall BM.

[0257] The cross-section of the second reflective pattern REP can be formed as at least one of the following triangular shapes: right triangle, equilateral triangle, and isosceles triangle.

[0258] Each triangular peak of the second reflective pattern REP includes an inclined surface (e.g., a first surface) REPa formed by projecting at a corresponding angle from one side of the partition wall BM, and a side surface (e.g., a second side surface) REPb on the side that contacts the second reflective film RF. The second reflective pattern REP includes a beveled edge (e.g., a third surface) REPc formed at an angle along the tip portion formed by the inclined surface REPa and the side surface REPb (e.g., extending from the inclined surface REPa to the side surface REPb). The inclined surface REPa may be positioned above the beveled edge REPc, and the beveled edge REPc may be arranged to face the light-emitting element LE. The opening defined by the partition wall BM may be narrowed by the inclined surface REPa. The angle θ between the inclined surface REPa and the side surface REPb may be greater than 90 degrees.

[0259] Figure 13 This illustrates the display panel along one or more other embodiments. Figure 5 An example of a cross-sectional view taken by line I-I'. Figure 14 It is shown in detail Figure 13 A cross-sectional view of the example area A2.

[0260] Figure 13 and Figure 14 and Figure 6 and Figure 7 The difference lies in that the light-emitting element LE has an optical pattern LP on its top, and the separator BM includes a first separator BM1 and a second separator BM2. Figure 13 and Figure 14 In the middle, omission and Figure 6 and Figure 7The embodiments are described repeatedly, and the main description is consistent with... Figure 6 and Figure 7 The differences between the embodiments.

[0261] An optical pattern LP is disposed on the upper part of the light-emitting element LE and has a concave lens shape (e.g., recessed downwards). The optical pattern LP may contact at least a portion of the top surface of the light-emitting element LE. The width of the optical pattern LP may be wider than the width of the light-emitting element LE. The optical pattern LP may completely cover the light-emitting element LE, but is not limited thereto.

[0262] Optical patterns (LP) are used to refract light emitted from the top of the light-emitting element (LE). For example, optical patterns (LP) can focus light to provide a narrow viewing angle.

[0263] The separator BM may include a first separator BM1 and a second separator BM2. The first separator BM1 may be disposed on the second planarized organic membrane 180, and the second separator BM2 may be disposed on the first separator BM1.

[0264] Each of the first partition wall BM1 and the second partition wall BM2 may have a constant tapered shape whose width decreases as it moves upward, but is not limited thereto. The second reflective film RF may be disposed within the space formed by the first partition wall BM1 and the second partition wall BM2. The second reflective film RF may be disposed on the side surfaces of the first partition wall BM1 and the second partition wall BM2.

[0265] The first light conversion layer QDL1, the second light conversion layer QDL2, and the light transmission layer TPL can be formed in the space formed by the first partition wall BM1 and the second partition wall BM2.

[0266] When the partition wall BM is formed as multiple layers, the first light conversion layer QDL1 and the second light conversion layer QDL2 can have sufficient space. Therefore, it has the advantage of being able to perform light conversion effectively and increasing the thickness of the display device 10.

[0267] Figure 15 It shows the display panel and Figure 5 A cross-sectional view of an example of the section corresponding to line II-II'. Figure 16 It is shown in detail Figure 15 A cross-sectional view of an example of the first type of light-emitting element.

[0268] consider Figure 5 Reference Figure 15 and Figure 16 The first sub-pixel SPX1 may include a 1-1 light-emitting element LE1-1 as a first type of light-emitting element and a 2-1 light-emitting element LE2-1 as a second type of light-emitting element.

[0269] The substrate SUB can be made of insulating materials such as glass or polymer resin.

[0270] Thin-film transistor (TFTL) layers can be arranged on a substrate SUB.

[0271] The thin-film transistor layer (TFTL) may include a barrier film (BR), a thin-film transistor (TFT1), a first gate insulating film (131), a second gate insulating film (132), an interlayer insulating film (141), a first planarizing organic film (160), and a second planarizing organic film (180). (See reference...) Figure 6 The thin-film transistor layer (TFTL) is described in detail, and redundant descriptions will not be repeated.

[0272] The pixel electrodes PXE1 and PXE1' and the common electrodes CE1 and CE1' can be arranged on the second planarized organic film 180.

[0273] 1-1 Light-emitting element LE1-1 can be arranged on pixel electrode PXE1 and common electrode CE1, and 2-1 Light-emitting element LE2-1 can be arranged on pixel electrode PXE1' and common electrode CE1'.

[0274] Already referred to Figure 8 and Figure 9 The detailed description of the 2-1 light-emitting element LE2-1 is described in detail, so the description will not be repeated.

[0275] Reference Figure 16 1-1 Light-emitting element LE1-1 and Figure 9 The difference between the LE2-1 2-1 light-emitting element and the LE2-1 is that it does not include the reflective pattern RFP.

[0276] Already referred to Figure 8 and Figure 9 The light-emitting element LE2-1 has been described in detail, so the description will not be repeated.

[0277] After selectively irradiating each sub-pixel with a first type of light-emitting element using a laser lift-off (LLO) process, a second type of light-emitting element can be selectively irradiated onto each sub-pixel using a laser lift-off (LLO) process to transfer light-emitting elements with different structures onto the substrate. This transfer method is an example and is not limited to it.

[0278] Figure 17 This illustrates a display panel according to one or more other embodiments. Figure 5 A cross-sectional view of an example of the section corresponding to line II-II'.

[0279] Reference Figure 17The first optical lens LP1 is arranged on the upper part of the 1-1 light-emitting element LE1-1, and the second optical lens LP2 is arranged on the upper part of the 2-1 light-emitting element LE2-1. This is consistent with... Figure 15 The implementation methods differ. Figure 17 In the middle, omission and Figure 15 The embodiments are described repeatedly, and the main description is consistent with... Figure 15 The differences between the embodiments.

[0280] Reference Figure 17 The first optical lens LP1 is arranged in the shape of an upwardly convex lens on the upper part of the 1-1 light-emitting element LE1-1. The width of the first optical lens LP1 may be wider than the width of the 1-1 light-emitting element LE1-1. The first optical lens LP1 can completely cover the 1-1 light-emitting element LE1-1. The first optical lens LP1 can diffuse the light emitted from the 1-1 light-emitting element LE1-1, thereby helping the display device 10 to provide a wide viewing angle.

[0281] The second optical lens LP2 is arranged above the 2-1 light-emitting element LE2-1 in a concave lens shape (e.g., downwardly recessed). The width of the second optical lens LP2 may be wider than the width of the 2-1 light-emitting element LE2-1. The second optical lens LP2 may completely cover the 2-1 light-emitting element LE2-1. The second optical lens LP2 may focus the light emitted from the 2-1 light-emitting element LE2-1, thereby helping the display device 10 to provide a narrow viewing angle.

[0282] Figure 18 It is a layout diagram showing the pixels of a display area according to one or more embodiments.

[0283] Figure 18 Implementation examples and Figure 5 The difference in the embodiment is that the light-emitting element LE is stacked with pixel electrodes PXE1, PXE2, and PXE3 in each of the first sub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixel SPX3. Figure 18 In the embodiments, the related Figure 5 The embodiments are described repeatedly.

[0284] Reference Figure 18The first sub-pixel SPX1 includes first pixel electrodes PXE1 and PXE1', multiple first-type light-emitting elements LE1-1, second-type light-emitting elements LE2-1, and first light conversion layers QDL1 and QDL1'. The second sub-pixel SPX2 includes second pixel electrodes PXE2 and PXE2', multiple first-type light-emitting elements LE1-2, and second light conversion layers QDL2 and QDL2'. The third sub-pixel SPX3 includes third pixel electrodes PXE3 and PXE3', multiple first-type light-emitting elements LE1-3, second-type light-emitting elements LE2-3, and a light transmission layer (or a third light conversion layer) TPL.

[0285] Each of the first pixel electrode PXE1, the second pixel electrode PXE2, and the third pixel electrode PXE3 can have a rectangular planar shape with a short side in the first direction DR1 and a long side in the second direction DR2. The area of ​​the first sub-pixel SPX1, the area of ​​the second sub-pixel SPX2, and the area of ​​the third sub-pixel SPX3 can be set according to the light conversion efficiency of the first light conversion layer QDL1 and the second light conversion layer QDL2. For example, the lower the light conversion efficiency, the larger the area of ​​the sub-pixel can be.

[0286] Each of pixel electrodes PXE1, PXE2, and PXE3 can be electrically connected to at least one transistor via pixel connection holes CT1, CT2, and / or CT3. For example, each of pixel electrodes PXE1, PXE2, and PXE3 can be electrically connected to a fourth transistor of the corresponding sub-pixel. Figure 4 The second electrode of the fourth transistor T4 and the sixth transistor ( Figure 4 The second electrode of the sixth transistor in the process.

[0287] Multiple light-emitting elements (LEs) can be arranged on each of pixel electrodes PXE1, PXE2, and PXE3. The same number of light-emitting elements (LEs) can be arranged on each of pixel electrodes PXE1, PXE2, and PXE3. For example, two light-emitting elements (LEs) can be arranged on each of pixel electrodes PXE1, PXE2, and PXE3. The light-emitting elements (LEs) arranged on a pixel electrode PXE1, PXE2, and PXE3 are of the same type. For example, the two light-emitting elements (LEs) arranged on the first pixel electrode PXE1 can be first-type light-emitting elements LE1-1.

[0288] The first light conversion layer QDL1 can be completely stacked with the multiple light-emitting elements LE of the first sub-pixel SPX1 and the first pixel electrode PXE1. The area of ​​the first light conversion layer QDL1 can be larger than the area of ​​the first pixel electrode PXE1. The first light conversion layer QDL1 can convert or shift the peak wavelength of the incident light to another corresponding peak wavelength and emit light. For example, the first light conversion layer QDL1 can convert or shift the third light emitted from the multiple light-emitting elements LE of the first sub-pixel SPX1 into the first light.

[0289] The second light conversion layer QDL2 can be completely stacked with the second pixel electrode PXE2 and multiple light-emitting elements LE of the second sub-pixel SPX2. The area of ​​the second light conversion layer QDL2 can be larger than the area of ​​the second pixel electrode PXE2. The second light conversion layer QDL2 can convert or shift the peak wavelength of the incident light to another corresponding peak wavelength and then emit it. For example, the second light conversion layer QDL2 can convert or shift the third light emitted from the multiple light-emitting elements LE of the second sub-pixel SPX2 into second light.

[0290] The light-transmitting layer TPL can be completely stacked with the third pixel electrode PXE3 and multiple light-emitting elements LE of the third sub-pixel SPX3. The light-transmitting layer TPL can directly transmit incident light. For example, the light-transmitting layer TPL can directly transmit third light emitted from the multiple light-emitting elements LE of the third sub-pixel SPX3.

[0291] Figure 19 It shows the display panel and Figure 18 A cross-sectional view of an example of the section corresponding to line I1-I1'. Figure 20 It is shown in detail Figure 19 A cross-sectional view of the example area A2. Figure 21 Is as Figure 20 Enlarged view of an example of a second type of light-emitting element, 2-1. Figure 22 Is as Figure 20 Enlarged view of another example of the second type of light-emitting element, 2-1.

[0292] Figure 19 and Figure 20 Implementation examples and Figure 6 and Figure 7 The difference in the embodiment is that each of the plurality of light-emitting elements LE is a vertical micro-LED extending on a third-direction DR3. A vertical micro-LED refers to an LED having a structure in which a first semiconductor layer SEM1, an active layer MQW, and a second semiconductor layer SEM2 are arranged sequentially on a third-direction DR3, which is a vertical direction.

[0293] exist Figure 19 and Figure 20In the embodiments, the repetition with Figure 6 and Figure 7 The description of the embodiments is repeated.

[0294] Reference Figure 19 and Figure 20 The pixel electrode layer can be disposed on the second planarized organic film 180. The pixel electrode layer may include a first pixel electrode PXE1', a second pixel electrode PXE2', and a third pixel electrode PXE3'.

[0295] In one or more embodiments, the reflective layer may be disposed on the top surface of the first pixel electrode PXE1', the second pixel electrode PXE2', and the third pixel electrode PXE3'.

[0296] The reflective layer can reflect light traveling downwards from the second-type light-emitting elements LE2-1, LE2-2, and LE2-3, and emit light onto the top surfaces of the second-type light-emitting elements LE2-1, LE2-2, and LE2-3. Therefore, because light loss of the second-type light-emitting elements LE2-1, LE2-2, and LE2-3 can be reduced, the light efficiency of the second-type light-emitting elements LE2-1, LE2-2, and LE2-3 can be improved.

[0297] The second type of light-emitting elements LE2-1, LE2-2 and LE2-3 are arranged on the first pixel electrode PXE1', the second pixel electrode PXE2' and the third pixel electrode PXE3'.

[0298] Each of the plurality of second-type light-emitting elements LE2-1, LE2-2, and LE2-3 may have a length of several μm to several hundred μm in the first direction DR1, a length in the second direction DR2, and a length in the third direction DR3, respectively. For example, each of the plurality of second-type light-emitting elements LE2-1, LE2-2, and LE2-3 may have a length of approximately 100 μm or less in the first direction DR1, a length in the second direction DR2, and a length in the third direction DR3, respectively.

[0299] Reference Figure 21 The second type of light-emitting elements LE2-1, LE2-2 and LE2-3 may include a conductive layer, a first semiconductor layer SEM1, an active layer MQW, a second semiconductor layer SEM2, a contact electrode CTE, a first protective film INS1, a first reflective film RFL and a second protective film INS2.

[0300] The first protective film INS1 can be a film used to protect the bottom and side surfaces of the light-emitting element LE and to reduce or prevent contact between the first reflective film RFL and the semiconductor layer. Therefore, the first protective film INS1 can be made of an inorganic film (such as silicon nitride (SiN)). x), silicon oxynitride (SiON), silicon oxide (SiO) x Titanium oxide (TiO) x ) or aluminum oxide (AlO x (The insulating film) is formed.

[0301] The protective film (e.g., the first protective film INS1 and / or the second protective film INS2) can be made of materials such as silicon nitride (SiN). x ), silicon oxynitride (SiON), silicon oxide (SiO) x Titanium oxide (TiO) x ) or aluminum oxide (AlO x Inorganic membrane formation.

[0302] The protective film has one or more openings for electrically connecting the first semiconductor layer SEM1 and the contact electrodes CTE. In one or more embodiments, the first protective film INS1 includes one opening. The contact electrodes CTE may be disposed on the first protective film INS1. Each of the plurality of contact electrodes CTE may be disposed between the pixel electrodes PXE1', PXE2', and PXE3' and the first protective film INS1. The contact electrodes CTE may be connected to the first semiconductor layer SEM1 that is exposed and not covered by the first protective film INS1.

[0303] Contact electrode CTEs can include one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu). For example, multiple contact electrode CTEs can be formed as a two-layer structure of chromium (Cr) and gold (Au), a three-layer structure of titanium (Ti), aluminum (Al), and titanium (Ti), or a three-layer structure of indium tin oxide (ITO), silver (Ag), and indium tin oxide (ITO) to increase reflectivity.

[0304] The first reflective film RFL can surround the side surface of the light-emitting element LE on the first protective film INS1. The first reflective film RFL may not be arranged on the light-emitting element LE, but is not limited thereto.

[0305] The second protective film INS2 reduces or prevents electrical connections between the first reflective film RFL and other components, and also protects the first reflective film RFL. The second protective film INS2 covers the side surfaces and both ends of the light-emitting element LE on the outer surface of the first reflective film RFL to protect it. Therefore, through the second protective film INS2, the first reflective film RFL is not electrically connected to the semiconductor layer of the light-emitting element LE or to the contact electrodes CTE1 and CTE2.

[0306] In one or more other embodiments, such as Figure 22As shown, the first reflective film RFL may surround the side surface of the light-emitting element LE and may cover a portion of the top surface of the light-emitting element LE. The first reflective film RFL may have an opening superimposed on the first opening OP1 defined by the first protective film INS1. Therefore, the first reflective film RFL may be disposed on the top surface of the light-emitting element LE except for the first opening OP1. The top surface of the second semiconductor layer SEM2 may still be exposed by the first opening OP1. The first opening OP1 includes the center of the light-emitting element LE and may be disposed in the central region of the top surface of the light-emitting element LE, but is not limited thereto.

[0307] As the opening of the first reflective film RFL narrows, the flatness of the light-emitting element LE can be increased. However, since the luminous efficiency may decrease as the opening of the first reflective film RFL narrows, the flatness and luminous efficiency of the light-emitting element LE should be considered when designing the area of ​​the first opening OP1.

[0308] The common electrode CE can be disposed on the top surface of each of the plurality of second-type light-emitting elements. For example, the common electrode CE can be electrically connected to the second semiconductor layer SEM2 of the second-type light-emitting element. The common electrode CE can be a common layer formed in the first sub-pixel SPX1', the second sub-pixel SPX2', and the third sub-pixel SPX3'.

[0309] The common electrode CE can be made of a transparent conductive material (TCO) that can transmit light (such as indium tin oxide (ITO) and indium zinc oxide (IZO)).

[0310] Pixel electrodes PXE1', PXE2', and PXE3' can be referred to as anode electrodes or first electrodes, and the common electrode CE can be referred to as cathode electrode or second electrode. A bonding electrode BE can be positioned between the contact electrode CTE and the pixel electrode PXE1.

[0311] Figure 23 This illustrates the display panel along one or more other embodiments. Figure 18 An example sectional view of the section cut by line II1-II1'. Figure 24 It is shown in detail Figure 23 A cross-sectional view of an example of the first type of light-emitting element.

[0312] consider Figure 18 Reference Figure 23 and Figure 24 The first sub-pixel SPX1 may include a 1-1 light-emitting element LE1-1 as a first type of light-emitting element and a 2-1 light-emitting element LE2-1 as a second type of light-emitting element.

[0313] The first type transistor of the first sub-pixel SPX1 can be controlled to be... Figure 4The seventh transistor T7 in the middle is driven, and the second type of transistor can be controlled by... Figure 4 The ninth transistor T9 in the circuit is driven.

[0314] The substrate SUB can be made of insulating materials such as glass or polymer resin.

[0315] Thin-film transistor (TFTL) layers can be arranged on a substrate SUB.

[0316] The thin-film transistor layer (TFTL) may include a barrier film (BR), a thin-film transistor (TFT1), a first gate insulating film (131), a second gate insulating film (132), an interlayer insulating film (141), a first planarizing organic film (160), and a second planarizing organic film (180). (See reference...) Figure 6 The thin-film transistor layer (TFTL) has been described in detail, so redundant descriptions will not be repeated.

[0317] Pixel electrodes PXE1 and PXE1' can be arranged on the second planarized organic film 180.

[0318] 1-1 Light-emitting element LE1-1 can be arranged on pixel electrode PXE1, and 2-1 Light-emitting element LE2-1 can be arranged on pixel electrode PXE1'.

[0319] Already referred to Figure 21 and Figure 22 The detailed description of the 2-1 light-emitting element LE2-1 is described in detail, so redundant descriptions will not be repeated.

[0320] Reference Figure 24 1-1 Light-emitting element LE1-1 and Figure 21 The difference between the LE2-1 2-1 light-emitting element and the LE2-1 is that it does not include the reflective pattern RFP.

[0321] Figure 25 This illustrates the display panel along one or more other embodiments. Figure 18 An example sectional view of the section cut by line II1-II1'.

[0322] Reference Figure 25 The first optical lens LP1 is arranged on the upper part of the 1-1 light-emitting element LE1-1, and the second optical lens LP2 is arranged on the upper part of the 2-1 light-emitting element LE2-1. This is consistent with... Figure 23 The implementation methods differ. Figure 25 In the middle, omission and Figure 23 The embodiments are described repeatedly, and the main description is consistent with... Figure 23 The differences between the embodiments.

[0323] Reference Figure 25The first optical lens LP1 is arranged in the shape of an upwardly convex lens on the upper part of the 1-1 light-emitting element LE1-1. The width of the first optical lens LP1 may be wider than the width of the 1-1 light-emitting element LE1-1. The first optical lens LP1 can completely cover the 1-1 light-emitting element LE1-1. The first optical lens LP1 can diffuse the light emitted from the 1-1 light-emitting element LE1-1, thereby helping the display device 10 to provide a wide viewing angle.

[0324] The second optical lens LP2 is arranged above the 2-1 light-emitting element LE2-1 in a concave lens shape (e.g., downwardly recessed). The width of the second optical lens LP2 may be wider than the width of the 2-1 light-emitting element LE2-1. The second optical lens LP2 may completely cover the 2-1 light-emitting element LE2-1. The second optical lens LP2 may focus the light emitted from the 2-1 light-emitting element LE2-1, thereby helping the display device 10 to provide a narrow viewing angle.

[0325] Figure 26 It is along one or more other embodiments Figure 5 A sectional view taken by line I-I'. Figure 27 yes Figure 26 A magnified view of region B1.

[0326] Figure 26 and Figure 27 and Figure 6 and Figure 7 The difference in this embodiment is that the first light conversion layer QDL1, the second light conversion layer QDL2, the light transmission layer TPL, and the multiple color filters CF1, CF2, and CF3 are not arranged. Figure 26 and Figure 27 In the middle, omission and Figure 6 and Figure 7 The embodiments are described repeatedly, and the main description is consistent with... Figure 6 and Figure 7 The differences between the embodiments.

[0327] Reference Figure 26 and Figure 27 The capping layer CAP can be arranged on the light-emitting element LE and the separator BM.

[0328] The light-emitting element (LE) and the separator wall (BM) can be surrounded by the cover layer (CAP).

[0329] The fourth organic membrane 213 can be arranged on the capping layer CAP.

[0330] The fifth organic membrane 214 can be disposed on the fourth organic membrane 213. The fourth organic membrane 213 or the fifth organic membrane 214 can be omitted.

[0331] Figure 28This illustrates the display panel along one or more other embodiments. Figure 5 An example sectional view of the section cut by line II-II'.

[0332] Figure 28 and Figure 15 The difference in this embodiment is that the first light conversion layer QDL1, the second light conversion layer QDL2, the light transmission layer TPL, and the multiple color filters CF1, CF2, and CF3 are not arranged. Figure 28 In the middle, omission and Figure 15 The embodiments are described repeatedly, and the main description is consistent with... Figure 15 The differences between the embodiments.

[0333] consider Figure 26 Reference Figure 28 The light-emitting element (LE) and the separator wall (BM) can be surrounded by the cover layer (CAP).

[0334] The fourth organic membrane 213 can be arranged on the capping layer CAP.

[0335] The fifth organic membrane 214 can be disposed on the fourth organic membrane 213. The fourth organic membrane 213 or the fifth organic membrane 214 can be omitted.

[0336] Figure 29 and Figure 30 This is a diagram illustrating a smartwatch including a display device according to one or more embodiments.

[0337] Reference Figure 29 and Figure 30 The display device 10_1 according to one or more embodiments can be applied to a smartwatch 1000_1, which is one of the smart devices.

[0338] The flat shape of the display device 10_1 can be square or circular, but is not limited to this, and can be modified in various ways (such as ellipse).

[0339] Figure 31 This is an exploded perspective view of a smartwatch including a display device according to one or more embodiments.

[0340] Reference Figure 31 The smartwatch 1000_1 may include a main unit BP and a wearable unit BD.

[0341] The main unit BP may include a display panel 100 on which images are displayed, a cover window CW on the display panel 100, a bottom cover BC below the display panel 100, an intermediate frame MF between the cover window CW and the bottom cover BC, and a battery BT between the intermediate frame MF and the bottom cover BC. In addition to the battery BT, the main processor controlling the smartwatch 1000_1, a communication chipset for wireless communication with external devices, and a circuit board containing memory, etc., may be additionally arranged between the intermediate frame MF and the bottom cover BC.

[0342] The main unit BP can sequentially include the bottom cover BC, battery BT, middle frame MF, display panel 100, and cover window CW.

[0343] A cover window (CW) is disposed on the upper part of the display panel 100 to protect the display panel 100 and transmit light emitted from the display panel 100. As described above, the cover window CW may include a light-blocking portion to block a portion of the light emitted from the display panel 100. The cover window CW may be made of transparent plastic, glass, or tempered glass.

[0344] The overlay window CW can be arranged to overlap with the display panel 100 and cover the front of the display panel 100. The overlay window CW typically has a shape similar to that of the display panel 100 in planar respects, but its size can be larger than that of the display panel 100. For example, the overlay window CW can protrude outwards from the display panel 100. The planar shape of the overlay window CW can be the same as the planar shape of the main unit BP. For example, the planar shape of the overlay window CW can be approximately circular, but is not limited to this, and can have various shapes, such as polygons or ellipses, like squares.

[0345] The intermediate frame MF is a connecting member used to join the cover window CW and the bottom cover BC, and is arranged between the cover window CW and the bottom cover BC. For example, the intermediate frame MF may include a bracket.

[0346] The bottom cover BC is a housing disposed below the display panel 100. The bottom cover BC may include a central cover portion BCP and a peripheral portion BS disposed around the central cover portion BCP.

[0347] The center cap BCP is located at the center of the bottom cap BC and can be roughly flat.

[0348] The peripheral portion BS can be arranged to surround the central cover portion BCP. The peripheral portion BS can be a portion that bends and curves from the central cover portion BCP. The peripheral portion BS can be bent from the edge of the central cover portion BCP. In some embodiments, the peripheral portion BS can include a curved surface having a curvature (e.g., a predetermined curvature), and other portions can be flat. The degree (or angle) at which the peripheral portion BS bends from the central cover portion BCP can be obtuse, but is not limited to, and can also be right angle or acute angle.

[0349] The storage space BC-S can be formed by the central cover portion BCP and the outer portion BS. The battery BT can be placed in the storage space BC-S.

[0350] The battery BT can be connected to a circuit board on which the main processor and other components are mounted. The display device 10_1 can be electrically connected to the circuit board to receive digital video signals, timing signals, power, etc.

[0351] The bottom cover BC is placed on the outermost rear surface of the electronic device and may include at least one of plastic, metal, and glass materials, and may include a color coating layer. For example, according to one example, the bottom cover BC may be a flat glass with a transparent, translucent, or opaque color coating layer.

[0352] According to another example, the bottom cover BC may have the same shape as the cover window CW and may include glass material with a color-coated layer. For example, according to another example, the bottom cover BC may have a structure symmetrical to the cover window CW with an intermediate frame MF located between the bottom cover BC and the cover window CW, and may include a transparent, translucent, or opaque color-coated layer.

[0353] The wearable part BD is the part used to secure the main unit BP to the user's wrist, and can be, for example, a strap, chain, or bracelet.

[0354] Figure 32 This is an example view of a virtual reality (VR) device including a display device according to one or more embodiments.

[0355] Reference Figure 32 The head-mounted display device 1000_2 according to one or more embodiments includes a display device housing 1100, a housing cover 1200, a first eyepiece 1210, a second eyepiece 1220, and a head-mounted strap 1300.

[0356] The display device housing 1100 houses the display device. The head-mounted display device 1000_2 according to one or more embodiments also includes a first optical component located between the corresponding first display device and the first eyepiece 1210.

[0357] The housing cover 1200 is positioned to cover the open surface of the display device housing 1100. The housing cover 1200 may include a first eyepiece 1210 for placing the user's left eye and a second eyepiece 1220 for placing the user's right eye. Although the first eyepiece 1210 and the second eyepiece 1220 are... Figure 32 The positioning is done separately, but this disclosure is not limited thereto. The first eyepiece 1210 and the second eyepiece 1220 can also be combined into one.

[0358] The head-mounted display device 1000_2 is secured to the user's head via a headband 1300, such that the first eyepiece 1210 and the second eyepiece 1220 of the housing cover 1200 are held in place over the user's left and right eyes, respectively. When the housing cover 1200 is made lightweight and compact, the head-mounted display device 1000_2 may include, for example... Figure 33 The eyeglasses frame shown is not the headband 1300.

[0359] The display device housing 1100 houses the display device. Additionally, the head-mounted display device 1000_2 may also include a battery for power supply, an external memory slot for accommodating external memory, and an external connection port and wireless communication module for receiving image sources. The external connection port may be a Universal Serial Bus (USB) terminal, a display port, or an HDMI terminal, and the wireless communication module may be a 5G communication module, a 4G communication module, a Wi-Fi® module, or a Bluetooth® module (Wi-Fi® is a registered trademark of the non-profit Wi-Fi Alliance, and Bluetooth® is a registered trademark of BluetoothSig, Inc., Kirkland, WA).

[0360] Figure 33 This is an example view of a VR device including a display device according to one or more embodiments. Figure 33 A VR device 1000_3 is shown, in which a display device 10_4 according to one or more embodiments has been applied.

[0361] Reference Figure 33 The VR device 1000_3 according to one or more embodiments may be a device in the form of glasses. The VR device 1000_3 according to the embodiments may include a display device 10_4, a left lens 10a, a right lens 10b, a support frame 20, eyeglass temples 30a and 30b, a reflective member 40, and a display device housing 50.

[0362] exist Figure 33 The example shown is a case where the VR device 1000_3 is an eyeglass-type display device including eyeglass temples 30a and 30b. That is, the VR device 1000_3 according to the embodiment is not limited to... Figure 33The VR device 1000_3 shown can be applied to various other electronic devices in various forms.

[0363] The display device housing 50 can accommodate the display device 10_4 and the reflective member 40. The image displayed on the display device 10_4 can be reflected by the reflective member 40 and provided to the user's right eye through the right lens 10b. Therefore, the user can view the VR image displayed on the display device 10_4 through their right eye.

[0364] Although Figure 33 The display device housing 50 is located at the right end of the support frame 20, but this disclosure is not limited thereto. For example, the display device housing 50 may also be located at the left end of the support frame 20. In this case, the image displayed on the display device 10_4 can be reflected by the reflective member 40 and provided to the user's left eye through the left lens 10a. Therefore, the user can view the VR image displayed on the display device 10_4 through their left eye. Alternatively, the display device housing 50 may be located at both the right and left ends of the support frame 20. In this case, the user can view the VR image displayed on the display device 10_4 through both their left and right eyes.

[0365] Figure 34 This is an example view showing a vehicle dashboard and central instrument panel including a display device according to one or more embodiments. Figure 34 Vehicles in which display devices 10_a to 10_e according to one or more embodiments are shown.

[0366] Reference Figure 34 The display devices 10_a to 10_c according to the embodiments can be applied to the instrument cluster of a vehicle, the central instrument panel of a vehicle, or the central information display (CID) located on the instrument panel of a vehicle. Additionally, the display devices 10_d and 10_e according to the embodiments can be applied to interior mirror displays that replace the side mirrors of a vehicle.

[0367] Figure 35 This is an example view of a transparent display device including a display apparatus according to one or more embodiments.

[0368] Reference Figure 35 The display device 10_5 according to one or more embodiments can be applied to a transparent display device. The transparent display device can transmit light while displaying an image IM. Therefore, a user located in front of the transparent display device can not only view the image IM displayed on the display device 10_5, but also view the object RS or background located behind the transparent display device. When the display device 10_5 is applied to a transparent display device, the substrate of the display device 10_5 may include a light-transmitting portion or may be made of a light-transmitting material.

[0369] However, it should be understood that the aspects and features of the embodiments of this disclosure are not limited to those set forth herein. The above and other aspects of this disclosure will become more apparent to those skilled in the art to which this disclosure pertains by referring to the claims and their equivalents, which will be included therein.

Claims

1. A display device, the display device comprising: Base; A transistor layer, comprising a first transistor and a second transistor; as well as The sub-pixel includes a first type of light-emitting element and a second type of light-emitting element, the first type of light-emitting element being configured to be driven by a first transistor, the second type of light-emitting element being configured to be driven by a second transistor and including a first reflective pattern having a triangular cross-section at the lower part of the second type of light-emitting element and including a reflective surface inclined toward the center of the lower part.

2. The display device according to claim 1, wherein The first reflective pattern is set to multiple, and The first reflective pattern is on the corresponding side of the second type of light-emitting element, such that the reflective surfaces face each other.

3. The display device of claim 2, wherein, The second type of light-emitting element includes: Semiconductor layer; A reflective film is provided on the side and top surfaces of the semiconductor layer and defines an opening. A first protective film is disposed between the semiconductor layer and the reflective film; and The second protective film is located on the outside of the reflective film.

4. The display device according to claim 3, wherein The first reflective pattern is separated from the area overlapping the opening.

5. The display device according to claim 1, further comprising: A partition wall is located on the transistor layer and surrounds the first type of light-emitting element and the second type of light-emitting element in a plan view; as well as At least one second reflective pattern having a triangular cross-section adjacent to the upper part of the partition wall and surrounding the second type of light-emitting element in a plan view.

6. The display device of claim 5, wherein, The at least one second reflective pattern includes a first surface protruding from the partition wall at an angle, a second surface in full contact with the partition wall, and a third surface below the first surface and extending from the first surface to the second surface.

7. The display device of claim 6, wherein, The angle is 90 degrees or greater.

8. The display device according to claim 5, wherein The second reflective pattern is located horizontally above the second type of light-emitting element.

9. The display device of claim 8, wherein, The partition wall has a tapered shape that narrows in the upward direction.

10. The display device according to claim 8, wherein, The first reflective pattern and the second reflective pattern comprise at least one of aluminum and silver.

11. The display device according to claim 1, further comprising a first optical pattern, the first optical pattern comprising a concave lens above the second type of light-emitting element.

12. The display device according to claim 11, further comprising a second optical pattern, the second optical pattern comprising an upwardly convex lens above the first type of light-emitting element.

13. The display device of claim 1, wherein, The first transistor is configured to operate in a wide viewing angle mode, and The second transistor is configured to operate in a narrow-view mode.

14. The display device according to claim 5, further comprising: A wavelength conversion layer, within the space defined by the partition wall; as well as The cover layer, outer coating layer, and color filter layer are arranged sequentially above the partition wall.

15. A display device, the display device comprising: Base; Transistor layer, above the substrate; A pixel electrode layer, located above the transistor layer; The light-emitting element has a first reflective pattern with a triangular cross-section above the pixel electrode layer. The first reflective pattern is located at the lower part of the light-emitting element and is inclined towards the center of the light-emitting element. as well as A partition wall surrounds the light-emitting element in the plan view.

16. The display device of claim 15, wherein, The light-emitting element includes: Semiconductor layer; A reflective film is defined on the side and top surfaces of the semiconductor layer and in an opening separated from the first reflective pattern in a plan view; A first protective film is disposed between the semiconductor layer and the reflective film; and The second protective film is located on the outside of the reflective film.

17. The display device of claim 16, further comprising a second reflective pattern of one or more triangular cross-sections, the second reflective pattern of one or more triangular cross-sections surrounding the light-emitting element in a plan view on a side adjacent to the upper portion of the partition wall, and including a first surface projecting from the partition wall at an angle, a second surface in complete contact with the side of the partition wall, and a third surface below the first surface and extending from the first surface to the second surface.

18. The display device of claim 17, wherein, The second reflective pattern, consisting of one or more triangular cross-sections, is positioned horizontally above the light-emitting element.

19. The display device according to claim 17, further comprising an optical pattern, the optical pattern including a concave lens above the light-emitting element.

20. An electronic device, the electronic device comprising: A display panel for displaying images includes: a substrate; a transistor layer including a first transistor and a second transistor; and sub-pixels including a first type of light-emitting element and a second type of light-emitting element, the first type of light-emitting element being configured to be driven by the first transistor, the second type of light-emitting element being configured to be driven by the second transistor and including a first reflective pattern having a triangular cross-section at the lower portion of the second type of light-emitting element and including a reflective surface inclined toward the center of a surface of the second type of light-emitting element.

Images