Electronic device

Abstract

This application relates to an electronic device. The electronic device includes: a light-emitting element layer connected to a driving element layer, the driving element layer including signal lines connected to a pixel driving portion, an organic film, and an inorganic film, the signal lines including fan-out lines defining a pad portion at one end; an encapsulation layer on the light-emitting element layer, the encapsulation layer including an inorganic encapsulation layer; and a dam spaced apart from the light-emitting element layer in a planar direction, the dam including an organic layer and having a side surface closest to the light-emitting element layer and including an inclined portion with a different inclination angle in a cross-sectional view. A stepped region is defined between the pad portion and the light-emitting element layer, the stepped region overlapping a first side surface of the dam. A first portion of the fan-out line overlaps with the stepped region and is parallel to the planar direction in a plan view.

Description

Technical Field

[0001] This disclosure relates herein to electronic devices. More specifically, this disclosure relates to electronic devices including optical films. Background Technology

[0002] Various display panels are being developed for use in multimedia electronic devices such as televisions, mobile phones, tablet computers, navigation units, and game consoles. A display panel may include a display area in which an image is displayed and a peripheral area surrounding the display area as a non-display area. Pixels (the smallest unit for displaying images) may be disposed in the display area. Each pixel may include pixel circuitry and a light-emitting element connected to the pixel circuitry. Fan-out lines for providing signals and voltages to the pixels may be disposed in the peripheral area. Summary of the Invention

[0003] Dams or embankments used to prevent the leakage of organic and / or inorganic materials during the process of forming an encapsulation layer covering the light-emitting elements within an electronic device may be formed in the peripheral region. During the manufacturing process of the electronic device, cracks may appear in the encapsulation layer located on the side surfaces of the dams or embankments. When moisture is introduced from the outside of the electronic device due to these cracks, fan-out lines located in the peripheral region to provide signals and voltages to the pixels in the display area may be corroded.

[0004] This disclosure provides an electronic device with improved process reliability.

[0005] Embodiments of the present invention provide an electronic device comprising: a base substrate including a display area and a peripheral area adjacent to the display area; a light-emitting element layer disposed in the display area and including a pixel defining film having a plurality of openings defined therein and a plurality of light-emitting elements respectively disposed in the openings and configured to emit light; a driving element layer disposed between the base substrate and the light-emitting element layer and including a plurality of pixel driving portions respectively connected to the light-emitting elements, a plurality of signal lines respectively connected to the pixel driving portions, at least one organic film and at least one inorganic film; an encapsulation layer disposed on the light-emitting element layer and including at least one inorganic encapsulation layer; and a dam disposed in the peripheral area, extending along a first direction, spaced apart from the display area in a second direction intersecting the first direction, and including an organic layer, wherein the signal lines include a plurality of fan-out lines disposed in the peripheral area and defining pad portions at one end thereto, the peripheral area including a stepped region defined between the pad portions and the display area, a first side surface of the dam overlapping the stepped region including at least two inclined portions having different inclination angles in a cross-sectional view, and the first portion of each of the fan-out lines overlapping the stepped region being parallel to the second direction in a plan view.

[0006] In some embodiments, the electronic device according to an embodiment of the present invention may further include a driver chip connected to the pad portion.

[0007] In some embodiments, the electronic device according to an embodiment of the present invention may further include a circuit board connected to the pad portion.

[0008] In this implementation, the tilt angle can be less than approximately 90 degrees.

[0009] In an embodiment, the organic layer of the embankment may be in the same layer as at least one of the organic film of the driving element layer and at least one of the pixel defining film.

[0010] In an embodiment, the electronic device according to an embodiment of the present invention may further include an optical film disposed on the encapsulation layer and covering the stepped region, wherein the embankment may overlap one end of the optical film in a plan view.

[0011] In one embodiment, the inorganic encapsulation layer may cover the stepped region, and the optical film may cover one end of the inorganic encapsulation layer.

[0012] In an implementation, each of the fan-out lines may further include: a second portion extending from one end of the first portion toward the display area and inclined relative to the first portion in a plan view; and a third portion extending from the other end of the first portion toward the pad portion and inclined relative to the first portion in a plan view.

[0013] In one implementation, the embankment may have a frame shape surrounding the display area.

[0014] In an implementation, the first side surface may have at least one curved surface.

[0015] In an embodiment of the present invention, an electronic device includes a display panel and an optical film disposed on the display panel. The display panel includes a substrate, an inorganic layer disposed on the substrate, a fan-out line disposed between the substrate and the inorganic layer, an organic light-emitting element disposed on the inorganic layer and including an anode, a light-emitting layer and a cathode, a dam, and an encapsulation layer. The dam is disposed on the inorganic layer, extends along a first direction in a plan view, is spaced apart from the organic light-emitting element in a second direction intersecting the first direction, and overlaps with the fan-out line. The encapsulation layer covers the organic light-emitting element and includes a first inorganic encapsulation layer, an organic encapsulation layer and a second inorganic encapsulation layer. One end of the optical film overlaps with the dam in a plan view. The first side surface of the dam facing the organic light-emitting element includes at least two inclined portions with different inclination angles in a cross-sectional view. The first portion of the fan-out line that overlaps with the first side surface is parallel to the second direction in a plan view.

[0016] In the implementation, each of the tilt angles can be less than approximately 90 degrees.

[0017] In one embodiment, the embankment may include multiple organic layers, and the first side surface may be defined by the side surfaces of at least two of the organic layers.

[0018] In one embodiment, the embankment may include multiple organic layers, and the first side surface may be defined by any one of the organic layers.

[0019] In an embodiment, the organic layer may include a first organic layer, a second organic layer, and a third organic layer stacked sequentially, wherein the second organic layer may cover the first organic layer, and the third organic layer may be spaced apart from the first organic layer and cover the second organic layer, and the first side surface may be defined by the third organic layer.

[0020] In an implementation, the organic layer may include a first organic layer, a second organic layer, and a third organic layer stacked sequentially, wherein the second organic layer may expose the side surface of the first organic layer, and the third organic layer may cover the exposed side surface of the first organic layer.

[0021] In one embodiment, the second side surface of the embankment, which is oriented in the opposite direction to the first side surface, may have a shape different from that of the first side surface.

[0022] In one embodiment, at a location overlapping with the fan-out line, at least one of the first inorganic encapsulation layer and the second inorganic encapsulation layer may contact at least a portion of the inorganic layer.

[0023] In an embodiment, the fan-out line may further include a second portion extending from one end of the first portion and inclined in a plan view relative to the first and second directions.

[0024] In an embodiment, the fan-out line may further include a third portion extending from the other end of the first portion and overlapping one end of the optical film. Attached Figure Description

[0025] The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention. In the drawings: Figure 1 This is a perspective view of an electronic device according to an embodiment of the present invention; Figure 2 This is an exploded perspective view of a display device according to an embodiment of the present invention; Figure 3A This is a cross-sectional view of an electronic device according to an embodiment of the present invention; Figure 3B This is a cross-sectional view of a display module according to an embodiment of the present invention; Figure 4A This is a plan view of a display panel according to an embodiment of the present invention; Figure 4B This is an equivalent circuit diagram of a pixel according to an embodiment of the present invention; Figure 5A and Figure 5B Each is an enlarged cross-sectional view of a region of the display panel according to an embodiment of the present invention; Figure 6 This is a schematic diagram of a portion of the manufacturing process of a display panel according to an embodiment of the present invention; Figure 7A and Figure 7B Each is a schematic cross-sectional view of the embankment according to an embodiment of the present invention; Figure 8A and Figure 8B Each is a plan view of an electronic device according to an embodiment of the present invention; Figure 9 This is a plan view showing a portion of a display panel according to an embodiment of the present invention; Figure 10A This is a plan view showing a portion of a display panel according to an embodiment of the present invention; Figure 10B It shows the relationship with Figure 10A A cross-sectional view of a portion of the display panel corresponding to the area; Figure 11A and Figure 11B Each is a plan view illustrating a portion of the manufacturing steps of a display panel according to an embodiment of the present invention; Figure 12 It is a block diagram of an electronic device according to an embodiment; and Figure 13 Schematic diagrams of electronic devices according to various embodiments are shown. Detailed Implementation

[0026] In this specification, it will be understood that when an element (or region, layer, part, etc.) is referred to as being associated with another element (e.g., "on" another element," "connected to," or "attached to" another element), it may be directly disposed on, directly connected to, or directly attached to the other element, or other elements may be disposed between them. Conversely, when an element (or region, layer, part, etc.) is referred to as being directly associated with another element (e.g., "directly on" another element," "directly connected to," or "directly attached to" another element), no other elements may be disposed between them.

[0027] The same reference numerals or symbols always denote the same elements. In the accompanying drawings, the thickness, scale, and dimensions of the elements are exaggerated in order to effectively describe the technical content.

[0028] As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed elements. Therefore, reference to “a” element followed by “the” element in a claim includes one element and multiple elements. For example, “a element” has the same meaning as “at least one element” unless the context clearly indicates otherwise. “At least one” will not be construed as limiting “a” or “one”. “Or” means “and / or”.

[0029] It will be understood that although the terms “first,” “second,” etc., may be used herein to describe various elements, these elements are not limited by these terms. These terms are used only to distinguish one element from another. For example, without departing from the scope of the invention, the first element discussed below may be referred to as the second element. Similarly, the second element may be referred to as the first element.

[0030] In this specification, the singular expressions “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0031] In addition, the terms "below," "under," "on the lower side," "above," "above," "on the upper side," etc., are used to describe the relationships between the elements shown in the accompanying drawings. These terms are relative concepts and are described based on the directions indicated in the drawings.

[0032] Given the measurements discussed and the errors associated with the measurement of a particular quantity (i.e., limitations of the measurement system), the terms “about” or “approximately” as used herein include the value and mean within an acceptable deviation of the particular value as determined by one of ordinary skill in the art. For example, “about” may mean within one or more standard deviations, or within ±30%, ±20%, ±10%, or ±5% of the value.

[0033] Unless otherwise specified, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. It will also be understood that terms, such as those defined in common dictionaries, shall be interpreted as having the meaning consistent with their meaning in the context of the relevant art and shall not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0034] It will also be understood that the terms “comprises,” “includes,” “has,” and / or “comprising,” “including,” “having,” when used in this specification, specify the presence of the stated features, quantities, steps, operations, elements, components, or combinations thereof, but do not preclude the possibility of the presence or addition of one or more other features, quantities, steps, operations, elements, components, or combinations thereof.

[0035] Embodiments are described herein with reference to sectional views, which are schematic illustrations of idealized embodiments. Therefore, deviations from the illustrated shapes are expected due to factors such as manufacturing techniques and / or tolerances. Consequently, the embodiments described herein should not be construed as limited to the specific shapes of the regions shown herein, but will include shape deviations, for example, due to manufacturing processes. For instance, regions shown or described as flat may generally have rough and / or non-linear characteristics. Furthermore, sharp corners shown may be rounded. Therefore, the regions shown in the figures are schematic in nature, and their shapes are not intended to represent the precise shapes of the regions, nor are they intended to limit the scope of the claims.

[0036] In the following description, embodiments of the invention will be described with reference to the accompanying drawings.

[0037] Figure 1 This is a perspective view of an electronic device ED according to an embodiment of the present invention. Figure 2 This is an exploded perspective view of a display device DD according to an embodiment of the present invention. Figure 3A This is a cross-sectional view of an electronic device ED according to an embodiment of the present invention. Figure 3B This is a cross-sectional view of the display module DM according to an embodiment of the present invention.

[0038] An electronic device (ED) can be activated in response to an electrical signal. The electronic device (ED) can include various implementations. For example, the electronic device (ED) can be or include a display device (DD), such as a smartwatch, tablet computer, laptop computer, computer, and smart TV.

[0039] An electronic device ED can display an image IM on a display surface IS parallel to a plane defined by a first direction DR1 and a second direction DR2 that intersect each other. The image IM can be viewed on a third direction DR3 that intersects each of the first direction DR1 and the second direction DR2. The display surface IS on which the image IM is displayed can correspond to the front surface of the electronic device ED. The image IM can include both still images and moving images.

[0040] In this embodiment, the front and rear surfaces may be opposite each other on a third direction DR3, and the normal direction of each of the front and rear surfaces may be parallel to the third direction DR3. The spacing between the front and rear surfaces on the third direction DR3 may correspond to the thickness of the electronic device ED on the third direction DR3 (e.g., the thickness direction). Meanwhile, the directions indicated by the first direction DR1, the second direction DR2, and the third direction DR3 have a relative concept and can therefore be changed to other directions.

[0041] The electronic device (ED) can detect external input applied from the outside (e.g., the exterior of the electronic device (ED), the exterior of the display device (DD), etc.). External input can include various types of input provided from outside the electronic device (ED), such as through an input tool. For example, external input can include not only touch made through a part of the body (e.g., a user's hand), but also external input applied by an input tool approaching or adjacent to the electronic device (ED) within a predetermined distance (e.g., hovering). Furthermore, external input can be of various types, such as force, pressure, temperature, or light.

[0042] The display surface IS of an electronic device ED can be divided into a transmissive region TA and a border region BZA. The transmissive region TA can be the area in which an image IM is displayed. The user views the image IM through the transmissive region TA. In this embodiment, the transmissive region TA is shown as a quadrilateral shape with rounded vertices in a planar view. However, this is shown as an example. The transmissive region TA can have various shapes and is not limited to any one embodiment.

[0043] The border region BZA is adjacent to the transmission region TA. The border region BZA may have a predetermined color. The border region BZA may surround the transmission region TA in a planar view. Therefore, the planar shape of the transmission region TA may be substantially defined by the border region BZA. However, this is shown as an example, and the border region BZA may be configured to be adjacent only to one side of the transmission region TA, or it may be omitted. The electronic device ED according to embodiments of the present invention may include various embodiments and is not limited to any one of them.

[0044] An electronic device ED may include a display device DD and a housing EDC (casing). The display device DD may include a window WM, a display module DM, a driving module EM, an optical film OTF, and a lower module LM. The display module DM may include a display panel DP and an input sensor ISP disposed on the display panel DP. The display panel DP generates an image IM, and the input sensor ISP acquires coordinate information of external input (e.g., a touch event).

[0045] The window WM can be made of a transparent material that allows the output of images, light, etc. For example, the window WM can be made of glass, sapphire, plastic, etc. The window WM is shown as a single layer, but is not limited to this, and can include multiple layers. Meanwhile, although not shown, the bezel area BZA of the display device DD described above can be substantially defined by the bezel pattern BP of the window WM. The bezel pattern BP can be formed by depositing or printing a material with low light transmittance, such as colored ink, resin, conductive patterns, etc., onto the window WM.

[0046] The display module DM can display an image IM in response to electrical signals and send / receive information about external inputs. The display module DM can be defined as a valid area AA and a peripheral area NAA. The valid area AA can be defined as the area or planar area in which the image provided by the display module DM is output from the electronic device ED.

[0047] The peripheral region NAA is adjacent to the effective region AA. For example, the peripheral region NAA may surround the effective region AA. However, this is shown as an example, and the peripheral region NAA can be defined in various shapes and is not limited to any one embodiment. According to an embodiment, the effective region AA of the display module DM may correspond to at least a portion of the transmissive region TA.

[0048] The display module DM may include a display panel DP and an input sensor ISP. The display panel DP according to embodiments of the present invention may be an emitting display panel, but is not particularly limited thereto. For example, the display panel DP may be an organic light-emitting display panel, an inorganic light-emitting display panel, or a quantum dot light-emitting display panel. The light-emitting layer of an organic light-emitting display panel may include organic light-emitting materials, and the light-emitting layer of an inorganic light-emitting display panel may include inorganic light-emitting materials. The light-emitting layer of a quantum dot light-emitting display panel may include quantum dots, quantum rods, etc. Hereinafter, the display panel DP is described as an organic light-emitting display panel.

[0049] The display panel DP includes a base layer SUB, a circuit element layer DP-CL disposed on the base layer SUB, a display element layer DP-OLED, and a thin-film encapsulation layer TFE. The display panel DP can be an emitting display panel, and there are no particular limitations. For example, the display panel DP can be an organic light-emitting display panel or a quantum dot light-emitting display panel. The light-emitting layer of an organic light-emitting display panel includes organic light-emitting materials. The light-emitting layer of a quantum dot light-emitting display panel includes quantum dots and quantum rods. Hereinafter, the display panel DP is described as an organic light-emitting display panel. Although not shown separately, the display panel DP may also include functional layers such as an anti-reflective layer and a refractive index control layer.

[0050] The base layer SUB may include at least one plastic film. The base layer SUB may be a flexible substrate and includes plastic substrates, glass substrates, metal substrates, organic / inorganic composite substrates, etc.

[0051] The circuit element layer DP-CL includes at least one intermediate insulating layer and circuit elements. The intermediate insulating layer includes at least one intermediate inorganic film and at least one intermediate organic film. The circuit elements include signal lines, pixel driving circuits, etc., which will be described in detail later.

[0052] The display element layer DP-OLED (or light-emitting element layer DP-OLED) includes at least organic light-emitting diodes (OLEDs). The display element layer DP-OLED may also include organic films, such as pixel-defining films. The display area DM-DA described below can correspond to an area or planar area in which light emitted from the organic light-emitting diodes is displayed, and the non-display area DM-NDA can correspond to an area in which light is not displayed, i.e., an area in which no organic light-emitting diodes are disposed.

[0053] A thin-film encapsulation layer (TFE) (or encapsulation layer TFE) seals the DP-OLED display element layer. The TFE includes at least one inorganic film (hereinafter, inorganic encapsulation film). The TFE may also include at least one organic film (hereinafter, organic encapsulation film). The inorganic encapsulation film protects the DP-OLED display element layer from moisture / oxygen, while the organic encapsulation film protects the DP-OLED display element layer from foreign matter such as dust particles. The inorganic encapsulation film may include a silicon nitride layer, a silicon oxynitride layer and a silicon oxide layer, a titanium oxide layer, an aluminum oxide layer, etc. The organic encapsulation film may include an acrylic organic layer, but is not limited thereto.

[0054] The input sensor ISP, which forms the input sensing layer, can be "directly mounted" on the display panel DP. According to an embodiment of the invention, the input sensor ISP can be formed on the display panel DP using a continuous process. That is, when the input sensor ISP is directly mounted on the display panel DP, the adhesive film used to bond the input sensor ISP and the display panel DP can be omitted. Here, the "directly mounted" element or layer can form an interface therebetween. Furthermore, the input sensor ISP can be omitted in the display module DM according to an embodiment of the invention.

[0055] The optical film OTF reduces the reflectivity of external light incident from above the window WM. According to embodiments of the present invention, the optical film OTF can be a retardation film, a polarizing film, or a film with other optical effects. The optical film OTF may also include a protective film disposed on the upper or lower portion.

[0056] The optical film OTF can be disposed on the input sensor ISP. That is, the optical film OTF can be disposed between the input sensor ISP and the window WM. The input sensor ISP, the optical film OTF, and the window WM can be bonded together with an adhesive layer.

[0057] A first adhesive layer AF1 is disposed between the input sensor ISP and the optical film OTF, and a second adhesive layer AF2 is disposed between the optical film OTF and the window WM. Therefore, the optical film OTF can be bonded to the input sensor ISP through the first adhesive layer AF1, and the window WM can be bonded to the optical film OTF through the second adhesive layer AF2.

[0058] As an example of the invention, adhesive layers AF1 and AF2 may each comprise an optically clear adhesive film (OCA). However, the material of each of adhesive layers AF1 and AF2 is not limited thereto, and may comprise a typical adhesive or a removable adhesive. For example, adhesive layers AF1 and AF2 may each comprise a pressure-sensitive adhesive (PSA), an optically clear adhesive (OCA), or an optically clear resin (OCR).

[0059] Meanwhile, this is shown as an example, and the display device DD according to an embodiment of the present invention may also include an anti-reflective layer (not shown) directly disposed on the display module DM. The anti-reflective layer may be directly disposed on the input sensor ISP, or it may be disposed between the input sensor ISP and the display panel DP. The anti-reflective layer may include a black matrix layer defining a plurality of openings therein, or it may include a color filter layer. In this case, the optical film OTF and the first adhesive layer AF1 may be omitted. In addition, besides the optical film OTF, functional layers performing other functions, such as protective layers, may be disposed between the display module DM and the window WM.

[0060] The driver module EM controls the driving of the display module DM. The driver module EM can be connected to pads (not shown) on the display module DM for electrical connection at the pads. The driver module EM may include a circuit board FCB and a driver chip DIC. The circuit board FCB can be electrically connected to the display panel DP, such as at a portion of the non-display area DM-NDA. Optionally, the circuit board FCB can be electrically connected to the display panel DP and the input sensor ISP.

[0061] The circuit board FCB can be bonded to the display module DM via a bonding process. The circuit board FCB can be electrically connected to the display module DM via an anisotropic conductive adhesive layer. The driver chip DIC can be mounted in the non-display area DM-NDA of the display module DM. The driver chip DIC may include driving circuitry (e.g., data driving circuitry) for driving the pixels of the display panel DP.

[0062] The circuit board FCB may include multiple driving elements. Each driving element may include circuitry for converting externally input signals into signals required by the driving chip DIC or the display module DM. Optionally, the circuit board FCB may include a grounding wire for electrostatic discharge of any electrostatic discharge introduced into the circuit board FCB or the display module DM. Optionally, a separate rigid circuit board may be provided, and the circuit board FCB may consist only of signal lines for the electrical connection between the circuit board and the display module DM. The circuit board FCB may include various electrical components and is not limited to any single embodiment.

[0063] In this embodiment, when the electronic device ED includes a circuit board FCB housed within a housing EDC, at least a portion of the circuit board FCB can be bent to be positioned below the display module DM. Optionally, at least a portion of the display module DM can be bent, and therefore the circuit board FCB can be positioned below the display module DM. Optionally, the circuit board FCB can be omitted when all driving elements included in the circuit board FCB are mounted on the display module DM.

[0064] The lower module LM is mounted on the rear surface of the display module DM. Because the lower module LM is mounted on the rear surface of the display module DM, the impact resistance of the display device DD can be improved. The lower module LM can be fixed to the rear surface of the display module DM using an adhesive layer.

[0065] The housing EDC can be attached to the window WM and defines the appearance of the electronic device ED. The housing EDC houses the display device DD. The housing EDC absorbs impacts from the outside and prevents foreign objects / moisture from penetrating into the electronic device ED, thus protecting the components housed in the housing EDC. Furthermore, as an example of the present invention, the housing EDC can be arranged in the form of connecting multiple housing members.

[0066] Figure 4A This is a plan view of the display panel DP according to an embodiment of the present invention. Figure 4B This is an equivalent circuit diagram of pixel PX according to an embodiment of the present invention. In the following text, reference will be made to... Figure 4A and Figure 4B The present invention is described. Meanwhile, in conjunction with the references... Figures 1 to 3B Components that are described identically will be represented by the same reference numerals or symbols, and repeated descriptions will be omitted.

[0067] refer to Figure 4AThe display panel DP can define a display area DP-DA and a non-display area DP-NDA surrounding the display area DP-DA. The display area DP-DA and the non-display area DP-NDA can be distinguished by whether pixels PX are set within them or not. Pixels PX are set within the display area DP-DA. The scan drive section SDV, data drive section, and transmit drive section EDV can be set within the non-display area DP-NDA. The data drive section can be part of the circuitry configured in the driver chip DIC. The display area DP-DA and the non-display area DP-NDA of the display panel DP correspond to... Figure 3B The display module DM is shown with display area DM-DA and non-display area DM-NDA. Meanwhile, the display area DP-DA and non-display area DP-NDA of the display panel DP may not have the same area, size, or position as the display area DM-DA and non-display area DM-NDA of the display module DM, and can vary depending on the structure / design of the display panel DP.

[0068] The display panel DP may include pixels PX, initialization scan lines GIL1 to GILm, compensation scan lines GCL1 to GCLm, write scan lines GWL1 to GWLm, black scan lines GBL1 to GBLm, transmit control lines ECL1 to ECLm, data lines DL1 to DLn, first control line CSL1 and second control line CSL2, drive voltage line PL, and pads PD, wherein multiple pads PD are provided to define multiple pads PD. Here, "m" and "n" are natural numbers greater than or equal to 2. In the figures and text of this disclosure, reference numerals indicating elements in the singular form may also be used to represent multiple elements.

[0069] Pixel PX can be connected to the initialization scan lines GIL1 to GILm, the compensation scan lines GCL1 to GCLm, the write scan lines GWL1 to GWLm, the black scan lines GBL1 to GBLm, the emission control lines ECL1 to ECLm, and the data lines DL1 to DLn.

[0070] Initialization scan lines GIL1 to GILm, compensation scan lines GCL1 to GCLm, write scan lines GWL1 to GWLm, and black scan lines GBL1 to GBLm can extend in the first direction DR1 and be electrically connected to the scan driver section SDV. Data lines DL1 to DLn can extend in the second direction DR2 and pass through a bend region to be electrically connected to the driver chip DIC. Transmit control lines ECL1 to ECLm can extend in the first direction DR1 and be electrically connected to the transmit driver section EDV.

[0071] The driving voltage line PL may include a portion extending along the second direction DR2 and a portion inclined relative to the second direction DR2. The driving voltage line PL can provide a driving voltage to the pixel PX.

[0072] Figure 4B An equivalent circuit diagram of one pixel PXij from a plurality of pixels PX is shown as an example. Since each of the plurality of pixels PX has the same circuit configuration, detailed descriptions of the remaining pixels PX are omitted by describing the circuit configuration of pixel PXij.

[0073] Pixel PXij is connected to the i-th data line DL1 to DLn, the j-th initialization scan line GILj among the initialization scan lines GIL1 to GILm, the j-th compensation scan line GCLj among the compensation scan lines GCL1 to GCLm, the j-th write scan line GWLj among the write scan lines GWL1 to GWLm, the j-th black scan line GBLj among the black scan lines GBL1 to GBLm, the j-th transmit control line ECLj among the transmit control lines ECL1 to ECLm, the first drive voltage line VL1 and the second drive voltage line VL2, and the first initialization voltage line VL3 and the second initialization voltage line VL4. Here, "i" is an integer equal to or greater than 1 and equal to or less than "n", and "j" is an integer equal to or greater than 1 and equal to or less than "m".

[0074] Pixel PXij includes a light-emitting element (LD) and a pixel circuit (PDC). The light-emitting element LD can be a light-emitting diode (LED). As an example of the invention, the light-emitting element LD can be an organic light-emitting diode including an organic light-emitting layer, but is not particularly limited thereto. The pixel circuit (PDC) can be electrically connected to the light-emitting element LD and control the amount of current flowing in the light-emitting element LD in response to a data signal Di. The light-emitting element LD can emit light with a predetermined brightness corresponding to the amount of current supplied from the pixel circuit (PDC).

[0075] The pixel circuit PDC may include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, and a seventh transistor T7, as well as a first capacitor Cst, a second capacitor Cbst, and a third capacitor Nbst. According to the present invention, the configuration of the pixel circuit PDC is not limited to... Figure 4B The implementation method shown. Figure 4B The pixel circuit PDC shown is just an example, and the configuration of the pixel circuit PDC can be changed and implemented.

[0076] At least one of the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 can be a transistor having a low-temperature polycrystalline silicon (LTPS) semiconductor layer. At least one of the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 can be a transistor having an oxide semiconductor layer. For example, the third transistor T3 and the fourth transistor T4 can be oxide semiconductor transistors, and the first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 can be LTPS transistors.

[0077] Specifically, the first transistor T1, which directly affects the brightness of the light-emitting element (LD), comprises a semiconductor layer containing polycrystalline silicon with high reliability. As a result, a high-resolution display device can be realized. Simultaneously, since oxide semiconductors have high carrier mobility and low leakage current, the voltage drop is not significant even during long driving times. That is, since color changes in the image due to voltage drop are not significant even during low-frequency driving, low-frequency driving is possible. Therefore, due to the advantage of low leakage current of oxide semiconductors, at least one of the third transistor T3 and the fourth transistor T4 connected to the gate electrode of the first transistor T1 can be used as an oxide semiconductor, thus preventing leakage current that might flow to the gate electrode and reducing power consumption.

[0078] The j-th initialization scan line GILj, the j-th compensation scan line GCLj, the j-th write scan line GWLj, the j-th black scan line GBLj, and the j-th transmit control line ECLj can respectively transmit the j-th initialization scan signal GIj, the j-th compensation scan signal GCj, the j-th write scan signal GWj, the j-th black scan signal GBj, and the j-th transmit control signal EMj to pixel PXij. The i-th data line DL transmits the i-th data signal Di to pixel PXij. The i-th data signal Di can have the same characteristics as the input to the display device DD (see...). Figure 3A The voltage level corresponding to the image signal.

[0079] The first driving voltage line VL1 and the second driving voltage line VL2 can respectively transmit the first driving voltage ELVDD and the second driving voltage ELVSS to the pixel PXij. Furthermore, the first initialization voltage line VL3 and the second initialization voltage line VL4 can respectively transmit the first initialization voltage VINT and the second initialization voltage VAINT to the pixel PXij.

[0080] A first transistor T1 is connected between a first driving voltage line VL1 for receiving a first driving voltage ELVDD and a light-emitting element LD. The first transistor T1 includes a first electrode connected to the first driving voltage line VL1 via a fifth transistor T5, a second electrode connected to the pixel electrode (or anode) of the light-emitting element LD via a sixth transistor T6, and a third electrode (e.g., a gate electrode) connected to one end of a first capacitor Cst (e.g., a first node N1). The first transistor T1 can receive the i-th data signal Di transmitted by the i-th data line DL1 according to the switching operation of the second transistor T2, and provide driving current to the light-emitting element LD.

[0081] The second transistor T2 is connected between the i-th data line DLi and the first electrode of the first transistor T1. The second transistor T2 includes a first electrode connected to the i-th data line DLi, a second electrode connected to the first electrode of the first transistor T1, and a third electrode (e.g., a gate electrode) connected to the j-th write scan line GWLj. The second transistor T2 can be turned on in response to the j-th write scan signal GWj received via the j-th write scan line GWLj, and transmits the i-th data signal Di transmitted from the i-th data line DLi to the first electrode of the first transistor T1. One end of the second capacitor Cbst can be connected to the third electrode of the second transistor T2, and the other end of the second capacitor Cbst can be connected to the first node N1.

[0082] A third transistor T3 is connected between the second electrode of the first transistor T1 and the first node N1. The third transistor T3 includes a first electrode connected to the third electrode of the first transistor T1, a second electrode connected to the second electrode of the first transistor T1, and a third electrode (e.g., a gate electrode) connected to the j-th compensation scan line GCLj. The third transistor T3 can be turned on in response to a j-th compensation scan signal GCj received via the j-th compensation scan line GCLj, thereby connecting the third electrode and the second electrode of the first transistor T1 to each other, allowing the first transistor T1 to be diode-connected. One end of a third capacitor Nbst can be connected to the third electrode of the third transistor T3, and the other end of the third capacitor Nbst can be connected to the first node N1.

[0083] A fourth transistor T4 is connected between the first node N1 and the first initialization voltage line VL3 to which the first initialization voltage VINT is applied. The fourth transistor T4 includes a first electrode connected to the first initialization voltage line VL3 to which the first initialization voltage VINT is transmitted, a second electrode connected to the first node N1, and a third electrode (e.g., a gate electrode) connected to the j-th initialization scan line GILj. The fourth transistor T4 is turned on in response to the j-th initialization scan signal GIj received via the j-th initialization scan line GILj. The turned-on fourth transistor T4 transmits the first initialization voltage VINT to the first node N1 and initializes the potential of the third electrode of the first transistor T1 (i.e., the potential of the first node N1).

[0084] The fifth transistor T5 includes a first electrode connected to the first driving voltage line VL1, a second electrode connected to the first electrode of the first transistor T1, and a third electrode (e.g., a gate electrode) connected to the j-th emission control line ECLj. The sixth transistor T6 includes a first electrode connected to the second electrode of the first transistor T1, a second electrode connected to the pixel electrode (e.g., the second node N2) of the light-emitting element LD, and a third electrode (e.g., a gate electrode) connected to the j-th emission control line ECLj.

[0085] The fifth transistor T5 and the sixth transistor T6 are simultaneously turned on in response to the j-th transmit control signal EMj received via the j-th transmit control line ECLj. The first drive voltage ELVDD applied via the turned-on fifth transistor T5 can be compensated by the diode-connected first transistor T1, and then transmitted to the light-emitting element LD via the sixth transistor T6.

[0086] The seventh transistor T7 includes a first electrode connected to a second initialization voltage line VL4 to which the second initialization voltage VAINT is transmitted, a second electrode connected to a second electrode of the sixth transistor T6, and a third electrode (e.g., a gate electrode) connected to the j-th black scan line GBLj. The voltage level of the second initialization voltage VAINT may be lower than or equal to the voltage level of the first initialization voltage VINT.

[0087] One end of the first capacitor Cst is connected to the third electrode of the first transistor T1, and the other end of the first capacitor Cst is connected to the first driving voltage line VL1. The cathode of the light-emitting element LD can be connected to the second driving voltage line VL2 for transmitting the second driving voltage ELVSS. The voltage level of the second driving voltage ELVSS can be lower than the voltage level of the first driving voltage ELVDD.

[0088] Some of the transistors T1, T2, T3, T4, T5, T6, and T7 can be P-type transistors, and the rest can be N-type transistors. For example, T1, T2, T5, T6, and T7 can be P-type transistors, and T3 and T4 can be N-type transistors.

[0089] Meanwhile, the configuration of the pixel circuit PDC according to the present invention is not limited to Figure 4B The implementation method shown. Figure 4B The pixel circuit PDC shown is merely an example, and the configuration of the pixel circuit PDC can be changed and implemented differently. For example, the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 can be P-type transistors, or all of them can be N-type transistors. Optionally, the first transistor T1, the second transistor T2, the fifth transistor T5, and the sixth transistor T6 can be P-type transistors, and the third transistor T3, the fourth transistor T4, and the seventh transistor T7 can be N-type transistors. Furthermore, the number of transistors or capacitors constituting the pixel circuit PDC according to embodiments of the present invention can be changed in various ways and is not limited to any one embodiment.

[0090] Return to reference Figure 4A The first control line CSL1 can be connected to the scan drive section SDV and extends towards the lower end of the non-display area DP-NDA. The second control line CSL2 can be connected to the transmit drive section EDV and extends towards the lower end of the non-display area DP-NDA.

[0091] In the plan view, the pad PD (or pad portion PD) can be positioned adjacent to the lower end of the non-display area DP-NDA. In this embodiment, the pad PD can be positioned spaced apart from each other along the first direction DR1. The pad PD can be defined on the end of the signal line extending along the second direction DR2 that extends to the lower end of the non-display area DP-NDA. In this embodiment, the pad PD can be defined on the ends of the first control line CSL1, the second control line CSL2, and the drive voltage line PL, as well as the ends of the lines connected to the driver chip DIC. Meanwhile, the pads overlapping with and connected to the driver chip DIC can be defined on the ends of data lines DL1 to DLn, and the data lines DL1 to DLn can be electrically connected to the pad PD. The circuit board FCB can be electrically connected to the pad PD via an anisotropic conductive adhesive layer.

[0092] Furthermore, the display panel DP according to an embodiment of the present invention may include a dam portion DMP and a dike portion BNP. The dam portion DMP, acting as a dam, may extend along the boundary of the display area DP-DA. The dam portion DMP may have a frame shape surrounding the display area DP-DA. The dam portion DMP may include at least one organic film. The dam portion DMP may also be considered as a "dke" of the display panel DP.

[0093] The embankment BNP is positioned separately from the dam section DMP. The embankment BNP can be positioned between the display area DP-DA and the pad area PA. Multiple pad areas PA can be configured, including a first pad area PA1 and a second pad area PA2 (see reference). Figure 8A and Figure 8B The first pad region PA1 can be a region in which a pad PD is disposed, wherein the pad PD is a first pad on which a circuit board FCB is disposed. The second pad region PA2 can be a region in which a second pad (not shown) for connecting to a driver chip DIC is disposed, and may overlap with the driver chip DIC. This is shown as an example, and either the first pad region PA1 or the second pad region PA2 may be omitted, so that only one of the regions may exist; however, embodiments of the present invention are not limited to any one of these embodiments.

[0094] The dam portion BNP may have a strip shape in which its main portion extends along a first direction DR1. The dam portion BNP may extend across the fan-out line RTL. The dam portion BNP may overlap with the fan-out line RTL in a plan view. The dam portion BNP may include at least one organic membrane.

[0095] In this embodiment, the non-display area DP-NDA may include a normal area NA and a stepped area GA. The normal area NA may be a region different from the stepped area GA, such as a region surrounding the stepped area GA. The normal area NA, the stepped area GA, and the pad area PA may be located at the lower portion of the non-display area DP-NDA.

[0096] The stepped region GA can exist between the driver chip DIC and the active area AA (or display area DP-DA), or between the pad PD and the active area AA. The stepped region GA can overlap with at least a portion of the embankment BNP in a plan view. The side surface of the embankment BNP overlapping the stepped region GA can include two or more segments with different tilt angles. The tilt angle can be less than about 90 degrees. According to the invention, the side surface of the embankment BNP can be segmented into segments with relatively small tilt angles in the stepped region GA, and therefore the steps on the side surface of the embankment BNP can be formed into a shape with a relatively slow and continuous curve. Therefore, it is possible to prevent the inorganic layer covering the side surface of the embankment BNP from being deposited or from being damaged due to pressure. This will be described in detail later.

[0097] Furthermore, the stepped region GA may overlap with at least a portion of the fan-out line RTL in the plan view. The fan-out line RTL may be an extension of a signal line in the display area DP-DA, or it may be a conductor separated from the signal line and formed in the non-display area DP-NDA. The fan-out line RTL may extend along the second direction DR2 to the pad area PA. One end of the fan-out line RTL may be connected to the driver chip DIC or may be set to the pad PD to connect to the circuit board FCB.

[0098] The fan-out line RTL can be divided into a first part L1, a second part L2, and a third part L3 along the length of the corresponding fan-out line. The first part L1 can be set between the stepped region GA and the effective region AA (or the display region DP-DA), and the first part L1 and the second part L2 can be tilted relative to the second direction DR2.

[0099] The portion of the signal line that overlaps with the stepped region GA can be parallel to the second direction DR2 in the plan view. That is, the portion of the signal line that overlaps with the stepped region GA may exclude (e.g., may be excluded) the sloping portion that intersects with the second direction DR2. Therefore, the area where the signal line intersects with the stepped region GA can be minimized, and thus the possibility of the signal line being damaged in the stepped region GA can be reduced. When overlapping, components can be positioned along the same line in a direction (such as along the thickness direction, lateral direction, etc.). For example, one component can be above or below another component along the thickness direction so that they are considered to overlap, but is not limited to this. This will be described later.

[0100] The stepped region GA may overlap with at least a portion of the organic film disposed between the pad PD and the active region AA (or the display region DP-DA), which is closer to the lower end of the non-display region DP-NDA. In this embodiment, since the dam portion BNP is relatively closer to the pad PD or driver chip DIC than the dam portion DMP, the stepped region GA may be defined to overlap with at least a portion of the dam portion BNP. However, this is shown as an example, and if the dam portion DMP is relatively closer to the pad PD or driver chip DIC than the dam portion BNP, the stepped region GA may overlap with the dam portion DMP or another organic film, and is not limited to any one embodiment.

[0101] Figure 5A and Figure 5B Each is an enlarged cross-sectional view of a region of the display panel DP according to an embodiment of the present invention. Figure 6 This is a schematic diagram of a process in a method of manufacturing (or providing) a display panel DP according to an embodiment of the present invention.

[0102] Figure 5A The area in which a portion of pixel PX is set is shown, and Figure 5B The area in which the stepped region GA is set is shown. Figure 6 It shows Figure 5B Enlarged views of some of the components shown (i.e., some components at the end portion of the display panel DP). Reference will be made below. Figures 5A to 6 The present invention is described. Meanwhile, in conjunction with the references... Figures 1 to 4B Components that are described identically will be represented by the same reference numerals or symbols, and repeated descriptions will be omitted.

[0103] Figure 5A Two transistors T1 and T2 (hereinafter, transistor T1 and transistor T2) are shown, as well as a light-emitting element OLED (e.g., Figure 4B (LD in the first transistor T1 and the second transistor T2). Each of them corresponds to the LD in the second transistor T2. Figure 4B One of the transistors in pixel PXij shown. Figure 5A Showing more details Figure 3B The diagram shows the base layer SUB, the circuit element layer DP-CL, the display element layer DP-OLED, and the encapsulation layer TFE.

[0104] The base layer SUB may include multiple layers stacked along the third direction DR3. In this embodiment, the base layer SUB may include a first base layer PI1, a first overlay layer BR1, a second base layer PI2, and a second overlay layer BR2. However, this is shown as an example, and the base layer SUB may be a single layer or may include other numbers of layers, and is not limited to any one embodiment.

[0105] The first base layer PI1 can be disposed on the bottommost side. The first base layer PI1 can include organic materials. For example, the first base layer PI1 can include one of polyimide (PI), polyethylene naphthalate (PEN), polyethylene terephthalate (PET), polyarylate, polycarbonate (PC), polyetherimide (PEI), and polyethersulfone (PES).

[0106] A first capping layer BR1 may be disposed on a first base layer PI1. The first capping layer BR1 may include an inorganic material. For example, the first capping layer BR1 may include at least one of silicon oxide, silicon oxynitride, aluminum oxide, titanium oxide, silicon nitride, zirconium oxide, hafnium oxide, and amorphous silicon.

[0107] The second base layer PI2 can be disposed on the first cover layer BR1. The second base layer PI2 may include organic materials. The organic materials included in the second base layer PI2 may be the same as those included in the first base layer PI1.

[0108] A second capping layer BR2 may be disposed on the second base layer PI2. The second capping layer BR2 may include inorganic materials. The inorganic materials included in the second capping layer BR2 may be the same as those included in the first capping layer BR1.

[0109] The circuit element layer DP-CL can be disposed on the second cover layer BR2. The circuit element layer DP-CL includes at least multiple insulating layers and circuit elements. In the following description, the insulating layer may include organic and / or inorganic layers. The circuit elements include signal lines, driving circuits for pixels (PX), etc. The circuit element layer DP-CL can be formed by processes such as coating and deposition to form insulating, semiconductor, and conductive layers, and by processes such as photolithography to pattern the insulating, semiconductor, and conductive layers.

[0110] In this embodiment, the light-shielding pattern BML can be disposed at the bottom of the circuit element layer DP-CL. That is, the light-shielding pattern BML can be disposed on the second cover layer BR2. As a light-blocking layer (or electrical shielding layer), the light-shielding pattern BML can block the influence of the potential caused by polarization on the first transistor T1. In addition, the light-shielding pattern BML can block external light from reaching the first transistor T1. In embodiments of the present invention, the light-shielding pattern BML can be a floating electrode (or a floating conductive pattern) insulated from another electrode or conductive line. The light-shielding pattern BML can include molybdenum.

[0111] A barrier layer (BRL) can be disposed on a light-shielding pattern (BML). The barrier layer (BRL) prevents foreign matter from being introduced from the outside. The barrier layer (BRL) may include a silicon oxide layer and a silicon nitride layer. Each of the silicon oxide layer and the silicon nitride layer can be disposed in multiples, and the silicon oxide layer and the silicon nitride layer can be stacked alternately.

[0112] A buffer layer (BFL) can be disposed on the barrier layer (BRL). The buffer layer (BFL) improves the adhesion between the base layer (SUB) and the conductive or semiconductor pattern. The buffer layer (BFL) may include a silicon oxide layer and a silicon nitride layer. The silicon oxide layer and the silicon nitride layer can be stacked alternately.

[0113] A first semiconductor pattern SP1 is disposed on the buffer layer BFL. The first semiconductor pattern SP1 may include a silicon semiconductor. The first semiconductor pattern SP1 may be a polycrystalline silicon semiconductor. However, embodiments of the present invention are not limited thereto, and the first semiconductor pattern SP1 may include amorphous silicon.

[0114] The first semiconductor pattern SP1 may include an input region (or a first portion), an output region (or a second portion), and a channel region (or a third portion) defined between the input and output regions. The channel region of the first semiconductor pattern SP1 may be defined to correspond to the first control electrode GE1, which will be described later. The input and output regions are doped with dopants and have relatively high conductivity compared to the channel region. The input and output regions may be doped with n-type dopants. In this embodiment, an n-type first transistor T1 is described as an example, but the first transistor T1 may be a p-type transistor.

[0115] A first insulating layer 10 is disposed on the buffer layer BFL. The first insulating layer 10 is associated with multiple pixels PX (see [link]). Figure 4A The first insulating layer 10 is commonly overlapped with and covers the first semiconductor pattern SP1. The first insulating layer 10 may be an inorganic layer and / or an organic layer, and has a single-layer or multi-layer structure. The first insulating layer 10 may include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon oxynitride, zirconium oxide, and hafnium oxide. In this embodiment, the first insulating layer 10 may be a single-layer silicon oxide layer.

[0116] The first control electrode GE1 is disposed on the first insulating layer 10. The first control electrode GE1 overlaps with the channel region of the first semiconductor pattern SP1.

[0117] A second insulating layer 20 covering the first control electrode GE1 is disposed on the first insulating layer 10. The second insulating layer 20 is disposed on the plurality of pixels PX (see [link]). Figure 4AThe layers overlap in a common manner. The second insulating layer 20 may be an inorganic layer and / or an organic layer, and may have a single-layer or multi-layer structure. The second insulating layer 20 may include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon oxynitride, zirconium oxide, and hafnium oxide. In this embodiment, the second insulating layer 20 may be a single-layer silicon oxide layer.

[0118] The upper electrode UE can also be disposed on the second insulating layer 20. The upper electrode UE can overlap with the first control electrode GE1.

[0119] The lower control electrode GE2-B of the second transistor T2 can also be disposed on the second insulating layer 20. The lower control electrode GE2-B can overlap with the second semiconductor pattern SP2. The lower control electrode GE2-B and the upper control electrode GE2-U together can form a dual gate.

[0120] The lower control electrode GE2-B and the upper electrode UE can be in the same layer as each other.

[0121] When in the same layer, components can be formed in the same process and / or comprise the same material as each other, components can be corresponding parts of the same material layer, components can be on the same layer by forming an interface with the same lower or upper layer, components can be coplanar with each other or set with the same thickness, etc., and are not limited thereto.

[0122] A third insulating layer 30 covering the upper electrode UE and the lower control electrode GE2-B is disposed on the second insulating layer 20. The third insulating layer 30 may be an inorganic layer and / or an organic layer, and may have a single-layer or multi-layer structure. The third insulating layer 30 may include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon oxynitride, zirconium oxide, and hafnium oxide. In this embodiment, the third insulating layer 30 may be a single-layer silicon oxide layer.

[0123] The second semiconductor pattern SP2 is disposed on the third insulating layer 30. The second semiconductor pattern SP2 may include an oxide semiconductor. The second semiconductor pattern SP2 may include a crystalline or amorphous oxide semiconductor. For example, the oxide semiconductor may include metal oxides such as zinc (Zn), indium (In), gallium (Ga), tin (Sn), and titanium (Ti), or mixtures of metals such as zinc (Zn), indium (In), gallium (Ga), tin (Sn), and titanium (Ti) and their oxides. The oxide semiconductor may include indium tin oxide (ITO), indium gallium zinc oxide (IGZO), zinc oxide (ZnO), indium zinc oxide (IZnO), zinc indium oxide (ZIO), indium oxide (InO), titanium oxide (TiO), indium zinc tin oxide (IZTO), zinc tin oxide (ZTO), etc.

[0124] The second semiconductor pattern SP2 may include an input region (or a first portion), an output region (or a second portion), and a channel region (or a third portion) defined between the input and output regions. The input and output regions may include impurities. The channel region of the second semiconductor pattern SP2 may be defined to correspond to the upper control electrode GE2-U, which will be described later.

[0125] The impurities in the second semiconductor pattern SP2 can be reduced metallic materials. The input and output regions can include metallic materials reduced from metal oxides included in the channel region. Therefore, the second transistor T2 can reduce leakage current and thus function as a switching element with improved switching characteristics.

[0126] A fourth insulating layer 40 covering the second semiconductor pattern SP2 is disposed on the third insulating layer 30. The fourth insulating layer 40 may be an inorganic layer and / or an organic layer, and may have a single-layer or multi-layer structure. The fourth insulating layer 40 may include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon oxynitride, zirconium oxide, and hafnium oxide.

[0127] The upper control electrode GE2-U is disposed on the fourth insulating layer 40. The upper control electrode GE2-U overlaps with the second semiconductor pattern SP2.

[0128] A fifth insulating layer 50 covering the control electrode GE2-U is disposed on the fourth insulating layer 40. The fifth insulating layer 50 may be an inorganic layer and / or an organic layer, and may have a single-layer or multi-layer structure. The fifth insulating layer 50 may include at least one of alumina, titanium oxide, silicon oxide, silicon oxynitride, zirconium oxide, and hafnium oxide.

[0129] A first input electrode DE1, a first output electrode SE1, a second input electrode DE2, and a second output electrode SE2 are disposed on a fifth insulating layer 50. The first input electrode DE1 and the first output electrode SE1 are connected to the first semiconductor pattern SP1 via a first contact hole CH1 and a second contact hole CH2 that expose the input and output regions of the first semiconductor pattern SP1, respectively. The first contact hole CH1 and the second contact hole CH2 penetrate the first insulating layer 10 to the fifth insulating layer 50. One or more of the first insulating layers 10 to the fifth insulating layer 50 may be further referred to as "insulating layers".

[0130] The second input electrode DE2 and the second output electrode SE2 are connected to the second semiconductor pattern SP2 through a third contact hole CH3 and a fourth contact hole CH4 that expose the input and output regions of the second semiconductor pattern SP2, respectively. The third contact hole CH3 and the fourth contact hole CH4 penetrate the fifth insulating layer 50 and the fourth insulating layer 40.

[0131] The display panel DP according to the embodiment may further include a control bridging pattern BBP disposed on the fourth insulating layer 40. The control bridging pattern BBP may branch off from a portion of the upper control electrode GE2-U. That is, the control bridging pattern BBP and the upper control electrode GE2-U may be a single unit, in the same layer as each other. The control bridging pattern BBP may be connected to the lower control electrode GE2-B through a fifth contact hole CH5. The fifth contact hole CH5 penetrates the third insulating layer 30 and the fourth insulating layer 40.

[0132] A sixth insulating layer 60 covering the first input electrode DE1, the first output electrode SE1, the second input electrode DE2, and the second output electrode SE2 is disposed on the fifth insulating layer 50. The sixth insulating layer 60 may be an organic layer and may have a single-layer or multi-layer structure.

[0133] The connection electrode CNE is disposed on the sixth insulating layer 60. The connection electrode CNE can be connected to the first output electrode SE1 through the sixth contact hole CH6 penetrating the sixth insulating layer 60.

[0134] A seventh insulating layer 70 (or passivation layer) covering the connecting electrode CNE is disposed on the sixth insulating layer 60. The seventh insulating layer 70 may be an organic layer and may have a single-layer or multi-layer structure.

[0135] In this embodiment, the sixth insulating layer 60 and the seventh insulating layer 70 may be single-layer polyimide-based resin layers. The embodiments of the present invention are not limited thereto, and the sixth insulating layer 60 and the seventh insulating layer 70 may include at least one selected from acrylic resin, methacrylic resin, polyisoprene, ethylene-based resin, epoxy-based resin, urethane resin, cellulose-based resin, siloxane-based resin, polyamide-based resin, and dinoflagellated resin.

[0136] The light-emitting element OLED is disposed on the seventh insulating layer 70. The anode AE ​​of the light-emitting element OLED is disposed on the seventh insulating layer 70. The anode AE ​​is connected to the connecting electrode CNE through the seventh contact hole CH7 penetrating the seventh insulating layer 70.

[0137] The display element layer DP-OLED may include a light-emitting element OLED and a pixel-defining film PDL. The pixel-defining film PDL is disposed on a seventh insulating layer 70. At least one opening OP may be defined in the pixel-defining film PDL. The opening OP of the pixel-defining film PDL exposes at least a portion of the anode AE ​​to the outside of the pixel-defining film PDL. The opening OP of the pixel-defining film PDL may define the light-emitting region PXA of a pixel PX. For example, multiple pixels PX (see...) Figure 4A The pixels (PX) can be arranged according to specific rules in the plan view of the display panel (DP). The area containing multiple pixels (PX) can correspond to a reference. Figure 4A The described display area DP-DA may include a light-emitting area PXA and a non-light-emitting area NPXA adjacent to the light-emitting area PXA. The non-light-emitting area NPXA may surround the light-emitting area PXA in a plan view.

[0138] A hole control layer (HCL) can be commonly disposed in the emitting region PXA and the non-emitting region NPXA. Common layers such as the hole control layer HCL can be commonly formed in multiple pixels PX (see [link to documentation]). Figure 4A The hole control layer (HCL) can include a hole transport layer and a hole injection layer.

[0139] An organic light-emitting layer (EML) is formed on the hole control layer (HCL). The EML can be formed only in the region corresponding to the opening (OP). The EML can be formed separately on multiple pixels (PX) (see [link]). Figure 4A Each of the following is a list of characters.

[0140] In this embodiment, a patterned organic light-emitting layer (EML) is shown as an example, but the EML can be commonly disposed in multiple pixels (PX). In this case, the EML can generate white light. Furthermore, the EML can have a multi-layered structure.

[0141] An electronic control layer (ECL) is disposed on the organic light-emitting layer (EML). The ECL may include an electron transport layer and an electron injection layer. A cathode (CE) is disposed on the ECL. The ECL and CE are commonly disposed on multiple pixels (PX) (see [link to PX]). Figure 4A )middle.

[0142] An encapsulation layer TFE is disposed on the cathode CE. The encapsulation layer TFE is commonly disposed within multiple pixels PX. In this embodiment, the encapsulation layer TFE directly covers the cathode CE. The encapsulation layer TFE may cover the light-emitting element OLED. The encapsulation layer TFE may include two inorganic encapsulation layers LIL and UIL, and an organic encapsulation layer OL disposed between them. In embodiments of the invention, the encapsulation layer TFE may include multiple inorganic layers and multiple organic layers stacked alternately.

[0143] The inorganic encapsulation layers LIL and UIL protect the OLED light-emitting element from moisture / oxygen, while the organic encapsulation layer OL protects the OLED light-emitting element from foreign matter such as dust particles. The inorganic encapsulation layers LIL and UIL may include, but are not particularly limited to, silicon nitride layers, silicon oxynitride layers, silicon oxide layers, titanium oxide layers, aluminum oxide layers, etc. The organic encapsulation layer OL may include an acrylic organic layer, and is not particularly limited thereto.

[0144] One or more layers from PI1 to UIL can extend from the display area DP-DA to the non-display area DP-NDA.

[0145] refer to Figure 5B A dam portion DMP can be formed by stacking patterns in at least some of the same layers as the insulating layers constituting the display panel DP. In this embodiment, the dam portion DMP may include a first dam portion DMPa and a second dam portion DMPb. The first dam portion DMPa, which is the first dam, and the second dam portion DMPb, which is the second dam, may be patterns that are partially separated from different layers of the display area DP-DA through predetermined openings. The first dam portion DMPa may be disposed on the sixth insulating layer 60 and have a structure in which a second layer 70-A, which is in the same layer as the seventh insulating layer 70, and a third layer PDL-A, which is in the same layer as the pixel defining film PDL, are stacked. The second dam portion DMPb may include a stacked first layer 60-B, a second layer 70-B, a third layer PDL-B, and a fourth layer SPC-B, wherein the first layer 60-B is in the same layer as the sixth insulating layer 60, the second layer 70-B is in the same layer as the seventh insulating layer 70, and the third layer PDL-B is in the same layer as the pixel defining film PDL. The fourth SPC-B layer can be additionally stacked on top of the third PDL-B layer and includes organic material. The dam portion DMP can include an organic layer. Therefore, the dam portion DMP can be formed with a predetermined height and can prevent material overflow, for example, during the formation of the organic encapsulation layer OL of the encapsulation layer TFE.

[0146] Simultaneously, the conductive pattern CDP can be disposed between adjacent layers constituting the dam portion DMP. The conductive pattern CDP can electrically connect the fan-out line RTL and the data line DL-1 to each other. In this embodiment, the data line DL-1 may include a first layer DB as the lower layer and a second layer DU as the upper layer. However, this is shown as an example, and the data line DL-1 may be a single layer, or the conductive pattern CDP may be omitted. In this case, the data line DL-1 may be partially extended to define the extended portion of the data line DL-1 constituting the fan-out line RTL, and is not limited to any one embodiment. Furthermore, the number of layers constituting the dam portion DMP is not limited, and the dam portion DMP may be formed as a single organic layer.

[0147] The embankment section (BNP) is positioned at the end of the display panel (DP) and spaced apart from the dam section (DMP). The embankment section (BNP) can be positioned between multiple pads (PD) and the display area (DP-DA). The pads (PD) can be connected to the fan-out line (RTL). The pads (PD) can be the connection portion connected to the driver chip (DIC) described above, or the pads (PD) connected to the circuit board (FCB), and are not limited to any particular embodiment.

[0148] The dam portion BNP can be formed by stacking at least some of the insulating layers constituting the display panel DP. In this embodiment, the dam portion BNP may include a first layer 60-C in the same layer as the sixth insulating layer 60, a second layer 70-C in the same layer as the seventh insulating layer 70, and a third layer PDL-C in the same layer as the pixel defining film PDL. The dam portion BNP may include a first side surface SF1 facing the display area DP-DA or closest to the display area DP-DA and a second side surface SF2 facing the pad PD. The second side surface SF2 may be oriented in the second direction DR2 in a direction opposite to that of the first side surface SF1.

[0149] The first side surface SF1 may include two or more inclined portions S1 and S2. The inclined portions S1 and S2 may have different inclination angles. The inclination angle may be relative to the upper surface of the base layer SUB and may be less than about 90 degrees. The inclined portions S1 and S2 may include a first inclined portion S1 and a second inclined portion S2. The first inclined portion S1 may be a surface connected to the upper surface UF of the embankment BNP, and the second inclined portion S2 may be positioned lower than the first inclined portion S1, i.e., closer to the base layer SUB. In this embodiment, a flat surface between the first inclined portion S1 and the second inclined portion S2 is shown, but embodiments of the invention are not limited thereto. Additional inclined portions may also be included at the upper surface UF between the first inclined portion S1 and the second inclined portion S2, and embodiments of the invention are not limited to any one of these embodiments.

[0150] In this embodiment, the first inclined portion S1 and the second inclined portion S2 may be defined by different layers. For example, the first inclined portion S1 may be defined by the side surface of the third layer PDL-C, and the second inclined portion S2 may be defined by the side surface of the second layer 70-C. However, this is shown as an example, and the first inclined portion S1 and the second inclined portion S2 may be defined by a single layer, and the embodiment is not limited to any one of these embodiments.

[0151] The cross-section of the second side surface SF2 can have various shapes. In this embodiment, the second side surface SF2 is shown as an inclined portion having a single inclined angle different from that of the first side surface SF1. The first side surface SF1 and the second side surface SF2 may not be aligned with each other, i.e., they may be in different DR1-DR3 planes. However, this is shown as an example, and the second side surface SF2 may have the same shape as the first side surface SF1 so that they are coplanar with each other in the same DR1-DR3 plane, be inclined surfaces with different shapes, or may not have an inclined portion, and is not limited to any one embodiment.

[0152] According to the present invention, the embankment BNP can be an organic film structure that is closest to the pad PD, and the step variation in the first side surface SF1 can be reduced by forming the first side surface SF1 into multiple inclined portions.

[0153] Specifically, refer to Figure 6 This illustrates the attachment of an optical film OTF to a portion of a display panel DP. For clarity, the end portion of the encapsulation layer TFE that contacts the embankment BNP is schematically shown as a single inorganic layer.

[0154] Attaching an optical film OTF may include applying force along the optical film OTF using a roller RLR. The roller RLR may roll along the rolling direction RLD and press the optical film OTF toward the display panel DP, and the optical film OTF may be attached to the upper surface of the display panel DP via an adhesive layer (not shown).

[0155] The scrolling direction RLD can be from the center of the display area DP-DA to the pad PD, that is, from the display area DP-DA to the pad area PA. Figure 6 In the diagram, the directions AAD from the pad area PA toward the display area DP-DA and DCD from the display area DP-DA toward the pad PD are indicated by arrows.

[0156] As described above, the first side surface SF1 of the embankment BNP may include two or more inclined portions S1 and S2 having different inclination angles from each other. The first inclined portion S1 and the second inclined portion S2 have different inclination angles from each other. Furthermore, in this embodiment, the first inclined portion S1 and the second inclined portion S2 may be defined by the upper surfaces of different organic layers, but are not limited thereto.

[0157] The encapsulation layer TFE contacts the fifth insulating layer 50, which is an inorganic layer, extends along the first side surface SF1 of the embankment BNP, and covers at least a portion of the first side surface SF1. The fifth insulating layer 50, which is an inorganic layer, can form a step together with the inclined portions S1 and S2 of the first side surface SF1 of the embankment BNP.

[0158] When the optical film OTF is rolled, the pressure applied from the roller RLR can be transmitted to the embankment BNP due to the protruding shape of the embankment BNP. In this case, the first side surface SF1 of the embankment BNP can be the surface facing the roller RLR in the rolling direction RLD and is the first to contact the roller RLR. Due to the large height within the step of the first side surface SF1 and the large height of the upper surface UF of the embankment BNP, the impact generated by the collision with the roller RLR may be significant. However, even if the overall protrusion of the embankment BNP is large, the repulsive force of the embankment BNP against the movement of the roller RLR can be minimized when the overall distance of the step of the first side surface SF1 is gradually segmented into two different inclinations along the second direction DR2. That is, the influence of the embankment BNP during the movement of the roller RLR can be reduced, and therefore the roller RLR can smoothly roll upward to the upper surface UF of the embankment BNP and press the optical film OTF.

[0159] The first step can be defined by the second inclined portion S2 and the portion of the embankment BNP between the second inclined portion S2 and the first inclined portion S1. Here, the portion can have an inclination angle smaller than that of the second inclined portion S2, for example, it can be flat.

[0160] Therefore, according to the present invention, by segmenting the inclined portion so that the first side surface SF1 of the embankment BNP has multiple inclined angles and minimizing the height of the step of the first side surface SF1 of the embankment BNP, the impact generated by the collision between the optical film OTF and the embankment BNP during the process of attaching the optical film OTF can be minimized, and damage to the lower inorganic layers 10, 20, 30, 40 and 50 due to the impact can be minimized. Therefore, the risk of moisture infiltration and damage to the fan-out line RTL due to damage to the lower inorganic layers 10, 20, 30, 40 and 50 can be reduced, and the manufacturing process reliability of electronic devices can be improved.

[0161] Figure 7A and Figure 7B Each of the above is a schematic cross-sectional view of the embankment sections BNP1 and BNP2 according to an embodiment of the present invention. Referring below... Figure 7A and Figure 7B The present invention is described. Meanwhile, in conjunction with the references... Figures 1 to 6 Components that are described identically will be represented by the same reference numerals or symbols, and repeated descriptions will be omitted.

[0162] refer to Figure 7A and Figure 7B The embankments BNP1 and BNP2 can be formed by stacking three organic layers OL1, OL2, and OL3 on the inorganic layer IL. The inorganic layer IL can be a covering fan-out line RTL (see [link to RTL]). Figure 4A() layers, and include Figure 5B At least one of the insulating layers 10, 20, 30, 40, and 50 shown. Each of the organic layers OL1, OL2, and OL3 may be Figure 5B The organic layer shown is one of the organic layers 60, 70 and PDL or an additional organic layer, and is not limited to any one embodiment.

[0163] refer to Figure 7A The first side surface SF11 of the embankment BNP1 may include multiple inclined portions SLP1, SLP2, and SLP3. Inclined portions SLP1, SLP2, and SLP3 may include a first inclined portion SLP1, a second inclined portion SLP2, and a third inclined portion SLP3, each having a predetermined inclination angle relative to the second direction DR2, and at least two inclined portions may have different inclination angles from each other. In this embodiment, the inclination angle of the first side surface SF11 may decrease in the second inclined portion SLP2 compared to the first inclined portion SLP1, and increase in the third inclined portion SLP3 compared to the second inclined portion SLP2. That is, the inclination angle of the first side surface SF11 may not only decrease along the second direction DR2 but may also increase along it. It is shown that the inclination angle of the third inclined portion SLP3 is greater than the inclination angle of the first inclined portion SLP1, but the embodiments of the present invention are not limited to this, and the inclination angle of the third inclined portion SLP3 may be less than or equal to the inclination angle of the first inclined portion SLP1.

[0164] The second organic layer OL2 covers both the upper and side surfaces of the first organic layer OL1, and the third organic layer OL3 covers both the upper and side surfaces of the second organic layer OL2. The first side surface SF11 of the embankment BNP1 may be defined by the side surface of the third organic layer OL3. In this case, the upper surface of the third organic layer OL3 may be located at a position higher than the upper surface of the second organic layer OL2, and the third organic layer OL3 may include inclined portions that are further segmented compared to the side surface of the second organic layer OL2. According to the invention, by forming a plurality of inclined portions SLP1, SLP2 and SLP3 along the first side surface SF11, the inclination of the step according to the height of the embankment BNP1 can be gradually segmented. Therefore, the step variation in the first side surface SF11 can be reduced, and thus the adhesion of the optical film OTF (see Figure 6 The impact generated during the process is based on the collision between the roller RLR and the embankment BNP1 at the third inclined section SLP3.

[0165] refer to Figure 7BThe first side surface SF12 of the embankment BNP2 may include multiple inclined portions SLP1, SLP2 and SLP3. The first side surface SF12 of the embankment BNP2 may have a shape corresponding to the embankment BNP1 described above, and therefore repeated descriptions will be omitted.

[0166] The first side surface SF12 of the embankment BNP2 can be defined by the side surface of the third organic layer OL3. However, the stacking configuration of the organic layers OL1, OL2, and OL3 can differ from that of the third organic layer OL3. Figure 7A The stacking configuration is as follows. Specifically, the second organic layer OL2 may only cover the upper surface of the first organic layer OL1 and expose the side surfaces of the first organic layer OL1. The third organic layer OL3 may not only cover the upper and side surfaces of the second organic layer OL2, but also cover the exposed side surfaces of the first organic layer OL1.

[0167] In this embodiment, the first side surface SF12 of the embankment BNP2 can be controlled according to the stacking pattern and angle of the first organic layer OL1 and the second organic layer OL2. According to the invention, by forming a plurality of inclined portions SLP1, SLP2, and SLP3 at the first side surface SF12, the steps according to the height of the embankment BNP2 can be gradually segmented. Therefore, the step variation in the first side surface SF12 can be reduced, and thus the adhesion of the optical film OTF (see [link to OTF]) can be minimized. Figure 6 The impact generated during the process is based on the collision between the roller RLR and the embankment BNP2 at the third inclined section SLP3.

[0168] refer to Figure 6 , Figure 7A and Figure 7B For each portion of the side surface defined by the change in tilt angle, such as the sequential third tilt portion SLP3 (at the first angle), the second tilt portion SLP2 (at the second angle), and the first tilt portion SLP1, the second angle following the first angle along the rolling direction RLD can be smaller than the first angle. The stepped region GA can be defined from one end of the first side surface SF1 toward the dam portion DMP. (Reference) Figure 4A and Figure 5B For example, the stepped region GA may not overlap with the dam section DMP, such as being spaced apart from the dam section DMP along the second direction DR2.

[0169] Figure 8A and Figure 8B Each is a plan view of an electronic device ED according to an embodiment of the present invention. Figure 8A and Figure 8B Each schematically illustrates the display panel DP and the circuit board FCB, corresponding to... Figure 4A The display panel (DP) and circuit board (FCB). References will be made below. Figure 8Aand Figure 8B The present invention is described. Meanwhile, in conjunction with the references... Figures 1 to 7B Components that are described identically will be represented by the same reference numerals or symbols, and repeated descriptions will be omitted.

[0170] refer to Figure 8A In the display panel DP, the dam section BNP can be omitted. In this case, the organic film closest to the first pad region PA1 or the second pad region PA2 can be part of the dam section DMP. Therefore, the stepped region GA can overlap with the inner surface of the dam section DMP facing the display region DP-DA. Since the inner surface of the dam section DMP includes multiple inclined portions with different inclination angles, the steps of the inner surface can be segmented. Its detailed description corresponds to the dam section BNP described above (see...). Figure 5B The first side surface SF1 (see) Figure 5B A detailed description of () will be omitted, and therefore repeated descriptions will be omitted. That is to say, Figure 8A The inner surface of the dam section DMP can have the inclined structure of the first side surface SF1 described above.

[0171] In the planar diagram, the fan-out line RTL can have a linear shape parallel to the second direction DR2 within the stepped region GA. That is, the third portion L3 of the first portion L1, second portion L2, and third portion L3 of the fan-out line RTL can have a length that overlaps with the stepped region GA. Therefore, the overlap area between the fan-out line RTL and the stepped region GA can be minimized, and the area of ​​the attached optical film OTF within the stepped region GA can be minimized (see...). Figure 6 The impact generated during the process is based on the collision with the dam section DMP.

[0172] refer to Figure 8B Multiple dam sections DMP1 and DMP2 can be configured, and the dam section BNP can be omitted in the display panel DP. Dam sections DMP1 and DMP2 can include a first dam section DMP1, which is an inner dam, and a second dam section DMP2, which is an outer dam, formed as a spaced-apart structure. In this case, the organic film closest to the first pad region PA1 or the second pad region PA2 can be the second dam section DMP2.

[0173] The stepped region GA can be formed between the first dam section DMP1 and the second dam section DMP2, and overlaps with the inner surface of the facing display area DP-DA of the second dam section DMP2. Since the inner surface of the second dam section DMP2 includes multiple inclined portions with different inclination angles, the steps of the inner surface overlapping the stepped region GA can be segmented. Its detailed description corresponds to the embankment section BNP described above (see...). Figure 5BThe first side surface SF1 (see) Figure 5B A detailed description of () will be omitted, and therefore repeated descriptions will be omitted. That is to say, Figure 8B The inner surface of the second dam section DMP2 can have the inclined structure of the first side surface SF1 described above.

[0174] In the planar diagram, the fan-out line RTL can have a linear shape parallel to the second direction DR2 within the stepped region GA. That is, the third portion L3 of the first portion L1, second portion L2, and third portion L3 of the fan-out line RTL can have a length that overlaps with the stepped region GA. Therefore, the overlap area between the fan-out line RTL and the stepped region GA can be minimized, and the area of ​​the attached optical film OTF within the stepped region GA can be minimized (see...). Figure 6 The impact generated during the process is based on the collision with the dam section DMP.

[0175] Figure 9 This is a plan view showing a portion of a display panel DP according to an embodiment of the present invention. (Reference) Figure 9 The display panel DP may include a first fan-out line RTL_L and a second fan-out line RTL_U, which are disposed on different layers among the layers disposed on the base layer SUB. The second fan-out line RTL_U, which is an upper fan-out line, may be disposed on a layer above the first fan-out line RTL_L, which is a lower fan-out line, and at least one insulating layer may be disposed between the first fan-out line RTL_L and the second fan-out line RTL_U.

[0176] Relative to the stepped region GA, each of the first sector RTL_L and the second sector RTL_U may include a first portion L1 disposed between the stepped region GA and the display area DP-DA, and a portion disposed between the stepped region GA and the pad PD (see [link to documentation]). Figure 4A The second part L2 between the first part L1 and the second part L2, and the third part L3 connecting the first part L1 and the second part L2 to each other. The first part L1 and the third part L3 may be inclined or parallel to the second direction DR2, and the third part L3 may be designed to be parallel to the second direction DR2. The third part L3 intersecting the stepped region GA may be designed to have a minimum dimension (or length) in the direction from the display region DP-DA to the pad region PA.

[0177] The display panel DP according to this embodiment may include fan-out lines RTL_U and RTL_L disposed on different layers, and thus the contact, electrical influence, and total planar area along the base layer SUB between the first fan-out line RTL_L and the second fan-out line RTL_U can be minimized. Therefore, the planar space between the first fan-out line RTL_L and the second fan-out line RTL_U in the plan view can be formed narrowly, which makes it possible to design fine pitch of the fan-out line RTLs, and can be advantageous for forming a high-resolution display panel.

[0178] Furthermore, the fan-out lines RTL_U and RTL_L according to the invention may include a third portion L3 parallel to the second direction DR2 in the stepped region GA, and thus can minimize the route (e.g., length) traversed along the stepped region GA. This can be substantially equivalent to minimizing the planar area of ​​the fan-out lines RTL_U and RTL_L overlapping with the stepped region GA.

[0179] As described above, the stepped region GA can be achieved during the process of attaching the optical film OTF to the stacked structure of the underlying display panel DP, possibly with rollers RLR (see above). Figure 6 The area where a collision occurs, and the impact or force generated by the collision is transmitted to it. According to the invention, even if the encapsulation layer TFE to which the optical film OTF is attached is damaged, by designing the third portion L3 of the fan-out lines RTL_U and RTL_L overlapping the stepped region GA parallel to the second direction DR2, the area (e.g., planar area) of the fan-out lines RTL_U and RTL_L exposed due to the damaged encapsulation layer TFE can be minimized. Therefore, the process reliability of the display panel DP can be improved.

[0180] Figure 10A This is a plan view showing a portion of a display panel DP according to an embodiment of the present invention. Figure 10B It shows the relationship with Figure 10A A cross-sectional view of the display panel DP, which corresponds to a portion of the area. Figure 10A It shows the relationship with Figure 9 The region corresponding to the region, and Figure 10B The components of the display panel DP are shown schematically. Reference will be made below. Figure 10A and Figure 10B The present invention is described. Meanwhile, in conjunction with the references... Figures 1 to 9 Components that are described identically will be represented by the same reference numerals or symbols, and repeated descriptions will be omitted.

[0181] like Figure 10AAs shown, each of the fan-out lines RTL_U and RTL_L can include a third portion L3 in the stepped region GA parallel to the second direction DR2. Figure 10A It can basically correspond to Figure 9 Therefore, repeated descriptions will be omitted.

[0182] like Figure 10B As shown, the first inorganic layer IL1 can be disposed between the first fan-out line RTL_L and the second fan-out line RTL_U, and the second fan-out line RTL_U can be covered by the second inorganic layer IL2. For ease of illustration, the embankment BNP is shown as a single layer, and the encapsulation layer TFE can cover the embankment BNP and the second inorganic layer IL2. For ease of description, Figure 10B The components shown may correspond to one of the insulating layers 10, 20, 30, 40, 50, 60, 70, PDL, LIL, OL and UIL described above, or may be shown in part, and repeated descriptions will be omitted.

[0183] Points E1, E2, and E3 are indicated along the first side surface SF1 of the embankment BNP. Points E1, E2, and E3 can be sequentially positioned within the stepped region GA in the direction from the pad region PA to the display region DP-DA (i.e., towards one end OTF_E of the optical film OTF and one end TFE_E of the encapsulation layer TFE). Each of the ends OTF_E of the optical film OTF and TFE_E of the encapsulation layer TFE can be the farthest end of the respective layer from the display region DP-DA. The optical film OTF can extend further than one end TFE_E of the encapsulation layer TFE, for example, to define an extended portion of the optical film OTF. Here, the extended portion can define one end OTF_E of the optical film OTF.

[0184] Points E1, E2, and E3 can indicate the change in tilt angle of the first side surface SF1 relative to the adjacent tilt angle. In the interval WD from point E1 to point E3, each of the fan-out lines RTL_L and RTL_U can have a linear shape extending in the second direction DR2 in the plan view.

[0185] The first tilt angle AG1, the second tilt angle AG2, and the third tilt angle AG3, measured at the first point E1, the second point E2, and the third point E3 respectively, can be different from each other. In this embodiment, among the first tilt angle AG1, the second tilt angle AG2, and the third tilt angle AG3, the second tilt angle AG2 can be the smallest, and the third tilt angle AG3 can be the largest. The third point E3 can be one end of the first side surface SF1, which is one end of the embankment BNP.

[0186] Furthermore, the inclination shape of each of the first point E1, the second point E2, and the third point E3 can be different. In this embodiment, within the portion of the embankment BNP, the inclination portion passing through the first point E1 can have a relatively convex curved surface shape (its inclination angle increases toward the first point E1), the inclination portion between the first point E1 and the second point E2 can have a relatively concave curved surface shape, and the inclination portion between the second point E2 and the third point E3 can again have a convex curved surface shape. That is, when the first side surface SF1 includes a curved surface, the first point E1, the second point E2, and the third point E3 can be inflection points of the angular change of the first side surface SF1.

[0187] Simultaneously, the tilt angle of the first side surface SF1 can increase and then gradually decrease in the direction from the second point E2 to the third point E3. Therefore, a tail can be formed at one end of the first side surface SF1. Thus, the step connecting or intersecting with the second inorganic layer IL2 at the third point E3 can be minimized, and the impact with the roller RLR during attachment of the optical film OTF to the stacked structure can be minimized. According to embodiments of the present invention, the first side surface SF1 may include tilted portions with different tilt angles, and the tilted portions may be configured in various shapes, such as flat surfaces and curved surfaces, but are not limited to any one embodiment.

[0188] Figure 11A and Figure 11B Each is a plan view illustrating the process of manufacturing (or providing) a display panel DP according to an embodiment of the present invention. Figure 11A and Figure 11B Each showed the same as Figure 10A The area shown (where the operation to form the embankment BNP is provided) corresponds to the planar area. Reference will be made below. Figure 11A and Figure 11B The present invention is described. Meanwhile, in conjunction with the references... Figures 1 to 10B Components that are described identically will be represented by the same reference numerals or symbols, and repeated descriptions will be omitted.

[0189] refer to Figure 11A The dammed BNP can be formed using a photolithography process employing a mask MSK1. The mask MSK1 can include an opening region (OPA) and a slit region (SLA). The organic film used to form the dammed BNP can be formed throughout the base layer SUB (see [link to documentation]). Figure 5B The organic film described for this method may include one or more of the organic layers described above, from which various thickness portions of the embankment BNP are formed. The mask MSK1 may be integrally formed with an integral mask for forming the organic film formed in the display area DP-DA.

[0190] The opening region OPA can correspond to the area where the organic film is removed from the underlying preliminary stack structure. The organic film can be easily removed by an exposure dose through the opening region OPA. The slit region SLA can be a region comprising solid portions of a mask MSK1, which are spaced apart from each other and have openings (e.g., slits) therebetween. When the width of the slit in the second direction DR2 is relatively large, the exposure dose through the mask MSK1 can be relatively large. According to this embodiment, a sloping portion shape whose thickness decreases in the opposite direction of the second direction DR2 (i.e., in the direction from the display area DP-DA to the pad area PA) can be formed by designing the slit region SLA to include slits whose width decreases along the stepping region GA in the opposite direction of the second direction DR2. Furthermore, multiple sloping portions can be easily formed by controlling the spacing between slits, the width of the slits, and / or the number of slits.

[0191] refer to Figure 11B The mask MSK2 may include an opening region OPA and a halftone region HFA. In this embodiment, for ease of description, the halftone region HFA and the opening region OPA are shown with different shades. The opening region OPA may be a full-tone region. Since the exposure dose in the halftone region HFA is relatively low compared to the opening region OPA, the sloping portion of the embankment BNP can be formed by removing only a portion of the underlying organic film.

[0192] The embankment BNP according to an embodiment of the present invention can be formed by various manufacturing methods, as long as the first side surface SF1 is formed with different inclined portions, and is not limited to any one embodiment.

[0193] The display device DD according to the embodiments can be applied to various electronic devices. The electronic device ED according to the embodiments may include the display device DD described above, and may also include additional modules or devices with additional functions in addition to the display device DD.

[0194] Figure 12 This is a block diagram of an electronic device ED according to an embodiment. (Reference) Figure 12 The electronic device ED according to the embodiment may include a display module DM, a processor PP, a memory MM, and a power module PM. The electronic device ED may correspond to... Figure 1 The electronic device ED is shown.

[0195] The processor PP may include at least one of a central processing unit (CPU), an application processor (AP), a graphics processing unit (GPU), a communication processor (CP), an image signal processor (ISP), and a controller. In embodiments, the processor PP may be functionally or structurally divided into two or more, and such processor PPs may be provided. For example, the processor PP may include a main processor having a first driver chip including a central processing unit, and an auxiliary processor having a second driver chip including a controller, wherein the auxiliary processor receives image signals from the main processor and processes the image signals to conform to the interface specifications of the display module DM.

[0196] The memory MM may include at least one of non-volatile memory and volatile memory. Data required for the operation of the processor PP or the display module DM may be stored in the memory MM. When the processor PP executes the application program stored in the memory MM, image data signals and / or input control signals may be transmitted to the display module DM, and the display module DM may process the provided signals and output image information through the display screen.

[0197] A power module (PM) may include a power supply module such as a power adapter or battery device and a power conversion module that converts the power supplied by the power supply module to generate the power required for the operation of electronic devices (EDs). Power conversion using a power conversion module may include, but is not limited to, DC-DC conversion, AC-DC conversion, and DC-AC conversion.

[0198] At least one of the components of the electronic device ED described above may be included in the display device DD according to the embodiments described above. Furthermore, some of the discrete modules included in a functionally unified module may be included in the display device DD, and other discrete modules may be provided separately from the display device DD. For example, the display device DD may include a display module DM and an auxiliary processor of a processor PP, and the main processor of the processor PP, the memory MM, and the power module PM may be provided as another device in the electronic device ED that is not a display device. As another example, the power module PM may be provided in the display device DD and supply power to the processor PP and the memory MM of the non-display device DD provided in the electronic device ED, and the embodiments of the present invention are not limited to the above examples.

[0199] Figure 13 Schematic diagrams of electronic devices according to various embodiments are shown.

[0200] refer to Figure 13The various electronic devices to which the display device DD according to the embodiments can be applied include not only electronic devices ED for displaying images (such as smartphones ED_1a, tablet PCs ED_1b, laptop computers ED_1c, televisions ED_1d, and desktop displays ED_1e), but also wearable electronic devices including display modules DM (such as smart glasses ED_2a, head-mounted displays ED_2b, and smartwatches ED_2c), and automotive electronic devices ED_3 including display modules DM (such as central information displays (CIDs) installed on the instrument panel, central dashboard, and dashboard of a car, interior mirror displays, etc.).

[0201] Figure 13 Electronic devices ED may include Figure 12 The components shown. For example, the smartphone ED_1a may include... Figure 12 The diagram shows a display module DM, a processor PP, a memory MM, and a power module PM. The smartphone ED_1a may also include a communication module and a battery device. Power supplied from the battery device can be converted by the power module PM and supplied to the processor PP, the memory MM, and the display module DM. In some embodiments, the display device used in the smartphone ED_1a may include the display module DM and may also include the power module PM. The processor PP and the memory MM may be provided as chips mounted on a motherboard for external devices, but embodiments of the invention are not limited thereto.

[0202] According to the present invention, the impact applied to the display panel DP during the attachment of the optical film OTF can be mitigated. Furthermore, according to the present invention, the area of ​​the image fan-out line RTL signal lines exposed to the outside of the display panel DP due to the impact occurring during the attachment of the optical film OTF can be minimized. Therefore, the possibility of signal line damage can be reduced. Thus, the manufacturing process reliability of the electronic device ED can be improved.

[0203] The present invention has been described above with reference to embodiments thereof. However, those skilled in the art will understand that various modifications and alterations can be made to the present invention, as long as such modifications and alterations do not depart from the spirit and scope of the invention as set forth in the appended claims. Therefore, the scope of the present invention is not limited to the contents stated in the detailed description of the specification, but should be determined by the claims.

Claims

1. Electronic devices, including: The base substrate includes a display area and a peripheral area adjacent to the display area; A light-emitting element layer, in the display area, the light-emitting element layer includes a pixel defining film having an opening defined therein and a light-emitting element in the opening; A driving element layer is provided between the base substrate and the light-emitting element layer. The driving element layer includes a pixel driving portion, a signal line, an organic film, and an inorganic film. The pixel driving portion is connected to the light-emitting element, and the signal line is connected to the pixel driving portion. The signal line includes a fan-out line in the peripheral region and defines a pad portion at one end thereon. An encapsulation layer is provided on the light-emitting element layer, the encapsulation layer comprising an inorganic encapsulation layer; as well as A dam portion, in the peripheral region, extends along a first direction and is spaced apart from the display area in a second direction intersecting the first direction. The dam portion includes an organic layer and has a first side surface closest to the display area. The first side surface includes at least two inclined portions adjacent in the second direction and having different inclination angles in a cross-sectional view. in, The peripheral region includes a stepped region defined between the pad portion and the display area, the stepped region overlapping the first side surface of the embankment, and The first portion of the fan-out line overlaps with the stepped region and is parallel to the second direction in the plan view.

2. The electronic device according to claim 1, further comprising a driver chip connected to the pad portion.

3. The electronic device of claim 1, further comprising a circuit board connected to the pad portion.

4. The electronic device according to claim 1, wherein, The tilt angle is less than 90 degrees.

5. The electronic device according to claim 4, wherein, The organic layer of the embankment is in the same layer as the organic film of the driving element layer, or in the same layer as the pixel defining film.

6. The electronic device of claim 1, further comprising an optical film, the optical film being on the encapsulation layer and covering the stepped region, one end of the optical film being furthest from the display area, and in, The embankment overlaps with one end of the optical film.

7. The electronic device according to claim 6, wherein, The inorganic encapsulation layer covers the stepped area, and one end of the inorganic encapsulation layer is furthest from the display area. The optical film covers one end of the inorganic encapsulation layer.

8. The electronic device according to claim 1, wherein, The fan-out line also includes: The second portion extends from one end of the first portion toward the display area, and the second portion is inclined relative to the first portion in the plan view; and The third portion extends from the other end of the first portion toward the pad portion, and the third portion is inclined relative to the first portion in the plan view.

9. The electronic device according to claim 1, wherein, The embankment has a frame shape surrounding the display area.

10. The electronic device according to claim 1, wherein, The first side surface of the embankment has a curved surface.

11. Electronic devices, including: The display panel includes: Substrate, An inorganic layer, on the substrate, Fan-out lines are located between the substrate and the inorganic layer. A light-emitting element, situated on the inorganic layer, comprises an anode, a light-emitting layer, and a cathode. A dam, on the inorganic layer, overlaps with the fan-out line, extends along a first direction, and is spaced apart from the light-emitting element in a second direction intersecting the first direction. The dam includes an organic layer and has a first side surface facing the light-emitting element along the second direction. The first side surface includes at least two inclined portions adjacent in the second direction and having different inclination angles in a cross-sectional view. An encapsulation layer covering the light-emitting element, the encapsulation layer comprising a first inorganic encapsulation layer, an organic encapsulation layer, and a second inorganic encapsulation layer, and An optical film, on the display panel, includes an end that overlaps with the embankment. The first portion of the fan-shaped line overlaps with the first side surface of the embankment and is parallel to the second direction in the plan view.

12. The electronic device according to claim 11, wherein, Within the first side surface of the embankment, each of the tilt angles is less than 90 degrees.

13. The electronic device according to claim 11, wherein, Within the embankment: The organic layers are configured in multiple ways to define multiple organic layers, and The first side surface of the embankment is defined by the respective side surfaces of at least two of the plurality of organic layers.

14. The electronic device according to claim 11, wherein, Within the embankment: The organic layers are configured in multiple ways to define multiple organic layers, and The first side surface of the embankment is defined by any one of the plurality of organic layers.

15. The electronic device according to claim 14, wherein, Within the embankment: The plurality of organic layers includes a first organic layer, a second organic layer, and a third organic layer stacked sequentially. The second organic layer covers the first organic layer. The third organic layer is spaced apart from the first organic layer and covers the second organic layer, and The first side surface of the embankment is defined by the third organic layer.

16. The electronic device according to claim 14, wherein, Within the embankment: The plurality of organic layers includes a first organic layer, a second organic layer, and a third organic layer stacked sequentially. The second organic layer exposes the side surface of the first organic layer, and The third organic layer covers the exposed side surface of the first organic layer.

17. The electronic device according to claim 11, wherein, The embankment also includes a second side surface opposite to the first side surface along the second direction, and The second side surface has a shape different from that of the first side surface in the cross-sectional view.

18. The electronic device according to claim 11, wherein, At the location where it overlaps with the fan-out line, at least one of the first inorganic encapsulation layer and the second inorganic encapsulation layer is in contact with the inorganic layer.

19. The electronic device according to claim 11, wherein, The fan-out line further includes a second portion that extends from one end of the first portion and is inclined relative to the first and second directions in a plane defined by the intersecting first and second directions.

20. The electronic device according to claim 19, wherein, The fan-out line also includes a third portion that extends from the other end of the first portion and overlaps with the said end of the optical film.

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