A method for manufacturing a high aspect ratio semiconductor device

Abstract

This application discloses a method for fabricating a high aspect ratio semiconductor device, relating to the field of semiconductor fabrication technology. The method includes: providing a substrate layer; forming at least one high aspect ratio trench structure in the substrate layer, the aspect ratio of the trench structure being greater than or equal to 5:1; depositing at least one silicon layer within the trench structure, the silicon layer conformally covering the bottom and sidewalls of the trench structure, and forming pores between the silicon layers at the bottom and sidewalls of the trench structure; and performing a thermal oxidation treatment on the trench structure with the deposited silicon layer, so that the silicon layer is completely oxidized to form a silicon oxide layer, thereby forming a high aspect ratio filling structure within the pores. The high aspect ratio semiconductor device fabricated by this application has a highly dense filling structure, simple fabrication process, and high process compatibility.

Description

Technical Field

[0001] This invention relates to the field of semiconductor fabrication technology, and more specifically to a method for fabricating a high aspect ratio semiconductor device. Background Technology

[0002] As micro-electro-mechanical systems (MEMS) devices and silicon photonics integrated devices develop towards higher integration, miniaturization, and higher performance, the fabrication process commonly requires the formation of high aspect ratio structures such as deep trenches, deep holes, or waveguide trenches in the substrate to achieve functions such as electrical isolation, mechanical support, or optical field confinement. Reliable filling of these high aspect ratio trench structures, especially achieving void-free, low-stress, and high-quality oxide filling, has become a key process issue restricting device performance and yield.

[0003] In existing technologies, methods such as low-pressure chemical vapor deposition (LPCVD), plasma-enhanced chemical vapor deposition (PECVD), high-density plasma chemical vapor deposition (HDPCVD), or atomic layer deposition (ALD) are commonly used to directly deposit silicon oxide material in high aspect ratio trenches to achieve filling. However, these methods still have significant shortcomings in practical applications: for example, vapor-deposited silicon oxide tends to preferentially grow at the trench opening in high aspect ratio trenches, leading to premature closure at the top and the formation of voids or gaps inside the trench; plasma-related processes may also introduce ion bombardment damage and additional stress; while ALD processes offer good conformality, their deposition rate is low and process cost is high, making it difficult to meet the needs of large-scale manufacturing.

[0004] For structures such as silicon waveguides, which are extremely sensitive to interface quality and film stress, the aforementioned direct oxide filling method can easily introduce interface defects and stress concentration at the waveguide sidewalls, thereby increasing light scattering loss and affecting the optical performance and long-term reliability of the device. How to achieve oxide filling that balances high filling quality, low porosity, low stress, and good process compatibility in high aspect ratio trench structures remains a pressing technical problem to be solved in this field. Summary of the Invention

[0005] One objective of this invention is to provide a method for fabricating high aspect ratio semiconductor devices, solving the technical problem in the prior art of achieving silicon oxide filling that simultaneously achieves gapless filling, low stress, high film quality, and good process compatibility within high aspect ratio trench structures.

[0006] Another objective of this invention is to further enhance the volume expansion effect during the conversion of silicon crystal layers to silicon oxide.

[0007] According to the purpose of this invention, a method for fabricating a high aspect ratio semiconductor device is provided, comprising: A substrate is provided in which at least one high aspect ratio trench structure is formed, wherein the aspect ratio of the trench structure is greater than or equal to 5:1; At least one silicon layer is deposited within the trench structure, the silicon layer covering the bottom and sidewalls of the trench structure in a conformal deposition manner, and pores are formed between the silicon layer at the bottom and sidewalls of the trench structure; The trench structure on which the silicon crystal layer is deposited is subjected to thermal oxidation treatment, so that the silicon crystal layer is completely oxidized to form a silicon oxide layer, thereby forming a high aspect ratio filling structure in the pores.

[0008] Optionally, the silicon crystal layer deposition process is any one of low-pressure chemical vapor deposition, rapid thermal chemical vapor deposition, and plasma-enhanced chemical vapor deposition; Preferably, the thickness of the silicon crystal layer is proportional to the width of the trench structure, and the material of the silicon crystal layer is amorphous silicon, polycrystalline silicon, doped amorphous silicon, or doped polycrystalline silicon.

[0009] Optionally, the deposition temperature of the silicon crystal layer is any value between 400℃ and 620℃, and the pressure is any value between 100mTorr and 500mTorr.

[0010] Optionally, the precursor gas for the deposition process of the silicon crystal layer is at least one of dichlorosilane, trichlorosilane, silicon tetrachloride, phosphine, silane, or disilane.

[0011] Optionally, the oxidation temperature of the thermal oxidation treatment is any value between 550℃ and 1350℃.

[0012] Optionally, the oxidizing medium for the thermal oxidation treatment is any one of dry oxygen, wet oxygen, or water vapor.

[0013] Optionally, the oxidation time of the thermal oxidation treatment is determined based on the thickness of the silicon crystal layer.

[0014] Optionally, the substrate layer includes a silicon substrate, an insulating layer, and a semiconductor structure layer stacked sequentially from bottom to top, wherein the semiconductor structure layer is a deep silicon etched structure, a silicon optical waveguide structure, or a lithium niobate thin film structure.

[0015] Optionally, the thickness of the silicon crystal layer in a single deposition is any value between 5 nm and 1000 nm.

[0016] Optionally, when the semiconductor structure layer of the substrate is the silicon optical waveguide structure, the step of depositing at least one silicon crystal layer in the trench structure further includes: The groove structure is then subjected to annealing.

[0017] This invention deposits a conformal silicon crystal layer within a high aspect ratio trench structure and utilizes the volume expansion effect during its thermal oxidation process to gradually fill the pores originally located inside the trench structure with silicon oxide, thereby achieving a void-free or virtually void-free filling of the high aspect ratio trench structure. This significantly improves the filling integrity, the density of the filling layer, and the reliability of the device structure, and the process is simple and has good compatibility.

[0018] Furthermore, by limiting the oxidation temperature of the thermal oxidation process to the range of 550℃-1350℃, this invention enables the silicon crystal layer to undergo a controlled and sufficient oxidation reaction under different thermal budget conditions. Lower oxidation temperatures help to slow down the oxidation rate, reduce oxidation stress concentration, and suppress the generation of interface defects, while higher oxidation temperatures help to increase the oxidation rate and the density of the oxide layer, thereby enhancing the volume expansion effect during the conversion of the silicon crystal layer to silicon oxide.

[0019] The above description is merely an overview of the technical solution of the present invention. In order to better understand the technical means of the present invention and to implement it in accordance with the contents of the specification, the preferred embodiments of the present invention are described in detail below with reference to the accompanying drawings. Attached Figure Description

[0020] The following sections will describe some specific embodiments of the invention in detail by way of example and not limitation, with reference to the accompanying drawings. The same reference numerals in the drawings denote the same or similar parts or portions. Those skilled in the art should understand that these drawings are not necessarily drawn to scale. In the drawings: Figure 1 This is a schematic structural diagram of a semiconductor device according to an embodiment of the present invention; Figure 2 This is a focused ion beam scanning electron microscope image of a semiconductor device according to an embodiment of the present invention; Figure 3 This is a schematic structural diagram of a substrate layer according to an embodiment of the present invention; Figure 4This is a schematic flowchart of a method for fabricating a semiconductor device according to an embodiment of the present invention; Figure 5 This is a schematic structural diagram of a trench structure according to an embodiment of the present invention; Figure 6 This is a focused ion beam scanning electron microscope image of a trench structure according to an embodiment of the present invention; Figure 7 This is a schematic structural diagram of silicon crystal layer deposition according to an embodiment of the present invention; Figure 8 This is a focused ion beam scanning electron microscope image of silicon crystal layer deposition according to an embodiment of the present invention; Figure 9 This is a focused ion beam scanning electron microscope image of the semiconductor device according to Embodiment 1 of the present invention; Figure 10 This is a focused ion beam scanning electron microscope image of the semiconductor device according to Comparative Example 1 of the present invention.

[0021] Figure label: 100 - Semiconductor device, 10 - Substrate layer, 11 - Silicon substrate, 12 - Insulating layer, 13 - Semiconductor structure layer, 131 - Trench structure, 20 - Silicon crystal layer, 21 - Pore, 30 - Filled structure. Detailed Implementation

[0022] The specific embodiments of the present invention will be described in further detail below with reference to the accompanying drawings and examples. The following examples are for illustrative purposes only and are not intended to limit the scope of the invention.

[0023] To make the above-mentioned objectives, features, and advantages of this application more apparent and understandable, the specific embodiments of this application will be described in detail below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are for illustrative purposes only and are not intended to limit the scope of this application. Furthermore, it should be noted that, for ease of description, only the parts relevant to this application are shown in the accompanying drawings, not the entire structure. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without inventive effort are within the scope of protection of this application.

[0024] The terms “comprising” and “having”, and any variations thereof, used in this application are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or apparatus that includes a series of steps or units is not limited to the steps or units listed, but may optionally include steps or units not listed, or may optionally include other steps or units inherent to such process, method, product, or apparatus.

[0025] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0026] Figure 1 This is a schematic structural diagram of a semiconductor device according to an embodiment of the present invention. Figure 2 This is a focused ion beam scanning electron microscope image of a semiconductor device according to an embodiment of the present invention. Figure 3 This is a schematic structural diagram of a substrate layer according to an embodiment of the present invention. Figure 4 This is a schematic flowchart illustrating a method for fabricating a semiconductor device according to an embodiment of the present invention. Figure 5 This is a schematic structural diagram of a trench structure according to an embodiment of the present invention. Figure 6 This is a focused ion beam scanning electron microscope image of a trench structure according to an embodiment of the present invention. Figure 7 This is a schematic structural diagram of silicon crystal layer deposition according to an embodiment of the present invention. Figure 8 This is a focused ion beam scanning electron microscope image of silicon crystal layer deposition according to an embodiment of the present invention.

[0027] like Figure 1 and Figure 2 As shown, the present invention provides a method for fabricating a high aspect ratio semiconductor device 100. The substrate layer 10 of the semiconductor device 100 includes a silicon substrate 11, an insulating layer 12, and a semiconductor structure layer 13 (see reference 10) stacked sequentially from bottom to top. Figure 3 Semiconductor structure layer 13 can be a deep silicon etched structure, a silicon optical waveguide structure, or a lithium niobate thin film structure.

[0028] like Figure 4 As shown, the method for fabricating the semiconductor device 100 includes: Step S100: Provide a substrate layer 10, and form at least one high aspect ratio trench structure 131 in the substrate layer 10 (refer to...) Figure 5 and Figure 6 The depth-to-width ratio of the trench structure 131 is greater than or equal to 5:1; Step S200: Deposit at least one silicon layer 20 within the trench structure 131 (refer to...) Figure 7 and Figure 8 The silicon layer 20 covers the bottom and sidewalls of the trench structure 131 in a conformal deposition manner, and pores 21 are formed between the silicon layers 20 at the bottom and sidewalls of the trench structure 131 (see reference). Figure 7 and Figure 8 ); Step S300: The trench structure 131 with the deposited silicon crystal layer 20 is subjected to thermal oxidation treatment, so that the silicon crystal layer 20 is completely oxidized to form a silicon oxide layer, so as to form a high aspect ratio filling structure 30 in the pores 21.

[0029] In this embodiment, the method for fabricating a high aspect ratio semiconductor device 100 includes a substrate layer 10 comprising a silicon substrate 11, an insulating layer 12, and a semiconductor structure layer 13 stacked sequentially from bottom to top. The semiconductor structure layer 13 forms at least one trench structure 131 with a high aspect ratio. First, at least one silicon crystal layer 20 is deposited in the trench structure 131, covering the bottom wall and sidewalls of the trench structure 131 in a conformal deposition manner. Pores 21 are formed between the silicon crystal layers 20. The silicon crystal layers 20 in the trench structure 131 are subjected to thermal oxidation treatment so that the silicon crystal layers 20 are completely oxidized to form a silicon oxide layer, that is, a filling structure 30 that can be used to fill the pores 21 is formed in the voids.

[0030] In this embodiment, by depositing a conformal silicon crystal layer 20 in the high aspect ratio trench structure 131 and utilizing the volume expansion effect during its thermal oxidation process, the pores 21 originally located inside the trench structure 131 are gradually filled by silicon oxide, thereby achieving a void-free or essentially void-free filling of the high aspect ratio trench structure 131. This significantly improves the filling integrity, the density of the filling layer, and the reliability of the device structure, and the process is simple and has good compatibility.

[0031] In this embodiment, a silicon crystal layer 20 is formed on the bottom and sidewalls of the trench structure 131 by conformal deposition, so that the silicon crystal layer 20 forms a pore structure 21 extending along the depth direction inside the trench structure 131, thereby providing growth space for the volume expansion of silicon oxide during the subsequent thermal oxidation process, and avoiding the internal void residue caused by the premature closure of the trench opening during the deposition process.

[0032] In this embodiment, during the thermal oxidation process, the silicon crystal layer 20 is transformed into a silicon oxide layer from the surface to the inside. Accompanied by the volume expansion effect of the oxidation reaction, the silicon oxide layer grows along the inside of the trench structure 131 towards the pores 21, thereby filling the pores 21 and forming a continuous and dense silicon oxide filling structure 30 inside the trench structure 131, which significantly reduces or eliminates the filling voids.

[0033] In a preferred embodiment, the thickness of the silicon crystal layer 20 is proportional to the width of the trench structure 131. The silicon crystal layer 20 is made of amorphous silicon, polycrystalline silicon, doped amorphous silicon, or doped polycrystalline silicon. The doping element in the doped polycrystalline silicon or doped amorphous silicon can be phosphorus or boron. The introduction of phosphorus or boron can adjust the carrier concentration and lattice defect distribution of the silicon crystal layer 20, which is beneficial to improve the structural uniformity of the silicon crystal layer 20 during deposition and subsequent heat treatment. At the same time, it can accelerate the oxidation reaction of silicon to silicon oxide and improve the density and growth consistency of the oxide layer.

[0034] In this embodiment, by making the thickness of the silicon layer 20 proportional to the width of the trench structure 131, the deposition thickness of the silicon layer 20 can be adaptively adjusted according to the trench structure 131 of different sizes. This ensures that the trench can be fully filled after thermal oxidation while ensuring the formation of the pore structure 21, thereby improving the consistency of filling of trench structures 131 of different sizes and the process stability.

[0035] In one embodiment, the silicon crystal layer 20 is made of polycrystalline silicon, and the preset volume ratio of polycrystalline silicon oxidized to form silicon oxide is 0.46, i.e., to obtain... A thick silicon oxide layer requires consumption A polycrystalline silicon layer. When the width of trench structure 131 is First, a silicon layer 20 of a predetermined thickness is deposited within the trench structure 131. The predetermined thickness refers to the thickness of the silicon layer 20 deposited on the sidewall surface and along the normal direction of the sidewall. The predetermined thickness is the product of a predetermined volume ratio and half the width of the trench structure 131, i.e., the predetermined thickness is... .

[0036] In this embodiment, amorphous silicon, polycrystalline silicon, or their doped forms are used as the silicon layer 20 material, which enables good conformal deposition and rapid and uniform transformation into a silicon oxide layer during thermal oxidation, thereby obtaining a dense, low-defect filled structure 30. Simultaneously, the introduction of doping facilitates the control of the deposition rate and oxidation behavior of the silicon layer 20, improving the flexibility of the process window.

[0037] In a further embodiment, the deposition process of the silicon layer 20 is any one of low-pressure chemical vapor deposition, rapid thermal chemical vapor deposition, and plasma-enhanced chemical vapor deposition, which enables the silicon layer 20 to achieve continuous and controllable deposition coverage on the bottom and sidewalls of the high aspect ratio trench structure 131. The appropriate deposition method can be flexibly selected according to different device structures and process thermal budgets, thereby effectively controlling the thickness uniformity, density, and morphological characteristics of the silicon layer 20, ensuring the stable performance of the volume expansion effect during subsequent thermal oxidation, and forming a dense, continuous, and void-free silicon oxide filling structure 30 inside the trench.

[0038] In a further embodiment, the deposition temperature of the silicon layer 20 is any value between 400°C and 620°C, that is, the deposition temperature of the silicon layer 20 can be 400°C, 450°C, 500°C, 550°C, 600°C or 620°C, or any other value between 400°C and 620°C. The pressure is any value between 100mTorr and 500mTorr, that is, the deposition pressure of the silicon layer 20 can be 100mTorr, 200mTorr, 300mTorr, 400mTorr or 500mTorr, or any other value between 100mTorr and 500mTorr. In this embodiment, by limiting the deposition temperature of the silicon layer 20 to the range of 400℃-620℃ and the deposition pressure to the range of 100mTorr-500mTorr, the deposition process can achieve stable and controllable growth of the silicon layer 20 under low thermal budget conditions. This is beneficial for forming a uniform, dense, and continuous conformal capping layer on the bottom and sidewalls of the high aspect ratio trench structure 131. At the same time, the above-mentioned temperature and pressure windows can effectively suppress excessive deposition at the top caused by excessively rapid surface reactions or gas phase reactions, thereby avoiding premature closure of the trench structure 131 entrance. This ensures that the trench structure 131 retains a pore structure 21 suitable for subsequent thermal oxidation volume expansion, thereby promoting the gradual expansion and full filling of silicon oxide inside the trench structure 131 during thermal oxidation. This achieves a void-free, high-quality oxide filling of the high aspect ratio structure, improving device structural consistency and process stability.

[0039] In a further embodiment, the precursor gas for the deposition process of the silicon layer 20 is at least one of dichlorosilane, trichlorosilane, silicon tetrachloride, phosphine, or disilane. This allows the deposition reaction mechanism and growth rate of the silicon layer 20 to be flexibly controlled according to the decomposition temperature, reactivity, and surface reaction characteristics of different precursors. This facilitates reaction-constrained deposition within the high aspect ratio trench structure 131, thereby improving the uniformity of the silicon layer 20 coverage on the bottom and sidewalls of the trench and reducing the risk of over-deposition at the opening of the trench structure 131. Simultaneously, different chlorosilane or silane precursors can effectively suppress particle formation and improve the film density and purity during deposition, providing a favorable foundation for the stable and uniform oxidation and volume expansion filling of the silicon layer 20 during subsequent thermal oxidation.

[0040] In a further embodiment, the oxidation temperature of the thermal oxidation process is any value within the range of 550℃ to 1350℃. That is, the oxidation temperature can be 550℃, 600℃, 700℃, 800℃, 900℃, 1000℃, 1100℃, 1200℃, 1300℃, or 1350℃, or any other value within the range of 550℃ to 1350℃. In this embodiment, by limiting the oxidation temperature of the thermal oxidation process to the range of 550℃ to 1350℃, the silicon crystal layer 20 can undergo a controlled and sufficient oxidation reaction under different thermal budget conditions. Lower oxidation temperatures are beneficial for slowing down the oxidation rate, reducing oxidation stress concentration, and suppressing the generation of interface defects, while higher oxidation temperatures are beneficial for increasing the oxidation rate and the density of the oxide layer, thereby enhancing the volume expansion effect during the conversion of the silicon crystal layer 20 to silicon oxide.

[0041] In this embodiment, by flexibly selecting the oxidation temperature within the wide temperature window, silicon oxide can grow gradually along the sidewalls and bottom inside the high aspect ratio trench structure 131 and extend into the pore 21 region, thereby effectively eliminating the pores 21 and completely filling the structure, while taking into account film quality, stress control and process compatibility.

[0042] In a further embodiment, the oxidation medium for thermal oxidation is any one of dry oxygen, wet oxygen, or water vapor, allowing for flexible control over the oxidation rate of the silicon crystal layer 20, the growth mode of the silicon oxide layer, and the film density according to the device structure characteristics and filling requirements. Dry oxygen oxidation is beneficial for forming a silicon oxide layer with high density and excellent interface quality, suitable for device structures with high requirements for optical loss and electrical reliability. Wet oxygen or water vapor oxidation can significantly increase the oxidation rate, enhance the volume expansion effect during the conversion of the silicon crystal layer 20 to silicon oxide, and accelerate the filling process of the pores 21 inside the high aspect ratio trench structure 131. By selecting the above-mentioned different oxidation media, gapless filling of the high aspect ratio structure can be achieved while ensuring the quality of the silicon oxide layer, improving filling efficiency and widening the process window, thereby improving the flexibility and stability of semiconductor device 100 manufacturing.

[0043] In a further embodiment, after the oxidation temperature and oxidation medium of the thermal oxidation process are determined, the oxidation time of the thermal oxidation process is determined according to the size of the pores 21, so that the oxidation reaction of the silicon crystal layer 20 can be precisely controlled in the time dimension. This ensures that the volume expansion generated by the silicon oxide layer during the growth process is just used to fill the pore 21 region. This not only avoids the problem of pore 21 residue and incomplete filling caused by insufficient oxidation time, but also prevents excessive volume expansion, stress accumulation or film cracking caused by excessive oxidation.

[0044] In a further embodiment, the thickness of a single deposition of the silicon layer 20 is any value between 5nm and 1000nm. That is, the deposition process of the silicon layer 20 can have a thickness of 5nm, 10nm, 50nm, 100nm, 200nm, 500nm, 700nm, 900nm, or 1000nm per deposition, or any other value between 5nm and 1000nm. In this embodiment, by limiting the thickness of a single deposition of the silicon layer 20 to the range of 5nm-1000nm, the growth process of the silicon layer 20 within the high aspect ratio trench structure 131 has good controllability and adaptability. A smaller single deposition thickness is beneficial to improving the conformal coverage of the silicon layer 20 at the bottom and sidewalls of the trench, reducing the risk of overgrowth of the trench structure 131 at the opening, thereby maintaining the connectivity of the pre-set pores 21 inside the trench structure 131. A larger single deposition thickness is beneficial to improving the overall deposition efficiency and reducing the number of process cycles. That is, by flexibly selecting the single deposition thickness within the above thickness range, a balance can be achieved between deposition uniformity and process efficiency, and suitable initial structural conditions can be provided for the volume expansion generated when the silicon layer 20 is converted to silicon oxide during the subsequent thermal oxidation process.

[0045] In a further embodiment, when the semiconductor structure layer 13 in the substrate layer 10 is a silicon optical waveguide structure, the step of depositing at least one silicon crystal layer 20 within the trench structure 131 further includes: The groove structure 131 is annealed.

[0046] In this embodiment, when the semiconductor structure layer 13 in the substrate layer 10 is a silicon optical waveguide structure, the trench structure 131 is annealed before depositing at least one silicon crystal layer 20 in the trench structure 131. This helps to release the internal stress introduced by the silicon optical waveguide during the etching and film formation process and repair the structural defects at the sidewalls and bottom walls, thereby reducing the stress concentration and interface defect density inside the waveguide structure.

[0047] In this embodiment, the annealing step described above can effectively improve the geometric stability and flatness of the trench structure 131, providing a more stable and uniform growth interface for the conformal deposition of the subsequent silicon crystal layer 20. This leads to the formation of a dense, low-stress silicon oxide filling layer with excellent interface quality during the subsequent thermal oxidation filling process, reducing light scattering and transmission loss, and improving the optical performance and long-term reliability of the silicon optical waveguide device.

[0048] The technical solution of this application will be further described below with reference to specific embodiments. Example 1

[0049] In the fabrication method of the high aspect ratio semiconductor device 100, a substrate layer 10 is provided, comprising a silicon substrate 11, an insulating layer 12, and a semiconductor structure layer 13 stacked sequentially from bottom to top. The semiconductor structure layer 13 forms at least one trench structure 131 with a high aspect ratio. First, at least one silicon crystal layer 20 is deposited in the trench structure 131, covering the bottom wall and sidewalls of the trench structure 131 in a conformal deposition manner. The deposition process of the silicon crystal layer 20 is low-pressure chemical vapor deposition at a deposition temperature of 500°C. The silicon crystal layer 20 is made of polycrystalline silicon and pores 21 are formed between the silicon crystal layers 20. The silicon crystal layer 20 in the trench structure 131 is subjected to thermal oxidation treatment so that the silicon crystal layer 20 is completely oxidized to form a silicon oxide layer. The oxidation temperature of the thermal oxidation treatment is 950°C and the oxidation medium is wet oxygen, that is, a filling structure 30 that can be used to fill the pores 21 is formed in the pores, and the high aspect ratio semiconductor device 100 with the filling structure 30 is obtained.

[0050] Comparative Example 1 The only difference between Comparative Example 1 and Example 1 is that the pores 21 are filled by a deposition process, while the silicon crystal layer 20 is not thermally oxidized.

[0051] Figure 9 This is a focused ion beam scanning electron microscope image of the semiconductor device according to Embodiment 1 of the present invention. Figure 10 This is a focused ion beam scanning electron microscope image of the semiconductor device according to Comparative Example 1 of the present invention.

[0052] The high aspect ratio semiconductor devices 100 prepared in Example 1 and Comparative Example 1 were characterized to obtain the following results: Figure 9 and Figure 10 The image shown is a focused ion beam scanning electron microscope image.

[0053] like Figure 9 As shown, in the semiconductor device 100 structure prepared in Example 1, the trench structure 131 is densely filled with structures 30, and there are no pores 21. However, the semiconductor device 100 structure prepared in Comparative Example 1 exhibits obvious large pore structures 21 (see reference). Figure 10 The results show that in Example 1, a semiconductor device 100 with a densely filled structure 30 can be prepared by using a silicon crystal layer 20 deposition process combined with a thermal oxidation process.

[0054] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0055] The embodiments described above are merely illustrative of several implementations of the present invention, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these all fall within the protection scope of the present invention. Therefore, the protection scope of this invention patent should be determined by the appended claims.

Claims

1. A method for fabricating a high aspect ratio semiconductor device, characterized in that, include: A substrate is provided in which at least one high aspect ratio trench structure is formed, wherein the aspect ratio of the trench structure is greater than or equal to 5:1; At least one silicon layer is deposited within the trench structure, the silicon layer covering the bottom and sidewalls of the trench structure in a conformal deposition manner, and pores are formed between the silicon layer at the bottom and sidewalls of the trench structure; The trench structure on which the silicon crystal layer is deposited is subjected to thermal oxidation treatment, so that the silicon crystal layer is completely oxidized to form a silicon oxide layer, thereby forming a high aspect ratio filling structure in the pores.

2. The method for fabricating a high aspect ratio semiconductor device according to claim 1, characterized in that, The deposition process of the silicon crystal layer is any one of low-pressure chemical vapor deposition, rapid thermochemical vapor deposition, and plasma-enhanced chemical vapor deposition. Preferably, the thickness of the silicon crystal layer is proportional to the width of the trench structure, and the material of the silicon crystal layer is amorphous silicon, polycrystalline silicon, doped amorphous silicon, or doped polycrystalline silicon.

3. The method for fabricating a high aspect ratio semiconductor device according to claim 2, characterized in that, The deposition temperature of the silicon crystal layer is any value between 400℃ and 620℃, and the pressure is any value between 100mTorr and 500mTorr.

4. The method for fabricating a high aspect ratio semiconductor device according to claim 2, characterized in that, The precursor gas for the deposition process of the silicon crystal layer is at least one of dichlorosilane, trichlorosilane, silicon tetrachloride, or disilane.

5. The method for fabricating a high aspect ratio semiconductor device according to claim 1, characterized in that, The oxidation temperature of the thermal oxidation treatment is any value between 550℃ and 1350℃.

6. The method for fabricating a high aspect ratio semiconductor device according to claim 5, characterized in that, The oxidizing medium for the thermal oxidation treatment is any one of dry oxygen, wet oxygen, or water vapor.

7. The method for fabricating a high aspect ratio semiconductor device according to any one of claims 1-6, characterized in that, The oxidation time of the thermal oxidation treatment is determined based on the pore size.

8. The method for fabricating a high aspect ratio semiconductor device according to claim 1, characterized in that, The substrate layer includes a silicon substrate, an insulating layer, and a semiconductor structure layer stacked sequentially from bottom to top. The semiconductor structure layer is a deep silicon etched structure, a silicon waveguide structure, or a lithium niobate thin film structure.

9. The method for fabricating a high aspect ratio semiconductor device according to claim 1, characterized in that, The thickness of the silicon crystal layer in a single deposition is any value between 5nm and 1000nm.

10. The method for fabricating a high aspect ratio semiconductor device according to claim 8, characterized in that, When the semiconductor structure layer of the substrate is the silicon optical waveguide structure, the step prior to the step of depositing at least one silicon crystal layer in the trench structure further includes: The groove structure is then subjected to annealing.

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