Method for improving in-plane uniformity of deep reactive ion etching and semiconductor apparatus

Abstract

The application discloses a control method for improving in-plane uniformity of deep reactive ion etching and a semiconductor device. The method comprises the following steps: performing first etching on a first wafer for N cycles to obtain a first depth difference between a center region and an edge region; performing second etching on a second wafer for N cycles and inserting a compensation cycle at a first average interval to obtain a second depth difference between the center region and the edge region; obtaining a single-cycle compensation gain generated by each compensation cycle according to the first depth difference and the second depth difference; obtaining a required number of compensation cycles according to the first depth difference and the single-cycle compensation gain; obtaining a second average interval between adjacent two compensation cycles according to the number of cycles N and the required number of compensation cycles; and inserting a compensation cycle at the second average interval when performing third etching on a third wafer for M cycles. The application can effectively reduce the etching depth difference and improve the control precision.

Description

Technical Field

[0001] This application relates to the field of semiconductor processing technology, and in particular to a control method and semiconductor equipment for improving the in-plane uniformity of deep reactive ion etching. Background Technology

[0002] With the rapid development of microelectromechanical systems (MEMS), 3D packaging, and other high aspect ratio silicon microstructure devices, the requirements for uniform depth of etching across different areas of the entire wafer in deep silicon etching processes are constantly increasing. Especially in the manufacturing process of microelectromechanical system cavities, through-silicon vias, deep trench structures, and other high aspect ratio silicon structures, it is often necessary to achieve silicon etching processing with a large area, a large depth, and high uniformity on the same wafer.

[0003] In existing deep silicon etching processes such as deep reactive ion etching (DRIE), etching uniformity is usually affected by factors such as plasma density distribution, ion flux distribution, reactive gas transport, cavity evacuation direction, wafer temperature distribution, and edge electric field effect. These factors can easily cause different etching rates between the central region and the edge region of the wafer, resulting in differences in etching depth between the central region and the edge region, thus affecting the uniformity of in-plane etching depth.

[0004] Traditional methods primarily improve in-plane uniformity of etching depth by adjusting parameters such as pressure, gas flow rate, source power, bias power, etching time, or passivation time. However, these parameters typically affect the entire wafer and are difficult to differentiate between the center and edge regions. Simply reducing the overall etching rate or increasing the overall passivation intensity may improve over-etching in some areas, but it can also easily lead to under-etching in other areas, bottom residue, trench termination, sidewall morphology degradation, or decreased process efficiency. Therefore, a new optimization method is needed that can improve the etching uniformity of the entire wafer while meeting high-performance requirements. Summary of the Invention

[0005] The purpose of this application is to overcome the above-mentioned problems in the prior art and to provide a control method and semiconductor device for improving the uniformity of deep reactive ion etching.

[0006] To achieve the above objectives, the technical solution of this application is as follows: According to a first aspect of this application, embodiments of this application provide a method for controlling the in-plane uniformity of deep reactive ion etching, comprising: After N cycles of first etching on the first wafer, the first depth difference between the etched structure in the central region and the etched structure in the edge region is obtained. Each cycle includes a passivation layer deposition step, a bottom passivation layer removal step, and an etching step in sequence. After performing N cycles of second etching on the second wafer, the second depth difference between the etched structure in the central region and the etched structure in the edge region is obtained. The difference between the second etching and the first etching is that m cycles out of N cycles are selected as the estimated m compensation cycles according to the first average interval. When performing the compensation cycle and proceeding to the bottom passivation layer removal step, the radial source power allocation ratio of the slower etching rate in the central region and the edge region is increased, and the bias power is decreased to reduce the etching depth difference between the central region and the edge region. Based on the difference between the first depth difference and the second depth difference, the single-cycle compensation gain of each compensation cycle in reducing the etching depth difference is calculated. The required number of compensation cycles (n) is calculated based on the ratio of the first depth difference to the single-cycle compensation gain. Based on N cycles and n compensation cycles, the required second average interval between two adjacent compensation cycles is calculated. The third wafer is etched for M cycles. The difference between the third and second etches is that the first average interval is replaced by the second average interval, and a compensation cycle is inserted every second average interval during the execution of M cycles.

[0007] In some embodiments, M and N may be the same or different, and m and n are greater than 1.

[0008] In some embodiments, when performing cycles other than the compensation cycle and proceeding to the bottom passivation layer removal step, a first radial source power distribution ratio is established between the central region and the edge region, and a first bias power is used. When the etching rate of the central region is slower than that of the edge region, during the execution of the compensation cycle and the bottom passivation layer removal step, a second radial source power distribution ratio greater than the first radial source power distribution ratio is established between the central region and the edge region, and a second bias power less than the first bias power is used. This ensures that when the bottom passivation layer of the etched structure in the central region is completely removed, the bottom passivation layer of the etched structure in the edge region still remains. This allows the effective etching time for etching the wafer material below the bottom of the etched structure in the central region to be longer than that for etching the edge region during the etching step in the corresponding cycle. The effective etching time for etching the wafer material below the bottom of the structure is determined by the following: Conversely, when the etching rate of the central region is faster than that of the edge region, during the compensation cycle and up to the bottom passivation layer removal step, the third radial source power allocation ratio between the central region and the edge region is adjusted to be less than the first radial source power allocation ratio, and a third bias power less than the first bias power is used. This ensures that when the bottom passivation layer of the etched structure in the edge region is completely removed, the bottom passivation layer of the etched structure in the central region still remains. This ensures that during the etching step in the corresponding cycle, the effective etching time for etching the wafer material below the bottom of the etched structure in the edge region is greater than the effective etching time for etching the wafer material below the bottom of the etched structure in the central region, thereby compensating for the etching rate difference between the central region and the edge region.

[0009] In some embodiments, the first wafer, the second wafer, and the third wafer are the same wafer. When obtaining the first depth difference and the second depth difference, multi-point acquisition of depth data of the etched structure in the central region is performed on the first radial ring of the first wafer and the second wafer, and multi-point acquisition of depth data of the etched structure in the edge region is performed on the second radial ring of the first wafer and the second wafer. The average value of the depth data is used as the basis for calculating the first depth difference and the second depth difference.

[0010] In some embodiments, the first radial ring is located at a radius of 0.45 to 0.65 of the first wafer and the second wafer, and the second radial ring is located at a radius of 0.8 to 0.95 of the first wafer and the second wafer.

[0011] In some embodiments, the target depth difference between the etched structure in the allowed central region and the etched structure in the edge region is Δ. t The calculation of the n compensation cycle numbers satisfies the following formula: n = ceil[(Δ0 - Δ t Formula 1 Where ceil[ ] is the floor function, Δ0 is the first depth difference, and G is the single-cycle compensation gain. The calculation of the single-cycle compensation gain G satisfies the following formula: G = (Δ0 - Δ m Formula 2 Where, Δ m This is the second depth difference.

[0012] In some embodiments, the calculation of the second average interval satisfies the following formula three: q = (N - n) / n (Formula 3) Where q is the second average interval, rounded to the nearest integer.

[0013] In some embodiments, the method further includes verifying the applicability of the calculation results for the second average interval, specifically including: Based on the calculated second average interval q, three frequencies are set as qp, q, and q+p, where p = 1 to 3; The fourth wafer is etched for N cycles. The difference between the fourth and second etches is that the first average interval is replaced by the second average interval with qp, q, and q+p respectively for the fourth etch. During the N cycles, a compensation cycle is inserted every second average interval corresponding to the frequency. The frequency used in the fourth etching with the smallest in-plane uniformity value is selected as the second average interval actually used when performing the third etching on the third wafer. The fourth wafer is the same as the third wafer.

[0014] In some embodiments, the second radial source power allocation ratio is 55:45 to 70:30.

[0015] In some embodiments, the third radial source power allocation ratio is 45:55 to 30:70.

[0016] In some embodiments, the second bias power is 0W to 10W.

[0017] In some embodiments, the third bias power is 0W to 10W.

[0018] According to a second aspect of this application, embodiments of this application also provide a semiconductor device for performing a control method for improving in-plane uniformity of deep reactive ion etching as provided in any of the embodiments of the first aspect above.

[0019] The embodiments of this application may have, or at least have, the following advantages: (1) By inserting a compensation cycle at certain intervals (second average interval) in the normal cycle (relative to the compensation cycle) of deep reactive ion etching of the wafer, and by increasing the radial source power distribution ratio of the slower etching rate in the central region and the edge region and decreasing the bias power when performing the compensation cycle and proceeding to the bottom passivation layer removal step, the removal rate of the bottom passivation layer of the etched structure in the faster etching rate region can be slowed down, so that when the bottom passivation layer of the etched structure in the slower etching rate region is completely removed, the bottom passivation layer of the etched structure in the faster etching rate region still remains. This allows for a delay in the start time of etching the wafer material below the bottom of the etched structure in the faster etch rate region during the corresponding etching step in the cycle (i.e., the effective etching time for etching the wafer material below the bottom of the etched structure in the slower etch rate region is greater than the effective etching time for etching the wafer material below the bottom of the etched structure in the faster etch rate region), thereby reducing the etching increment per cycle and compensating for the etching rate difference between the central and edge regions, thus reducing the etching depth difference between the central and edge regions.

[0020] (2) By employing an experimental method, the etching depth difference data (first depth difference) collected after etching according to the normal cycle (first etching) is compared with the etching depth difference data (second depth difference) collected after etching according to the compensation cycle with an estimated number inserted in the normal cycle (second etching). The single-cycle compensation gain of each compensation cycle in reducing the etching depth difference is calculated, and the required second average interval is then calculated and used for etching during mass production (third etching). This improves the control accuracy of the method for improving the uniformity of the deep reactive ion etching surface and can effectively reduce the etching depth difference between the central region and the edge region. Furthermore, by verifying the applicability of the calculation results of the second average interval, the control level of the method is further improved.

[0021] Other advantages of this application will be described in the following detailed description. Attached Figure Description

[0022] Figure 1 This is a flowchart of a method for controlling the uniformity of deep reactive ion etching (DRIE) planes, provided as a preferred embodiment of this application.

[0023] Figure 2 This is a schematic diagram illustrating the difference in etching depth between the central region and the edge region after a first etching of a first wafer, provided as a preferred embodiment of this application.

[0024] Figure 3 This is a schematic diagram illustrating the difference in etching depth between the central region and the edge region after a second etching of a second wafer, provided as a preferred embodiment of this application.

[0025] Figure 4 This is a schematic diagram showing the deposition of a passivation layer on the inner wall of an etched structure during a passivation layer deposition step in a compensation cycle, as provided in a preferred embodiment of this application.

[0026] Figure 5 This is a schematic diagram showing that, in a preferred embodiment of this application, the bottom passivation layer of the etched structure in the central region is completely removed during the bottom passivation layer removal step of the compensation cycle, while the bottom passivation layer of the etched structure in the edge region still remains.

[0027] Figure 6 This is a schematic diagram illustrating the start-up time delay for etching the wafer material below the bottom of the etching structure in an edge region with a faster etching rate during an etching step of a compensation cycle, as provided in a preferred embodiment of this application.

[0028] Figure 7 This is a schematic diagram illustrating the compensation effect on the radial etching depth difference between the central region and the edge region after performing a compensation cycle, according to a preferred embodiment of this application.

[0029] Figure 8 This is a schematic diagram of a central region, intermediate region and outer ring region defined on a wafer for depth data acquisition, provided as a preferred embodiment of the present application.

[0030] Figure 9 This is a schematic diagram illustrating a preferred embodiment of the present application, in which a compensation cycle is performed once every second average interval to reduce the difference in etching depth between the central region and the edge region after the third etching of the third wafer.

[0031] Figure 10 This is a schematic diagram comparing the etching depth difference between the central region and the edge region after verification of corresponding etching on a fourth wafer at three different frequencies and a second average interval, as provided in a preferred embodiment of this application.

[0032] Figure 11 This is a schematic diagram showing the comparison of etching depth compensation effects at different radial positions on a wafer after performing a second and fourth etching, according to a preferred embodiment of this application.

[0033] In the figure: 10. First wafer; 11. First etched structure; 12. Second etched structure; 20. Second wafer; 21. Third etched structure; 211. Third intermediate etched structure; 22. Fourth etched structure; 221. Fourth intermediate etched structure; 30. Third wafer; 31. Fifth etched structure; 32. Sixth etched structure; 40. Fourth wafer; 41. Seventh etched structure; 42. Eighth etched structure; 50. Passivation layer. Detailed Implementation

[0034] This application addresses the problem in existing deep reactive ion etching (DRIE) processes where different etching rates occur between the central and edge regions of a wafer, leading to differences in etching depth between the central and edge regions and thus affecting the uniformity of in-plane etching depth. It provides a method for improving the control of in-plane uniformity in deep reactive ion etching, comprising: After N cycles of first etching on the first wafer, the first depth difference between the etched structure in the central region and the etched structure in the edge region is obtained. Each cycle includes a passivation layer deposition step, a bottom passivation layer removal step, and an etching step in sequence. After performing N cycles of second etching on the second wafer, the second depth difference between the etched structure in the central region and the etched structure in the edge region is obtained. The difference between the second etching and the first etching is that m cycles out of N cycles are selected as the estimated m compensation cycles according to the first average interval. When performing the compensation cycle and proceeding to the bottom passivation layer removal step, the radial source power allocation ratio of the slower etching rate in the central region and the edge region is increased, and the bias power is decreased to reduce the etching depth difference between the central region and the edge region. Based on the difference between the first depth difference and the second depth difference, the single-cycle compensation gain of each compensation cycle in reducing the etching depth difference is calculated. The required number of compensation cycles (n) is calculated based on the ratio of the first depth difference to the single-cycle compensation gain. Based on N cycles and n compensation cycles, the required second average interval between two adjacent compensation cycles is calculated. The third wafer is etched for M cycles. The difference between the third and second etches is that the first average interval is replaced by the second average interval, and a compensation cycle is inserted every second average interval during the execution of M cycles.

[0035] This application compensates for the difference in etching rate between the central and edge regions by inserting compensation cycles at regular intervals during the normal cycle of deep reactive ion etching on wafers. Furthermore, through experimental comparison and calculation, the average insertion interval of the compensation cycles actually required for mass production was obtained, improving control accuracy and effectively reducing the difference in etching depth between the central and edge regions.

[0036] This application also provides a semiconductor device for performing the above-described control method for improving in-plane uniformity of deep reactive ion etching.

[0037] The specific embodiments of this application will now be described in detail with reference to the accompanying drawings.

[0038] refer to Figure 1 This application provides a method for improving the in-plane uniformity of deep reactive ion etching, which may include the following steps in sequence: Step S11: Perform N cycles of first etching on the first wafer to obtain the first depth difference between the central region and the edge region.

[0039] In some embodiments, multiple identical wafers are selected, including a first wafer, a second wafer, a third wafer, etc., and a central region and an edge region surrounding the central region are defined on the surface of the wafers. Multiple cycles of etching are performed on the surface of the wafers using a deep reactive ion etching process to form multiple etched structures on the surface of the wafers, including etched structures located in the central region and etched structures located in the edge regions.

[0040] Each cycle of the deep reactive ion etching (DRIE) process sequentially includes a passivation layer deposition step, a bottom passivation layer removal step, and an etching step, forming a periodic cycle through multiple cycles. The passivation layer deposition step deposits a passivation layer (primarily fluorocarbon polymer material) on the inner wall of the etched structure. The bottom passivation layer removal step etches away the passivation layer located at the bottom of the inner wall of the etched structure, allowing for further etching of the exposed wafer material at the bottom of the inner wall, thus increasing the etching depth of the etched structure. By cyclically executing the passivation layer deposition, bottom passivation layer removal, and etching steps, multiple etched structures with high aspect ratios can ultimately be formed on the central and edge regions of the wafer surface.

[0041] In some embodiments, the etched structure may include deep trenches, deep holes, or through holes.

[0042] In some embodiments, the wafer material may include silicon, etc., but is not limited thereto.

[0043] In some embodiments, the passivation layer deposition step may use a fluorocarbon gas (e.g., C4F8) to deposit the passivation layer. The etching step may use a fluorine-containing gas (e.g., SF6) to etch the wafer material.

[0044] refer to Figure 2 The schematic diagram shows a local structure on the right radius of the first wafer 10. Figure 2A hollow arrow pointing to the left indicates the center direction of the first wafer 10. A central region A and an edge region B surrounding the central region A are defined radially to the right of the first wafer 10. In some embodiments, the first wafer 10 can be used as a reference wafer (reference piece), and a first etching process (N cycles, normal cycle) is performed on the surface of the first wafer 10 using existing conventional deep reactive ion etching technology. This etching process forms multiple etched structures on the surface of the first wafer 10, including a first etched structure 11 located in the central region A and a second etched structure 12 located in the edge region B.

[0045] N can be multiple. For example, N can be more than 2, or more than 5, or more than 10, or more than 50, or more than 100, or more than 300, or more than 500, etc.

[0046] When performing the first etching of the first wafer 10 using the existing deep reactive ion etching process, factors such as plasma density distribution, ion flux distribution, reactive gas transport, cavity evacuation direction, wafer temperature distribution, and edge electric field effect cause different etching rates between the central region A and the edge region B on the first wafer 10. This results in a difference between the etching depth of the first etched structure 11 in the central region A and the etching depth of the second etched structure 12 in the edge region B, thus affecting the uniformity of the in-plane etching depth. Therefore, the control method for improving the in-plane uniformity of deep reactive ion etching provided in the embodiments of this application can be used to improve this.

[0047] After the first etching is performed, the etching depth of the first etched structure 11 and the etching depth of the second etched structure 12 are measured (when measuring the etching depth of multiple first etched structures 11 and the etching depth of multiple second etched structures 12, the average value is taken), and the difference is calculated by subtraction. The etching depth difference, which reflects the difference in etching rate between the central region A and the edge region B, is obtained, i.e., the first depth difference h1, which is used as the reference depth difference.

[0048] When calculating the first depth difference h1, the method is to subtract the etching depth of the larger etching depth of the first etching structure 11 and the etching depth of the smaller etching depth to ensure that the calculated first depth difference h1 is a positive value.

[0049] It should be noted that when etching a silicon wafer using deep reactive ion etching (DRIE), the etching rate of the edge region B is typically greater than that of the central region A, resulting in a greater etching depth of the second etched structure 12 than that of the first etched structure 11. In this case, calculating the first depth difference h1 requires subtracting the etching depth of the first etched structure 11 from the etching depth of the second etched structure 12. The embodiments of this application will be described in detail below using this as an example.

[0050] refer to Figure 8 In some embodiments, to facilitate the acquisition of etching depth data and ensure the representativeness of the acquired etching depth data, a central region I, an intermediate region II, and an outer region III can be defined concentrically around the surface of the first wafer 10 in a radial direction from the center. Multiple depth data are acquired at various points in the central region I, intermediate region II, and outer region III (generally at least four evenly spaced measurement points; for example, four to five measurement points can be evenly selected in the central region I, four to eight in the intermediate region II, and at least eight in the outer region III). The average value of the etching depth data of the multiple first etching structures 11 and the average value of the etching depth data of the multiple second etching structures 12 are used as the basis for calculating the first depth difference h1 (and the maximum, minimum, and standard deviation can be recorded). The central region I and intermediate region II are located in the central region A, and the outer region III is located in the edge region B. The etching depth data acquired in the central region I can be used to monitor whether a new deviation occurs at the wafer center during the implementation of the method of this application. The etching depth data collected in the intermediate zone II can serve as the primary reference for implementing compensation cycles and making process adjustments. The etching depth data collected in the outer zone III can be used to monitor the compensation effect of reducing etching depth differences.

[0051] In some embodiments, when obtaining the first depth difference h1, multi-point acquisition of depth data of the etching structure (first etching structure 11) for the central region A is performed on the first radial ring of the defined first wafer 10, and multi-point acquisition of depth data of the etching structure (second etching structure 12) for the edge region B is performed on the second radial ring of the defined first wafer 10, and the average value of the depth data is used as the basis for calculating the first depth difference h1.

[0052] In some embodiments, the first radial ring is located in the intermediate region II, and its radius can vary within the inner and outer boundaries of the intermediate region II. The second radial ring is located in the outer ring region III, and its radius can vary within the inner and outer boundaries of the outer ring region III.

[0053] In some embodiments, the first radial ring is located at a radius of 0.45 to 0.65 of the first wafer 10 (where the radius of the first radial ring is r1, the radius of the first wafer 10 is R, and r1 / R = 0.45 to 0.65), and the second radial ring is located at a radius of 0.8 to 0.95 of the first wafer 10 (where the radius of the second radial ring is r2, the radius of the first wafer 10 is R, and r2 / R = 0.8 to 0.95). That is, the radius of the first radial ring can vary between 0.45 and 0.65 of the radius of the first wafer 10, and the radius of the second radial ring can vary between 0.8 and 0.95 of the radius of the first wafer 10.

[0054] In some embodiments, the maximum value of the radius of the central region I can be selected to be within 0.2 of the radius of the first wafer 10 (assuming the radius of the central region I is r3 and the radius of the first wafer 10 is R, r3 / R≤0.2).

[0055] Step S12: Perform N cycles of second etching on the second wafer, and insert compensation cycles at the first average interval to reduce the etching depth difference between the central region and the edge region, and obtain the second depth difference between the central region and the edge region.

[0056] refer to Figure 3 In some embodiments, the second wafer 20 may be used as a compensation calibration wafer (compensation calibration wafer), and a modified deep reactive ion etching process, which is formed by adjusting the conventional deep reactive ion etching process used in the first etching, is used to perform a second etching of N cycles on the surface of the second wafer 20, thereby etching a plurality of etched structures on the surface of the second wafer 20, including a third etched structure 21 located in the central region A and a fourth etched structure 22 located in the edge region B.

[0057] In some embodiments, the difference between the second etching and the first etching is that, when performing the improved deep reactive ion etching process, the total number of N cycles remains constant, and m cycles (m < N) from the N cycles are selected according to a first average interval as the estimated m compensation cycles to be executed (i.e., in the total number of N cycles, compensation cycles are inserted and executed according to the first average interval, and the compensation cycles also sequentially include the passivation layer deposition step, the bottom passivation layer removal step, and the etching step. In other words, the m compensation cycles are first estimated, and then the first average interval is calculated based on the number of N cycles). When the compensation cycle is executed and the bottom passivation layer removal step is reached, relative to the compensation cycle... In addition to the other cycles (Nm cycles in the second etching and N cycles in the first etching), the radial source power allocation ratio of the slower etching rate in the central region A and the edge region B is increased (i.e., based on the first etching result, when the etching rate of the first etched structure 11 is slower than the etching rate of the second etched structure 12, the radial source power allocation ratio of the central region A relative to the edge region B is increased), and the bias power is reduced to reduce the etching depth difference between the central region A and the edge region B (i.e., based on the first depth difference h1 of the first wafer 10, process adjustments are implemented on the second wafer 20 for the third and fourth etched structures that are being formed).

[0058] If the other cycles besides the compensation cycle (Nm cycles in the second etching and N cycles in the first etching) are referred to as normal cycles, then except for the adjustment of the radial source power allocation ratio and bias power relative to the normal cycle when performing the bottom passivation layer removal step, the compensation cycle is consistent with the normal cycle in other aspects.

[0059] Using the improved deep reactive ion etching process described above, the surface of the second wafer 20 is etched for N cycles to form a third etched structure 21 located in the central region A and a fourth etched structure 22 located in the edge region B. Then, the same method described above for obtaining the first depth difference h1 can be used (see reference). Figure 8 The second depth difference h2 between the third etched structure 21 in the central region A and the fourth etched structure 22 in the edge region B after the second etching is calculated. The second depth difference h2 is calculated by subtracting the smaller etching depth from the larger etching depth of the third etched structure 21 and the fourth etched structure 22. (Generally, if the first depth difference h1 is calculated by subtracting the etching depth of the central region A from the etching depth of the edge region B, then the second depth difference h2 is also calculated by subtracting the etching depth of the central region A from the etching depth of the edge region B, and vice versa.)

[0060] After performing a second etching on the second wafer 20 using the aforementioned improved deep reactive ion etching process, and by inserting compensation cycles at the first average interval within a total of N cycles, the etching depth difference between the central region A and the edge region B is reduced, making the second depth difference h2 less than the first depth difference h1 (h2 < h1). Figure 2 and Figure 3 As shown.

[0061] In some embodiments, when performing other cycles besides the compensation cycle (Nm cycles in the second etching and N cycles in the first etching) and reaching the bottom passivation layer removal step of the corresponding cycle, a first radial source power allocation ratio is established between the central region A and the edge region B, and a first bias power is used. When the etching rate of the central region A is slower than the etching rate of the edge region B, when performing the compensation cycle and reaching the bottom passivation layer removal step, a second radial source power allocation ratio greater than the first radial source power allocation ratio is established between the central region A and the edge region B, and a second bias power less than the first bias power is used. This ensures that when the bottom passivation layer of the etched structure of the central region A is completely removed, the bottom passivation layer of the etched structure of the edge region B still remains. This ensures that when performing the etching step in the corresponding cycle, the effective etching time for etching the wafer material below the bottom of the etched structure of the central region A is greater than the effective etching time for etching the wafer material below the bottom of the etched structure of the edge region B. Conversely, when the etching rate of the central region A is faster than that of the edge region B, during the compensation cycle and up to the bottom passivation layer removal step, the central region A and the edge region B are adjusted to have a third radial source power allocation ratio that is less than the first radial source power allocation ratio, and a third bias power that is less than the first bias power is used. This ensures that when the bottom passivation layer of the etched structure in the edge region B is completely removed, the bottom passivation layer of the etched structure in the central region A still remains. This allows the effective etching time for etching the wafer material below the bottom of the etched structure in the edge region B to be greater than the effective etching time for etching the wafer material below the bottom of the etched structure in the central region A during the corresponding etching step, thereby compensating for the etching rate difference between the central region A and the edge region B.

[0062] refer to Figures 4-7 Taking the example that the etching rate of the central region A is slower than that of the edge region B, after performing the first etching on the first wafer 10 and obtaining the first depth difference h1, it can be seen that the etching rate of the first etched structure 11 is slower than that of the second etched structure 12, that is, the etching rate of the central region A is slower than that of the edge region B. Figure 2As shown. Thus, during the second etching of the second wafer 20, if a normal cycle other than the compensation cycle (i.e., the process used during the first etching) is used at the start of etching, then after several etching cycles (corresponding to the first average interval), a third intermediate etching structure 211 (i.e., the third etching structure in formation) will be formed in the central region A, and a fourth intermediate etching structure 221 (i.e., the fourth etching structure in formation) will be formed in the edge region B. Similarly, because the etching rate in the central region A is slower than that in the edge region B, the etching depth of the third intermediate etching structure 211 will be less than the etching depth of the fourth intermediate etching structure 221. Figure 4 As shown.

[0063] To eliminate or reduce the etching depth difference between the third intermediate etch structure 211 and the fourth intermediate etch structure 221, a compensation cycle can be inserted after several normal cycles corresponding to the first average interval. When performing the compensation cycle, firstly, a passivation layer deposition step is performed to deposit a passivation layer 50 on the inner walls of the third intermediate etch structure 211 and the inner walls of the fourth intermediate etch structure 221.

[0064] Then, a bottom passivation layer removal step is performed to etch and remove the passivation layer 50 located at the bottom of the inner wall of the third intermediate etched structure 211 and the bottom of the inner wall of the fourth intermediate etched structure 221. During the bottom passivation layer removal step, considering that the etching rate of the central region A is slower than that of the edge region B, an improved method is used: increasing the original radial source power allocation ratio of the central region A relative to the edge region B, and reducing the bias power relative to the normal cycle. This reduction in bias power weakens the ion bombardment intensity at the bottom of the fourth intermediate etched structure 221, thus slowing down the removal rate of the passivation layer 50 at the bottom of the fourth intermediate etched structure 221, where the etching rate is faster. Simultaneously, the relatively increased radial source power allocation in the central region A ensures sufficient removal of the passivation layer 50 at the bottom of the third intermediate etched structure 211, maintaining a strong depassivation capability in the central region. Thus, during the compensation cycle, when the passivation layer 50 at the bottom of the third intermediate etched structure 211 is completely removed, a certain amount of the passivation layer 50 at the bottom of the fourth intermediate etched structure 221 remains, such as... Figure 5As shown. Therefore, when performing the etching step in this cycle, the start time for etching the wafer material below the bottom of the fourth intermediate etching structure 221 can be delayed (because the remaining passivation layer 50 at the bottom needs to be removed first before etching the wafer material exposed at the bottom after removing the passivation layer 50), and etching of the wafer material below the bottom of the third intermediate etching structure 211 can be started immediately. Therefore, this delay time can be used to form an etching segment of a certain depth below the bottom of the third intermediate etching structure 211 relative to the fourth intermediate etching structure 221, such as... Figure 6 As shown.

[0065] In this way, the etching increment of the fourth intermediate etching structure 221 during a single compensation cycle can be reduced, and when the etching step is completed, the bottom depth of the third intermediate etching structure 211 and the bottom depth of the fourth intermediate etching structure 221 become close, such as... Figure 7 As shown, during the etching process, the difference in etching rate between the central region A and the edge region B is compensated. Therefore, by inserting a certain number of compensation cycles, the difference in etching depth between the central region A and the edge region B can be reduced in the end.

[0066] Step S13: Based on the difference between the first depth difference and the second depth difference, calculate the single-cycle compensation gain of each compensation cycle for reducing the etching depth difference.

[0067] In some embodiments, by subtracting the first depth difference h1 from the second depth difference h2, the single-cycle compensation gain (i.e., the reduction in etching depth per unit) of each of the estimated m compensation cycles for reducing the etching depth difference between the central region A and the edge region B can be obtained.

[0068] In some embodiments, let the first depth difference h1 be Δ0 and the second depth difference h2 be Δ m If the estimated number of compensation cycles is m and the single-cycle compensation gain is G, then the calculation of the single-cycle compensation gain G can satisfy the following formula: G = (Δ0 - Δ m Formula 2 When the calculated G > 0, it indicates that the compensation direction is correct. Conversely, if G ≤ 0, it indicates that the compensation direction is incorrect, and the radial source power allocation ratio and the magnitude of the bias power in the compensation cycle should be readjusted.

[0069] Step S14: Calculate the required number of compensation cycles based on the ratio of the first depth difference to the single-cycle compensation gain.

[0070] In some embodiments, by dividing the first depth difference h1 by the single-cycle compensation gain obtained in the previous step, the actual number of compensation cycles required during the second etching can be obtained, which is used to correct the estimated m compensation cycles.

[0071] In some embodiments, the target depth difference between the etched structure of the allowed central region A and the etched structure of the edge region B is Δ. t If the actual number of compensation cycles required during the second etching is n, then the calculation of the required number of n compensation cycles can satisfy the following formula: n = ceil[(Δ0 - Δ t Formula 1 Here, ceil[ ] is the floor function.

[0072] Step S15: Based on the N number of cycles and the required number of compensation cycles, calculate the second average interval between two adjacent compensation cycles.

[0073] In some embodiments, a second average interval between two adjacent compensation cycles actually required for the second etching can be obtained by dividing N cycle numbers and n compensation cycle numbers, and this interval is used to correct the first average interval.

[0074] In some embodiments, let the second average interval be q (i.e., insert one compensation cycle every q normal cycles), and let N be the total number of cycles during the second etching. Then, the calculation of the second average interval can satisfy the following formula three: q = (N - n) / n (Formula 3) Where q is the second average interval, rounded to the nearest integer.

[0075] Step S16: Perform a third etching for M cycles on the third wafer, and during the third etching, insert a compensation cycle at the second average interval.

[0076] In some embodiments, a modified scheme, in which one compensation cycle is inserted at a second average interval, can be used to perform M cycles of actual mass production etching (third etching) on ​​a third wafer, which is a product wafer. The difference between the third etching and the second etching is that, when performing the third etching, the estimated first average interval is replaced with the second average interval, and a compensation cycle is inserted every second average interval during the execution of M cycles.

[0077] In some embodiments, M and N are the same or different (preferably the difference rate between M and N is within 15%); m and n are greater than 1 (generally, n > m, then the second average interval is smaller than the first average interval).

[0078] refer to Figure 9 In some embodiments, a third etching process of M cycles is performed on the third wafer 30. During the execution of these M cycles, a compensation cycle is inserted every second average interval of normal cycle count. Given that the etching rate of the central region A is known to be slower than that of the edge region B in this example, when the compensation cycle is executed and the bottom passivation layer removal step is reached, the radial source power allocation ratio of the central region A relative to the edge region B is increased, and the bias power is decreased to compensate for the etching rate difference between the central region A and the edge region B. Ultimately, multiple etched structures are formed on the surface of the third wafer 30, including a fifth etched structure 31 located in the central region A and a sixth etched structure 32 located in the edge region B. It can be seen that by correcting the average interval of the inserted compensation cycle, the third depth difference h3 between the etching depth of the fifth etched structure 31 and the etching depth of the sixth etched structure 32 becomes smaller, i.e., the third depth difference h3 is less than the second depth difference h2 (h3 < h2).

[0079] In some embodiments, the applicability of the calculation results of the second average interval can be verified, specifically including: First, based on the calculated second average interval q, three different frequencies of the second average interval are set as qp, q, and q+p, where p = 1 to 3.

[0080] Then, the fourth wafer 40 (which is the same wafer as the second wafer 20) serving as the verification wafer (verification piece) undergoes N cycles of fourth etching. The difference between the fourth and second etching is that, during the fourth etching, qp, q, and q+p are used as the second average interval values ​​to replace the first average interval, and the fourth etching is performed once at each of these three different frequencies (three different second average interval values ​​qp, q, and q+p). Furthermore, during the N cycles, a compensation cycle is inserted every corresponding second average interval, etching multiple etched structures onto the surface of the fourth wafer 40, including a seventh etched structure 41 located in the central region A and an eighth etched structure 42 located in the edge region B, as shown below. Figure 10 As shown.

[0081] After performing a fourth etching at three different frequencies, the difference in etching rate between the central region A and the edge region B can be observed as follows: Figure 10 As shown. Wherein, when qp is used as the first frequency of the second average interval, there is a fourth depth difference h4 between the etching depth of the seventh etching structure 41 and the etching depth of the eighth etching structure 42 (the fourth depth difference h4 is obtained by subtracting the etching depth of the seventh etching structure 41 from the etching depth of the eighth etching structure 42, the same below), as... Figure 10As shown in (a); when q is used as the second frequency of the second average interval, there is a fifth depth difference h5 between the etching depth of the seventh etching structure 41 and the etching depth of the eighth etching structure 42, as shown in (a). Figure 10 As shown in (b); when q+p is used as the third frequency of the second average interval, there is a sixth depth difference h6 between the etching depth of the seventh etching structure 41 and the etching depth of the eighth etching structure 42, as shown in (b). Figure 10 As shown in (c) in the figure.

[0082] Then, the frequency used in the fourth etching step with the smallest in-plane uniformity value is selected as the second average interval actually used during the third etching on the third wafer 30. For example, Figure 10 The example shown is that the fourth depth difference h4, the fifth depth difference h5, and the sixth depth difference h6 increase sequentially (without overshoot). By further calculating the in-plane uniformity, the frequency used for the fourth etching with the smallest in-plane uniformity value can be used as the second average interval actually used when performing the third etching on the third wafer 30, based on the calculation results.

[0083] In some embodiments, the following formula four is recommended for calculating in-plane uniformity: U = (D max - D min ) / (2D avg Formula 4 (100% × 100%) Where U represents in-plane uniformity, and D max D represents the maximum etching depth. min D is the minimum etching depth. avg This represents the average etching depth.

[0084] In some embodiments, when it is known from the results of the first etching that the etching rate of the central region A is slower than that of the edge region B, the second radial source power allocation ratio used during the second, third, and fourth etching processes is: radial source power allocation ratio of the central region A : radial source power allocation ratio of the edge region B = 55:45 to 70:30. However, this is not limited to this, provided that the second radial source power allocation ratio is greater than the first radial source power allocation ratio.

[0085] In some embodiments, when it is known from the results of the first etching that the etching rate of the central region A is faster than the etching rate of the edge region B, the third radial source power allocation ratio used during the second, third, and fourth etching processes is: radial source power allocation ratio of the central region A : radial source power allocation ratio of the edge region B = 45:55 to 30:70. However, this is not a limitation, provided that the third radial source power allocation ratio is less than the first radial source power allocation ratio.

[0086] In some embodiments, when it is known from the result of the first etching that the etching rate of the central region A is slower than that of the edge region B, the second bias power used during the second, third, and fourth etching processes, and during the execution of the compensation cycle and the bottom passivation layer removal step, is 0W to 10W. However, this is not a limitation, provided that the second bias power is less than the first bias power.

[0087] In some embodiments, when it is known from the result of the first etching that the etching rate of the central region A is faster than the etching rate of the edge region B, the third bias power used during the second, third, and fourth etching processes, and during the execution of the compensation cycle and the bottom passivation layer removal step, is 0W to 10W. However, this is not a limitation, provided that the third bias power is less than the first bias power.

[0088] In one embodiment, a calibration procedure is recommended (taking the etching rate of the central region A as a slower rate than that of the edge region B as an example): (1) Perform 300 cycles of first etching on the reference wafer (first wafer 10), with the first radial source power allocation ratio being 50:50, the first bias power being 80W, and the bottom passivation layer removal step taking 1.5s. Record the total number of cycles N. total (300), Etching depth D in central area I C Intermediate region II etching depth D M Etching depth D in outer ring region III E And calculate the first depth difference h1 and the in-plane uniformity U.

[0089] (2) Keep the total number of cycles unchanged at 300, and replace, for example, 5 to 15 normal cycles with the estimated compensation cycles (it is recommended to take m = 10 or 12 in the first round). In this example, replace 12 normal cycles in the 300 cycles with the estimated 12 compensation cycles, and perform the second etching of 300 cycles on the compensation calibration wafer (second wafer 20). The second radial source power allocation ratio is 65:35, the second bias power is 0W, the time for the bottom passivation layer removal step is 1.5s, and record the total number of cycles N. total Central area I etching depth D C Intermediate region II etching depth D M Etching depth D in outer ring region III E And calculate the second depth difference h2 and the in-plane uniformity U.

[0090] The obtained etching depth D of the central region I C Intermediate region II etching depth D M Etching depth D in outer ring region III E Depth difference Δ (Δ=D)E -D M The depth differences (including the first depth difference h1 corresponding to the first etching, the second depth difference h2 corresponding to the second etching, and the fourth depth difference h4 corresponding to the fourth etching) and the data of in-plane uniformity U are shown in Table 1.

[0091] Table 1

[0092] (3) Based on the data in Table 1, calculate the single-cycle compensation gain G using Formula 2. The calculation results are as follows: G = (6.0 - 2.4) / 12 = 0.30μm / cycle (4) Let the allowable target depth difference Δ t The actual number of compensation cycles required for the second etching is n, and the second average interval q is calculated using Formula 1 and Formula 3, respectively. The calculation results are as follows: n = ceil[(6.0 - 1.0) / 0.30] = 17 times The 17th value is the integer value obtained by rounding up from approximately 16.67 times the calculated value.

[0093] q = (300 - 17) / 17 ≌ 16.65 = 17 (repeating numbers) Where q is the integer value obtained by rounding the calculated value of 16.65 to 17 using the rounding method.

[0094] Therefore, the preferred verification condition is to insert one compensation cycle every 17 normal cycles. Simultaneously, it is recommended to verify the 14:1, 17:1, and 20:1 conditions (with p=3).

[0095] (5) Keep the total number of cycles unchanged at 300 cycles, and set three frequencies around the above calculation results, such as 14, 17, and 20. Replace 14, 17, and 20 normal cycles in the 300 cycles with 14, 17, and 20 compensation cycles respectively. Perform the fourth etching of 300 cycles on the verification wafer (fourth wafer 40). The second radial source power allocation ratio is 65:35, the second bias power is 0W, the time for the bottom passivation layer removal step is 1.5s, and record the total number of cycles N. total Central area I etching depth D C Intermediate region II etching depth D M Etching depth D in outer ring region III E And calculate the in-plane uniformity U of the fourth depth difference h4 to the sixth depth difference h6 and the corresponding etching.

[0096] Frequency 17, corresponding to the condition of lowest U value and no outer ring taper or bottom residue, was selected as the second average interval actually used during the third etching on the third wafer 30. The corresponding etching depth D in the central region I was obtained. C Intermediate region II etching depth D M Etching depth D in outer ring region III E The data for depth difference Δ (fifth depth difference h5) and in-plane uniformity U are recorded in Table 1.

[0097] If the total number of etching cycles is large, resulting in a large etching depth, the etching process can be divided into initial, intermediate, and final stages, and calibrated separately according to the above process to avoid the situation where the single compensation gain is not constant in different depth segments.

[0098] The etching depth compensation effect produced at different radial positions of the second wafer 20 and the fourth wafer 40 after the second and fourth etching processes described above, compared with that of the first wafer 10 after the first etching process described above, is as follows: Figure 11 As shown. By Figure 11 As can be seen, on the second wafer 20 and the fourth wafer 40, the etching depth of the middle region II increases sequentially compared to the first wafer 10, while the etching depth of the outer region III decreases sequentially compared to the first wafer 10. The etching depth of the central region I also decreases sequentially compared to the first wafer 10, but the change is not significant and remains within the allowable range. Therefore, the etching depth difference between the central region A and the edge region B is reduced, and the in-plane uniformity is also improved sequentially compared to the first wafer 10 (the in-plane uniformity value decreases sequentially). The above results show that when a compensation cycle is inserted into the overall cycle of the deep reactive ion etching process, it has a significant effect on reducing the etching depth difference between the central region A and the edge region B and improving the in-plane uniformity. Furthermore, by verifying the calculated second average interval and selecting the optimal second average interval frequency as the actual second average interval used when performing the third etching (mass production etching) on ​​the third wafer 30 (product wafer), the compensation effect is further enhanced.

[0099] In a second aspect, embodiments of this application also provide a semiconductor device for performing a control method for improving in-plane uniformity of deep reactive ion etching as provided in any of the embodiments of the first aspect above.

[0100] In some embodiments, the semiconductor device includes a plasma processing device, such as an inductively coupled plasma (ICP) processing device or a capacitively coupled plasma (CCP) processing device. A host / slave computer configured within the plasma processing device can be used to execute the control method for improving in-plane uniformity in deep reactive ion etching provided in the embodiments of this application.

[0101] In summary, this embodiment of the application inserts compensation cycles at certain intervals (second average intervals) during the normal cycle (relative to the compensation cycle) of deep reactive ion etching on the wafer. When executing the compensation cycle and reaching the bottom passivation layer removal step, by increasing the radial source power allocation ratio of the slower etching rate region (center region A) and edge region B, and decreasing the bias power, the removal rate of the bottom passivation layer 50 of the etched structure in the faster etching rate region can be slowed down. This delays the start-up time of etching the wafer material below the bottom of the etched structure in the faster etching rate region during the corresponding etching step in the cycle, thereby reducing the etching increment per cycle and compensating for the etching rate difference between center region A and edge region B, thus reducing the etching depth difference between them. Furthermore, through experimental comparison, calculation, and verification, the average insertion interval (frequency) of the compensation cycles actually used in mass production was obtained, improving control accuracy and control level. This application is applicable to deep trenches, deep holes, release trenches, through holes and other high aspect ratio silicon structures in deep silicon etching, and is especially suitable for MEMS devices and TSV structures that have high requirements for the consistency of etching depth within the wafer plane.

[0102] The above are merely preferred embodiments of this application. These embodiments are not intended to limit the scope of protection of this application. Therefore, any equivalent changes made based on the description and drawings of this application should also be included within the scope of protection of this application.

Claims

1. A method for controlling the uniformity of deep reactive ion etching surfaces, characterized in that, include: After N cycles of first etching on the first wafer, the first depth difference between the etched structure in the central region and the etched structure in the edge region is obtained. Each cycle includes a passivation layer deposition step, a bottom passivation layer removal step, and an etching step in sequence. After performing N cycles of second etching on the second wafer, the second depth difference between the etched structure in the central region and the etched structure in the edge region is obtained. The difference between the second etching and the first etching is that m cycles out of N cycles are selected as the estimated m compensation cycles according to the first average interval. When performing the compensation cycle and proceeding to the bottom passivation layer removal step, the radial source power allocation ratio of the slower etching rate in the central region and the edge region is increased, and the bias power is decreased to reduce the etching depth difference between the central region and the edge region. Based on the difference between the first depth difference and the second depth difference, the single-cycle compensation gain of each compensation cycle for reducing the etching depth difference is calculated. The required number of compensation cycles (n) is calculated based on the ratio of the first depth difference to the single-cycle compensation gain. Based on N cycles and n compensation cycles, the required second average interval between two adjacent compensation cycles is calculated. The third wafer is etched for M cycles. The difference between the third and second etches is that the first average interval is replaced by the second average interval, and a compensation cycle is inserted every second average interval during the execution of M cycles.

2. The method for controlling the uniformity of deep reactive ion etching as described in claim 1, characterized in that, M and N may be the same or different, and m and n are greater than 1.

3. The method for controlling the uniformity of deep reactive ion etching as described in claim 1, characterized in that, When performing cycles other than the compensation cycle and reaching the bottom passivation layer removal step, a first radial source power distribution ratio exists between the central region and the edge region, and a first bias power is used. When the etching rate of the central region is slower than that of the edge region, during the compensation cycle and reaching the bottom passivation layer removal step, a second radial source power distribution ratio greater than the first radial source power distribution ratio is adjusted to exist between the central region and the edge region, and a second bias power less than the first bias power is used. This ensures that when the bottom passivation layer of the etched structure in the central region is completely removed, the bottom passivation layer of the etched structure in the edge region still remains. This allows the effective etching time for etching the wafer material below the bottom of the etched structure in the central region to be longer than that for etching the wafer material below the bottom of the etched structure in the edge region during the corresponding etching step. The effective etching time for etching the wafer material is determined by the following: Conversely, when the etching rate of the central region is faster than that of the edge region, during the compensation cycle and up to the bottom passivation layer removal step, the central region and the edge region are adjusted to have a third radial source power allocation ratio that is less than the first radial source power allocation ratio, and a third bias power that is less than the first bias power is used. This ensures that when the bottom passivation layer of the etched structure in the edge region is completely removed, the bottom passivation layer of the etched structure in the central region still remains. This allows the effective etching time for etching the wafer material below the bottom of the etched structure in the edge region to be greater than the effective etching time for etching the wafer material below the bottom of the etched structure in the central region during the corresponding etching step, thereby compensating for the etching rate difference between the central region and the edge region.

4. The method for controlling the uniformity of deep reactive ion etching as described in claim 1, characterized in that, The first wafer, the second wafer, and the third wafer are the same wafer. When obtaining the first depth difference and the second depth difference, multi-point acquisition of depth data of the etched structure in the central region is performed on the first radial ring of the first wafer and the second wafer, and multi-point acquisition of depth data of the etched structure in the edge region is performed on the second radial ring of the first wafer and the second wafer. The average value of the depth data is used as the basis for calculating the first depth difference and the second depth difference.

5. The method for controlling the uniformity of deep reactive ion etching as described in claim 4, characterized in that, The first radial ring is located at a radius of 0.45 to 0.65 of the first wafer and the second wafer, and the second radial ring is located at a radius of 0.8 to 0.95 of the first wafer and the second wafer.

6. The method for controlling the uniformity of deep reactive ion etching as described in claim 1, characterized in that, Let the target depth difference between the etching structure of the allowed central region and the etching structure of the edge region be Δ t Then the calculation of the number of n compensation cycles satisfies the following formula one: n = ceil[(Δ0 - Δ t Formula 1 Where ceil[ ] is the floor function, Δ0 is the first depth difference, and G is the single-cycle compensation gain. The calculation of the single-cycle compensation gain G satisfies the following formula: G = (Δ0 - Δ m Formula 2 Where, Δ m This is the second depth difference.

7. The method for controlling the uniformity of deep reactive ion etching as described in claim 6, characterized in that, The calculation of the second average interval satisfies the following formula three: q = (N - n) / n (Formula 3) Where q is the second average interval, rounded to the nearest integer.

8. The method for controlling the uniformity of deep reactive ion etching as described in claim 7, characterized in that, It also includes verifying the applicability of the calculation results for the second average interval, specifically including: Based on the calculated second average interval q, three frequencies are set as qp, q, and q+p, where p = 1 to 3; The fourth wafer is etched for N cycles. The difference between the fourth and second etches is that the first average interval is replaced by the second average interval with qp, q, and q+p respectively for the fourth etch. During the N cycles, a compensation cycle is inserted every second average interval corresponding to the frequency. The frequency used in the fourth etching with the smallest in-plane uniformity value is selected as the second average interval actually used when performing the third etching on the third wafer. The fourth wafer is the same as the third wafer.

9. The method for controlling the uniformity of deep reactive ion etching as described in claim 3, characterized in that, The second radial source power allocation ratio is 55:45 to 70:30; and / or, the third radial source power allocation ratio is 45:55 to 30:70; and / or, the second bias power is 0W to 10W; and / or, the third bias power is 0W to 10W.

10. A semiconductor device, characterized in that, The semiconductor device is used to perform the control method for improving in-plane uniformity of deep reactive ion etching as described in any one of claims 1-9.

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