Chip package structure

Abstract

A chip package structure includes a first chip, a conductive clip, a second chip, and a third chip. The first chip includes a first power transistor. The conductive clip is disposed on the first chip. The second chip includes a sense transistor, and the second chip is disposed on the conductive clip, wherein the second chip is configured to sense a current of the first chip, wherein the second chip and the first chip each have a semiconductor substrate and the semiconductor substrate of the second chip and the semiconductor substrate of the first chip are separated from each other. The third chip is disposed on the conductive clip, wherein the third chip is configured to drive the first chip.

Description

Technical Field

[0001] This invention relates to a packaging structure, and more particularly to a chip packaging structure. Background Technology

[0002] With technological advancements, power semiconductor devices are moving towards intelligent power stage packaging, which can provide monitoring signals such as voltage or current. Generally, to provide these signals, sensing transistors and related circuitry are placed in the low-side power chip. However, integrating these transistors and circuitry into the low-side chip increases manufacturing costs. Furthermore, the footprint design must be adjusted to suit the function and requirements of the power semiconductor device. For example, power semiconductor devices with current sensing capabilities differ from those without, requiring custom footprint designs for each type of device. This increases overall package design and manufacturing costs and makes flexible adjustments difficult. Summary of the Invention

[0003] This invention relates to a chip packaging structure that can flexibly incorporate current sensing functionality as needed while reducing design and manufacturing costs.

[0004] According to an embodiment of the present invention, a chip package structure includes a first chip, a conductive clip, a second chip, and a third chip. The first chip includes a first power transistor. The conductive clip is disposed on the first chip. The second chip includes a sensing transistor and is disposed on the conductive clip, wherein the second chip is configured to sense the current of the first chip, and wherein the second chip and the first chip each have a semiconductor substrate, and the semiconductor substrates of the second chip and the first chip are separated from each other. The third chip is disposed on the conductive clip, wherein the third chip is configured to drive the first chip.

[0005] In the chip packaging structure according to an embodiment of the present invention, the drain of the sensing transistor is electrically connected to the drain of the first power transistor via a conductive clip.

[0006] In the chip packaging structure according to an embodiment of the present invention, the gate and source of the sensing transistor are electrically connected to the third chip via wire bonding.

[0007] In the chip packaging structure according to an embodiment of the present invention, the orthographic projection of the second chip on the conductive clip overlaps with the orthographic projection of the first chip on the conductive clip.

[0008] In the chip packaging structure according to an embodiment of the present invention, the orthographic projection of the second chip on the conductive clip does not overlap with the orthographic projection of the third chip on the conductive clip.

[0009] In the chip packaging structure according to an embodiment of the present invention, the process conditions for manufacturing the second chip are matched with the process conditions for manufacturing the first chip.

[0010] In the chip packaging structure according to an embodiment of the present invention, the chip packaging structure further includes a lead frame, wherein the first chip is die-bonded to the lead frame, and the gate of the first power transistor is electrically connected to the third chip through the lead frame.

[0011] In the chip packaging structure according to an embodiment of the present invention, the chip packaging structure further includes a fourth chip disposed between the lead frame and the conductive clip, and the third chip is configured to drive the first chip and the fourth chip.

[0012] In the chip packaging structure according to an embodiment of the present invention, the fourth chip includes a second power transistor, the gate of the second power transistor is electrically connected to the third chip through wire bonding, and the drain of the second power transistor is electrically connected to the drain of the sensing transistor through a conductive clip.

[0013] In the chip packaging structure according to an embodiment of the present invention, the drain of the first power transistor, the drain of the second power transistor, and the drain of the sensing transistor are all electrically connected to a conductive clamp.

[0014] Based on the above, the chip packaging structure of the present invention includes a first chip, a second chip, a third chip, and a conductive clip. The second chip and the first chip each have a semiconductor substrate, and the second chip has a sensing transistor configured to sense the current of the first chip. In this way, compared to integrating the sensing transistor into the first chip, the design and manufacturing costs of the first chip can be reduced. Furthermore, the chip packaging structure allows for flexible arrangement of the second chip as needed, increasing its application flexibility. Attached Figure Description

[0015] Figure 1 This is a top view schematic diagram of a chip packaging structure according to an embodiment of the present invention;

[0016] Figure 2 This is a cross-sectional schematic diagram of a chip packaging structure according to an embodiment of the present invention;

[0017] Figure 3 This is a circuit diagram of a chip packaging structure according to an embodiment of the present invention. Detailed Implementation

[0018] Reference will now be made in detail to exemplary embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same component reference numerals are used in the drawings and description to denote the same or similar parts.

[0019] Figures 1 to 3These are, respectively, a top view, a cross-sectional view, and a circuit diagram of a chip packaging structure according to an embodiment of the present invention. Figure 2 It can be along Figure 1 A cross-sectional view showing a section cut along line A-A'. For clarity, Figure 1 The conductive clip 140 and the first chip 110 are drawn in perspective, and some components are omitted. This is for illustrative purposes. Figure 3 The connection between the gate GS and source SS of the sensing transistor TS is only schematically shown to the third chip 130, and its circuitry is not shown in the third chip 130.

[0020] Please refer to Figures 1 to 3 The chip package structure 10 includes a first chip 110, a second chip 120, a third chip 130, and a conductive clip 140. The conductive clip 140 is disposed on the first chip 110, and the second chip 120 and the third chip 130 are disposed on the conductive clip 140. In some embodiments, the second chip 120 and the third chip 130 are spaced apart from each other in the horizontal direction (e.g., the y-direction), that is, the orthographic projection of the second chip 120 on the conductive clip 140 does not overlap with the orthographic projection of the third chip 130 on the conductive clip 140. In other words, if light in the z-direction shines on the second chip 120 / third chip 130, the shadows formed by the two on the xy plane of the conductive clip 140 will not overlap.

[0021] In some embodiments, the orthographic projection of the second chip 120 onto the conductive clip 140 overlaps with the orthographic projection of the first chip 110 onto the conductive clip 140. That is, a portion of the conductive clip 140 is located between the second chip 120 and the first chip 110. In some embodiments, the orthographic projection of the first chip 110 onto the conductive clip 140 does not overlap with the orthographic projection of the third chip 130 onto the conductive clip 140.

[0022] In some embodiments, the chip package structure 10 further includes a fourth chip 150, which is disposed below the conductive clip 140, and the orthographic projection of the fourth chip 150 on the conductive clip 140 overlaps with the orthographic projection of the third chip 130 on the conductive clip 140. That is, a portion of the conductive clip 140 is located between the fourth chip 150 and the third chip 130. In some embodiments, the orthographic projection of the fourth chip 150 on the conductive clip 140 does not overlap with the orthographic projection of the first chip 110 on the conductive clip 140.

[0023] The first chip 110, the second chip 120, the third chip 130, and the fourth chip 150 are independent semiconductor chips, each with its own semiconductor substrate. That is, the semiconductor substrates of the first chip 110, the second chip 120, the third chip 130, and the fourth chip 150 are separate from each other.

[0024] In some embodiments, the first chip 110, the second chip 120, and the fourth chip 150 can be electrically connected to each other via conductive clips 140. In some embodiments, the third chip 130 can be electrically connected to the first chip 110, the second chip 120, and / or the fourth chip 150 via wire bonding.

[0025] In some embodiments, the chip package structure 10 further includes a lead frame 100. The first chip 110 and the fourth chip 150 are located between the lead frame 100 and the conductive clip 140.

[0026] In some embodiments, the lead frame 100 may include a first support portion 102 and a second support portion 104. The first support portion 102 and the second support portion 104 are spatially separated from each other. For example, the first support portion 102 and the second support portion 104 may be arranged in the y-direction and separated from each other. In some embodiments, the first support portion 102 is configured to be connected to a high-potential signal, and the second support portion 104 is configured to be connected to a ground signal.

[0027] In some embodiments, the first chip 110 is flip-chip bonded to the first carrier portion 102 of the lead frame 100, that is, the active surface 110a of the first chip 110 faces downward toward the first carrier portion 102, and the back surface 110b of the first chip 110 faces upward toward the conductive clip 140. In some embodiments, the first chip 110 can be fixed to the first carrier portion 102 by a conductive adhesive layer 161. In this document, the active surface of the chip refers to the side on which the active component (e.g., a transistor) is disposed on the semiconductor substrate, and the back surface of the chip refers to the other side of its semiconductor substrate disposed relative to the active component. Therefore, the active surface and the back surface are opposite each other.

[0028] In some embodiments, a fourth chip 150 is disposed on a second carrier portion 104, with the active surface 150a of the fourth chip 150 facing upwards and towards the conductive clip 140, and the back surface 150b of the fourth chip 150 facing downwards and towards the second carrier portion 104. In some embodiments, the fourth chip 150 can be fixed to the second carrier portion 104 by a conductive adhesive layer 165.

[0029] In some embodiments, the conductive clip 140 can be fixed to the first chip 110 and the fourth chip 150 by conductive adhesive layer 163 and conductive adhesive layer 166.

[0030] In some embodiments, the active surface 120a of the second chip 120 faces upward, and the back surface 120b of the second chip 120 faces downward towards the conductive clip 140. The second chip 120 can be fixed to the conductive clip 140 by a conductive adhesive layer 164. In some embodiments, the active surface 130a of the third chip 130 faces upward, and the back surface 130b of the third chip 130 faces downward towards the conductive clip 140. The third chip 130 can be fixed to the conductive clip 140 by an adhesive layer 167.

[0031] In some embodiments, the lead frame 100 further includes a plurality of pin portions (including a first pin portion 106 and a second pin portion 108) which can be used to electrically connect the chip package structure 10 to external components. The plurality of pin portions are spatially separated from the first carrier portion 102 and the second carrier portion 104. For example, the plurality of pin portions may be disposed around the first carrier portion 102 or the second carrier portion 104.

[0032] In some embodiments, the first pin portion 106 is adjacent to one side of the first carrier portion 102 and its orthographic projection in the z-direction partially overlaps with the first chip 110. In some embodiments, the second pin portion 108 is adjacent to one side of the second carrier portion 104.

[0033] In some embodiments, the first chip 110 includes a first power transistor T1. In some embodiments, the first chip 110 may be a low-side MOS chip configured as a switch for grounding, such as... Figure 3 As shown. In some embodiments, the active surface 110a of the first chip 110 includes a gate pad 110G and a source pad 110S, while the back surface 110b of the first chip 110 includes a drain pad 110D. The source pad 110S can be connected to the first carrier portion 102 through a conductive adhesive layer 161, so that the source S1 of the first power transistor T1 of the first chip 110 is electrically connected to the first carrier portion 102. The gate pad 110G can be electrically connected to the first pin portion 106 through a conductive adhesive layer 162, and as shown... Figure 1 As shown, the first pin portion 106 can be electrically connected to the corresponding pad of the third chip 130 via wire bonding, so that the gate G1 of the first power transistor T1 can be electrically connected to the third chip 130 via the lead frame 100. The drain pad 110D can be electrically connected to the conductive clip 140 via the conductive adhesive layer 163, so that the drain D1 of the first power transistor T1 is electrically connected to the conductive clip 140.

[0034] In some embodiments, the fourth chip 150 includes a second power transistor T2. In some embodiments, the fourth chip 150 may be a high-side MOS chip configured as a switch at the input power supply VDD terminal, such as... Figure 3 As shown. In some embodiments, the active surface 150a of the fourth chip 150 includes a gate pad 150G, a source pad 150S, and a drain pad 150D. The source pad 150S can be electrically connected to the second pin portion 108 via a bonding wire 174, so that the source S2 of the second power transistor T2 of the fourth chip 150 is electrically connected to the second pin portion 108. The gate pad 150G can be electrically connected to the corresponding pad of the third chip 130 via a bonding wire 176, so that the gate G2 of the second power transistor T2 is electrically connected to the third chip 130. The drain pad 150D can be electrically connected to the conductive clip 140 via a conductive adhesive layer 166, so that the drain D2 of the second power transistor T2 is electrically connected to the conductive clip 140.

[0035] In some embodiments, the second chip 120 includes a sensing transistor TS, and the second chip 120 is configured to sense the current of the first chip 110. In some embodiments, the active surface 120a of the second chip 120 includes a gate pad 120G and a source pad 120S, while the back surface 120b of the second chip 120 includes a drain pad 120D. The source pad 120S can be electrically connected to a corresponding pad of the third chip 130 via a bonding wire 172, so that the source SS of the sensing transistor TS of the second chip 120 is electrically connected to the third chip 130. The gate pad 120G can be electrically connected to a corresponding pad of the third chip 130 via a bonding wire 170, so that the gate GS of the sensing transistor TS is electrically connected to the third chip 130. The drain pad 120D can be electrically connected to a conductive clip 140 via a conductive adhesive layer 164, so that the drain DS of the sensing transistor TS is electrically connected to the conductive clip 140.

[0036] In this way, the drain DS of the sensing transistor TS, the drain D1 of the first power transistor T1, and the drain D2 of the second power transistor T2 of the fourth chip 150 can be electrically connected to each other through the conductive clip 140. That is, the sensing transistor TS of the second chip 120 shares a drain with the first power transistor T1 of the first chip 110 and the second power transistor T2 of the fourth chip 150. It should be noted that the above embodiment is described from the viewpoint that the first power transistor T1 is an n-type power transistor and the second power transistor T2 is a p-type power transistor. In another embodiment, if the upper and lower bridge switches of a conventional power converter are used, that is, both the first power transistor T1 and the second power transistor T2 are n-type power transistors, and the drain of the first power transistor T1 is electrically connected to the source of the second power transistor T2, then only the sensing transistor TS of the second chip 120 shares a drain with the first power transistor T1 of the first chip 110. Based on this, general engineers can arrange the layout and configuration of each terminal pad in each chip, each component in the lead frame, the conductive clip 140, and each wire bonding, which will not be described in detail here.

[0037] In some embodiments, the sensing transistor TS of the second chip 120 may share a common gate with the first power transistor T1 of the first chip 110 and / or the second power transistor T2 of the fourth chip 150. For example, such as Figure 3 As shown, the gate GS of the sensing transistor TS, the gate G1 of the first power transistor T1, and the gate G2 of the second power transistor T2 can be electrically connected to the third chip 130, and the gate GS of the sensing transistor TS can be electrically connected to the gate G1 of the first power transistor T1 and / or the gate G2 of the second power transistor T2 through the wiring of the third chip 130.

[0038] The second chip 120 can sense the current of the first chip 110 by having the sensing transistor TS and the transistor of the chip under test (e.g., the first power transistor T1 of the first chip 110) share a common drain and a common gate, so that the current flowing through the sensing transistor TS is in a predetermined ratio to the current flowing through the first power transistor T1. Furthermore, the current of the first power transistor T1 of the first chip 110 can be deduced by measuring the voltage generated by the current in the sensing transistor TS through a resistor (not shown), thus enabling the second chip 120 to sense the current of the first chip 110. In some embodiments, the second chip 120 may also be configured to sense the current of a fourth chip 150, but this invention is not limited thereto.

[0039] Since the sensing transistor TS is independently located in the second chip 120 rather than integrated into the first chip 110, the design and manufacturing costs of the first chip 110 can be reduced. Furthermore, the second chip 120 can be flexibly configured according to the current sensing function requirements of the package structure without corresponding adjustments to the design of the lead frame 100, thereby increasing the flexibility of the application.

[0040] In some embodiments, the process conditions for manufacturing the second chip 120 are matched with the process conditions for manufacturing the first chip 110, and the second chip 120 is located directly above the first chip 110. This can make the components in the second chip 120 (e.g., sensing transistor TS) and the components in the first chip 110 (e.g., first power transistor T1) respond more consistently to temperature changes, thereby improving the accuracy of current monitoring of the second chip 120.

[0041] In some embodiments, the third chip 130 is configured to drive the first chip 110 and the fourth chip 150. In some embodiments, the third chip 130 may include logic lines 132 and gate drivers 134 to control the switching of transistors in the first chip 110 and the fourth chip 150.

[0042] In some embodiments, conductive adhesive layers 161 to 166 may include soldering materials, such as solder paste, silver paste, or other suitable soldering materials. In some embodiments, adhesive layer 167 may be an insulating adhesive layer, such as including epoxy resin, die attach film, or other suitable insulating adhesive materials, but the invention is not limited thereto. In other embodiments, adhesive layer 167 may also be a conductive adhesive material having a similar material to conductive adhesive layers 161 to 166.

[0043] In summary, the chip packaging structure of the present invention includes a first chip, a second chip, a third chip, and a conductive clip. The second chip and the first chip each have a semiconductor substrate, and the second chip has a sensing transistor configured to sense the current of the first chip. This reduces the design and manufacturing costs of the first chip compared to integrating the sensing transistor into the first chip. Furthermore, the chip packaging structure allows for flexible placement of the second chip as needed, increasing its application flexibility.

[0044] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A chip package structure, characterized by, include: The first chip includes a first power transistor; A conductive clip is disposed on the first chip; A second chip, including a sensing transistor, is disposed on the conductive clip, wherein the second chip is configured to sense the current of the first chip, wherein the second chip and the first chip each have a semiconductor substrate and the semiconductor substrate of the second chip is separate from the semiconductor substrate of the first chip. as well as A third chip is disposed on the conductive clip, wherein the third chip is configured to drive the first chip.

2. The chip packaging structure according to claim 1, characterized in that, The drain of the sensing transistor is electrically connected to the drain of the first power transistor via the conductive clip.

3. The chip package structure of claim 1, wherein, The gate and source of the sensing transistor are electrically connected to the third chip via wire bonding.

4. The chip package structure of claim 1, wherein, The orthographic projection area of ​​the second chip on the conductive clamp overlaps with the orthographic projection area of ​​the first chip on the conductive clamp.

5. The chip package structure of claim 1, wherein, The orthographic projection area of ​​the second chip on the conductive clamp will not overlap with the orthographic projection area of ​​the third chip on the conductive clamp.

6. The chip package structure of claim 1, wherein, The process conditions for manufacturing the second chip are matched with the process conditions for manufacturing the first chip.

7. The chip package structure of claim 1, wherein, The chip packaging structure also includes: A lead frame, wherein the first chip is flip-chip bonded to the lead frame, and the gate of the first power transistor is electrically connected to the third chip through the lead frame.

8. The chip package structure of claim 7, wherein, The chip packaging structure also includes: A fourth chip is disposed between the lead frame and the conductive clip, and the third chip is configured to drive the first chip and the fourth chip.

9. The chip package structure of claim 8, wherein, The fourth chip includes a second power transistor, the gate of which is electrically connected to the third chip via a wire bonding, and the drain of which is electrically connected to the drain of the sensing transistor via the conductive clip.

10. The chip package structure of claim 9, wherein, The drain of the first power transistor, the drain of the second power transistor, and the drain of the sensing transistor are all electrically connected to the conductive clamp.

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