Deep trench isolation structure and method for manufacturing deep trench isolation structure

Abstract

This invention provides a deep trench isolation structure and a method for fabricating such a structure, relating to the field of semiconductor technology. The deep trench isolation structure includes a substrate, a buffer layer, and a filling layer. An isolation trench is formed on the first surface of the substrate. The buffer layer covers the sidewalls and bottom wall of the isolation trench, while the filling layer fills the isolation trench and contacts the buffer layer. This allows the buffer layer to separate the filling layer and the substrate. The buffer layer is configured to expand in volume to compensate for the tensile stress caused by the substrate. Compared to existing technologies, this invention utilizes a buffer layer to separate the filling layer and the substrate. Furthermore, the buffer layer expands in volume during annealing, thereby compensating for the tensile stress caused by the substrate's cooling and shrinkage. This prevents the initiation and propagation of cracks and avoids delamination of the material layers, providing high reliability and long-life insulation protection for the isolation structure.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and more specifically, to a deep trench isolation structure and a method for fabricating the deep trench isolation structure. Background Technology

[0002] In devices built using advanced DTI-on-SOI (deep trench isolation on silicon insulator) technology, the trench design, which penetrates the top silicon layer and the buried oxide layer, provides superior electrical isolation characteristics. However, in actual SiO2 filling processes, through-type surface cracks caused by uneven internal stress have become a key issue affecting yield. The main reason is that during the annealing and cooling stage, the shrinkage of the silicon substrate (thermal expansion coefficient 2.6 ppm / ℃) is much greater than that of the SiO2 filling layer (0.5 ppm / ℃), resulting in transverse tensile stress within the SiO2. When this stress exceeds its fracture strength, cracks form.

[0003] The current industry-standard approach is to optimize the annealing process profile, mitigating stress accumulation by controlling the rate of temperature change or extending the process time. However, these methods struggle to completely suppress crack formation at the mechanistic level and may introduce new lattice defects due to increased high-temperature duration or lead to higher costs due to extended process time. Particularly in trench structures with ever-increasing aspect ratios, the uniformity of coverage achieved by traditional annealing processes is limited, resulting in less than ideal repair outcomes. Summary of the Invention

[0004] The purpose of this invention is to provide a deep trench isolation structure and a method for preparing the deep trench isolation structure, which can block the initiation and propagation of cracks and provide high reliability and long life insulation protection for the isolation structure.

[0005] In a first aspect, the present invention provides a deep trench isolation structure, comprising: A substrate having opposing first and second surfaces, wherein the first surface is provided with isolation trenches; A buffer layer covering the sidewalls and bottom wall of the isolation trench; A filler layer that fills the isolation trench and contacts the buffer layer to separate the filler layer and the substrate; During annealing, the buffer layer is configured to expand in volume during the annealing process to compensate for the tensile stress caused by the cooling and shrinkage of the substrate.

[0006] In an optional embodiment, the buffer layer comprises a YSZ thin film, the substrate comprises silicon, and the filler layer comprises silicon dioxide.

[0007] In an optional embodiment, the substrate includes a bottom silicon layer, a buried oxide layer, and a top silicon layer, wherein the buried oxide layer is disposed on the bottom silicon layer, the top silicon layer is disposed on the buried oxide layer, the first surface is located on the side of the top silicon layer away from the bottom silicon layer, and the isolation trench passes through the top silicon layer and exposes the buried oxide layer.

[0008] In an optional implementation, the thickness of the buffer layer is greater than or equal to 30 nm.

[0009] In an optional embodiment, the sidewalls and bottomwalls of the isolation trench are further formed with a linear oxide layer, and the buffer layer is formed on the surface of the linear oxide layer.

[0010] In a second aspect, the present invention provides a method for preparing a deep trench isolation structure, used to prepare the deep trench isolation structure as described in the foregoing embodiments, the method comprising: A substrate is provided, wherein the substrate has opposing first and second surfaces; An isolation trench is formed on the first surface; A buffer layer is deposited on the sidewalls and bottom wall of the isolation trench to form a buffer layer; A filling layer is deposited in the isolation trench; Annealing repairs damage; During annealing, the buffer layer is configured to expand in volume to compensate for the tensile stress caused by the cooling and shrinkage of the substrate.

[0011] In an optional embodiment, the step of depositing a buffer layer on the sidewalls and bottom wall of the isolation trench includes: A linear oxide layer is grown on the sidewalls and bottom wall of the isolation trench; A buffer layer is formed by depositing at least one layer on the surface of the linear oxide layer using atomic deposition.

[0012] In an optional embodiment, the step of depositing a buffer layer at least on the surface of the linear oxide layer using atomic deposition includes: Atomic deposition was used, with Zr(NMe2)4 and Y(NMe2)3 as metal sources and H2O as oxygen source, and alternating pulses were applied at 200°C to obtain a YSZ thin film at least on the surface of the linear oxide layer.

[0013] In an optional implementation, prior to the annealing step for repairing damage, the method further includes: The filling layer is ground and planarized.

[0014] In an optional implementation, after the annealing step to repair damage, the method further includes: The filler layer is partially etched so that it is flush with the first surface.

[0015] The beneficial effects of the embodiments of the present invention include: The deep trench isolation structure and its preparation method provided in this embodiment of the invention have an isolation trench formed on the first surface of a substrate. A buffer layer covers the sidewalls and bottom wall of the isolation trench, and a filling layer fills the isolation trench and contacts the buffer layer, thereby enabling the buffer layer to separate the filling layer and the substrate. The thermal expansion coefficient of the substrate is greater than that of the filling layer. The buffer layer is configured to expand in volume during annealing to compensate for the tensile stress caused by the substrate.

[0016] Compared with the prior art, the deep trench isolation structure and its preparation method provided in this embodiment of the invention utilize a buffer layer to separate the filling layer and the substrate. The buffer layer can expand in volume during annealing, thereby compensating for the tensile stress caused by the cooling and shrinkage of the substrate. This can prevent the initiation and propagation of cracks and also avoid the delamination of materials in each layer, providing high reliability and long life insulation protection for the isolation structure. Attached Figure Description

[0017] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the present invention and should not be regarded as a limitation on the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 This is a schematic diagram of a deep trench isolation structure provided in an embodiment of the present invention; Figure 2 for Figure 1 A magnified view of a section at point II; Figures 3 to 7 This is a schematic diagram of the process flow for the fabrication method of the deep trench isolation structure provided in an embodiment of the present invention.

[0019] Icons: 100 - Deep trench isolation structure; 110 - Substrate; 111 - First surface; 112 - Second surface; 113 - Isolation trench; 114 - Bottom silicon; 115 - Buried oxide layer; 116 - Top silicon; 117 - Linear oxide layer; 118 - Protective layer; 119 - Padding oxide layer; 130 - Buffer layer; 150 - Filling layer. Detailed Implementation

[0020] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. The components of the embodiments of the present invention described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0021] Therefore, the following detailed description of the embodiments of the invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the invention without inventive effort are within the scope of protection of the invention.

[0022] It should be noted that similar labels and letters in the following figures indicate similar items. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures.

[0023] In the description of this invention, it should be noted that if terms such as "upper," "lower," "inner," or "outer" are used to indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship in which the product of this invention is usually placed, they are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this invention.

[0024] Furthermore, the terms "first" and "second" are used only to distinguish descriptions and should not be interpreted as indicating or implying relative importance.

[0025] As disclosed in the background section, the inventors' research revealed that the causes of through-type surface cracks can be summarized in two aspects: Firstly, the thermal expansion coefficient of silicon (2.6 ppm / ℃) is significantly higher than that of SiO2 (0.5 ppm / ℃). This thermal mismatch between materials leads to a much larger shrinkage of the silicon substrate 110 than that of the filling medium (SiO2) during the annealing cooling stage. This induces significant lateral tensile stress within SiO2. When this stress exceeds the material's fracture strength, tearing occurs at the most vulnerable centerline of the structure, resulting in a crack. Secondly, the excessively rapid heating and cooling rates during annealing further exacerbate the concentration effect of thermal stress, promoting crack formation. These cracks not only become residual spaces for chemical reagents in subsequent wet processes but may also release active impurities under high temperature or electric field conditions, causing performance degradation phenomena such as device leakage and threshold drift. In severe cases, these cracks can even spread to the entire wafer, causing systemic contamination of the production line.

[0026] To address the crack problem, the current industry standard is to optimize the annealing process profile, mitigating stress accumulation by controlling the rate of temperature change or extending the process time. However, these methods struggle to completely suppress crack formation at the mechanistic level and may introduce new lattice defects due to increased high-temperature duration or lead to higher costs due to extended process time. Especially in trench structures with ever-increasing aspect ratios, the uniformity of coverage achieved by traditional annealing processes is limited, resulting in less than ideal repair outcomes.

[0027] To address the aforementioned problems, embodiments of the present invention provide a novel deep trench isolation structure 100 and a method for preparing the deep trench isolation structure 100. It should be noted that, unless otherwise specified, the features in the embodiments of the present invention can be combined with each other.

[0028] See Figure 1 and Figure 2 This invention provides a deep trench isolation structure 100 that can block the initiation and propagation of cracks, providing high reliability and long life insulation protection for the isolation structure.

[0029] The deep trench isolation structure 100 provided in this embodiment of the invention includes a substrate 110, a buffer layer 130, and a filling layer 150. The substrate 110 has a first surface 111 and a second surface 112 facing each other. An isolation trench 113 is formed on the first surface 111. The buffer layer 130 is disposed within the isolation trench 113 and covers the sidewalls and bottom wall of the isolation trench 113. The filling layer 150 fills the isolation trench 113 and contacts the buffer layer 130, thereby separating the filling layer 150 and the substrate 110. The coefficient of thermal expansion of the substrate 110 is greater than that of the filling layer 150. The buffer layer 130 is configured to expand in volume during annealing to compensate for the tensile stress caused by the cooling and shrinkage of the substrate 110.

[0030] It should be noted that the filler layer 150 completely fills the isolation trench 113, while the buffer layer 130 is embedded between the filler layer 150 and the substrate 110. Since the coefficient of thermal expansion of the substrate 110 is greater than that of the filler layer 150, the shrinkage of the substrate 110 during the annealing cooling stage is greater than that of the filler layer 150. This tends to induce lateral tensile stress within the filler layer 150, meaning that the cooling and shrinkage of the substrate 110 will cause tensile stress. However, this embodiment of the invention, through the additional design of the buffer layer 130, which is located between the filler layer 150 and the substrate 110, and can expand in volume during annealing, compensates for the tensile stress caused by the cooling and shrinkage of the substrate 110. This prevents the initiation and propagation of cracks, and also ensures that the substrate 110, the buffer layer 130, and the filler layer 150 are always tightly fitted, avoiding delamination of the materials and providing high reliability and long-life insulation protection for the isolation structure.

[0031] Furthermore, the buffer layer 130 comprises a YSZ thin film, the substrate 110 comprises silicon, and the filler layer 150 comprises silicon dioxide. The substrate 110 can be an SOI substrate 110, and the filler layer 150 is a silicon dioxide layer. Therefore, the deep trench isolation structure 100 provided in this embodiment of the invention can be a DTI-on-SOI structure (silicon-on-insulator deep trench isolation), thereby constructing the corresponding device. The coefficient of thermal expansion of silicon (2.6 ppm / ℃) is significantly higher than that of SiO2 (0.5 ppm / ℃). The buffer layer 130 comprises 1-5 mol% YSZ thin film, preferably 3 mol% YSZ thin film.

[0032] The 3 mol% YSZ thin film specifically refers to a 3 mol% yttrium oxide (Y₂O₃) stabilized zirconium oxide (ZrO₂) thin film, a thin film material that can be deposited using ALD (atomic layer deposition) and exhibits martensitic phase transformation and expansion when cooled to 800K. This material has applications in logic devices and gate engineering, memory devices, substrate 110 engineering and heterogeneous integration, microelectromechanical systems (MEMS), emerging devices, and cutting-edge research, and is commonly used as a gate dielectric layer, a dielectric layer for deep trench capacitors, and a resistive switching layer for memory devices. This material can be annealed in the same furnace as SiO₂, and contains only Zr / Y / O elements, thus being on the FAB whitelist and free from contamination. The compressive stress on adjacent films can be controlled by "volume expansion × film thickness," making the process controllable.

[0033] Furthermore, the 3 mol% YSZ film exhibits martensitic properties and can be annealed in the same furnace as SiO2. During film deposition at a relatively low temperature (200℃), the 3 mol% YSZ is primarily an amorphous phase. Due to the lower surface energy of the T phase compared to the M phase, the film contains nano-sized T phase nuclei. During heating, these nuclei gradually grow into T phase grains, accompanied by thermal expansion. During annealing, when the temperature drops to 800K, a martensitic phase transformation occurs, converting the T phase to the M phase and locking it in place. The transformation from tetragonal to monoclinic phase causes volume expansion at this point. Introducing the YSZ film into the isolation trench 113 utilizes the 3% volume expansion generated by the T→M phase transformation at 800K to compensate for the tensile stress caused by the cooling and shrinkage of silicon.

[0034] It should be noted that in this embodiment, atomic layer deposition (ALD) technology can be used to prepare a 3 mol% YSZ layer on the surface of the isolation trench 113, i.e., by doping 3 mol% yttrium oxide into zirconium oxide. Utilizing the excellent step coverage capability of ALD technology, perfect conformal deposition of the YSZ film on the sidewalls and bottom of the DTI can be achieved. More importantly, the martensitic phase transformation characteristics of YSZ material cause it to undergo approximately 3% volume expansion when the temperature drops to 800K. This characteristic can actively compensate for the tensile stress formed during cooling, thereby physically preventing the initiation and propagation of cracks, providing high reliability and long-life insulation protection for the DTI-on-SOI structure.

[0035] In some embodiments, the substrate 110 is an SOI substrate 110, including a bottom silicon 114, a buried oxide layer 115, and a top silicon 116. The buried oxide layer 115 is disposed on the bottom silicon 114, and the top silicon 116 is disposed on the buried oxide layer 115. A first surface 111 is located on the side of the top silicon 116 away from the bottom silicon 114. An isolation trench 113 passes through the top silicon 116 and exposes the buried oxide layer 115. Specifically, the isolation trench 113 penetrates from the top silicon 116 to the buried oxide layer 115, which can fully guarantee the isolation effect.

[0036] In some embodiments, the thickness of the buffer layer 130 is greater than or equal to 30 nm. Preferably, the buffer layer 130 can be 30 nm or 40 nm. The compressive stress on adjacent films can be controlled by "volume expansion × film thickness".

[0037] In some embodiments, a linear oxide layer 117 is further formed on the sidewalls and bottom wall of the isolation trench 113, and a buffer layer 130 is formed on the surface of the linear oxide layer 117. Specifically, the linear oxide layer 117 can repair the damage to the silicon material caused by etching to form the isolation trench 113, that is, it can repair the sidewalls and bottom wall of the isolation trench 113.

[0038] This invention also provides a method for preparing a deep trench isolation structure 100, which includes the following steps: S1: Provide a substrate 110.

[0039] See also Figure 3 The substrate 110 has a first surface 111 and a second surface 112. Specifically, the substrate 110 may be an SOI substrate 110, including a bottom silicon 114, a buried oxide layer 115 and a top silicon 116. The buried oxide layer 115 is disposed on the bottom silicon 114, the top silicon 116 is disposed on the buried oxide layer 115, the first surface 111 is located on the side of the top silicon 116 away from the bottom silicon 114, and an isolation trench 113 passes through the top silicon 116 and exposes the buried oxide layer 115.

[0040] S2: An isolation trench 113 is formed on the first surface 111.

[0041] See also Figure 4 Specifically, firstly, a pad oxide layer 119 and a Si3N4 protective layer 118 are sequentially deposited on the first surface 111, and a window is opened on the Si3N4 to expose the predetermined area of ​​the isolation trench 113. Then, plasma etching (such as Cl2 / HBr mixed gas) is used to etch away the area that needs to be formed into deep trench isolation in the top silicon 116. The etching stops when the buried oxide layer 115 is reached, thereby exposing the buried oxide layer 115 to the isolation trench 113.

[0042] S3: A buffer layer 130 is deposited on the sidewalls and bottomwalls of the isolation trench 113 to form a buffer layer 130.

[0043] See also Figure 5 Specifically, a linear oxide layer 117 can first be grown on the sidewalls and bottom wall of the isolation trench 113, and then a buffer layer 130 can be deposited at least on the surface of the linear oxide layer 117 using atomic deposition (ALD). Utilizing the excellent step coverage capability of ALD technology, perfect conformal deposition of the YSZ film on the sidewalls and bottom of the DTI can be achieved. Furthermore, the YSZ film will also cover the surface of Si3N4 during deposition.

[0044] In actual fabrication, a linear oxide layer 117 can be grown first in a furnace tube to repair damage to the silicon substrate 110 caused during etching. Then, atomic deposition is used with Zr(NMe2)4 and Y(NMe2)3 as metal sources and H2O as the oxygen source, alternating pulses at 200°C to obtain a 3 mol% YSZ film on the surface of the linear oxide layer 117. Preferably, Zr(NMe2)4 and Y(NMe2)3 are used as metal sources, H2O as the oxygen source, alternating pulses are applied at 200°C, with 15 ZrO2 sub-cycles followed by one Y2O3 sub-cycle, for a total of 250 supercycles, to obtain a 30 nm 3 mol% Y2O3 stabilized zirconia ZrO2 film (YSZ).

[0045] S4: Deposit a filling layer 150 in the isolation trench 113.

[0046] See Figure 6Specifically, LPTEOS (Low Pressure Tetraethyl Orthosilicate) can be deposited in the furnace tube. For example, in a chemical vapor deposition process, TEOS vapor is introduced into the reaction chamber and undergoes a thermal decomposition reaction under high temperature (typically about 700°C) and low pressure conditions to deposit a SiO2 film on the surface of the linear oxide layer 117. This film has good shape retention and filling ability and can uniformly cover the isolation trench 113.

[0047] S5: Grind and flatten the filler layer 150.

[0048] See Figure 7 Specifically, LPTEOS is ground onto the YSZ plane on Si3N4 using chemical mechanical polishing (CMP) to complete the planarization of the filler layer 150.

[0049] S5: Annealing repairs damage.

[0050] High-temperature rapid annealing can be used to repair damage and densify oxides. The thermal expansion coefficient of the substrate 110 is greater than that of the filler layer 150, and the buffer layer 130 is configured to expand in volume during annealing to compensate for the tensile stress caused by the cooling and shrinkage of the substrate 110, thereby solving the problem of cracks easily occurring in this step in conventional techniques.

[0051] S6: Partially etch the filling layer 150 so that the filling layer 150 is flush with the first surface 111.

[0052] Please continue reading Figure 1 Specifically, the fill layer 150 can be etched back to ensure that the top of the isolation trench 113 is flush with the surface of the top silicon layer 116. Finally, excess thin film materials such as YSZ and Si3N4 on the surface of the non-isolation trench 113 area are removed by wet etching.

[0053] In summary, the deep trench isolation structure 100 and its preparation method provided in the embodiments of the present invention have an isolation trench 113 formed on the first surface 111 of the substrate 110, a buffer layer 130 covering the sidewalls and bottom wall of the isolation trench 113, and a filling layer 150 filling the isolation trench 113 and contacting the buffer layer 130, thereby enabling the buffer layer 130 to separate the filling layer 150 and the substrate 110. The thermal expansion coefficient of the substrate 110 is greater than that of the filling layer 150, and the buffer layer 130 is configured to expand in volume during annealing to compensate for the tensile stress caused by the substrate 110.

[0054] Compared to existing technologies, the deep trench isolation structure 100 and its fabrication method provided in this invention utilize a buffer layer 130 to separate the filling layer 150 and the substrate 110. The buffer layer 130 expands in volume during annealing, thereby compensating for the tensile stress caused by the cooling and shrinkage of the substrate 110. This prevents the initiation and propagation of cracks and avoids delamination of the materials, providing high reliability and long-life insulation for the isolation structure. Based on the principle of mechanical equilibrium, it actively applies compensating stress rather than passively repairing, fundamentally eliminating the root cause of through-cracks in the SiO2 filling layer 150. Furthermore, it only introduces one thin film compatible with SiO2 annealing in the same furnace, without changing the original process baseline, requiring no additional pattern design, and without increasing the photomask in the layout design. The process is simple and highly compatible.

[0055] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A deep trench isolation structure, comprising: include: A substrate having opposing first and second surfaces, wherein the first surface is provided with isolation trenches; A buffer layer covering the sidewalls and bottom wall of the isolation trench; A filler layer that fills the isolation trench and contacts the buffer layer to separate the filler layer and the substrate; During annealing, the buffer layer is configured to expand in volume to compensate for the tensile stress caused by the substrate.

2. The deep trench isolation structure of claim 1, wherein, The buffer layer comprises a YSZ thin film, the substrate comprises silicon, and the filler layer comprises silicon dioxide.

3. The deep trench isolation structure of claim 1 or 2, wherein, The substrate includes a bottom silicon layer, a buried oxide layer, and a top silicon layer. The buried oxide layer is disposed on the bottom silicon layer, and the top silicon layer is disposed on the buried oxide layer. The first surface is located on the side of the top silicon layer away from the bottom silicon layer, and the isolation trench passes through the top silicon layer and exposes the buried oxide layer.

4. The deep trench isolation structure of claim 1 or 2, wherein, The thickness of the buffer layer is greater than or equal to 30 nm.

5. The deep trench isolation structure of claim 1 or 2, wherein, The sidewalls and bottomwalls of the isolation trench are also formed with a linear oxide layer, and the buffer layer is formed on the surface of the linear oxide layer.

6. A method for producing a deep trench isolation structure according to claim 1, characterized by, The method includes: A substrate is provided, wherein the substrate has opposing first and second surfaces; An isolation trench is formed on the first surface; A buffer layer is deposited on the sidewalls and bottom wall of the isolation trench to form a buffer layer; A filling layer is deposited in the isolation trench; Annealing repairs damage; During annealing, the buffer layer is configured to expand in volume to compensate for the tensile stress caused by the cooling and shrinkage of the substrate.

7. The method of claim 6, wherein the method further comprises: The step of depositing a buffer layer on the sidewalls and bottom wall of the isolation trench includes: A linear oxide layer is grown on the sidewalls and bottom wall of the isolation trench; A buffer layer is formed by depositing at least one layer on the surface of the linear oxide layer using atomic deposition.

8. The method of claim 7, wherein the method further comprises: The step of depositing a buffer layer at least on the surface of the linear oxide layer using atomic deposition includes: Atomic deposition was used, with Zr(NMe2)4 and Y(NMe2)3 as metal sources and H2O as oxygen source, and alternating pulses were applied at 200°C to obtain a YSZ thin film at least on the surface of the linear oxide layer.

9. The method of claim 6, wherein the method further comprises: Prior to the annealing repair step, the method further includes: The filling layer is ground and planarized.

10. The method for preparing the deep trench isolation structure according to claim 6, characterized in that, Following the annealing repair step, the method further includes: The filler layer is partially etched so that it is flush with the first surface.

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