Semiconductor device and method of manufacturing the same

Abstract

This disclosure relates to semiconductor devices and methods for manufacturing the same. One method includes forming a semiconductor device on a substrate and forming an interconnect structure on the semiconductor device. The interconnect structure includes a metal plug comprising a first metal disposed in a first dielectric layer. A second dielectric layer is formed on the first dielectric layer. The second dielectric layer has an opening exposing the metal plug. A nitriding process is performed on the metal plug to form a nitrided layer on the metal plug.

Description

Technical Field

[0001] This disclosure relates to semiconductor devices and methods for manufacturing the same. Background Technology

[0002] As consumer devices become smaller and more powerful to meet consumer demands, the size of their components inevitably shrinks. The semiconductor devices that make up the main components of consumer devices such as smartphones and tablets are becoming increasingly smaller. This reduction in semiconductor device size is accompanied by advancements in semiconductor manufacturing technology, such as the formation of connections between semiconductor devices. As device size decreases, resistance increases in smaller connections, leading to a corresponding increase in heat generation within the device circuitry. Lower resistance connections are desirable in smaller devices. Lower resistance means less energy is lost as heat when current flows through the circuit, resulting in more efficient operation. Summary of the Invention

[0003] According to one aspect of this disclosure, a method is provided, comprising: forming a semiconductor device on a substrate; forming an interconnect structure on the semiconductor device, wherein the interconnect structure includes a metal plug, the metal plug including a first metal disposed in a first dielectric layer; forming a second dielectric layer on the first dielectric layer, the second dielectric layer having an opening for exposing the metal plug; and performing a nitriding process on the metal plug to form a nitriding layer on the metal plug.

[0004] According to another aspect of this disclosure, a method of manufacturing a semiconductor device is provided, comprising: forming at least one transistor on a substrate, the at least one transistor including at least one channel region, at least one gate dielectric layer, at least one gate electrode layer, and at least one source / drain region, wherein the at least one gate dielectric layer has a first dielectric constant k1; forming a first dielectric layer having a second dielectric constant k2 on the at least one transistor, wherein k1 > k2; forming a via in the first dielectric layer; forming a metal plug including a first metal in the via; performing a nitriding process on the metal plug; and forming a conductive contact electrically connected to the metal plug on the metal plug.

[0005] According to another aspect of this disclosure, a structure is provided, comprising: a semiconductor device disposed on a substrate; a metal plug disposed in a first dielectric layer above the semiconductor device, wherein the metal plug includes an inner layer and an outer layer, the inner layer including a first metal and the outer layer including a nitride of the first metal; an etch stop layer disposed above the first dielectric layer; and a second dielectric layer having an opening disposed above the first dielectric layer, wherein the opening is filled with a barrier layer and a fill layer embedded in the barrier layer, the fill layer including a material different from the barrier layer, and the etch stop layer being thinner than the first dielectric layer or the second dielectric layer. Attached Figure Description

[0006] This disclosure is best understood when read in conjunction with the accompanying drawings in the following detailed description. It should be emphasized that, in accordance with industry standard practice, the various features are not drawn to scale and are for illustrative purposes only. In fact, the dimensions of the various features may be arbitrarily increased or decreased for clarity of discussion.

[0007] Figure 1A and Figure 1B A semiconductor device according to an embodiment of the present disclosure is shown.

[0008] Figure 2 , Figure 3 , Figure 4 , Figure 5 , Figure 6 , Figure 7A , Figure 7B , Figure 8 , Figure 9 , Figure 10 and Figure 11 Cross-sectional views of various stages of a method for manufacturing a semiconductor device according to embodiments of the present disclosure are shown.

[0009] Figure 12 , Figure 13 , Figure 14 , Figure 15 , Figure 16A , Figure 16B , Figure 17A and Figure 17B Cross-sectional views of various stages of a method for manufacturing a semiconductor device according to embodiments of the present disclosure are shown.

[0010] Figure 18A A cross-sectional view of one stage of a method for manufacturing a semiconductor device according to an embodiment of the present disclosure is shown. Figure 18B and Figure 18C yes Figure 18A A detailed view of a portion of the content.

[0011] Figure 19 , Figure 20 , Figure 21 and Figure 22 Cross-sectional views of various stages of a method for manufacturing a semiconductor device according to embodiments of the present disclosure are shown.

[0012] Figure 23 and Figure 24 A semiconductor device according to an embodiment of the present disclosure is shown.

[0013] Figure 25 A flowchart of a method according to an embodiment of the present disclosure is shown.

[0014] Figure 26A flowchart illustrating a method for manufacturing a semiconductor device according to an embodiment of the present disclosure is shown.

[0015] Figure 27 A flowchart illustrating a method for manufacturing a semiconductor device according to an embodiment of the present disclosure is shown. Detailed Implementation

[0016] It will be understood that the following disclosure provides many different embodiments or examples for implementing various features of this disclosure. Specific embodiments or examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and not intended to be limiting. For example, the dimensions of elements are not limited to the disclosed range or values, but may depend on the device's process conditions and / or desired characteristics. Furthermore, in the following description, forming a first feature on or over a second feature can include embodiments where the first and second features are formed in direct contact, and may also include embodiments where an additional feature can be formed between the first and second features such that the first and second features do not need to be in direct contact. For simplicity and clarity, various features may be drawn arbitrarily at different scales.

[0017] Furthermore, for ease of description, spatially related terms such as “below,” “under,” “lower,” “above,” and “upper” may be used herein to describe the relationship between one element or feature shown in the figures and another element(s) or feature(s). These spatially related terms are intended to cover different orientations of the device in use or operation other than those depicted in the figures. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially related descriptors used herein may be interpreted accordingly. Additionally, the term “made of” may mean “comprising” or “consisting of.”

[0018] Furthermore, in the following manufacturing processes, one or more additional operations may exist between the described operations, and the order of operations may be changed. In this disclosure, the phrase "one of A, B, and C" means "A, B, and / or C" (A, B, C, A and B, A and C, B and C, or A, B, and C), and does not mean an element from A, an element from B, and an element from C, unless otherwise stated. Throughout the disclosure, source and drain are used interchangeably, and source / drain refers to one or both of the source and drain. One or more source / drain structures may individually or collectively refer to the source or drain, depending on the context. In the following embodiments, the materials, configurations, dimensions, processes, and / or operations described with respect to one embodiment (e.g., one or more figures) may be used in other embodiments, and their detailed description may be omitted.

[0019] The disclosed embodiments relate to a semiconductor device, specifically to a semiconductor device having low resistance and low leakage conductivity lines or wiring, and a method for manufacturing the same.

[0020] As semiconductor devices shrink in size, the space for electrical connections between front-end (FEOL) devices and back-end (BEOL) wiring layers decreases, increasing the contact resistance of these connections. In embodiments of this disclosure, low-resistance connections are provided that do not suffer from increased leakage current. Therefore, embodiments of this disclosure provide semiconductor devices that can operate at higher power and higher efficiency.

[0021] Embodiments of this disclosure relate to metal plug nitriding controlled by BEOL nitrogen impurity doping. Embodiments include: 1) directly applying nitrogen to the metal plug, such as by immersion in NH3, and 2) indirect metal nitride nitrogen transfer via an annealing operation. In some embodiments, the annealing is performed in an environment containing hydrogen. In embodiments of this disclosure, nitriding reduces leakage from the BEOL Cu trench to the mid-stage process (MEOL). Embodiments of this disclosure provide low contact resistance at the advanced node BEOL / MEOL interface, as well as low current and Cu... + leakage.

[0022] Figure 1A The diagram illustrates a semiconductor device structure according to an embodiment of the present disclosure. The structure includes a first dielectric layer 30, in which first conductive metal contacts or plugs 35, 40 are disposed, formed on one or more semiconductor devices or integrated circuit components 15 (e.g., transistors) disposed on a device region 20 disposed on a substrate 10. The conductive metal contacts or plugs include an inner metal layer 35 and an outer metal nitride layer 40. In some embodiments, the outer metal nitride layer 40 is a nitride of the metal constituting the inner metal layer 35. A second dielectric layer 50 is disposed on the first dielectric layer and the metal contacts or plugs 35, 40. Another contact 55, 60 is disposed in the second dielectric layer 50. In some embodiments, the first metal contacts or plugs 35, 40 are mid-process online (MEOL) contacts, and the second metal contacts or plugs 55, 60 are bottom-up online (BEOL) contacts.

[0023] Semiconductor device assembly 15 includes interconnect structures comprising multiple interconnect pattern (line) layers having conductive patterns and interconnecting various features in one portion of the die to other features of the die. In various embodiments, the interconnect structures are formed of a conductive material such as metal, and the semiconductor device includes several interconnect layers. Interconnect layers are commonly referred to as “Metal 0” or “M0” (representing the lowest interconnect level), “M1”, “M2”, and so on. These names are used in the art to denote features originating from various locations within the semiconductor device via conductive line interconnects. In some embodiments, metal interconnects connect transistor arrays to other arrays or other features.

[0024] Interconnect layer patterns in different layers are also coupled to each other vias extending vertically between one or more interconnect layers. In some embodiments, interconnect layer patterns are coupled to external features and can represent bit lines, signal lines, word lines, and various input / output connections.

[0025] Examples of devices that may benefit from one or more embodiments of this disclosure are semiconductor devices. For example, such devices may include static random access memory (SRAM) and / or other logic circuitry, passive elements (e.g., resistors, capacitors, and inductors), and active elements such as P-channel field-effect transistors (PFETs), N-channel FETs (NFETs), metal-oxide-semiconductor field-effect transistors (MOSFETs), complementary metal-oxide-semiconductor (CMOS) transistors (e.g., FinFETs and gate-all-around field-effect transistors (GAA FETs)), bipolar transistors, high-voltage transistors, high-frequency transistors, other memory cells, and combinations thereof. Semiconductor devices may include multiple semiconductor devices (e.g., transistors) that can be interconnected. In some embodiments, semiconductor device components are electrically coupled through underlying interconnect layers, which include wiring layers and vias formed in dielectric layers (e.g., interlayer dielectric (ILD) layers or intermetallic dielectric (IMD) layers). The wiring layers and vias of the interconnect layers may be formed of copper or copper alloys (e.g., AlCu), aluminum, tungsten, nickel, or any other suitable metal. However, it should be understood that, unless specifically required, this application should not be limited to a particular type of device.

[0026] In some embodiments, substrate 10 includes at least a single-crystal semiconductor layer on its surface portion. Substrate 10 may include single-crystal semiconductor materials, such as, but not limited to, Si, Ge, SiGe, GaAs, InSb, GaP, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb, and InP. Substrate 10 may include various regions that have been suitably doped with impurities (e.g., p-type or n-type conductivity). In some embodiments, dopants are, for example, boron difluoride (BF2) for n-type FinFETs and phosphorus for p-type FinFETs. In some embodiments, substrate 10 is made of crystalline Si.

[0027] Substrate 10 may include one or more buffer layers (not shown) in its surface region. The buffer layers can be used to gradually change the lattice constant from that of the substrate to the lattice constant of the source / drain structure. The buffer layers may be formed from epitaxially grown single-crystal semiconductor materials, such as, but not limited to, Si, Ge, GeSn, SiGe, GaAs, InSb, GaP, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb, GaN, and InP. In a particular embodiment, substrate 10 includes a silicon-germanium (SiGe) buffer layer epitaxially grown on silicon substrate 10. The germanium concentration of the SiGe buffer layer can increase from 30 atomic% germanium in the bottom buffer layer to 70 atomic% germanium in the top buffer layer.

[0028] In some embodiments, the semiconductor device 15 in the semiconductor device assembly region 20 includes a transistor, such as... Figure 1B The gate all-around field-effect transistor (GAA-FET) shown is an example, but the semiconductor device 15 disclosed herein is not limited to transistors or GAA-FETs. Figure 1B The structure includes a transistor 15 disposed on top of the transistor. Figure 1A Structure A. For example... Figure 1B As shown, structure 115 includes a first device portion 160a formed in a series of front-end process (FEOL) processes, a second device portion 160b formed in a series of middle-end process (MEOL) processes, and a third device portion 160c formed in a series of back-end process (BEOL) processes.

[0029] The first device portion 160a is configured as a GAA FET and includes a plurality of semiconductor layers 130 stacked along the Z direction and configured as a stacked channel region 130. Although Figure 1BThree stacked channel regions 130 are shown, but this disclosure is not limited thereto, and various other embodiments include different numbers of channel regions such that the number of channel regions 130 is ≥1. This embodiment including the GAA FET is provided by way of example only, and various other semiconductor devices (e.g., planar field-effect transistors (FETs), FinFETs, complementary field-effect transistors (CFETs), etc.) are provided in other embodiments.

[0030] The first device portion 160a also includes a gate structure surrounding each stacked channel region 130. The gate structure includes a conductive gate electrode layer 125 separated from the stacked channel region 130 by a gate dielectric layer 120. The first device portion 160a also includes source / drain regions 140 formed along the X direction at opposite ends of the stacked channel regions 130, and a plurality of dielectric internal spacers 135 electrically isolating the gate structure from the source / drain regions. The source / drain regions may refer to either source regions or drain regions. A first interlayer dielectric (ILD) layer 150 having a dielectric constant k3 is formed over the source / drain regions 140. A contact plug 155 is formed in the first ILD layer 150. The contact plug 155 forms a conductive contact with the source / drain regions 140. In some embodiments, a silicide layer 145 is disposed between the contact plug 155 and the source / drain regions 140. The silicide layer 145 has a higher conductivity than the source / drain region 140, and the contact plug 155 has a higher conductivity than the source / drain region 140. The contact plug is electrically connected to the through-hole contact or plugs 35, 40 in structure A.

[0031] In some embodiments, the gate dielectric layer 120 is made of a different material than the etch stop layers 25, 45, 65 and the dielectric layers 150, 30, 50, 70. In some embodiments, the etch stop layers 25, 45, 65 are made of a different material than the dielectric layers 150, 30, 50, 70. In some embodiments, at least one of the etch stop layers 25, 45, 65 is thinner than at least one of the dielectric layers 150, 30, 50, 70. In some embodiments, at least one of the etch stop layers 25, 45, 65 is thinner than any one of the dielectric layers 150, 30, 50, 70. In some embodiments, the dielectric constant of the gate dielectric layer 120 is greater than the dielectric constant of any of the etch stop layers 25, 45, 65 and any of the dielectric layers 150, 30, 50, 70.

[0032] Figures 2 to 11 This is a schematic diagram illustrating the various stages of manufacturing a semiconductor device according to embodiments of the present disclosure. To simplify this disclosure, Figures 3 to 11 The semiconductor device component region 20 and the substrate are not shown. It should be understood that, for additional embodiments of the method, [further details may be needed]. Figures 2 to 11 Additional operations are provided before, during, and after the process shown, and some of these operations can be substituted or eliminated. The order of operations / processes can be interchanged.

[0033] like Figure 2 As shown, a first etch stop layer 25 is formed over a semiconductor device assembly region 20, and a first dielectric layer 30 is formed over the etch stop layer 25. In some embodiments, the etch stop layer 25 is made of a nitride, such as silicon nitride, titanium nitride, or tantalum nitride. The etch stop layer 25 can be formed by atomic layer deposition (ALD), physical vapor deposition (PVD), chemical vapor deposition (CVD), electron beam evaporation, or any other suitable technique. In some embodiments, the thickness of the etch stop layer ranges from about 5 nm to about 40 nm, and in other embodiments from about 10 nm to about 20 nm. In some embodiments, the first dielectric layer 30 is made of silicon oxide, silicon nitride, silicon oxynitride (SiON), SiOCN, SiCN, fluorine-doped silicate glass (FSG), or a low-k dielectric material, and is formed by low-pressure CVD (LPCVD), plasma-enhanced CVD (PECVD), PVD, ALD, flowable CVD, or any suitable technique. In some embodiments, the etch stop layer 25 and the first dielectric layer 30 are made of different materials.

[0034] like Figure 3 As shown, the dielectric layer 30 and etch stop layer 25 are then etched to form an opening or via 80. In some embodiments, patterning is performed by photolithography and etching operations. In some embodiments, a photoresist layer is formed over the first dielectric layer 30. The photoresist layer is selectively exposed to photochemical radiation, and then the selectively exposed photoresist layer is developed to form a pattern corresponding to the via pattern to be formed. Using the patterned photoresist layer as a mask, the dielectric layer 30 and etch stop layer 25 are etched using a suitable etchant to form the via 80. The remaining photoresist layer is then removed using a suitable stripping or plasma ashing operation.

[0035] Etching can be performed using wet or dry etching techniques. In some embodiments, plasma etching is used to form the via 80. Different etching gases can be used to etch different layers. For example, in some embodiments, fluorocarbon gases (e.g., CF4, CHF3, or C4F8) or SF6 are used to etch the first dielectric layer 30; and fluorine-based gases (e.g., NF3, CF4, or SF6) or chlorine-based gases (e.g., Cl2, HCl, or CCl4) are used to etch the etch stop layer 25.

[0036] Metal is then deposited in the opening or via 80 to form a via contact or plug 35, such as Figure 4 As shown. In some embodiments, metal is deposited on top of the first dielectric layer 30, and excess metal covering the top of the first dielectric layer 30 is removed by an etch-back operation or by a chemical mechanical polishing (CMP) operation. The metal can be deposited by ALD, PVD, CVD, electron beam evaporation, electroplating, electroless plating, or any other suitable technique. In some embodiments, the metal includes at least one of Mo, W, Ru, Al, Au, Ag, Cu, Mn, Ni, Fe, Pt, Ta, Nb, Zr, Re, or Ir. In one embodiment, the metal is Mo, and in another embodiment, the metal is W. Mo has a lower resistivity than W, and Mo is less expensive than other metals such as Ru.

[0037] Next, as Figure 5 As shown, a second etch stop layer 45 is formed over the via contact or plug 35, and a second dielectric layer 50 is formed over the second etch stop layer 45. In some embodiments, the second etch stop layer 45 is made of a nitride, such as silicon nitride, titanium nitride, or tantalum nitride. The etch stop layer 45 can be formed by ALD, PVD, CVD, electron beam evaporation, or any other suitable technique. In some embodiments, the thickness of the etch stop layer ranges from about 5 nm to about 40 nm, and in other embodiments from about 10 nm to about 20 nm. In some embodiments, the second dielectric layer 50 is made of silicon oxide, silicon nitride, SiON, SiOCN, SiCN, fluorine-doped silicate glass (FSG), or a low-k dielectric material, and is formed by LPCVD, PECVD, PVD, ALD, flowable CVD, or any suitable technique. In some embodiments, the second dielectric layer 50 is made of a low-k dielectric material, such as fluorine-doped silicon dioxide, organosilicon glass (or carbon-doped oxide), porous silica, silsesquioxane, or spin-coated polymer dielectric material. In some embodiments, the second etch stop layer 45 and the second dielectric layer 50 are made of different materials.

[0038] like Figure 6 As shown, the second dielectric layer 50 and the second etch stop layer 45 are then etched to form a via or trench 85. In some embodiments, patterning is performed by photolithography and etching operations. In some embodiments, a photoresist layer is formed over the second dielectric layer 50. The photoresist layer is selectively exposed to photochemical radiation, and then the selectively exposed photoresist layer is developed to form a pattern corresponding to the via pattern to be formed. Using the patterned photoresist layer as a mask, the dielectric layer 50 and the etch stop layer 45 are etched using a suitable etchant to form the via or trench 85. The remaining photoresist layer is then removed using a suitable stripping or plasma ashing operation.

[0039] Etching can be performed using wet or dry etching techniques. In some embodiments, plasma etching is used to form vias or trenches 85. Different etching gases can be used to etch different layers. For example, in some embodiments, fluorocarbon gases (e.g., CF4, CHF3, or C4F8) or SF6 are used to etch the second dielectric layer 50; and fluorine-based gases (e.g., NF3, CF4, or SF6) or chlorine-based gases (e.g., Cl2, HCl, or CCl4) are used to etch the etch stop layer 45.

[0040] In some embodiments, such as Figure 7A As shown, nitriding of the metal via contact or plug 35 is then performed. In some embodiments, the nitriding operation includes applying a nitrogen-containing gas 90 to the via contact or plug 35 to form a metal nitride layer 40. In some embodiments, the nitrogen-containing gas 90 is NH3. In some embodiments, the structure is heated while the nitrogen-containing gas 90 is applied. In some embodiments, the structure is heated at a temperature ranging from about 300°C to about 500°C during the nitriding operation; in other embodiments, nitriding is performed at a temperature greater than about 350°C; and in still other embodiments, nitriding is performed at a temperature ranging from about 350°C to about 450°C. In some embodiments, the nitriding process is performed in a vacuum chamber at an internal pressure of about 0.1 Torr to about 100 Torr; in other embodiments, it is performed at a pressure of about 1 Torr to about 50 Torr; and in still other embodiments, it is performed at a pressure of about 5 Torr to about 10 Torr. In some embodiments, the duration of the nitriding process ranges from about 10 seconds to about 60 minutes; and in other embodiments, it ranges from about 1 minute to about 10 minutes. In some embodiments, nitriding of the via or plug 35 forms a nitriding layer 40 in the via or plug, the nitriding layer 40 extending to a depth T1 ranging from about 1 nm to about 12 nm, and in other embodiments from about 2 nm to about 6 nm. In some embodiments, the thickness T2 of the metal via contact or plug 35 ranges from about 60 nm to about 120 nm, and in other embodiments from about 30 nm to about 60 nm.

[0041] At nitriding parameters outside the scope of disclosure, the formation of metal nitrides may be insufficient, the resistivity of metal via contacts or plugs may increase excessively, current leakage may increase, or copper diffusion from overlay copper wiring to metal via contacts or plugs may increase.

[0042] like Figure 7B As shown, in some embodiments, during the nitriding process, a nitrogen-containing gas (e.g., ammonia) reacts with the native oxide layer 35a on the surface of the metal, converting the metal oxide into a metal nitride. In some embodiments, the nitrogen-containing gas also reacts with the metal. For example, in some embodiments, the following reaction occurs: 2Mo + 2NH3 → 2MoN + 3H2, MoO3 + 2NH3 → MoN + 3H2O, 4Mo + 2NH3 → 2Mo2N + 3H2, and 8MoO3 + 4NH3 → 4Mo2N + 6H2O + 9O2.

[0043] In some embodiments, all of the native oxides on the exposed upper surface of the metal plug are converted to metal nitrides, and some elemental metal is converted to metal nitrides. In some embodiments, the converted metal nitride layer is thicker than the native metal oxide layer. In some embodiments, when the metal is molybdenum, most of the metal nitride formed is Mo2N.

[0044] After the nitridation process, a conductive barrier layer 55 and a metal fill layer 60 are formed in the via or trench 85. As Figure 8 shown, in some embodiments, the conductive barrier layer 55 and the metal fill layer 60 extend above the top surface of the second dielectric layer 50. In some embodiments, the conductive barrier layer 55 includes at least one of tantalum, tantalum nitride, titanium, titanium nitride, tungsten, tungsten nitride, niobium, niobium nitride, zirconium, zirconium nitride, ruthenium, or nickel. In some embodiments, the fill layer 60 includes at least one of copper, aluminum, tungsten, molybdenum, or an alloy thereof. The conductive barrier layer 55 and the fill layer 60 can be formed by ALD, PVD, CVD, electron beam evaporation, electroplating, electroless plating, or any other suitable technique.

[0045] In some embodiments, the metal plug 35 is made of Mo. Although the resistivity of Mo2N (about 10 2 ±1 µohm-cm) is higher than that of Mo (about 10 1 ±0.1), the resistivity of Mo2N is lower than that of MoO2 (about 10 4 ±10 µohm-cm). At lower dielectric constant (k) values, current leakage is less likely to occur. The dielectric constant of Mo2N is 10 < k < 20, while the k of MoO2 is greater than 20. In addition, Mo2N provides an improved Cu diffusion barrier. For example, for Mo, Cu + leakage is observed at temperatures below 800°C, and for MoO2, Cu + leakage is observed at temperatures below 600°C, while in some embodiments, for Mo2N, Cu + leakage is suppressed up to about 1000°C.

[0046] In some embodiments, as Figure 9 shown, the excess barrier layer and fill layer material covering the top of the second dielectric layer 50 are removed by an etch back operation or by a CMP operation.

[0047] In some embodiments, a capping layer 75 is subsequently formed over the conductive barrier layer 55 and the filler layer 60, such as Figure 10 As shown. In some embodiments, the capping layer 75 is formed only on the conductive barrier layer 55 and the filler layer 60. In some embodiments, the capping layer 75 does not extend over the second dielectric layer 50. In some embodiments, a mask is formed on the structure using photolithographic patterning techniques prior to depositing the capping layer. In some embodiments, the capping layer 75 is made of at least one of tantalum, tungsten, cobalt, titanium, molybdenum, tantalum nitride, tungsten nitride, cobalt nitride, titanium nitride, or molybdenum nitride. In some embodiments, the capping layer 75 is made of cobalt or molybdenum. The capping layer 75 can be formed by ALD, PVD, CVD, electron beam evaporation, electroplating, electroless plating, or any other suitable technique. In some embodiments, the thickness of the capping layer 75 is from about 1 nm to about 10 nm, and in other embodiments it is from about 2 nm to about 5 nm.

[0048] like Figure 11 As shown, a third etch stop layer 65 is formed over the second dielectric layer 50 and / or the cap layer 75. A third dielectric layer 70 is formed over the third etch stop layer 65. In some embodiments, the third etch stop layer 65 is made of a nitride, such as silicon nitride, titanium nitride, or tantalum nitride. The third etch stop layer 65 can be formed by atomic layer evaporation (ALD), PVD, CVD, electron beam evaporation, or any other suitable technique. In some embodiments, the thickness of the third etch stop layer ranges from about 5 nm to about 40 nm, and in other embodiments from about 10 nm to about 20 nm. In some embodiments, the third dielectric layer 70 is made of silicon oxide, silicon nitride, SiON, SiOCN, SiCN, fluorine-doped silicate glass (FSG), or a low-k dielectric material, and is formed by LPCVD, PECVD, PVD, ALD, flowable CVD, or any suitable technique. In some embodiments, the third dielectric layer 70 is made of a low-k dielectric material, such as fluorine-doped silica, organosilicon glass (or carbon-doped oxide), porous silica, silsesquioxane, or spin-coated polymer dielectric material. In some embodiments, the third etch stop layer 65 and the third dielectric layer 70 are made of different materials. In some embodiments, the first etch stop layer 25, the second etch stop layer 45, and the third etch stop layer 65 are made of the same material; in other embodiments, the first etch stop layer 25 and the second etch stop layer 45, the first etch stop layer 25 and the third etch stop layer 65, or the second etch stop layer 45 and the third etch stop layer 65 are made of the same material. In some embodiments, the second dielectric layer 50 and the third dielectric layer 70 are made of the same material. In some embodiments, the first dielectric layer 30 is made of a different material than the second dielectric layer 50 and the third dielectric layer 70.

[0049] Figures 12 to 17B Cross-sectional views of various stages of a method for manufacturing a semiconductor device according to embodiments of the present disclosure are shown. It should be understood that, for additional embodiments of the method, [further details may be needed]. Figures 12 to 17B Additional operations are provided before, during, and after the process shown, and some of these operations can be substituted or eliminated. The order of operations / processes can be interchanged.

[0050] According to the references in this article Figures 2 to 6 The disclosed operation then forms a conductive barrier layer 55 and a metal filler layer 60 to form... Figure 12 The structure is as follows. In some embodiments, the conductive barrier layer 55 comprises at least one selected from tantalum, tantalum nitride, titanium, titanium nitride, tungsten, tungsten nitride, niobium, niobium nitride, zirconium, zirconium nitride, ruthenium, or nickel. In some embodiments, the filler layer 60 comprises at least one selected from copper, aluminum, tungsten, molybdenum, or alloys thereof. The conductive barrier layer 55 can be formed by ALD, PVD, CVD, or electron beam evaporation, or any other suitable technique. The filler layer 60 can be formed by ALD, PVD, CVD, electron beam evaporation, electroplating, electroless plating, or any other suitable technique.

[0051] Then, referencing this article Figure 9 The disclosed method removes excess barrier layer material and metal filler layer material, providing a structure with a flat upper surface, such as... Figure 13 As shown.

[0052] In some embodiments, a capping layer 75 is subsequently formed over the conductive barrier layer 55 and the filler layer 60, such as Figure 14 As shown. In some embodiments, the capping layer 75 is formed only on the conductive barrier layer 55 and the filler layer 60. In some embodiments, the capping layer 75 does not extend over the second dielectric layer 50. In some embodiments, a mask is formed on the structure using photolithographic patterning techniques prior to depositing the capping layer. In some embodiments, the capping layer 75 is made of at least one of tantalum nitride, tungsten nitride, cobalt nitride, titanium nitride, or molybdenum nitride. In some embodiments, the capping layer 75 is made of cobalt nitride or molybdenum nitride. The capping layer 75 can be formed by ALD, PVD, CVD, and electron beam evaporation. In some embodiments, the capping layer is formed by selective CVD co-deposition of a metal and a nitrogen-containing substance. For example, in one embodiment, cobalt is co-deposited with NH3 or N2 and H2 plasma. The nitrogen concentration in the metal nitride of the capping layer 75 can vary in different embodiments. For example, in some embodiments, the capping layer 75 is CoN. z Where 0.2≤z≤1. In some embodiments, the thickness of the capping layer 75 is about 1 nm to about 10 nm, and in other embodiments it is about 2 nm to about 5 nm.

[0053] like Figure 15 As shown, a third etch stop layer 65 is formed over the second dielectric layer 50 and / or the capping layer 75. In some embodiments, the third etch stop layer 65 is made of a nitride, such as silicon nitride, titanium nitride, or tantalum nitride. The third etch stop layer 65 can be formed by atomic layer evaporation, PVD, CVD, electron beam evaporation, or any other suitable technique. In some embodiments, the thickness of the third etch stop layer ranges from about 5 nm to about 40 nm, and in other embodiments from about 10 nm to about 20 nm. In some embodiments, the third etch stop layer 65 and the third dielectric layer 70 are made of different materials. In some embodiments, the first etch stop layer 25, the second etch stop layer 45, and the third etch stop layer 65 are made of the same material; in other embodiments, the first etch stop layer 25 and the second etch stop layer 45, the first etch stop layer 25 and the third etch stop layer 65, or the second etch stop layer 45 and the third etch stop layer 65 are made of the same material.

[0054] Figure 16A and Figure 16B A nitriding process according to an embodiment of the present disclosure is illustrated. In some embodiments, nitriding is performed by a thermal process, such that nitrogen diffuses from the conductive barrier layer 55 and / or the cap layer 75 to the metal via contact or plug 35 to form a metal nitride layer 40. Figure 16A and Figure 16BArrow 100 inside the structure illustrates the diffusion of nitrogen during the nitriding process. In some embodiments, annealing is performed in a hydrogen environment 95. In some embodiments, hydrogen is mixed with an inert gas (e.g., helium or argon). In some embodiments, the nitriding process is performed at a temperature ranging from about 300°C to about 500°C; in other embodiments, nitriding is performed at a temperature greater than about 350°C; and in still other embodiments, nitriding is performed at a temperature of about 350°C to about 450°C. In some embodiments, the nitriding operation is performed in a vacuum chamber at an internal pressure of about 10 Torr to about 500 Torr; in other embodiments, it is performed at a pressure greater than about 50 Torr; and in still other embodiments, it is performed at a pressure of about 100 Torr to about 200 Torr. In some embodiments, the duration of the nitriding operation ranges from about 1 minute to about 100 minutes; and in other embodiments, it ranges from about 5 minutes to about 20 minutes. In some embodiments, nitriding of the via or plug 35 forms a nitriding layer 40 in the via or plug, the nitriding layer 40 extending on the upper surface of the via or plug to a thickness T3 ranging from about 0.5 nm to about 6 nm, and in other embodiments from about 1 nm to about 3 nm. In some embodiments, the thickness T2 of the metal via contact or plug 35, 40 ranges from about 60 nm to about 120 nm, and in other embodiments from about 30 nm to about 60 nm. In some embodiments, the width W2 of the outer metal nitride layer on one of the sidewalls ranges from about 0.5 nm to about 6 nm, and in other embodiments from about 1 nm to about 3 nm. In some embodiments, the width W1 of the metal via contact or plug 35, 40 ranges from about 4 nm to about 40 nm, and in other embodiments from about 8 nm to about 20 nm.

[0055] In some embodiments, the thickness of the cobalt nitride capping layer 75 decreases after thermal nitriding, depending on the impurity level of the cobalt nitride capping layer. For example, at higher impurity levels (e.g., -C or O), the capping layer becomes more porous and shrinks more after thermal nitriding.

[0056] At nitriding parameters outside the scope of disclosure, the formation of metal nitrides may be insufficient, the resistivity of metal via contacts or plugs may increase excessively, current leakage may increase, or copper diffusion from overlay copper wiring to metal via contacts or plugs may increase.

[0057] In some embodiments, such as Figure 16A As shown, only the sidewalls of the metal via contact or plug 35 are nitrided to form a metal nitride layer 40, whereas in other embodiments, such as Figure 16B As shown, the top surface and sidewalls of the metal via contact or plug 35 are nitrided to form a metal nitride layer 40.

[0058] Figure 16B The initial nitride content of the conductive barrier layer 55 in the structure is greater than Figure 16A The nitride content of the conductive barrier layer 55 in the structure. For example, in Figure 16A In the illustrated embodiment, the formed conductive barrier layer 55 is composed of materials having the formula TaN y It is made of tantalum-rich tantalum nitride, where 0 ≤ y ≤ 0.6, and in Figure 16B In the illustrated embodiment, the formed conductive barrier layer 55 is composed of materials having the formula TaN y It is made of tantalum nitride, wherein 1.3 ≤ y ≤ 1.8. In some embodiments, Figure 16A The conductive barrier layer 55 shown is a metal or metal nitride, such as tantalum or tantalum nitride formed by PVD or a combination of ALD and PVD. For example, in some embodiments, Figure 16A The conductive barrier layer 55 in the structure is formed by PVD of tantalum, PVD of tantalum nitride, or a combination of ALD of tantalum nitride and PVD of tantalum. In some embodiments, Figure 16B The conductive barrier layer 55 shown is a metal nitride, such as tantalum nitride formed by ALD in an inert environment or a hydrogen plasma environment.

[0059] In some embodiments, both the conductive barrier layer 55 and the cap layer 75 release nitrogen during the thermal nitriding process, and the nitrogen then diffuses to the metal via contact or plug 35 and reacts with the native oxide on the metal via contact or plug to form a metal nitride layer 40.

[0060] In some embodiments, such as Figure 17A and Figure 17B As shown, then in Figure 16A and Figure 16B A third etch stop layer 65 and a third dielectric layer 70 are formed on top of the structure. The third etch stop layer 65 and the third dielectric layer 70 can be formed by means of materials referenced herein. Figure 11 The same materials and the same operations disclosed are used to form the product.

[0061] The present disclosure includes molybdenum plugs 35 and 40, a copper filler layer 60, a tantalum nitride barrier layer 55, a cobalt cap layer 75, and a... Figure 11 In corresponding structural embodiments, the resistivity of metal plugs 35 and 40 is 40% ± 0.1 higher than that of the corresponding devices that have not undergone nitriding. However, Cu + The leakage rate of Cu in the corresponding device that did not undergo the nitriding process is higher. + The leakage was reduced by 50% ± 0.1.

[0062] The present disclosure includes molybdenum plugs 35 and 40, a copper filler layer 60, a cobalt nitride cap layer 75, and a... Figure 17AIn corresponding structural embodiments, the resistivity of metal plugs 35 and 40 is 10% ± 0.1% higher than that of the corresponding devices that have not undergone nitriding. + Leakage is the Cu in the corresponding device that has not undergone the nitriding process. + Leakage of 10% ± 0.1%.

[0063] The present disclosure includes molybdenum plugs 35 and 40, a copper filler layer 60, a tantalum nitride barrier layer 55, a cobalt nitride cap layer 75, and a... Figure 17B In corresponding structural embodiments, the resistivity of metal plugs 35 and 40 is 20% ± 0.1% higher than that of the corresponding devices that have not undergone nitriding. + Leakage is the Cu in the corresponding device that has not undergone the nitriding process. + Leakage of 10% ± 0.1%.

[0064] Figure 18A A cross-sectional view of one stage of a method for manufacturing a semiconductor device according to an embodiment of the present disclosure is shown. Figure 18B and Figure 18C yes Figure 18A A detailed view of a portion of the content. Figure 18A The structure is in harmony with Figure 12 It is manufactured in the same manner as the structure. In some embodiments, the conductive barrier layer 55 comprises multiple layers. For example, as Figure 18B and Figure 18C As shown, the conductive barrier layer 55 includes a first barrier layer 55A and a second barrier layer 55B. The first barrier layer 55A and the second barrier layer 55B may include a metal layer and a metal nitride layer. For example, in... Figure 18B In this structure, the first barrier layer 55A is an ALD tantalum nitride layer, and the second barrier layer 55B is a PVD tantalum layer. Figure 18C In this embodiment, the order of the first barrier layer 55A and the second barrier layer 55B is reversed. Multiple conductive barrier layers can also be formed on... Figure 7A Above the structure.

[0065] Figures 19 to 22 Cross-sectional views of various stages of a method for manufacturing a semiconductor device according to embodiments of the present disclosure are shown. It should be understood that, for additional embodiments of the method, [further details may be needed]. Figures 19 to 22 Additional operations are provided before, during, and after the process shown, and some of these operations can be substituted or eliminated. The order of operations / processes can be interchanged.

[0066] According to the references in this article Figures 2 to 6 The disclosed operations are used to form Figure 6 The structure is then formed on the metal via contact or plug 35, and a self-assembled monolayer (SAM) 105 is formed thereon, such as... Figure 19As shown. In some embodiments, SAM is formed using an organic compound having an alkyne end group. In some embodiments, the alkyne is a C8 to C24 alkyne, and in other embodiments, the alkyne is a C12-C20 alkyne.

[0067] After forming SAM 105, as Figure 20 As shown, a conductive barrier layer 55 is formed on the exposed surface of the via or trench. The conductive barrier layer 55 is formed from any material and any operation disclosed herein for forming a conductive barrier layer. The conductive barrier layer 55 is not formed on the SAM 105. In some embodiments, the conductive barrier layer 55 is a material having the formula TaN. y Tantalum nitride, where 1.3≤y≤1.5.

[0068] Then remove SAM, such as Figure 21 As shown. SAM 105 can be removed by etching operations (e.g., piranha etching using a mixture of sulfuric acid and hydrogen peroxide) or by plasma ashing operations.

[0069] Then, as Figure 22 As shown, a metal filler layer 60 is formed over the conductive barrier layer 55 and the metal via contact or plug 35. The metal filler layer 60 can be formed from any material or technique disclosed herein for forming a metal filler layer. Figure 22 The structure can then undergo nitriding, and as described in this paper (referencing...). Figures 14 to 17B Further processing as disclosed.

[0070] Figure 23 and Figure 24 A semiconductor device according to an embodiment of the present disclosure is shown. Figure 23 An embodiment is shown in which a metal nitride layer 40 is formed on top of a metal through-hole contact or plug 35. (See reference herein) Figure 7A As disclosed, in some embodiments, the thickness T1 of the metal nitride outer layer 40 ranges from about 1 nm to about 12 nm, and in other embodiments from about 2 nm to about 6 nm. In some embodiments, the total thickness T2 of the metal via contacts or plugs 35, 40 ranges from about 60 nm to about 120 nm, and in other embodiments from about 30 nm to about 60 nm. In some embodiments, the width W1 of the metal via contacts or plugs 35 ranges from about 4 nm to about 40 nm, and in other embodiments from about 8 nm to about 20 nm. In some embodiments, the thickness T4 of the cap layer 75 ranges from about 1 nm to about 10 nm, and in other embodiments from about 2 nm to about 5 nm.

[0071] In some embodiments, the ratio of the thickness T1 of the metal nitride outer layer 40 to the thickness T2 of the metal via contact or plug 35, 40 ranges from about 0.008 to about 0.2, while in other embodiments, T1 / T2 ranges from about 0.06 to 0.1. In some embodiments, the ratio of the thickness T4 of the cap layer 75 to the thickness T1 of the metal nitride outer layer 40 ranges from about 0.08 to about 10, while in other embodiments, it ranges from about 0.2 to about 2.5.

[0072] Figure 24 An embodiment is shown in which a metal nitride layer 40 is formed on top of a metal through-hole contact or plug 35 and along its sidewalls. (See reference herein) Figure 16A and Figure 16B In some embodiments, the thickness T3 of the metal nitride outer layer 40 on the upper surface of the via or plug 35 ranges from about 0.5 nm to about 6 nm, and in other embodiments from about 1 nm to about 3 nm. In some embodiments, the thickness T2 of the metal via contact or plug 35, 40 ranges from about 60 nm to about 120 nm, and in other embodiments from about 30 nm to about 60 nm. In some embodiments, the width W2 of the metal nitride outer layer on one of the sidewalls ranges from about 0.5 nm to about 6 nm, and in other embodiments from about 1 nm to about 3 nm. In some embodiments, the width W1 of the metal via contact or plug 35, 40 ranges from about 4 nm to about 40 nm, and in other embodiments from about 8 nm to about 20 nm. In some embodiments, the thickness T4 of the cap layer 75 ranges from about 1 nm to about 10 nm, and in other embodiments from about 2 nm to about 5 nm.

[0073] In some embodiments, the ratio of the thickness T3 of the metal nitride outer layer 40 on the upper surface of the via contact or plug 35 to the thickness T2 of the metal via contact or plug 35, 40 ranges from about 0.004 to about 0.2, and in other embodiments, T3 / T2 ranges from about 0.02 to 0.1. In some embodiments, the ratio of the width W2 of the metal nitride outer layer 40 along the first direction (X direction) to the width W1 of the metal via contact or plug 35, 40 along the first direction (X direction) ranges from about 0.01 to about 0.3, and in other embodiments, it ranges from about 0.05 to about 0.2. In some embodiments, the ratio of the thickness T3 of the metal nitride outer layer 40 on the upper surface of the via contact or plug 35 to the width W1 of the metal via contact or plug 35, 40 ranges from about 0.01 to about 0.3, and in other embodiments, it ranges from about 0.05 to about 0.2. In some embodiments, the ratio of the width W2 of the outer metal nitride layer 40 on the sidewall of the metal via contact or plug 35, 40 to the thickness T2 of the metal via contact or plug 35, 40 ranges from about 0.004 to about 0.2, and in other embodiments from about 0.04 to about 0.1. In some embodiments, the ratio of the thickness T4 of the cap layer 75 to the thickness T3 of the outer metal nitride layer 40 on the upper surface of the contact via or plug ranges from about 0.08 to about 10, and in other embodiments from about 0.2 to about 2.5.

[0074] If the thickness and width of the outer metal nitride layer 40 and the cap layer 75, and the thickness and / or width ratio of the outer metal nitride layer 40, the metal via contact or plug 35, 40 and the cap layer 75 exceed the disclosed range, the formation of the metal nitride may be insufficient, the resistivity of the metal via contact or plug may increase excessively, current leakage may increase, or copper diffusion from the overlying copper wiring to the metal via contact or plug may increase.

[0075] Figure 25A flowchart of method 2500 according to an embodiment of the present disclosure is shown. The method includes operation S2505 of forming a semiconductor device 15 on a substrate 10. In operation S2510, an interconnect structure is formed on the semiconductor device, wherein the interconnect structure includes a metal plug 35 comprising a first metal disposed in a first dielectric layer 30. In operation S2515, a second dielectric layer 50 having an opening 85 exposing the metal plug 35 is formed on the first dielectric layer 30. In operation S2520, a nitriding process is performed on the metal plug 35. In some embodiments, in operation S2525, a conductive barrier layer 55 and a metal fill layer 60 are formed in the opening 85. In some embodiments, in operation S2530, the conductive barrier layer 55 and the metal fill layer 60 are planarized. In some embodiments, in operation S2535, a capping layer 75 comprising a metal nitride is formed on the conductive barrier layer 55 and the metal fill layer 60. In some embodiments, during operation S2540, an etch stop layer 65 is formed over the cap layer 75, and during operation S2545, a low-k dielectric layer 70 is formed over the etch stop layer 65. During operation S2550, nitrogen diffuses from the cap layer 75 to the metal plug 35 during the nitriding process.

[0076] Figure 26 A flowchart of a method 2600 for manufacturing a semiconductor device is shown. Method 2600 includes, in operation S2605, forming at least one transistor 15 on a substrate 10. The at least one transistor 15 includes at least one channel region 130, at least one gate dielectric layer 120, at least one gate electrode layer 125, and at least one source / drain region 140. The at least one gate dielectric layer 120 has a first dielectric constant k1. In operation S2610, forming a first dielectric layer 30 on the transistor 15. The first dielectric layer 30 has a second dielectric constant k2, where k1 > k2. In operation S2615, forming a via 80 in the first dielectric layer 30. In operation S2620, forming a metal plug 35 comprising a first metal in the via 80. Then, in operation S2625, performing a nitriding process on the metal plug 35. In operation S2630, forming conductive contacts 55, 60 electrically connected to the metal plug 35 on the metal plug. In some embodiments, in operation S2635, a second dielectric layer 50 is formed over the first dielectric layer 30. Then, in some embodiments, in operation S2640, an opening 85 is formed in the second dielectric layer 50, and in operation S2645, a conductive barrier layer 55 and a metal filler layer 60 are formed in the opening.

[0077] Figure 27A flowchart of a method 2700 for manufacturing a semiconductor device is shown. Method 2700 includes, in operation S2705, forming a metal plug 35 comprising a first metal in a first dielectric layer 30. The first dielectric layer has a first dielectric constant k1. In operation S2710, forming an etch stop layer 45 having a second dielectric constant k2 over the first dielectric layer 30. In operation S2715, forming a second dielectric layer 50 having a third dielectric constant k3 over the first dielectric layer 30 and the metal plug 35. The etch stop layer 45 is thinner than either the first dielectric layer 30 or the second dielectric layer 50, and k1 differs from k2 or k3. In operation S2720, forming an opening 85 in the second dielectric layer 50 to expose the metal plug 35. Then, in operation S2725, performing a thermal nitriding process on the metal plug at a temperature greater than 350°5. In some embodiments, in operation S2730, thermal nitriding converts the metal oxide of the first metal into a metal nitride. In some embodiments, during operation S2735, a conductive barrier layer 55 and a metal filler layer 60 are formed in the opening 85. Then, during operation S2740, a capping layer 75 comprising a metal nitride is formed over the barrier layer 55 and the filler layer 60.

[0078] Embodiments of this disclosure provide a low resistance and reduced current leakage and Cu + Leaking semiconductor devices. Leakage can occur at native metal oxide sites. Converting native metal oxide on the plug to metal nitride reduces leakage. In some embodiments, Cu... + Leaks have been reduced by 50% to 90%.

[0079] It will be understood that this document does not necessarily discuss all advantages, no particular advantage is necessary for all embodiments or examples, and other embodiments or examples may provide different advantages.

[0080] One embodiment of this disclosure is a method comprising forming a semiconductor device on a substrate and forming an interconnect structure on the semiconductor device. The interconnect structure includes a metal plug, the metal plug including a first metal disposed in a first dielectric layer. A second dielectric layer is formed on the first dielectric layer. The second dielectric layer has an opening exposing the metal plug. A nitriding process is performed on the metal plug to form a nitrided layer on the metal plug. In one embodiment, the first metal includes at least one of Mo or W. In one embodiment, the method includes forming a barrier layer and a fill layer in the opening. In one embodiment, the method includes planarizing the barrier layer and the fill layer. In one embodiment, the method includes forming a capping layer comprising a metal nitride on the barrier layer and the fill layer. In one embodiment, the metal nitride includes at least one of cobalt nitride or molybdenum nitride. In one embodiment, the method includes forming an etch stop layer on the capping layer and forming a low-k dielectric layer on the etch stop layer. In one embodiment, the nitriding process is performed after the capping layer is formed, and during the nitriding process, nitrogen diffuses from the capping layer to the metal plug. In one embodiment, the nitriding process is performed before the formation of the barrier layer and the fill layer. In one embodiment, the nitriding process is performed after the barrier layer and the filler layer are formed.

[0081] Another embodiment of this disclosure is a method of manufacturing a semiconductor device, the method comprising forming at least one transistor on a substrate, the at least one transistor including at least one channel region, at least one gate dielectric layer, at least one gate electrode layer, and at least one source / drain region. The at least one gate dielectric layer has a first dielectric constant k1. A first dielectric layer having a second dielectric constant k2 is formed on the at least one transistor, wherein k1 > k2. A via is formed in the first dielectric layer. A metal plug including a first metal is formed in the via. A nitriding process is performed on the metal plug. A conductive contact electrically connected to the metal plug is formed on the metal plug. In one embodiment, the first metal includes at least one of Mo or W. In one embodiment, forming the conductive contact includes forming a second dielectric layer on the first dielectric layer, forming an opening in the second dielectric layer to expose the metal plug, and forming a barrier layer and a fill layer in the opening. In one embodiment, the barrier layer includes tantalum nitride or titanium nitride. In one embodiment, the nitriding process is performed at a temperature in the range of 350°C to 450°C.

[0082] Another embodiment of this disclosure is a method of manufacturing a semiconductor device, the method comprising forming a metal plug comprising a first metal in a first dielectric layer having a first dielectric constant k1, the first dielectric layer being disposed on a substrate comprising the semiconductor device. An etch stop layer having a second dielectric constant is formed on the first dielectric layer. A second dielectric layer having a third dielectric constant k3 is formed on the first dielectric layer and the metal plug. The etch stop layer is thinner than either the first or second dielectric layer, and k1 differs from k2 or k3. An opening exposing the metal plug is formed in the second dielectric layer, and a thermal nitriding process is performed on the metal plug at a temperature greater than 350°C. In one embodiment, during the thermal nitriding process, a metal oxide of the first metal is converted into a metal nitride. In one embodiment, the thermal nitriding process is performed at a pressure ranging from 0.1 Torr to 100 Torr. In one embodiment, the method comprises forming a second dielectric layer on the first dielectric layer, the second dielectric layer having an opening exposing the metal plug. In one embodiment, the method comprises forming a barrier layer and a fill layer in the opening.

[0083] Another embodiment of this disclosure is a structure including a semiconductor device disposed on a substrate. A metal plug is disposed in a first dielectric layer above the semiconductor device. The metal plug includes an inner layer and an outer layer, the inner layer including a first metal and the outer layer including a nitride of the first metal. An etch stop layer is disposed above the first dielectric layer, and a second dielectric layer having an opening is disposed above the first dielectric layer. The opening is filled with a barrier layer and a fill layer embedded in the barrier layer, the fill layer including a material different from the barrier layer. The etch stop layer is thinner than either the first dielectric layer or the second dielectric layer. In one embodiment, the structure further includes a cap layer disposed above the barrier layer and the fill layer. In one embodiment, the cap layer does not extend above the second dielectric layer. In one embodiment, the cap layer includes at least one of elemental cobalt, elemental molybdenum, cobalt nitride, or molybdenum nitride. In one embodiment, the structure includes an etch stop layer disposed above the cap layer and the second dielectric material, wherein the etch stop layer and the second dielectric layer are made of different materials. In one embodiment, the ratio (T1 / T2) of the thickness T1 of the first metal nitride outer layer to the thickness T2 of the metal plug ranges from 0.008 to 0.2. In one embodiment, the structure includes a low-k dielectric layer above an etch stop layer, wherein the low-k dielectric layer and the etch stop layer are made of different materials. In one embodiment, the first metal includes at least one of Mo or W. In one embodiment, the barrier layer includes tantalum nitride or titanium nitride. In one embodiment, the fill layer includes at least one of copper, aluminum, tungsten, or molybdenum. In one embodiment, a metal plug is electrically coupled to an integrated circuit assembly.

[0084] Another embodiment of this disclosure is a semiconductor device including a component layer disposed on a substrate, wherein the component layer includes at least one integrated circuit component. A first dielectric layer having a first dielectric constant k1 extending along a first direction is disposed on the component layer. A metal via contact passes through the first dielectric layer and is electrically connected to the at least one integrated circuit component. The metal via contact includes an inner layer and an outer layer, the inner layer including a first metal and the outer layer including a nitride of the first metal. An etch stop layer having a second dielectric constant k2 extending along the first direction is disposed on the first dielectric layer, the etch stop layer having a first opening. A second dielectric layer having a third dielectric constant k3 extending along the first direction is disposed on the etch stop layer, the second dielectric layer having a second opening. A conductive barrier layer is disposed in the first opening and the second opening. A metal fill layer is disposed on the conductive barrier layer and embedded in the conductive barrier layer, wherein the metal fill layer is made of a material different from the conductive barrier layer and the first metal. The etch stop layer is made of a material different from the first dielectric layer and the second dielectric layer, and k2 is different from k1 or k3. The etch stop layer is thinner than the first dielectric layer or the second dielectric layer. The first dielectric layer, the etch stop layer, and the second dielectric layer are arranged along a second direction intersecting the first direction. In one embodiment, an outer layer of nitride comprising a first metal is located between an inner layer comprising the first metal and a conductive barrier layer, and the ratio (T1 / T2) of the thickness T1 of the outer layer along the second direction to the thickness T2 of the metal via contact along the second direction is in the range of 0.008 to 0.2. In one embodiment, T1 / T2 ranges from 0.06 to 0.1. In one embodiment, an outer layer of nitride comprising a first metal is located between an inner layer comprising the first metal and a conductive barrier layer along the first direction, and the ratio (W2 / W1) of the width W2 of the outer layer along the first direction to the width W1 of the metal via contact along the first direction is in the range of 0.01 to 0.3. In one embodiment, W1 / W2 ranges from 0.05 to 0.2.

[0085] Another embodiment of this disclosure is a semiconductor device including a transistor disposed on a substrate. The transistor includes a channel region, a gate dielectric layer, a gate electrode layer, a source / drain region, source / drain contacts electrically connected to the source / drain region, and a silicide layer disposed between the source / drain region and the source / drain contacts. The gate dielectric layer has a first dielectric constant k1. The silicide layer has a higher conductivity than the source / drain region, and the source / drain contacts have a higher conductivity than the silicide layer. A plug is located in the first dielectric layer disposed on the transistor. The plug includes an inner molybdenum layer and an outer molybdenum nitride layer. The first dielectric layer has a second dielectric constant k2, and k1 > k2. A second dielectric layer with an opening is disposed on the first dielectric layer. The opening is filled with a nitride barrier layer and a copper filler layer embedded in the nitride barrier layer. The nitride barrier layer is made of a different material than the outer molybdenum nitride layer. In one embodiment, the outer molybdenum nitride layer includes MoN. x Where 0.2 ≤ x ≤ 0.4. In one embodiment, the molybdenum nitride outer layer comprises Mo2N having a face-centered cubic crystal structure. In one embodiment, the semiconductor device includes a cobalt-containing capping layer or a molybdenum-containing capping layer selectively disposed over a barrier layer and a filler layer. In one embodiment, the cobalt-containing capping layer or the molybdenum-containing capping layer comprises at least one of elemental cobalt, elemental molybdenum, cobalt nitride, or molybdenum nitride.

[0086] The foregoing has outlined features of several embodiments to enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art should understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or the same advantages of the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made herein without departing from the spirit and scope of this disclosure.

[0087] Example 1. A method of manufacturing a semiconductor device, comprising: forming a semiconductor device on a substrate; forming an interconnect structure on the semiconductor device, wherein the interconnect structure includes a metal plug, the metal plug including a first metal disposed in a first dielectric layer; forming a second dielectric layer on the first dielectric layer, the second dielectric layer having an opening exposing the metal plug; and performing a nitriding process on the metal plug to form a nitrided layer on the metal plug.

[0088] Example 2. The method according to Example 1, wherein the first metal comprises at least one of Mo or W.

[0089] Example 3. The method according to Example 1 further includes forming a barrier layer and a fill layer in the opening.

[0090] Example 4. The method according to Example 3 further includes planarizing the barrier layer and the fill layer.

[0091] Example 5. The method according to Example 3 further includes forming a capping layer comprising a metal nitride over the barrier layer and the filler layer.

[0092] Example 6. The method according to Example 5, wherein the metal nitride comprises at least one of cobalt nitride or molybdenum nitride.

[0093] Example 7. The method according to Example 5 further includes: forming an etch stop layer over the cap layer; and forming a low-k dielectric layer over the etch stop layer.

[0094] Example 8. The method according to Example 5, wherein the nitriding process is performed after the cap layer is formed, and during the nitriding process, nitrogen diffuses from the cap layer to the metal plug.

[0095] Example 9. The method according to Example 3, wherein the nitriding process is performed prior to the formation of the barrier layer and the filler layer.

[0096] Example 10. The method according to Example 3, wherein the nitriding process is performed after the formation of the barrier layer and the filler layer.

[0097] Example 11. A method of manufacturing a semiconductor device, comprising: forming at least one transistor on a substrate, the at least one transistor including at least one channel region, at least one gate dielectric layer, at least one gate electrode layer, and at least one source / drain region, wherein the at least one gate dielectric layer has a first dielectric constant k1; forming a first dielectric layer having a second dielectric constant k2 on the at least one transistor, wherein k1 > k2; forming a via in the first dielectric layer; forming a metal plug including a first metal in the via; performing a nitriding process on the metal plug; and forming a conductive contact electrically connected to the metal plug on the metal plug.

[0098] Example 12. The method according to Example 11, wherein the first metal comprises at least one of Mo or W.

[0099] Example 13. The method according to Example 11, wherein forming the conductive contact further includes: forming a second dielectric layer over the first dielectric layer; forming an opening in the second dielectric layer to expose the metal plug; and forming a barrier layer and a filler layer in the opening.

[0100] Example 14. The method according to Example 13, wherein the barrier layer comprises tantalum nitride or titanium nitride.

[0101] Example 15. The method according to Example 11, wherein the nitriding process is performed at a temperature in the range of 350°C to 450°C.

[0102] Example 16. A semiconductor structure comprising: a semiconductor device disposed on a substrate; a metal plug disposed in a first dielectric layer above the semiconductor device, wherein the metal plug includes an inner layer and an outer layer, the inner layer including a first metal and the outer layer including a nitride of the first metal; an etch stop layer disposed above the first dielectric layer; and a second dielectric layer having an opening disposed above the first dielectric layer, wherein the opening is filled with a barrier layer and a fill layer embedded in the barrier layer, the fill layer comprising a material different from the barrier layer, and the etch stop layer being thinner than either the first dielectric layer or the second dielectric layer.

[0103] Example 17. The structure according to Example 16 further includes a cap layer disposed above the barrier layer and the filler layer.

[0104] Example 18. The structure according to Example 17, wherein the cap layer does not extend over the second dielectric layer.

[0105] Example 19. The structure according to Example 17, wherein the cap layer comprises at least one of element cobalt, element molybdenum, cobalt nitride, or molybdenum nitride.

[0106] Example 20. The structure according to Example 17, wherein the ratio T1 / T2 of the thickness T1 of the first metal nitride outer layer to the thickness T2 of the metal plug ranges from 0.008 to 0.2.

Claims

1. A method for manufacturing a semiconductor device, comprising: Semiconductor devices are formed on a substrate; An interconnect structure is formed on the semiconductor device. The interconnect structure includes a metal plug, and the metal plug includes a first metal disposed in a first dielectric layer; A second dielectric layer is formed on top of the first dielectric layer, the second dielectric layer having an opening exposing the metal plug; and A nitriding process is performed on the metal plug to form a nitrided layer on the metal plug.

2. The method of claim 1, wherein, The first metal includes at least one of Mo or W.

3. The method according to claim 1, further comprising forming a barrier layer and a fill layer in the opening.

4. The method of claim 3, further comprising planarizing the barrier layer and the filler layer.

5. The method of claim 3, further comprising forming a capping layer comprising a metal nitride over the barrier layer and the filler layer.

6. The method of claim 5, wherein, The metal nitride includes at least one of cobalt nitride or molybdenum nitride.

7. The method according to claim 5, further comprising: An etch stop layer is formed on top of the cap layer; as well as A low-k dielectric layer is formed on top of the etch stop layer.

8. The method of claim 5, wherein, The nitriding process is performed after the cap layer is formed, and during the nitriding process, nitrogen diffuses from the cap layer to the metal plug.

9. A method for manufacturing a semiconductor device, comprising: At least one transistor is formed on a substrate, the at least one transistor including at least one channel region, at least one gate dielectric layer, at least one gate electrode layer, and at least one source / drain region. Wherein, the at least one gate dielectric layer has a first dielectric constant k1; A first dielectric layer having a second dielectric constant k2 is formed on top of the at least one transistor. Where k1 > k2; A via is formed in the first dielectric layer; A metal plug comprising a first metal is formed in the via; The metal plug is subjected to a nitriding process; and A conductive contact electrically connected to the metal plug is formed on the metal plug.

10. A semiconductor structure, comprising: Semiconductor devices are mounted on a substrate; A metal plug is disposed in a first dielectric layer above the semiconductor device. The metal plug comprises an inner layer and an outer layer, the inner layer comprising a first metal, and the outer layer comprising a nitride of the first metal; An etch stop layer is disposed above the first dielectric layer; and A second dielectric layer with an opening is disposed on top of the first dielectric layer. The opening is filled with a barrier layer and a filler layer embedded in the barrier layer. The filler layer comprises a material different from the barrier layer. The etch stop layer is thinner than either the first dielectric layer or the second dielectric layer.

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