Chip, manufacturing method thereof, and electronic device

Abstract

This application provides a chip and its fabrication method, as well as an electronic device, relating to the field of chip technology. By fabricating power-off units and logic circuits on different substrates, various problems caused by existing on-chip power-off technologies can be solved. The chip includes a first die and a second die, connected by a bonding surface. The first die includes logic circuits and a first metal power network disposed on a first substrate. The second die includes multiple first power-off units and a second metal power network disposed on a second substrate. The second metal power network includes a first power line and a second power line. The multiple first power-off units are connected between the first power line and the second power line, and the second power line is connected to the first metal power network at the bonding surface, for supplying power to the logic circuit by controlling the on / off state between the first power line and the second power line.

Description

Technical Field

[0001] This application relates to the field of chip technology, and in particular to a chip and its manufacturing method, and an electronic device. Background Technology

[0002] As semiconductor technology continues to evolve, leakage power consumption accounts for an increasingly larger proportion of total power consumption. Without control, leakage power consumption can even reach 50% of the chip's total power consumption. Therefore, various methods for controlling static leakage current have emerged, among which power gating is one of the commonly used techniques for low-power chips. Power shutdown technology allows certain logic modules in a chip to be powered off when not in use and powered on again when needed. It can reduce leakage current in the power-off region to near zero, significantly reducing the chip's static power consumption.

[0003] On-chip power shutdown is a commonly used shutdown technique in current chip design. (Refer to...) Figure 1 As shown, in existing on-chip power-off technology, the power-off unit and logic module are fabricated on the same wafer, which can lead to various problems such as the area occupied by the power-off unit and inflexible placement, thus affecting the performance of the chip. Summary of the Invention

[0004] This application provides a chip and its fabrication method, as well as an electronic device, which solves various problems caused by existing on-chip power-off technology by fabricating the power-off unit and logic circuit on different substrates.

[0005] This application provides a chip including a first die and a second die, which are connected by a bonding surface. The first die includes a first substrate and logic circuits and a first metal power network disposed on the first substrate. The first metal power network is located on the side of the logic circuit near the bonding surface and is electrically connected to the logic circuit. The second die includes a second substrate and a plurality of first power-off units and a second metal power network disposed on the second substrate. The second metal power network is located on the side of the first power-off units near the bonding surface and is connected to the plurality of first power-off units. The second metal power network includes a first power line and a second power line. The plurality of first power-off units are connected between the first power line and the second power line, and the second power line is connected to the first metal power network at the bonding surface. The plurality of first power-off units are used to supply power to the logic circuit by controlling the on / off state between the first power line and the second power line.

[0006] This chip is constructed by bonding two dies (a first die and a second die). These two dies allow for the decoupling of the on-chip power distribution network (PDN) from the logic circuitry. In the first die, where the logic circuitry is located, only a portion of the metal power network (the first metal power network) is retained, simplifying the metal power network on the first die to meet the power supply needs of the logic circuitry. The remaining portion of the metal power network (the second metal power network) and the power shutdown units are located in the second die. This allows for flexible distribution of the power shutdown units, freeing up the area and wiring resources occupied by the power shutdown units, ensuring the robustness of the power network, and avoiding problems such as local signal congestion and timing disorders.

[0007] In some possible implementations, the first die includes a first region and a second region, with the power density of the first region being greater than that of the second region; the second die includes a third region and a fourth region; the first and second metal power networks include a first local metal power network and a second local metal power network; a first power-off unit located in the third region is connected to the logic circuit located in the first region via the first local metal power network, and a first power-off unit located in the fourth region is connected to the logic circuit located in the second region via the second local metal power network; the density of the first power-off units in the third region is greater than that in the fourth region. In other words, using the chip of this application, the power-off units can be flexibly designed according to the power density of the logic circuit in different regions (such as the first and second regions) of the first die. By optimizing the power-off units, the density of the corresponding power-off units in local high-power-density areas can be increased in a targeted manner to better meet the chip's requirements.

[0008] In some possible implementations, the wiring density in the first local metal power network is greater than that in the second local metal power network. That is, the wiring density in the corresponding metal power network (first local metal power network) can be increased specifically for high-power-density local areas, thereby increasing the robustness of the corresponding metal power network (first local metal power network) to better meet the chip's requirements.

[0009] In some possible implementations, the trace width in the first local metal power network is greater than the trace width in the second local metal power network. That is, for specific high-power-density regions, the trace width in the corresponding metal power network (first local metal power network) can be increased, thereby enhancing the robustness of the corresponding metal power network (first local metal power network) to better meet the chip's requirements.

[0010] In some possible implementations, the projections of the first region and the third region onto the second substrate overlap. This shortens the path of the first local metal power network connecting the first region and the third region, thus improving the power supply capability of the power network.

[0011] In some possible implementations, the projections of the second and fourth regions onto the second substrate overlap. This shortens the path of the second local metal power network connecting the second and fourth regions, thus improving the power supply capability of the power network.

[0012] In some possible implementations, the first metal power network includes a third power line connected to the logic circuit; the third power line is connected to the second power line at a bonding surface. In this way, the power-off unit can supply power to the logic circuit via the second and third power lines.

[0013] In some possible implementations, the second die also includes: a power connection pad and a ground connection pad; the power connection pad and ground connection pad are located on the side of the second substrate away from the second metal power network; the second metal power network also includes a first ground line connected to a plurality of first power-off units, and the first metal power network also includes a second ground line connected to logic circuits; the power connection pad is connected to a first power line; the ground connection pad is connected to a first ground line, and the first ground line and the second ground line are electrically connected at the bonding surface. In this case, the power path between the first power line and the second power line can be controlled by the power-off units.

[0014] In some possible implementations, the first die also includes a plurality of second power-off units disposed on the first substrate; the first metal power network includes a fourth power line and a fifth power line; the plurality of second power-off units are connected between the fourth power line and the fifth power line, and are used to supply power to the logic circuit by controlling the on / off state between the fourth power line and the fifth power line; the fourth power line is connected to the second metal power network, and the fifth power line is connected to the logic circuit. In this way, the second power-off units can control the power supply to a portion of the logic circuit.

[0015] This application also provides a method for fabricating a chip, which may include: providing a first die, including: fabricating a logic circuit on a first substrate and fabricating a first metal power network on the logic circuit; wherein the first metal power network is electrically connected to the logic circuit. Providing a second die, including: fabricating a plurality of first power-off units on a second substrate and fabricating a second metal power network on the first power-off units; wherein the second metal power network includes a first power line and a second power line; the plurality of first power-off units are connected between the first power line and the second power line, for supplying power to the logic circuit by controlling the on / off state between the first power line and the second power line. The side of the first die with the first metal power network is bonded to the side of the second die with the second metal power network; the second power line is connected to the first metal power network at the bonding surface.

[0016] The above-described fabrication method involves bonding two dies (a first die and a second die) to form a 3D chip. In this 3D chip, the on-chip power distribution network (PDN) is decoupled from the logic circuitry and disposed separately in the two dies. In the first die containing the logic circuitry, only a portion of the metal power network (i.e., the first metal power network) is retained, simplifying the metal power network on the first die to meet the power supply requirements of the logic circuitry. The remaining portion of the metal power network (the second metal power network) and the power-off units are both located in the second die. This allows for flexible distribution of the power-off units, frees up the area occupied by the power-off units and reduces the need for wiring resources, ensures the robustness of the power network, and avoids a series of problems such as local signal congestion and timing disorders.

[0017] This application also provides an electronic device including a circuit board and a chip as provided in any of the aforementioned possible implementations, the chip being electrically connected to the circuit board. Attached Figure Description

[0018] Figure 1 This is a schematic diagram of the structure of a chip provided in the prior art;

[0019] Figure 2 This is a schematic diagram of the structure of a chip provided in an embodiment of this application;

[0020] Figure 3 This is a schematic diagram of the distribution of an on-chip power-off unit provided in the prior art;

[0021] Figure 4 This is a schematic diagram of the distribution of an on-chip power-off unit provided in the prior art;

[0022] Figure 5A schematic diagram of the distribution of an on-chip power-off unit provided in an embodiment of this application;

[0023] Figure 6 This is a schematic diagram of the structure of a chip provided in an embodiment of this application;

[0024] Figure 7 A flowchart illustrating a chip fabrication method provided in this application embodiment;

[0025] Figure 8 A schematic diagram illustrating the chip manufacturing process provided in this application embodiment;

[0026] Figure 9 A schematic diagram illustrating the chip manufacturing process provided in this application embodiment;

[0027] Figure 10 This is a schematic diagram of a chip during the manufacturing process, provided as an embodiment of this application. Detailed Implementation

[0028] To make the objectives, technical solutions, and advantages of this application clearer, the technical solutions of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0029] The terms "first," "second," etc., used in the specification, embodiments, claims, and drawings of this application are for distinguishing purposes only and should not be construed as indicating or implying relative importance or order. "At least one" means one or more, and "more than" means two or more. "Installation," "connection," "linking," etc., should be interpreted broadly, for example, they can refer to electrical connections or mechanical connections; fixed connections or detachable connections or integral connections; direct connections or indirect connections through an intermediate medium; or internal communication between two elements. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion, such as including a series of steps or units. A method, product, or apparatus is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to these processes, methods, products, or apparatuses. "Upper," "lower," "left," "right," etc., are used only with respect to the orientation of components in the drawings. These directional terms are relative concepts used for relative description and clarification and may vary accordingly depending on the orientation of the components in the drawings.

[0030] First, a brief explanation of the technical terms used in this application will be provided.

[0031] A power distribution network (PDN) is a network within a chip responsible for transmitting power from the power source to various loads (such as field-effect transistors in logic circuits). The main goal of a PDN is to ensure a stable power supply to the loads while minimizing voltage drop, noise, and transient response time.

[0032] A PDN comprises several components, including a metal power network and power shutdown units. The metal power network is a network structure formed by one or more layers of metal traces. The power shutdown units, using switching devices (details below), control the on / off state of the lines within the metal power network. Under the control of the power shutdown units, the PDN transmits power to various loads through the metal power network.

[0033] This application provides an electronic device that uses a novel chip. The power-off unit and logic circuit are fabricated on different substrates (or wafers) and then bonded together to form the novel chip. This can free up the area and winding resources occupied by the power-off unit, and also avoid a series of problems such as local signal congestion and timing disorder.

[0034] This application does not limit the form of the aforementioned electronic device. The electronic device can be any electronic product with a chip, such as consumer electronics, home electronics, automotive electronics, financial terminal products, communication electronics, etc.

[0035] As illustrated, the aforementioned consumer electronics products can include mobile phones, tablet computers, laptops, personal computers (PCs), personal digital assistants (PDAs), smart wearable products (e.g., smartwatches, smart bracelets), virtual reality (VR) terminal devices, augmented reality (AR) terminal devices, drones, etc. Home electronics products can include smart door locks, televisions, smart speakers, refrigerators, robot vacuum cleaners, etc. In-vehicle electronics products can include in-vehicle navigation systems, in-vehicle displays, etc. Financial terminal products can include automated teller machines (ATMs), self-service electronic devices, etc. Communication electronic products can include servers, storage devices, radar, base stations, and other communication equipment.

[0036] Depending on actual needs, the above-mentioned electronic devices may also include other devices electrically connected to the chip, such as printed circuit boards (PCBs), input / output devices, etc. This application does not impose any restrictions on this.

[0037] The following provides a further description of the chip provided in the embodiments of this application.

[0038] As illustrated, this application provides a chip, such as... Figure 2 As shown, the chip includes a first die D1 and a second die D2, and the first die D1 and the second die D2 are connected by a bonding surface M. This application does not limit the bonding method between the first die D1 and the second die D2; for example, it can be hybrid bonding (HB). Of course, the chip may also include other dies stacked together, and this application does not limit this.

[0039] Continue to refer to Figure 2 As shown, the first die D1 includes a first substrate Sub1 and a first metal power network 10 and a logic circuit 11 disposed on the first substrate Sub1. The first metal power network 10 is located on the side of the logic circuit 11 near the bonding surface M, and the first metal power network 10 is electrically connected to the logic circuit 11. The second die D2 includes a second substrate Sub2 and a second metal power network 20 and a plurality of power-off units 21 (also referred to as first power-off units) disposed on the second substrate Sub2. The second metal power network 20 is located on the side of the plurality of power-off units 21 near the bonding surface M, and the second metal power network 20 is connected to the plurality of power-off units 21.

[0040] It should be noted that the power shutdown unit 21, also known as the power gating cell, is a control unit that realizes the power shutdown. They are used to control the connection and disconnection of the power supply or ground wire to realize the power supply control of the logic power supply.

[0041] As illustrated, the first substrate ub1 and the second substrate Sub2 mentioned above can be silicon substrates, but are not limited to this.

[0042] As illustrated, the aforementioned multiple power-off units 21 may be at least one of the following control devices: MTCMOS (multi-threshold complementary metal-oxide semiconductor cell, abbreviated as multi-threshold CMOS cell), PMOS (positive channel metal oxide semiconductor) power transistor, LDMOS (laterally diffused metal oxide semiconductor) power transistor, etc., but are not limited thereto.

[0043] Compared to existing technologies that place the entire on-chip power distribution network, including the power-off unit and the metal network, on the same substrate, there are several problems such as the power-off unit occupying area, inflexible placement, local signal congestion, and timing loss.

[0044] In the chip provided in this embodiment, the on-chip power distribution network (PDN) is decomposed. On the first substrate Sub1 where the logic circuit 11 is located, only a portion of the metal power network (i.e., the first metal power network 10) is retained, thus simplifying the metal power network on the first die D1 to meet the power supply needs of the logic circuit 11. The other portion of the metal power network (the second metal power network 20) ​​and the power shutdown unit 21 are both located on the second substrate Sub2. This allows for flexible distribution of the power shutdown unit 21, frees up the area occupied by the power shutdown unit 21 and the wiring resources, ensures the robustness of the power network, and avoids a series of problems such as local signal congestion and timing disorders.

[0045] Based on this, continue to refer to Figure 2As shown, in the second die D2, the second metal power network 20 includes a first power line VDD1, a second power line VDD2, and a first ground line VSS1 connected to the power shutdown unit 21. In the first die D1, the first metal power network 10 includes a third power line VDD3 and a second ground line VSS2 connected to the logic circuit 11. The first power line VDD1 is connected to the second power line VDD2 via the power shutdown unit 21, and the second power line VDD2 and the third power line VDD3 are connected at the bonding surface M. In this case, the power shutdown unit 21 is connected between the first power line VDD1 and the second power line VDD2, and the power path between them can be controlled. The second power line VDD2 is connected to the logic circuit 11 via the third power line VDD3, thus the power supply to the logic circuit 11 can be controlled by controlling the power shutdown unit 21.

[0046] Additionally, refer to Figure 2 As shown, the first ground line VSS1 in the second metal power network 20 and the second ground line VSS2 in the first metal power network 10 can be connected at the bonding surface M. Ground voltage is provided to the power shutdown unit 21 through the first ground line VSS1, and ground voltage is provided to the logic circuit 11 through the first ground line VSS1 and the second ground line VSS2.

[0047] Furthermore, a power connection pad P1 (VDD pad) and a ground connection pad P2 (VSS pad) are provided on the back side of the second die D2 (or the second substrate Sub). The power connection pad P1 is connected to the first ground line VSS1 and is used to provide power voltage to the power shutdown unit 21 and the logic circuit 11. The ground connection pad P2 is connected to the first ground line VSS1 and is used to provide ground voltage to the power shutdown unit 21 and the logic circuit 11 to meet the normal power supply requirements of the power shutdown unit 21 and the logic circuit 11.

[0048] This application does not limit the configuration of the power connection plate P1 and the ground connection plate P2. In practice, they can be configured as needed, such as micro bumps (bump / μbump), copper pillars (Cu pillar), hybrid bonding points, etc.

[0049] In existing technologies, because the power-off unit and the logic circuit are disposed on the same substrate, their distribution can mutually restrict each other. Illustrated, existing power-off unit arrangements can be broadly categorized into array arrangements (…). Figure 3 ) and circular distribution pattern ( Figure 4 ). refer to Figure 3As shown, in the array arrangement, power-off units are added to the logic cells in columns at regular intervals. This distribution requires a large number of power lines to be arranged above the power-off units, thus consuming significant wiring resources. (Reference) Figure 4 As shown, in the ring distribution method, the power-off unit surrounds the logic unit. This distribution method has the problem of high current resistance voltage drop (IR drop).

[0050] In contrast, with the design scheme of this application, since the power-off unit 21 and the logic circuit 11 are separately disposed on different substrates, the distribution of the power-off unit 21 and the distribution of the logic circuit 11 will not restrict each other, and the distribution of the power-off unit 21 can be flexibly adjusted according to the needs of the logic circuit 11, thereby avoiding the problems of occupying a large amount of winding resources and high current resistance voltage drop (IR drop) that occur in the prior art.

[0051] As illustrated, in some possible implementations, the power shutdown unit 21 and the corresponding metal power network (10, 20) can be flexibly designed according to the power consumption density of the logic circuit in different regions of the first die. By optimizing the power shutdown unit 21 and the metal power network (10, 20), the power supply of local high power density areas can be strengthened in a targeted manner to better meet the needs of the chip.

[0052] The aforementioned power density refers to the total energy consumption of the chip per unit projected area.

[0053] For illustrative purposes only, please refer to the following: Figure 5 As shown, in some possible implementations, the first die D1 includes a first region A1 and a second region A2, where the power density of the first region A1 is greater than that of the second region A2. The second die D2 includes a third region A3 and a fourth region A4. The power-off unit 21 in the third region A3 is connected to the logic circuit 11 in the first region A1 through a first local metal power network, and the power-off unit 21 in the fourth region A4 is connected to the logic circuit 11 in the third region A3 through a second local metal power network.

[0054] The aforementioned first local metal power network is part of the first metal power network 10 and the second metal power network 20, and is used to connect the logic circuit 11 in the first region A1 to the power shutdown unit 21 in the third region A3, so that the power control of the logic circuit 11 in the first region A1 can be realized through the power shutdown unit 21 in the third region A3.

[0055] The aforementioned second local metal power network is part of the first metal power network 10 and the second metal power network 20, and is used to connect the logic circuit 11 in the second region A2 to the power shutdown unit 21 in the fourth region A4, so that the power control of the logic circuit 11 in the second region A2 can be realized through the power shutdown unit 21 in the fourth region A4.

[0056] Based on this, continue to refer to Figure 5 As shown, the density of power-off units 21 in the third region A3 can be set to be greater than that in the fourth region A4. That is, for the high power consumption density in the first region A1, the density of power-off units 21 in the third region A3 is increased accordingly to strengthen this part of the power supply and meet the power supply requirements of the logic circuit 11 in the first region A1.

[0057] Of course, on this basis, the robustness of the first local metal power network (including power lines, ground lines, etc.) connected between the first region A1 and the third region A3 can be increased to further enhance the power supply capability of the logic circuit 11 in the first region A1.

[0058] For example, in some possible implementations, the wiring density in the first local metal power network can be set to be greater than that in the second local metal power network, thereby enhancing the robustness of the first local metal power network and thus improving the power supply capability to the first region A1.

[0059] For example, in some possible implementations, the trace width (i.e., line width) in the first local metal power network can be set to be greater than the trace width in the second local metal power network, thereby enhancing the robustness of the first local metal power network and thus improving the power supply capability to the first region A1.

[0060] In addition, it should be noted that this application does not restrict the relative positions of the first region A1 and the third region A3, or the relative positions of the second region A2 and the fourth region A4.

[0061] As shown in the illustration, among some possible implementation methods, see reference. Figure 5 As shown, the projections of the first region A1 and the third region A3 onto the second substrate can overlap, either completely or partially. In this case, the power-off unit 21 in the third region A3 is located directly below the first region A1. This shortens the path of the first local metal power network connecting the first region A1 and the third region A3, thus improving the power supply capability of the power network.

[0062] Similarly, in some possible implementation methods, refer to Figure 5As shown, the projections of the second region A2 and the fourth region A4 onto the second substrate can overlap, either completely or partially. In this case, the power-off unit 21 in the fourth region A4 is located directly below the second region A2. This shortens the path of the second local metal power network connecting the second region A2 and the fourth region A4, thus improving the power supply capability of the power network.

[0063] Based on this, refer to Figure 6 As shown, in some other possible implementations, a partial power-off unit 22 (also referred to as a second power-off unit) can be provided in the first die D1. In this case, the first metal power network 10 may also include a fourth power line VDD4 and a fifth power line VDD5. The power-off unit 22 is connected between the fourth power line VDD4 and the fifth power line to control the on / off of the power path between the fourth power line VDD4 and the fifth power line VDD5. The fourth power line VDD4 is connected to the second metal power network 20 (such as the first power line VDD1), and the fifth power line VDD5 is connected to a portion of the logic circuit 11. In this way, the power supply to the portion of the logic circuit 11 can be controlled by the second power-off unit 22.

[0064] In this case, some logic circuits 11 are powered by the power-off unit 21 in the second die D2, and some logic circuits 11 are powered by the power-off unit 22 inside the first die D1, which enables the chip to have greater design flexibility.

[0065] Of course, the power shutdown unit 22 is also connected to the ground wire (VSS2) in the first die D1 to provide ground voltage through the ground wire, thereby meeting the power supply requirements.

[0066] The configuration of the power-off unit 22 in the first die D1 and the power-off unit 21 in the second die D2 can be the same or different. This application does not impose any restrictions on this, and the configuration can be made as needed in practice.

[0067] As illustrated, the multiple power-off units 22 in the first die D1 can be at least one of the control devices such as multi-threshold CMOS units, PMOS power transistors, and LDMOS power transistors, but are not limited to this.

[0068] In addition, embodiments of this application also provide a method for manufacturing a chip, such as... Figure 7 As shown, the manufacturing method may include:

[0069] Step 100, Reference Figure 8As shown, a first die D1 is provided, including: fabricating a logic circuit 11 on a first substrate Sub1, and fabricating a first metal power network 10 on the logic circuit 11; wherein the first metal power network 10 is electrically connected to the logic circuit 11.

[0070] As shown in the illustration, among some possible implementation methods, see reference. Figure 8 As shown, a first substrate Sub1 (such as a silicon substrate) is provided, on which a logic device layer (such as a field-effect transistor) is fabricated, and on which a metal wiring layer is fabricated, to form a logic circuit 11. Then, a first metal power network 10 is fabricated on the logic circuit 11. This first metal power network 10 may include a third power line VDD3, a second ground line VSS2, etc., connected to the logic circuit 11; details can be found in the aforementioned descriptions and will not be repeated here. Finally, a connection structure can be fabricated on the top layer for subsequent bonding.

[0071] Step 200, Reference Figure 9 As shown, a second die D2 is provided, comprising: fabricating a plurality of power-off units 21 on a second substrate Sub2, and fabricating a second metal power network 20 on the power-off units 21. The second metal power network 20 includes a first power line VDD1 and a second power line VDD2. The plurality of power-off units 21 are connected between the first power line VDD1 and the second power line VDD2, and are used to supply power to the logic circuit 11 by controlling the on / off state between the first power line VDD1 and the second power line VDD2.

[0072] As shown in the illustration, among some possible implementation methods, see reference. Figure 9 As shown, a second substrate Sub2 (such as a silicon substrate) is provided, and multiple power-off units 21 (such as MTCMOS) are fabricated on the second substrate Sub2. A second metal power network 20 is fabricated on the multiple power-off units 21. The second metal power network 20 may include a first power line VDD1, a second power line VDD2, a first ground line VSS1, etc., connected to the multiple power-off units 21. The multiple power-off units 21 are connected between the first power line VDD1 and the second power line VDD2 to control the on / off state between the first power line VDD1 and the second power line VDD2. Finally, an interconnect structure can be fabricated on the top layer for subsequent bonding.

[0073] Step 300, Reference Figure 10 As shown, the side of the first die D1 with the first metal power network 10 is bonded to the side of the second die D2 with the second metal power network 20; the second power line VDD2 is connected to the first metal power network 10 at the bonding surface M.

[0074] Schematic, in some possible implementations, the front side of the first die D1 (i.e., the side where the first metal power network 10 is located) and the front side of the second die D2 (i.e., the side where the second metal power network 20 is located) are mixed-bonded. In this case, the second power line VDD2 is connected to the first power line VDD1 at the bonding surface M, and the first ground line VSS1 is connected to the second ground line VSS2 at the bonding surface M. In this way, power control of the logic circuit 11 is achieved through multiple power-off units 21.

[0075] The first die D1 and the second die D2 mentioned above can be C2C (chip to chip) bonding or W2W (wafer to wafer) bonding, and this application does not limit them in this regard.

[0076] Of course, after step 300, subsequent manufacturing processes can be carried out according to the needs of the chip. This application does not impose any restrictions on this, and in practice, manufacturing can be carried out according to actual needs.

[0077] It should be understood that, in the embodiments of this application, the order of the above-mentioned processes does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.

[0078] For other related content in the above manufacturing method, please refer to the corresponding description in the chip structure section above, which will not be repeated here; for other settings in the above chip structure embodiment, please refer to the above manufacturing method and related manufacturing methods for adjustment, which will not be repeated here.

[0079] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A chip, characterized in that, It includes a first die and a second die, and the first die and the second die are connected by a bonding surface; The first die includes a first substrate and a logic circuit and a first metal power network disposed on the first substrate. The first metal power network is located on the side of the logic circuit closer to the bonding surface, and the first metal power network is electrically connected to the logic circuit. The second die includes a second substrate and a plurality of first power-off units and a second metal power network disposed on the second substrate; the second metal power network is located on the side of the first power-off unit near the bonding surface, and the second metal power network is connected to the plurality of first power-off units. The second metal power network includes a first power line and a second power line; the plurality of first power shutdown units are connected between the first power line and the second power line, and the second power line is connected to the first metal power network at the bonding surface. The plurality of first power-off units are used to supply power to the logic circuit by controlling the on / off state between the first power line and the second power line.

2. The chip according to claim 1, characterized in that, The first die includes a first region and a second region, wherein the power density of the first region is greater than the power density of the second region; The second wafer includes a third region and a fourth region; The first metal power network and the second metal power network include a first local metal power network and a second local metal power network; The first power-off unit located in the third region is connected to the logic circuit located in the first region through the first local metal power network, and the first power-off unit located in the fourth region is connected to the logic circuit located in the second region through the second local metal power network. The density of the first power-off unit located in the third region is greater than the density of the first power-off unit located in the fourth region.

3. The chip according to claim 2, characterized in that, The wiring density in the first local metal power network is greater than the wiring density in the second local metal power network.

4. The chip according to claim 2 or 3, characterized in that, The trace width in the first local metal power network is greater than the trace width in the second local metal power network.

5. The chip according to any one of claims 2-4, characterized in that, The projections of the first region and the third region onto the second substrate have overlapping areas.

6. The chip according to any one of claims 1-5, characterized in that, The first metal power network includes a third power line connected to the logic circuit; The third power line is connected to the second power line at the bonding surface.

7. The chip according to any one of claims 1-6, characterized in that, The second die also includes: a power connection plate and a ground connection plate; The power connection pad and the ground connection pad are located on the side of the second substrate away from the second metal power network; The second metal power network also includes a first grounding wire connected to the plurality of first power shutdown units, and the first metal power network also includes a second grounding wire connected to the logic circuit; The power connector is connected to the first power cord; The grounding connection plate is connected to the first grounding wire, and the first grounding wire and the second grounding wire are electrically connected at the bonding surface.

8. The chip according to any one of claims 1-7, characterized in that, The first die also includes a plurality of second power-off units disposed on the first substrate; The first metal power network includes a fourth power line and a fifth power line; The plurality of second power shutdown units are connected between the fourth power line and the fifth power line, and are used to supply power to the logic circuit by controlling the on / off state between the fourth power line and the fifth power line; The fourth power line is connected to the second metal power network, and the fifth power line is connected to the logic circuit.

9. A method for manufacturing a chip, characterized in that, include: Providing a first die includes: fabricating a logic circuit on a first substrate and fabricating a first metal power network on the logic circuit; wherein the first metal power network is electrically connected to the logic circuit; Providing a second die includes: fabricating a plurality of first power-off units on a second substrate, and fabricating a second metal power network on the first power-off units; wherein the second metal power network includes a first power line and a second power line; the plurality of first power-off units are connected between the first power line and the second power line, and are used to supply power to the logic circuit by controlling the on / off state between the first power line and the second power line; The side of the first die with the first metal power network is bonded to the side of the second die with the second metal power network; the second power line is connected to the first metal power network at the bonding surface.

10. An electronic device, characterized in that, It includes a circuit board and a chip as described in any one of claims 1-8, wherein the chip is electrically connected to the circuit board.

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