A power amplifier module and its fabrication method

Abstract

This invention relates to the field of radio frequency technology, and particularly to a power amplifier module and its fabrication method. The method includes obtaining a substrate and forming a first cavity and a second cavity on the substrate; fixing a power amplifier chip and a power management chip respectively within the first cavity and the second cavity, and filling the first cavity and the second cavity with an insulating material, thereby encapsulating the power amplifier chip and the power management chip within the first cavity and the second cavity respectively; grinding the insulating material and the substrate to make the power amplifier chip and the power management chip flush with the surface of the substrate; compared with the prior art, this invention effectively improves the power efficiency and thermal stability of the power amplifier module.

Description

Technical Field

[0001] This invention relates to the field of radio frequency technology, and in particular to a power amplifier module and its fabrication method. Background Technology

[0002] With the rapid iteration of wireless communication technologies such as 5G and the Internet of Things, the market is placing increasingly higher demands on the power rating, energy efficiency, and integration of power amplifiers. As a core component in radio frequency (RF) communication systems, the performance of power amplifiers directly determines the transmission quality and coverage of the communication system. Gallium nitride (GaN), as a core representative material of third-generation wide-bandgap semiconductors, has significant advantages over first- and second-generation semiconductor materials, including wider operating frequency bands, higher operating voltages, higher power density per unit area, and higher thermal conductivity. Its electron mobility is 20 times that of silicon, and its breakdown electric field strength is 10 times that of silicon. It can operate stably at higher voltages, frequencies, and temperatures, and has become an important core direction for the future development of communication technologies, with increasingly widespread applications in the field of radio frequency (RF) / microwave power amplification.

[0003] GaN power semiconductor technology optimizes device structure, reduces parasitic elements, and employs shorter gate lengths and higher operating voltages, enabling GaN transistors to achieve higher output power density, wider bandwidth, and superior DC-to-RF conversion efficiency. Its power density can reach 3-5 times that of silicon-based devices, while its switching losses are only 1 / 5-1 / 10 of those of silicon-based devices. Compared with traditional semiconductor processes, GaN has irreplaceable advantages and has made a significant contribution to greatly improving the performance of RF / microwave power amplification, effectively meeting the application requirements of high power and high efficiency.

[0004] In practical applications, power amplifier modules not only need high reliability to ensure long-term stable operation, but also face stringent requirements regarding their overall size due to the miniaturization and integration trends in communication equipment. For high-power GaN power amplifier modules, the internal GaN chip is a depletion-type device. These devices are in a default conducting state under zero gate bias conditions, placing extremely stringent requirements on the power-on and power-off sequence of the gate and drain voltages. The principle of "negative first, positive second; positive first, negative second" must be strictly followed during power-on and power-off. Otherwise, unstable gate voltage or incorrect power-on sequence can easily cause a sudden surge in drain current, leading to device burnout. Therefore, additional negative voltage protection circuits and power-on sequence control circuits are required within the module to ensure safe and stable operation.

[0005] However, in existing power amplifier modules, the power control circuit is mostly composed of discrete circuits or multiple independent components. The modulation circuit occupies a large PCB area, which not only makes the overall module mounting process cumbersome and the production efficiency low, but also results in a large overall size of the final product. This makes it difficult to adapt to the installation requirements of miniaturized communication equipment and fails to achieve the dual technical goals of miniaturization and high reliability at the same time, thus limiting the promotion and application of GaN power semiconductor technology in miniaturized and high-reliability power amplification scenarios.

[0006] Therefore, there is an urgent need for a new power amplifier module and its fabrication method to solve the above-mentioned technical problems. Summary of the Invention

[0007] This invention provides a power amplifier module and its manufacturing method, aiming to provide a power amplifier module with small package size, high integration and good heat dissipation.

[0008] In a first aspect, the present invention provides a method for fabricating a power amplifier module, the method comprising the following steps:

[0009] S1. Obtain a substrate and form an inwardly recessed first cavity and a second cavity on the surface of the substrate. S2. Fix the power amplifier chip and the power management chip in the first cavity and the second cavity respectively, and fill the first cavity and the second cavity with insulating material, so that the power amplifier chip and the power management chip are respectively encapsulated in the first cavity and the second cavity; S3. Grind the same side of the insulating material and the substrate to make the power amplifier chip and the power management chip flush with the surface of the substrate; S4. An insulating dielectric layer is deposited on one side of the substrate after grinding to form a dielectric layer; and multiple micropores communicating with the first cavity and the second cavity are respectively opened on the dielectric layer based on photolithography. S5. A metal circuit layer is formed by sputtering and electroplating processes to deposit metal lines on the side of the dielectric layer away from the substrate, and one end of the metal line is electrically connected to the power amplifier chip and the power management chip through the micro-holes respectively, and the other end of the metal line extends to the surface of the dielectric layer away from the substrate. S6. The surface mount devices of the RF matching circuit and the power management chip are attached to the dielectric layer on the side away from the substrate, and the RF matching circuit and the power amplifier chip are bonded together by gold wire bonding. S7. A heat dissipation component is welded to the side of the substrate away from the dielectric layer to obtain the power amplifier module.

[0010] Preferably, the heat dissipation assembly includes a metal carrier plate welded and fixed to the side of the substrate away from the dielectric layer, and a metal heat sink material fixed to the side of the metal carrier plate away from the substrate; wherein the metal heat sink material and the metal carrier plate are sintered and fixed by metal solder material.

[0011] Preferably, the metal carrier plate is made of molybdenum-copper alloy, and the thermal conductivity of the metal carrier plate is 190~240 W / mK, and the coefficient of thermal expansion is 7×10⁻⁶. -6 / K~11×10 -6 / K.

[0012] Preferably, the metal heat sink material is a copper-molybdenum-copper alloy, and the thermal conductivity of the metal heat sink material is 200~280 W / mK, and the coefficient of thermal expansion is 8×10⁻⁶. -6 / K~12×10 -6 / K.

[0013] Preferably, the power management chip includes a DC-DC buck circuit, a gate voltage drive circuit, a gate voltage protection circuit, a first MOSFET, a second MOSFET, a first resistor, a first capacitor, a second capacitor, a third capacitor, and a fourth capacitor. The input terminal of the DC-DC buck circuit is used to receive an external DC voltage, and the output terminal of the DC-DC buck circuit is connected to the first input terminal of the gate voltage drive circuit. The DC-DC buck circuit is used to reduce the external DC voltage and output it to the gate voltage drive circuit. The second input terminal of the gate voltage driving circuit is used to receive external control signals. The output terminal of the gate voltage driving circuit is connected to the input terminal of the gate voltage protection circuit. The gate voltage driving circuit is used to generate an enable signal according to the external control signal and output it to the gate voltage protection circuit, and output a first driving voltage to the power amplifier chip. The first output terminal of the gate voltage protection circuit is connected to the gate of the first MOS transistor, and the second output terminal of the gate voltage protection circuit is connected to the gate of the second MOS transistor. The gate voltage protection circuit is used to control the first MOS transistor and the second MOS transistor to be turned on or off according to the received enable signal. The source of the first MOS transistor is used to receive the external DC voltage, and the drain of the first MOS transistor is used to output the second driving voltage to the power amplifier chip; The source of the second MOSFET is grounded, the drain of the second MOSFET is connected to the first terminal of the first resistor, and the second terminal of the first resistor is connected to the drain of the first MOSFET. The first terminal of the first capacitor and the first terminal of the second capacitor are respectively connected to the drain of the first MOS transistor. The second terminals of the first capacitor and the second terminals of the second capacitor are grounded. The first terminal of the third capacitor and the first terminal of the fourth capacitor are respectively connected to the output terminal of the gate voltage driving circuit. The second terminals of the third capacitor and the second terminals of the fourth capacitor are grounded.

[0014] Preferably, the radio frequency matching circuit includes an input matching circuit, an inter-stage matching circuit, and an output matching circuit, and the power amplifier chip includes a driver stage amplifier circuit and a final stage amplifier circuit. The input matching circuit, the driver stage amplifier circuit, the interstage matching circuit, the final stage amplifier circuit, and the output matching circuit are electrically connected in sequence.

[0015] Preferably, the substrate is a thermally conductive ceramic substrate.

[0016] Secondly, the present invention also provides a power amplifier module, which is manufactured using the power amplifier module manufacturing method described in any one of the above embodiments.

[0017] Compared with the prior art, the present invention creates a first cavity and a second cavity on the substrate and encapsulates the power amplifier chip and the power management chip within the first cavity and the second cavity, thereby enabling the power amplifier module to have superior RF performance, ultra-miniaturization and high reliability, and improving the power supply protection function of the power amplifier module. By selecting a metal heat sink material with high thermal conductivity and a metal carrier plate, the heat generated by the chip can be efficiently transferred downward to the casing base and carried away by the external heat dissipation system, effectively improving the power efficiency and thermal stability of the power amplifier module. Attached Figure Description

[0018] The present invention will now be described in detail with reference to the accompanying drawings. The above and other aspects of the present invention will become clearer and more readily understood through the detailed description following the accompanying drawings. In the drawings: Figure 1 This is a flowchart of the fabrication method of the power amplifier module provided in the embodiment of the present invention; Figure 2 This is a circuit block diagram of the power management chip of the power amplifier module provided in an embodiment of the present invention; Figure 3 This is a schematic diagram of the overall layout of the radio frequency path of the power amplifier module provided in an embodiment of the present invention; Figure 4 This is a schematic diagram of the substrate layer structure of the power amplifier module provided in an embodiment of the present invention; Figure 5 This is a schematic diagram of the overall hierarchical structure of the power amplifier module provided in an embodiment of the present invention; In the diagram, 100 is the power amplifier module; 1 is the substrate; 2 is the power amplifier chip; 21 is the driver stage amplifier circuit; 22 is the final stage amplifier circuit; 3 is the power management chip; 31 is the DC buck circuit; 32 is the gate voltage driver circuit; 33 is the gate voltage protection circuit; 4 is the RF matching circuit; 41 is the input matching circuit; 42 is the inter-stage matching circuit; 43 is the output matching circuit; 101 is the first cavity; 102 is the second cavity; 103 is the dielectric layer; 104 is the microvia; 105 is the metal wiring layer; 1051 is the pad window layer; 1052 is the solder mask layer; 1053 is the conductive via layer; 1054 is the RDL redistribution layer; 106 is the heat dissipation component; 1061 is the metal carrier board; 1062 is the metal heat sink material; and 1063 is the solder material. Detailed Implementation

[0019] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0020] Example 1 Please refer to Figures 1-4 The present invention provides a method for fabricating a power amplifier module 100, the method comprising the following steps: S1. Obtain substrate 1, and form an inwardly recessed first cavity 101 and a second cavity 102 on the surface of substrate 1.

[0021] In this embodiment of the invention, the substrate 1 is a thermally conductive ceramic substrate. By selecting a high thermal conductivity ceramic substrate, heat can be quickly conducted from the chip to the entire PCB.

[0022] S2. Fix the power amplifier chip 2 and the power management chip 3 in the first cavity 101 and the second cavity 102 respectively, and fill the first cavity 101 and the second cavity 102 with insulating material, so that the power amplifier chip 2 and the power management chip 3 are respectively encapsulated in the first cavity 101 and the second cavity 102.

[0023] S3. Grind the same side of the insulating material and the substrate 1 so that the power amplifier chip 2 and the power management chip 3 are flush with the surface of the substrate 1.

[0024] S4. An insulating dielectric layer is deposited on one side of the substrate 1 after grinding to form a dielectric layer 103; and a plurality of micropores 104 are formed on the dielectric layer 103 based on photolithography, which are respectively connected to the first cavity 101 and the second cavity 102.

[0025] S5. Metal lines are disposed on the side of the dielectric layer 103 away from the substrate 1 by sputtering and electroplating processes to form a metal line layer 105, and one end of the metal line is electrically connected to the power amplifier chip 2 and the power management chip 3 through the micro-hole 104 respectively, and the other end of the metal line extends to the surface of the dielectric layer 103 away from the substrate 1.

[0026] In this embodiment of the invention, the metal circuit layer 105 includes a pad window layer 1051, a solder mask layer 1052, a conductive via layer 1053, and an RDL redistribution layer 1054.

[0027] Among them, the pad window layer 1051 is used to precisely open the solder mask layer to expose the metal pads, delineate the soldering area, and realize the SMT assembly connection between the module and the external motherboard.

[0028] The solder mask layer 1052 is used to fully cover the non-soldered metal circuits, providing insulation, short circuit protection, oxidation resistance, mechanical scratch resistance, and reduced radio frequency loss protection.

[0029] The conductive via layer 1053 is used to build electrical interconnection channels between RDL wiring and chip pads in the cavity and to assist in heat conduction.

[0030] RDL redistribution layer 1054 is used to reconstruct the chip's micro pad traces, integrate RF matching and power / ground lines, and realize planar transmission of signal, power supply, and ground lines. S6, the RF matching circuit 4 and the surface mount device of the power management chip 3 are mounted on the dielectric layer 103 on the side away from the substrate 1, and the RF matching circuit 4 and the power amplifier chip 2 are bonded together with gold wire. In this embodiment of the invention, gold wire bonding refers to a wire bonding process that uses high-purity gold wire as a conductive medium and combines thermo-pressing / ultrasonic bonding to achieve mechanical fixation and electrical conduction between the pads of the power amplifier chip 2 and the pads of the radio frequency matching circuit 4.

[0031] S7. Heat dissipation component 106 is welded to the side of the substrate 1 away from the dielectric layer 103 to obtain the power amplifier module 100.

[0032] In this embodiment of the invention, the heat dissipation assembly 106 includes a metal carrier plate 1061 welded and fixed to the side of the substrate 1 away from the dielectric layer 103, and a metal heat sink material 1062 fixed to the side of the metal carrier plate 1061 away from the substrate 1; wherein the metal heat sink material 1062 and the metal carrier plate 1061 are sintered and fixed together by metal solder. The heat dissipation assembly 106 also includes solder material 1063, which is sintered between the metal carrier plate 1061 and the metal heat sink material 1062, and can bond and fix the two heat dissipation substrates; fill the interface gap to reduce thermal resistance and efficiently dissipate chip heat; buffer the thermal stress generated by thermal cycling and avoid interface delamination and cracking; and simultaneously conduct the two to form a complete ground plane, improving radio frequency grounding performance.

[0033] In this embodiment of the invention, the metal carrier plate 1061 is made of molybdenum-copper alloy, and the thermal conductivity of the metal carrier plate 1061 is 190~240 W / mK, and the coefficient of thermal expansion is 7×10⁻⁶. -6 / K~11×10 -6 / K.

[0034] The metal heat sink material 1062 is made of copper-molybdenum-copper alloy, and has a thermal conductivity of 200~280 W / mK and a coefficient of thermal expansion of 8×10⁻⁶. -6 / K~12×10 -6 / K.

[0035] By selecting copper-molybdenum copper, which has high thermal conductivity, as the metal heat sink material 1062 of the power amplifier module 100, and to avoid the problem of thermal expansion coefficient mismatch, molybdenum copper, which has high thermal conductivity and a thermal expansion coefficient similar to that of the metal heat sink material 1062, is selected as the metal carrier 1061. The metal carrier 1061 and the metal heat sink material 1062 are sintered together with metal solder. This heat dissipation method ensures that the heat generated by the chip can be efficiently transferred downward to the casing base and finally carried away by the external heat dissipation system, which greatly improves the power efficiency and thermal reliability of the power amplifier module 100.

[0036] In this embodiment of the invention, the power management chip 3 includes a DC step-down circuit 31, a gate voltage driving circuit 32, a gate voltage protection circuit 33, a first MOSFET M1, a second MOSFET M2, a first resistor R1, a first capacitor C1, a second capacitor C2, a third capacitor C3, and a fourth capacitor C4. The input terminal of the DC-DC step-down circuit 31 is used to receive external DC voltage, and the output terminal of the DC-DC step-down circuit 31 is connected to the first input terminal of the gate voltage driving circuit 32. The DC-DC step-down circuit 31 is used to reduce the external DC voltage and output it to the gate voltage driving circuit 32. The second input terminal of the gate voltage driving circuit 32 is used to receive the external control signal TTL. The output terminal of the gate voltage driving circuit 32 is connected to the input terminal of the gate voltage protection circuit 33. The gate voltage driving circuit 32 is used to generate an enable signal according to the external control signal and output it to the gate voltage protection circuit 33, and output the first driving voltage VG to the power amplifier chip 2. The first output terminal of the gate voltage protection circuit 33 is connected to the gate of the first MOS transistor M1, and the second output terminal of the gate voltage protection circuit 33 is connected to the gate of the second MOS transistor M2. The gate voltage protection circuit 33 is used to control the first MOS transistor M1 and the second MOS transistor M2 to be turned on or off according to the received enable signal. The source of the first MOS transistor M1 is used to receive the external DC voltage, and the drain of the first MOS transistor M1 is used to output the second driving voltage VD to the power amplifier chip 2; The source of the second MOS transistor M2 is grounded, the drain of the second MOS transistor M2 is connected to the first end of the first resistor R1, and the second end of the first resistor R1 is connected to the drain of the first MOS transistor M1; wherein, the first MOS transistor M1 is a PMOS transistor and the second MOS transistor M2 is an NMOS transistor.

[0037] The first terminal of the first capacitor C1 and the first terminal of the second capacitor C2 are respectively connected to the drain of the first MOS transistor M1. The second terminal of the first capacitor C1 and the second terminal of the second capacitor C2 are grounded. The first terminal of the third capacitor C3 and the first terminal of the fourth capacitor C4 are respectively connected to the output terminal of the gate voltage driving circuit 32. The second terminal of the third capacitor C3 and the second terminal of the fourth capacitor C4 are grounded.

[0038] When the power management chip 3 is working, the external DC voltage enters the power management chip 3 from the input terminal (Vin port) of the DC buck circuit 31. The gate voltage drive circuit 32 generates the negative voltage required for operation. The internal control logic module of the power management chip 3 first performs an EN enable judgment. The judgment condition is whether a negative voltage is generated. When the EN enable is turned on and the external control signal TTL is high, the voltage enters the first MOSFET M1. If the threshold voltage is met, the first MOSFET M1 is turned on, and the voltage outputs the second drive voltage (VD port) to the power amplifier chip 2. When the EN enable is turned on and the external control signal TTL is low, the first MOSFET M1 is turned off, and the voltage enters the second MOSFET M2, which discharges all the remaining charge on the load, thereby improving the conversion efficiency of the load voltage.

[0039] In this embodiment of the invention, the radio frequency matching circuit 4 includes an input matching circuit 41, an interstage matching circuit 42, and an output matching circuit 43, and the power amplifier chip 2 includes a driver stage amplifier circuit 21 and a final stage amplifier circuit 22. The input matching circuit 41, the driver stage amplifier circuit 21, the interstage matching circuit 42, the final stage amplifier circuit 22, and the output matching circuit 43 are electrically connected in sequence.

[0040] In this embodiment of the invention, since the power management chip 3 and the power amplifier chip 2 are packaged in the cavity of the substrate 1, all the pads that need to be connected are led to the upper layer of the substrate 1 through the wiring of the metal line layer 105. The input terminal Vin and the module-level control signal (TTL) of the DC power supply section are connected to the Vin and TTL signal pads on the upper layer of the substrate 1. The output terminal outputs the gate voltage and drain voltage required by the power amplifier chip 2, which are supplied to the driver stage amplifier circuit 21 and the final stage amplifier circuit 22 through the wiring on the upper layer of the substrate 1. In the radio frequency section, the power amplifier chip 2 and the radio frequency matching circuit 4 are connected by gold wire bonding. The radio frequency signal is input to the input matching circuit 41 and connected to the input terminal of the driver stage amplifier circuit 21 by gold wire bonding. The output pad of the driver stage amplifier circuit 21 is connected to the input terminal of the interstage matching circuit 42 by gold wire bonding. The output terminal of the interstage matching circuit 42 is connected to the input terminal of the final stage amplifier circuit 22. The output terminal of the final stage amplifier circuit 22 is connected to the output matching circuit 43.

[0041] Compared with the prior art, the present invention creates a first cavity and a second cavity on the substrate and encapsulates the power amplifier chip and the power management chip within the first cavity and the second cavity, thereby enabling the power amplifier module to have superior RF performance, ultra-miniaturization and high reliability, and improving the power supply protection function of the power amplifier module. By selecting a metal heat sink material with high thermal conductivity and a metal carrier plate, the heat generated by the chip can be efficiently transferred downward to the casing base and carried away by the external heat dissipation system, effectively improving the power efficiency and thermal stability of the power amplifier module.

[0042] Example 2 This invention also provides a power amplifier module, which is manufactured using the same method as described in the above embodiments and achieves the same technical effect. Please refer to the description in the above embodiments, which will not be repeated here.

[0043] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0044] The embodiments of the present invention have been described above with reference to the accompanying drawings. The disclosed embodiments are merely preferred embodiments of the present invention. However, the present invention is not limited to the specific embodiments described above. The specific embodiments described above are merely illustrative and not restrictive. Those skilled in the art can make many equivalent changes in form without departing from the spirit and scope of the claims of the present invention, and all such changes are within the protection scope of the present invention.

Claims

1. A method for fabricating a power amplifier module, characterized in that, The preparation method includes the following steps: S1. Obtain a substrate and form an inwardly recessed first cavity and a second cavity on the surface of the substrate. S2. Fix the power amplifier chip and the power management chip in the first cavity and the second cavity respectively, and fill the first cavity and the second cavity with insulating material, so that the power amplifier chip and the power management chip are respectively encapsulated in the first cavity and the second cavity; S3. Grind the same side of the insulating material and the substrate to make the power amplifier chip and the power management chip flush with the surface of the substrate; S4. An insulating dielectric layer is deposited on one side of the substrate after grinding to form a dielectric layer; and multiple micropores communicating with the first cavity and the second cavity are respectively opened on the dielectric layer based on photolithography. S5. A metal circuit layer is formed by sputtering and electroplating processes to deposit metal lines on the side of the dielectric layer away from the substrate, and one end of the metal line is electrically connected to the power amplifier chip and the power management chip through the micro-holes respectively, and the other end of the metal line extends to the surface of the dielectric layer away from the substrate. S6. The surface mount devices of the RF matching circuit and the power management chip are attached to the dielectric layer on the side away from the substrate, and the RF matching circuit and the power amplifier chip are bonded together by gold wire bonding. S7. A heat dissipation component is welded to the side of the substrate away from the dielectric layer to obtain the power amplifier module; The heat dissipation assembly includes a metal carrier plate welded and fixed to the side of the substrate away from the dielectric layer, and a metal heat sink material fixed to the side of the metal carrier plate away from the substrate; wherein the metal heat sink material and the metal carrier plate are sintered and fixed by metal solder material.

2. The method for fabricating the power amplifier module as described in claim 1, characterized in that, The metal carrier plate is made of molybdenum-copper alloy, and its thermal conductivity is 190~240 W / mK, with a coefficient of thermal expansion of 7×10⁻⁶. -6 / K~11×10 -6 / K.

3. The method for fabricating the power amplifier module as described in claim 1, characterized in that, The metal heat sink material is a copper-molybdenum-copper alloy, and its thermal conductivity is 200~280 W / mK, with a coefficient of thermal expansion of 8×10⁻⁶. -6 / K~12×10 -6 / K.

4. The method for fabricating the power amplifier module as described in claim 1, characterized in that, The power management chip includes a DC-DC buck circuit, a gate voltage drive circuit, a gate voltage protection circuit, a first MOSFET, a second MOSFET, a first resistor, a first capacitor, a second capacitor, a third capacitor, and a fourth capacitor. The input terminal of the DC-DC buck circuit is used to receive an external DC voltage, and the output terminal of the DC-DC buck circuit is connected to the first input terminal of the gate voltage drive circuit. The DC-DC buck circuit is used to reduce the external DC voltage and output it to the gate voltage drive circuit. The second input terminal of the gate voltage driving circuit is used to receive external control signals. The output terminal of the gate voltage driving circuit is connected to the input terminal of the gate voltage protection circuit. The gate voltage driving circuit is used to generate an enable signal according to the external control signal and output it to the gate voltage protection circuit, and output a first driving voltage to the power amplifier chip. The first output terminal of the gate voltage protection circuit is connected to the gate of the first MOS transistor, and the second output terminal of the gate voltage protection circuit is connected to the gate of the second MOS transistor. The gate voltage protection circuit is used to control the first MOS transistor and the second MOS transistor to be turned on or off according to the received enable signal. The source of the first MOS transistor is used to receive the external DC voltage, and the drain of the first MOS transistor is used to output the second driving voltage to the power amplifier chip; The source of the second MOSFET is grounded, the drain of the second MOSFET is connected to the first terminal of the first resistor, and the second terminal of the first resistor is connected to the drain of the first MOSFET. The first terminal of the first capacitor and the first terminal of the second capacitor are respectively connected to the drain of the first MOS transistor. The second terminals of the first capacitor and the second terminals of the second capacitor are grounded. The first terminal of the third capacitor and the first terminal of the fourth capacitor are respectively connected to the output terminal of the gate voltage driving circuit. The second terminals of the third capacitor and the second terminals of the fourth capacitor are grounded.

5. The method for fabricating the power amplifier module as described in claim 1, characterized in that, The radio frequency matching circuit includes an input matching circuit, an inter-stage matching circuit, and an output matching circuit; the power amplifier chip includes a driver stage amplifier circuit and a final stage amplifier circuit. The input matching circuit, the driver stage amplifier circuit, the interstage matching circuit, the final stage amplifier circuit, and the output matching circuit are electrically connected in sequence.

6. The method for fabricating the power amplifier module as described in claim 1, characterized in that, The substrate is a thermally conductive ceramic substrate.

7. A power amplifier module, characterized in that, The power amplifier module is manufactured using the method described in any one of claims 1-6.

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