A semiconductor package structure and a packaging method

Abstract

This invention provides a semiconductor packaging structure and packaging method, relating to the field of chip packaging technology. The semiconductor packaging structure includes a lower boss, a chip, and an upper boss. The back side of the chip is soldered to the lower boss using a flowable adhesive, and the front side of the chip is soldered to the upper boss using a patterned DAF film. The patterned DAF film includes at least two mutually discrete outer bonding islands, with a cutout area between the outer bonding islands. The packaging method includes the following steps: applying a flowable adhesive to the lower boss, attaching the back side of the chip to the lower boss, attaching the upper boss to the front side of the chip using the DAF film, and then curing. This invention uses a DAF film to solder the upper boss to the front side of the chip. The DAF film is a solid adhesive material, solving the problems of excess adhesive, uneven curvature, and voids that easily occur when using a flowable adhesive between the front side of the chip and the upper boss in the prior art.

Description

Technical Field

[0001] This invention relates to the field of chip packaging technology, and in particular to a semiconductor packaging structure and packaging method. Background Technology

[0002] In semiconductor packaging products using double-sided boss technology, the top and bottom surfaces of the chip are bonded to upper and lower bosses respectively, both using a flowable adhesive. However, during the mounting of the upper boss, because the bottom of the chip is not yet cured between it and the lower boss, the flowable adhesive between the chip and the lower boss is prone to overflow due to stress. The chip itself may also tilt, resulting in uneven thickness of the flowable adhesive on the upper boss due to chip tilt, and it may even spread to the sides of the chip, leading to electrical failure of the product. Furthermore, during the curing process, the flowable adhesive may shrink, pulling on the upper boss. During subsequent injection molding and curing, the upper boss is subjected to resin expansion and compression, creating gaps between it and the chip, causing electrical failure of the product. Summary of the Invention

[0003] In a first aspect, the present invention provides a semiconductor packaging structure, including a lower boss, a chip, and an upper boss. The back side of the chip is soldered to the lower boss by a flowable adhesive, and the front side of the chip is soldered to the upper boss by a patterned DAF film. The patterned DAF film includes at least two mutually discrete outer bonding islands, and the area between the outer bonding islands is a hollow area.

[0004] In an optional implementation, the patterned DAF film is a four-corner island bridge pattern, comprising four outer bonding islands located at the four corners of a rectangular area.

[0005] In an optional embodiment, the patterned DAF film further includes a central bonding island located at the geometric center of the rectangular region, with a hollow area between the central bonding island and the outer bonding island.

[0006] In an optional implementation, the patterned DAF film is a hexagonal island bridge pattern, comprising six outer bonding islands located at the six corners of a hexagonal region.

[0007] In an optional embodiment, the lower boss is disposed on the frame or substrate, the upper boss is disposed on one end of the jumper, and the other end of the jumper is connected to the frame or substrate.

[0008] The semiconductor packaging structure provided by this invention has the following beneficial effects: 1. The back of the chip is soldered to the lower boss using a conventional fluid adhesive, and the upper boss is soldered to the front of the chip using a DAF film. The DAF film is a solid adhesive material, which solves the problems of glue overflow, uneven curvature, and holes that are easily caused when using fluid adhesive between the front of the chip and the upper boss in the existing technology. In addition, the DAF film is easy to pre-form on the upper boss, which facilitates the optimization of the packaging process. 2. The patterned DAF film includes at least two mutually discrete outer bonding islands, with a hollow area between the outer bonding islands. The discrete outer bonding islands can decompose the continuous shrinkage stress, and the hollow area can release thermal stress and reduce the risk of chip tilting.

[0009] In a second aspect, the present invention provides a semiconductor packaging method, characterized by comprising the following steps: Provide a lower boss, apply a flowable adhesive to the lower boss, and mount the back of the chip to the lower boss; A top boss is provided, and a patterned DAF film is pre-coated on the top boss. The patterned DAF film includes at least two mutually discrete outer bonding islands, and there is a cutout area between the outer bonding islands. The top boss is attached to the front side of the chip through the DAF film. The process involves curing to obtain a semiconductor package structure.

[0010] In an optional implementation, during curing, the upper boss and the front side of the chip are cured at a first preset temperature, and the chip and the lower boss are cured at a second preset temperature, wherein the first preset temperature is lower than the second preset temperature.

[0011] In an optional implementation, the patterned DAF film is a four-corner island bridge pattern, comprising four outer bonding islands located at the four corners of a rectangular area.

[0012] In an optional embodiment, the patterned DAF film further includes a central bonding island located at the geometric center of the rectangular region, with a hollow area between the central bonding island and the outer bonding island.

[0013] In an optional implementation, the patterned DAF film is a hexagonal island bridge pattern, comprising six outer bonding islands located at the six corners of a hexagonal region.

[0014] The semiconductor packaging method provided by this invention has the following beneficial effects: 1. The back of the chip is soldered to the lower boss using a conventional fluid adhesive, and the upper boss is soldered to the front of the chip using a DAF film. The DAF film is a solid adhesive material, which solves the problems of glue overflow, uneven curvature, and holes that are easily caused when using fluid adhesive between the front of the chip and the upper boss in the existing technology. In addition, the DAF film is pre-formed on the upper boss, which optimizes the packaging process. 2. The patterned DAF film includes at least two mutually discrete outer bonding islands, with a hollow area between the outer bonding islands. During curing, the discrete outer bonding islands can decompose the continuous shrinkage stress, and the hollow area can release thermal stress, reducing the risk of chip tilting. Attached Figure Description

[0015] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0016] Figure 1 This is a schematic diagram of the semiconductor packaging method using double-sided boss technology in the prior art; Figure 2 This is a schematic diagram of a semiconductor packaging structure using a double-sided boss process in the prior art; Figure 3 This is one of the schematic diagrams illustrating defects in semiconductor packaging structures using double-sided boss technology in the prior art; Figure 4 This is the second schematic diagram illustrating the defects of semiconductor packaging structures using double-sided boss technology in the prior art. Figure 5 This is the third schematic diagram illustrating the defects of semiconductor packaging structures using double-sided boss technology in the prior art; Figure 6 A schematic flowchart of a semiconductor packaging method provided in an embodiment of the present invention; Figure 7 This is a schematic diagram of the semiconductor packaging structure provided in an embodiment of the present invention; Figure 8 This is a schematic diagram of the DAF film in the semiconductor packaging structure provided in an embodiment of the present invention.

[0017] Icons: 100 - Frame; 110 - Lower boss; 200 - Chip; 300 - Jumper; 310 - Upper boss; 400 - DAF membrane; 410 - Outer bonding island; 420 - Center bonding island; 500 - Flowable adhesive. Detailed Implementation

[0018] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. The components of the embodiments of the present invention described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0019] Therefore, the following detailed description of the embodiments of the invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the invention without inventive effort are within the scope of protection of the invention.

[0020] It should be noted that similar labels and letters in the following figures indicate similar items. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures.

[0021] In the description of this invention, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship commonly used when the product of this invention is in use. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this invention. In addition, the terms "first," "second," "third," etc., are only used to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0022] Furthermore, terms such as "horizontal," "vertical," and "sag" do not imply that components must be absolutely horizontal or suspended, but rather that they can be slightly tilted. For example, "horizontal" simply means that its direction is more horizontal relative to "vertical," and does not mean that the structure must be completely horizontal, but can be slightly tilted.

[0023] In the description of this invention, it should also be noted that, unless otherwise explicitly specified and limited, the terms "set," "install," "connect," and "link" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances.

[0024] The following detailed description of some embodiments of the present invention is provided in conjunction with the accompanying drawings. Unless otherwise specified, the following embodiments and features can be combined with each other.

[0025] Figure 1 This is a schematic diagram of the semiconductor packaging method using a double-sided boss process in the prior art. Figure 2 This is a schematic diagram of a semiconductor packaging structure using a double-sided boss process in the prior art, such as... Figure 1 and Figure 2 As shown, in the prior art, in the semiconductor packaging structure and method of double-sided boss process, the back side and front side of chip 200 are respectively soldered to the lower boss 110 and the upper boss 310 using a fluid adhesive 500. The fluid adhesive 500 can specifically be solder paste, silver paste, etc.

[0026] However, during the mounting of the upper boss 310, because the bottom of the chip 200 and the lower boss 110 are not yet cured, the fluid adhesive 500 between the chip 200 and the lower boss 110 is prone to overflow under pressure. Figure 3 As shown, the damage can even spread to the sides of chip 200, causing electrical failure in the product. Simultaneously, during this process, chip 200 itself may tilt, as... Figure 4 As shown, the fluid adhesive 500 of the subsequent upper boss 310 will have uneven thickness due to the tilt of the chip 200, and may even spread to the side of the chip 200, causing the product to fail electrically.

[0027] Simultaneously, during the curing process, the fluid adhesive 500 shrinks, pulling on the upper boss 310. During subsequent injection molding and curing, the upper boss 310 is subjected to resin expansion and compression, creating a gap between it and the chip 200. Figure 5 As shown, this causes electrical failure in the product.

[0028] This invention provides a semiconductor packaging structure, such as... Figure 7 As shown, the device includes a lower boss 110, a chip 200, and an upper boss 310. The back side of the chip 200 is soldered to the lower boss 110 using a flowable adhesive 500, and the front side of the chip 200 is soldered to the upper boss 310 using a patterned DAF film 400. The patterned DAF film 400 includes at least two mutually discrete outer bonding islands 410, with a cutout area between the outer bonding islands 410. Specifically, the flowable adhesive 500 is solder paste.

[0029] In this semiconductor packaging structure, a conventional flowable adhesive 500 is used to weld the back side of the chip 200 to the lower boss 110, and a DAF film 400 is used to weld the upper boss 310 to the front side of the chip 200. The DAF film 400 is a solid adhesive material, which solves the problems that are easy to cause by using flowable adhesive 500 between the front side of the chip 200 and the upper boss 310 in the prior art, such as glue overflow, uneven curvature, and holes. In addition, the DAF film 400 is easy to pre-form on the upper boss 310, which facilitates the optimization of the packaging process.

[0030] Compared to traditional flowable adhesives (such as solder paste), the DAF film 400 solution offers significant advantages: its solid film allows for highly uniform thickness control (5–120 μm selectable) and eliminates the need for high pressure, avoiding the adhesive volume fluctuations caused by printing or dot coating processes with flowable adhesives (500); the DAF film 400 does not flow before curing, completely eliminating the risk of adhesive overflow, while flowable adhesives (500) are prone to overflow in the molten state; thanks to the consistent adhesive layer thickness, the DAF film 400 effectively prevents chip tilting (200), solving the tilting problem caused by uneven thickness of flowable adhesives (500); in terms of void control, proper use of the DAF film 400 can form a void-free continuous adhesive interface, while flowable adhesives (500) are prone to voids; in terms of equipment compatibility, the DAF film 400 is also suitable for conventional die bonders, with a wider process window and higher tolerance to temperature and pressure; from a process cost perspective, the DAF film 400 has a moderate material cost and avoids increased costs due to defect rates due to high yield, making its overall performance superior to the flowable adhesive (500) solution.

[0031] In this semiconductor packaging structure, the patterned DAF film 400 includes at least two mutually discrete outer bonding islands 410, with a hollow area between the outer bonding islands 410. During curing, the discrete outer bonding islands 410 can decompose the continuous shrinkage stress, and the hollow area can release thermal stress, reducing the risk of chip 200 tilting.

[0032] This invention also provides a semiconductor packaging method for the semiconductor structure. Figure 6 This is a schematic flowchart of a semiconductor packaging method provided in an embodiment of the present invention, as shown below. Figure 6 As shown, the semiconductor packaging method includes the following steps: Provide a lower boss 110, apply a flowable adhesive 500 to the lower boss 110, and mount the back of the chip 200 to the lower boss 110. Specifically, the flowable adhesive 500 is solder paste. An upper boss 310 is provided, on which a patterned DAF film 400 is pre-coated. The patterned DAF film 400 includes at least two mutually discrete outer bonding islands 410, with a hollow area between the outer bonding islands 410. The upper boss 310 is mounted to the front side of the chip 200 through the DAF film 400. The process involves curing to obtain a semiconductor package structure.

[0033] In this packaging method, a conventional flowable adhesive 500 is used to weld the back side of the chip 200 to the lower boss 110, and a DAF film 400 is used to weld the upper boss 310 to the front side of the chip 200. The DAF film 400 is a solid adhesive material, which solves the problems of excess adhesive, uneven curvature, and voids that easily occur when using flowable adhesive 500 between the front side of the chip 200 and the upper boss 310 in existing technologies. The DAF film 400 is also pre-formed on the upper boss 310, optimizing the packaging process. The curing conditions of the DAF film 400 are lower than those of solder paste. During the curing process, the upper boss 310 and the front side of the chip 200 are already cured before the solder paste reaches a completely molten state, avoiding the risk of uncontrollable displacement between the solder paste, chip 200, and upper boss 310 during the curing process in existing processes (where solder paste is used on both the top and bottom).

[0034] The patterned DAF film 400 includes at least two mutually discrete outer bonding islands 410, with a hollow area between the outer bonding islands 410. During curing, the discrete outer bonding islands 410 can decompose the continuous shrinkage stress, and the hollow area can release thermal stress, reducing the risk of chip 200 tilting.

[0035] The patterning of the DAF film 400 can be achieved through laser cutting. Specifically, a whole sheet of DAF film 400 is first laminated onto the upper boss 310, and then the unwanted areas are ablated using laser cutting to form hollow areas, leaving the patterned outer bonding islands 410. Alternatively, a sheet of DAF film 400 with the desired pattern can be pre-cut using a mold, and then transferred, aligned, and adhered to the upper boss 310.

[0036] exist Figure 8 As shown, in the semiconductor packaging structure provided in this embodiment of the invention, the patterned DAF film 400 is a four-corner island bridge pattern, including four outer bonding islands 410 located at the four corners of a rectangular area, and a central bonding island 420 located at the geometric center of the rectangular area. A hollow area exists between the central bonding island 420 and the outer bonding islands 410. Figure 8 In the diagram, the gray area represents the DAF solid structure, and the white area represents the cutout area. In this embodiment, by arranging outer bonding islands 410 at the four corners and a central bonding island 420 at the center, stable support can be provided, and thermal stress can be released by utilizing the cutout area, thereby effectively controlling the tilt of the chip 200.

[0037] Figure 8 The image only shows the relative positional relationship between the central bonding island 420 and the outer bonding island 410, without specifying their area or proportion. In practical applications, the size of the chip 200 and the upper protrusion 310 can be adjusted to control the area of ​​the central bonding island 420 and the outer bonding island 410.

[0038] Increasing the area of ​​the central bonding island 420 can increase the bonding strength, but it also increases the risk of chip 200 tilting and the degree of stress concentration. Conversely, decreasing the area of ​​the central bonding island 420 will reduce the bonding strength, but it will also reduce the risk of chip 200 tilting and the degree of stress concentration.

[0039] Increasing the area of ​​the outer bonding island 410 can increase the bonding strength and significantly reduce the risk of chip 200 tilting, but it will also significantly increase the stress concentration. Conversely, decreasing the area of ​​the outer bonding island 410 will decrease the bonding strength, but it will also significantly increase the risk of chip 200 tilting and significantly reduce the stress concentration.

[0040] It should be noted that the above changes are compared with the same DAF membrane 400, rather than comparing the use of DAF membrane 400 with the use of conventional flowable adhesive 500.

[0041] In some embodiments, the patterned DAF film 400 is a four-corner island bridge pattern, including only four outer adhesive islands 410 located at the four corners of a rectangular area, excluding the central adhesive island 420. In these embodiments, the DAF film 400 exhibits moderate adhesive strength, moderate stress concentration, and good risk of chip 200 tilting, and the overall performance is still superior to that of the conventional flowable adhesive 500.

[0042] In some embodiments, the patterned DAF film 400 is a hexagonal island bridge pattern, including six outer bonding islands 410 located at the six corners of a hexagonal region. Compared to embodiments using a quadrangular island bridge pattern, when the DAF film 400 is a hexagonal island bridge pattern, the coverage of the DAF film 400 is lower than that of the quadrangular island bridge pattern, and the spacing between the outer bonding islands 410 is smaller. This reduces the ability to release thermal stress, which increases stress concentration and reduces adhesive strength. It also increases the risk of chip 200 tilting.

[0043] like Figure 7 As shown, in the semiconductor packaging structure provided in this embodiment of the invention, the lower boss 110 is disposed on the frame 100, the upper boss 310 is disposed at one end of the jumper 300, and the other end of the jumper 300 is connected to the frame 100 or the substrate. In other embodiments, the lower boss 110 can also be disposed on the frame 100 or the substrate in other ways, such as making the lower boss 110 an independent structure and then connecting it to the frame 100 or the substrate by processes such as soldering.

[0044] In the semiconductor packaging method provided in this embodiment of the invention, during curing, the upper boss 310 and the front side of the chip 200 are cured at a first preset temperature, and the chip 200 and the lower boss 110 are cured at a second preset temperature. The first preset temperature is lower than the second preset temperature. The first preset temperature is used to complete the curing of the DAF film 400, achieving curing of the upper boss 310 and the front side of the chip 200, while the second preset temperature is used to complete the curing of the solder paste, achieving curing of the lower boss 110 and the back side of the chip 200. Typically, the first preset temperature is 150°C to 180°C, and the second preset temperature is 200°C to 250°C.

[0045] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A semiconductor packaging structure, characterized in that, The device includes a lower boss (110), a chip (200), and an upper boss (310). The back side of the chip (200) is welded to the lower boss (110) by a flowable adhesive (500), and the front side of the chip (200) is welded to the upper boss (310) by a patterned DAF film (400). The patterned DAF film (400) includes at least two mutually discrete outer bonding islands (410), and the area between the outer bonding islands (410) is a hollow area.

2. The semiconductor packaging structure according to claim 1, characterized in that, The patterned DAF film (400) has a four-corner island bridge pattern, including four outer bonding islands (410) located at the four corners of a rectangular area.

3. The semiconductor packaging structure according to claim 2, characterized in that, The patterned DAF film (400) also includes a central bonding island (420) located at the geometric center of the rectangular region, and a hollow area is formed between the central bonding island (420) and the outer bonding island (410).

4. The semiconductor packaging structure according to claim 1, characterized in that, The patterned DAF film (400) has a hexagonal island bridge pattern, comprising six outer bonding islands (410) located at the six corners of the hexagonal region.

5. The semiconductor packaging structure according to claim 1, characterized in that, The lower boss (110) is disposed on the frame (100) or the substrate, the upper boss (310) is disposed at one end of the jumper (300), and the other end of the jumper (300) is connected to the frame (100) or the substrate.

6. A semiconductor packaging method, characterized in that, Includes the following steps: A lower boss (110) is provided, a flowable adhesive (500) is applied to the lower boss (110), and the back side of the chip (200) is attached to the lower boss (110). An upper boss (310) is provided, on which a patterned DAF film (400) is pre-coated. The patterned DAF film (400) includes at least two mutually discrete outer bonding islands (410), with a hollow area between the outer bonding islands (410). The upper boss (310) is attached to the front side of the chip (200) through the DAF film (400). The process involves curing to obtain a semiconductor package structure.

7. The semiconductor packaging method according to claim 6, characterized in that, During curing, the upper boss (310) and the front side of the chip (200) are cured at a first preset temperature, and the chip (200) and the lower boss (110) are cured at a second preset temperature. The first preset temperature is lower than the second preset temperature.

8. The semiconductor packaging method according to claim 6, characterized in that, The patterned DAF film (400) has a four-corner island bridge pattern, including four outer bonding islands (410) located at the four corners of a rectangular area.

9. The semiconductor packaging method according to claim 8, characterized in that, The patterned DAF film (400) also includes a central bonding island (420) located at the geometric center of the rectangular region, and a hollow area is formed between the central bonding island (420) and the outer bonding island (410).

10. The semiconductor packaging method according to claim 6, characterized in that, The patterned DAF film (400) has a hexagonal island bridge pattern, comprising six outer bonding islands (410) located at the six corners of the hexagonal region.

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