Cops package structure and preparation method thereof

Abstract

The application provides a CoPoS packaging structure and a preparation method thereof, and belongs to the technical field of advanced semiconductor packaging. The interposer in the CoPoS packaging structure adopts semi-insulating silicon carbide, and the intrinsic thermal conductivity of the semi-insulating silicon carbide reaches 370-490 W / (m*K). After replacing the glass or sapphire panel with low thermal conductivity, the bottleneck of high thermal resistance introduced by the panel material is eliminated, and the heat of the chip can be quickly conducted downward through the interposer body. The inside of the interposer is interwoven by a vertical thermal via array and a horizontal heat conduction network to form a heat dissipation matrix. The thermal via array provides a longitudinal low-thermal-resistance conduction path, and the horizontal heat conduction network uniformly spreads the heat in the horizontal direction. The two cooperate to decompose the local concentrated heat flow into a surface domain distribution, effectively inhibiting the formation of local hot spots. At the same time, the vertical thermal via array is responsible for heat conduction, and the electrical interconnection path is independent of each other in space and function, avoiding the influence of thermoelectric coupling on signal integrity.

Description

Technical Field

[0001] This application relates to the field of advanced semiconductor packaging technology, and in particular to the CoPoS packaging structure and its fabrication method. Background Technology

[0002] With the heat flux density of AI high-performance chips exceeding 500 W / cm², traditional packaging heat dissipation faces severe challenges. Existing CoWoS (Chip-on-Wafer-on-Substrate) technology uses a silicon interposer with a thermal conductivity of only about 150 W / (m·K), resulting in insufficient heat diffusion. CoPoS (Chip-on-Panel-on-Substrate) architecture replaces the silicon interposer with glass or sapphire panels, increasing the integration area, but the thermal conductivity of glass and sapphire is low, at approximately 1 W / (m·K) and 40 W / (m·K), respectively, further exacerbating the heat dissipation problem. Furthermore, traditional packaging has a single heat conduction path, with heat transferred only along the longitudinal path from chip to interposer to substrate to heat sink. This results in high longitudinal thermal resistance and poor lateral temperature uniformity. Traditional interposers rely on their own thermal conductivity, lacking structured heat diffusion capabilities, and the high coupling between electrical interconnects and the heat conduction path makes it difficult to balance signal integrity and heat dissipation efficiency. Silicon carbide has a thermal conductivity as high as 370–490 W / (m·K), but existing technologies have not yet developed a systematic thermal diffusion enhancement architecture for CoPoS packaging. Summary of the Invention

[0003] To address the problems of extremely low thermal conductivity of panel materials, lack of structured heat diffusion design in the interposer layer, and high coupling between electrical and thermal paths in existing CoPoS packaging, this paper presents a CoPoS packaging structure and its fabrication method aimed at constructing a low thermal resistance three-dimensional heat dissipation network and achieving thermoelectric function decoupling.

[0004] This application provides a CoPoS packaging structure, including:

[0005] An interposer layer, wherein the interposer layer is made of semi-insulating silicon carbide;

[0006] At least one computing chip is flip-chip mounted on one side of the interposer layer;

[0007] A heat dissipation matrix is ​​formed inside the interposer layer. The heat dissipation matrix includes a vertical heat through-hole array and a lateral heat conduction network embedded inside the interposer layer. The vertical heat through-hole array and the lateral heat conduction network are intertwined. The vertical heat through-hole array is used for heat conduction.

[0008] Optionally, the interposer layer also forms an electrical interconnect structure, which is decoupled from the vertical heat via array in terms of spatial location and transmission function.

[0009] Optionally, the resistivity of the interposer layer is ≥10. 11 Ω·cm.

[0010] Optionally, the hole walls of the vertical thermal via array are made of the intermediate layer body material.

[0011] Optionally, the diameter of the vertical heat through-hole array is 20μm-50μm, and the spacing between adjacent heat through-holes is 100μm-300μm.

[0012] Optionally, the thickness of the transverse heat-conducting network is 10μm-30μm.

[0013] Optionally, the computing chip includes at least one of a graphics processor, an application-specific integrated circuit, and a high-bandwidth memory, and the operating heat flux density of the computing chip is ≥500W / cm².

[0014] Optionally, it also includes:

[0015] A substrate is disposed on the side of the interposer layer opposite to the computing chip, and the substrate has metal heat diffusion pillars that are vertically aligned with the vertical heat via array.

[0016] Optionally, the interposer is interconnected with the substrate by thermo-press bonding, and the metal thermal diffusion pillars correspond one-to-one with the vias of the vertical thermal via array.

[0017] Optionally, the substrate comprises a high thermal conductivity resin-based composite material doped with silicon carbide whiskers, having a thermal conductivity ≥15W / (m·K).

[0018] Optionally, it also includes:

[0019] A heat sink is attached to the side of the substrate away from the interlayer.

[0020] Optionally, it also includes:

[0021] A heat sink is disposed on the side of the computing chip away from the interposer layer, and three-dimensional intersecting microchannels are etched inside the heat sink.

[0022] This application provides a method for fabricating a CoPoS packaging structure, including:

[0023] An interposer layer is prepared, the interposer layer being made of semi-insulating silicon carbide, and a heat dissipation matrix is ​​formed inside the interposer layer. The heat dissipation matrix includes a vertical heat via array and a lateral heat conduction network embedded inside the interposer layer. The vertical heat via array and the lateral heat conduction network are interwoven. The vertical heat via array is used for heat conduction.

[0024] At least one computing chip is flip-chip mounted on one side of the interposer layer.

[0025] Optionally, the step of preparing the interposer layer further includes: forming an electrical interconnect structure in the interposer layer, and decoupling the electrical interconnect structure from the vertical heat via array in terms of spatial location and transmission function.

[0026] Optionally, before interconnecting the interposer layer with the substrate, the method further includes:

[0027] A substrate is provided, wherein a metal thermal diffusion pillar is disposed therein;

[0028] The interlayer is interconnected with the substrate by a hot-press bonding process, so that the through-holes of the vertical thermal via array correspond one-to-one with the metal thermal diffusion pillars in the substrate.

[0029] The beneficial effects of the above technical solution are as follows:

[0030] In this technical solution, the interposer in the CoPoS packaging structure of this application uses semi-insulating silicon carbide, which has an intrinsic thermal conductivity of 370–490 W / (m·K). Replacing the low thermal conductivity glass or sapphire panel eliminates the high thermal resistance bottleneck introduced by the panel material, allowing chip heat to be rapidly conducted downwards through the interposer body. Inside the interposer, a heat dissipation matrix is ​​formed by an interwoven array of vertical thermal vias and a lateral thermal conductive network. The thermal via array provides a low thermal resistance conduction path in the vertical direction, while the lateral thermal conductive network evenly distributes heat horizontally. Together, they decompose locally concentrated heat flow into a planar distribution, effectively suppressing the formation of local hot spots. Simultaneously, the vertical thermal via array is dedicated to heat conduction and is spatially and functionally independent of the electrical interconnection paths, avoiding the impact of thermoelectric coupling on signal integrity. Attached Figure Description

[0031] One or more embodiments are illustrated by way of example with reference numerals in the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Elements with the same reference numerals in the drawings are denoted as similar elements. Unless otherwise stated, the figures in the drawings are not to be limited by scale.

[0032] Figure 1 This is a cross-sectional schematic diagram of one embodiment of the CoPoS packaging structure described in this application;

[0033] Figure 2 This is a flowchart illustrating an embodiment of the method for fabricating the CoPoS packaging structure described in this application.

[0034] Figure 3 This is a flowchart illustrating another embodiment of the method for fabricating the CoPoS packaging structure described in this application.

[0035] The names of the parts referred to by the numbers in the attached diagram are as follows:

[0036] 1. Computing chip; 2. Intermediate layer; 3. Substrate; 4. Heat sink; 5. Liquid cooling plate; 6. Electrical interconnect structure; 7. Heat dissipation matrix. Detailed Implementation

[0037] The advantages of this application are further illustrated below with reference to the accompanying drawings and specific embodiments.

[0038] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numerals in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this disclosure. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this disclosure as detailed in the appended claims.

[0039] The terminology used in this disclosure is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. The singular forms “a,” “the,” and “the” as used in this disclosure and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the term “and / or” as used herein refers to and includes any and all possible combinations of one or more of the associated listed items.

[0040] It should be understood that although the terms first, second, third, etc., may be used in this disclosure to describe various information, such information should not be limited to these terms. These terms are used only to distinguish information of the same type from one another. For example, without departing from the scope of this disclosure, first information may also be referred to as second information, and similarly, second information may also be referred to as first information. Depending on the context, the word "if" as used herein may be interpreted as "when," "when," or "in response to determination."

[0041] In the description of this application, it should be understood that the numerical labels before the steps do not indicate the order of the steps, but are only used to facilitate the description of this application and to distinguish each step, and therefore should not be construed as a limitation of this application.

[0042] The CoPoS packaging structure of this application embodiment can be applied to electronic devices with stringent heat dissipation requirements, such as data center AI accelerator cards, high-performance computing servers, autonomous driving vehicle computing platforms, edge AI inference devices, and 5G base station processing units.

[0043] The CoPoS packaging structure of this application is not only applicable to single-package scenarios with high-performance chips such as GPUs and ASICs, but can also be extended to various semiconductor packaging applications with high heat flux density chip heat dissipation requirements. For example, it can be applied to multi-chip stacked packaging, heterogeneous chip integration packaging, and advanced packaging architectures that require both high-density wiring and efficient heat dissipation. This application uses the CoPoS packaging of a high-performance AI chip as an example for illustration, but the scope of protection is not limited thereto.

[0044] In this embodiment, the heat generated by the high-performance chip is conducted longitudinally and diffused laterally through the heat dissipation matrix inside the semi-insulating silicon carbide interposer, and then further transferred downwards to the substrate and bottom heat sink. Finally, the heat is carried away from the package by an external cooling system. Specifically, a GPU main computing chip and six HBM high-bandwidth memory chips are flip-bonded to the upper surface of the silicon carbide interposer in a center-to-surround manner. A high thermal conductivity interface material is filled between the bottom of the chip and the interposer. The interface material can be a nano-silver sintered material, a graphene-reinforced thermally conductive material, a boron nitride thermally conductive material, or a diamond-filled thermally conductive material, with a thermal conductivity greater than 20 W / (m·K). This is only an example of one chip arrangement; in actual applications, the number and arrangement of chips can be flexibly adjusted according to computing power requirements. The silicon carbide interposer is made of semi-insulating silicon carbide with an intrinsic thermal conductivity of 370–490 W / (m·K). It integrates a heat dissipation matrix formed by an interwoven array of vertical heat vias and a lateral thermal conductive network. The vertical heat vias penetrate the upper and lower surfaces of the interposer, while the lateral thermal conductive network is embedded within the interposer and interconnects with the vertical heat vias. The interposer also forms an independent electrical interconnect structure, decoupled from the vertical heat via array in terms of spatial location and heat transfer function. An organic substrate and a silicon carbide-copper composite heat sink can be sequentially placed below the silicon carbide interposer. The organic substrate contains metal heat diffusion pillars that align with and contact the vertical heat via array, forming a complete low thermal resistance solid-state heat conduction path from the chip to the bottom heat sink.

[0045] This application proposes a CoPoS packaging structure to address the problems of extremely low thermal conductivity of the panel material, lack of structured thermal diffusion design in the interposer layer, and high coupling between electrical and thermal paths in existing CoPoS packaging. For example... Figure 1 The figure shown is a cross-sectional schematic diagram of a CoPoS packaging structure conforming to a preferred embodiment of this application. As can be seen from the figure, the CoPoS packaging structure provided in this embodiment mainly includes:

[0046] Intermediate layer 2, wherein the intermediate layer 2 is made of semi-insulating silicon carbide;

[0047] At least one computing chip 1 is flip-chip disposed on one side of the interposer layer 2;

[0048] A heat dissipation matrix 7 is formed inside the intermediary layer 2. The heat dissipation matrix 7 includes a vertical heat through-hole array and a lateral heat conduction network embedded inside the intermediary layer 2. The vertical heat through-hole array and the lateral heat conduction network are intertwined. The vertical heat through-hole array is used for heat conduction.

[0049] In this embodiment, the interposer 2 in the CoPoS packaging structure is made of semi-insulating silicon carbide, with an intrinsic thermal conductivity of 370–490 W / (m·K). Replacing the low thermal conductivity glass or sapphire panel eliminates the high thermal resistance bottleneck introduced by the panel material, allowing chip heat to be rapidly conducted downwards through the interposer 2 body. Inside the interposer 2, a heat dissipation matrix 7 is formed by an interwoven vertical thermal via array and a lateral thermal conductive network. The thermal via array provides a low thermal resistance conduction path in the vertical direction, while the lateral thermal conductive network evenly distributes heat horizontally. Together, they decompose locally concentrated heat flow into a planar distribution, effectively suppressing the formation of local hot spots. Simultaneously, the vertical thermal via array is dedicated to heat conduction and is spatially and functionally independent of the electrical interconnection paths, avoiding the impact of thermoelectric coupling on signal integrity.

[0050] In an optional embodiment, the interposer layer 2 is further formed with an electrical interconnect structure 6, which is decoupled from the vertical heat via array in terms of spatial location and transmission function.

[0051] In this embodiment, the electrical interconnect structure 6 and the vertical thermal via array are spatially separated and functionally independent. The electrical interconnect structure 6 handles signal transmission between chips, while the vertical thermal via array is specifically designed for rapid heat dissipation along the vertical direction of the chip; neither obstructs the other's path. This results in two advantages: firstly, the thermal via array does not need to consider electrical lead-out requirements, allowing for flexible arrangement of aperture and spacing according to heat dissipation needs, with heat conduction efficiency unconstrained by wiring density; secondly, the electrical interconnect structure 6 is unaffected by the thermal stress or leakage risks introduced by the thermal vias, ensuring the integrity of high-frequency signal transmission. The high resistivity of the silicon carbide substrate further isolates crosstalk between thermoelectric paths, completely separating the heat dissipation path from the signal path physically, achieving parallel improvements in both thermal and electrical performance of the overall package.

[0052] In an alternative embodiment, the resistivity of the interposer layer 2 is ≥10. 11The resistivity is Ω·cm. This resistivity is much higher than that of ordinary semiconductor materials, making the body of the interposer layer 2 almost electrically insulating. Under this condition, even if the vertical thermal via array inside the interposer layer 2 and the electrical interconnect structure 6 are arranged adjacently, they will not form a leakage path or generate parasitic coupling through the body of the interposer layer 2. The high resistivity provides an ideal low-loss substrate environment for the electrical interconnect structure 6. The dielectric loss is significantly reduced when high-frequency signals are transmitted in the redistribution layer, and signal integrity is maintained. No additional isolation structure is required between the thermal via array and the electrical interconnect structure 6, so they can be physically arranged closely without interference, improving the space utilization of the interposer layer 2. This is beneficial for meeting the dual requirements of efficient heat conduction and high-speed electrical transmission under high-density wiring conditions.

[0053] In an optional embodiment, the walls of the vertical thermal via array are made of the same material as the intermediate layer 2, without any conductive metal filling. This structure physically separates the thermal vias from the metal-filled vias used for electrical signal transmission. Since silicon carbide has an intrinsic thermal conductivity as high as 370–490 W / (m·K), heat can be conducted downwards along the via walls without passing through an additional material interface, resulting in lower thermal resistance and higher longitudinal heat transfer efficiency. Simultaneously, the absence of metal filling within the vias avoids stress concentration or interface cracking issues caused by the difference in thermal expansion coefficients between the metal and silicon carbide during temperature cycling, thus improving long-term operational reliability. Furthermore, eliminating metal filling simplifies the via fabrication process and reduces production costs.

[0054] In an optional embodiment, the diameter of the vertical thermal via array is 20μm-50μm, and the spacing between adjacent thermal vias is 100μm-300μm. Controlling the via diameter within this range ensures that each via has a sufficient thermally conductive cross-sectional area, allowing heat from the area beneath the chip to be effectively captured and rapidly dissipated longitudinally, while avoiding the impact of excessively large via diameters on the structural strength of the interposer layer 2. Setting the spacing between adjacent thermal vias to 100μm-300μm maintains a reasonable density distribution of the thermal vias within the interposer layer 2, ensuring that heat is evenly distributed across multiple vias in the lateral direction. This avoids heat dissipation blind spots caused by excessive spacing and also prevents excessive hollowing out of the interposer layer 2 material due to overly dense spacing, which would weaken its mechanical support capabilities. With the above dimensional coordination, the thermal via array and the lateral thermally conductive network work together to form a continuous and uniform three-dimensional heat diffusion channel throughout the entire chip projection area, effectively suppressing localized temperature peaks.

[0055] In an optional embodiment, the thickness of the lateral heat-conducting network is 10μm-30μm. This thickness range ensures that the lateral heat-conducting network has sufficient thermal conductivity cross-sectional area within the interposer layer 2, enabling the heat dissipated from the vertical heat via array to be rapidly spread horizontally across the entire surface area of ​​the interposer layer 2, preventing heat accumulation at the via outlets and the formation of localized temperature peaks. Simultaneously, this thickness value takes into account the overall thickness distribution of the interposer layer 2, ensuring that the lateral heat-conducting network does not excessively encroach on the vertical heat conduction path, nor does it affect the normal arrangement of the redistribution layer on the upper surface and the interconnect interfaces on the lower surface of the interposer layer 2. At this thickness, the lateral heat-conducting network and the vertical heat via array form sufficient contact area at their intersection, resulting in a smoother heat flow transition from vertical to horizontal, and ensuring the uniformity of heat diffusion throughout the entire heat dissipation matrix 7.

[0056] In an optional embodiment, the computing chip 1 includes at least one of a graphics processing unit (GPU), an application-specific integrated circuit (ASIC), and a high-bandwidth memory (HBM), and the operating heat flux density of the computing chip 1 is ≥500W / cm². Such chips generate a large amount of heat per unit area when operating at full load. Traditional packaging structures struggle to dissipate this concentrated heat in a timely manner, causing the chip junction temperature to rise rapidly, triggering frequency reduction protection, and preventing the actual computing power from being fully released. In this embodiment, a heat dissipation matrix 7, composed of a vertical thermal via array and a lateral thermal conductive network, is mounted on a semi-insulating silicon carbide interposer layer. This matrix rapidly dissipates the high-density heat flow beneath the chip along the vertical direction, while simultaneously distributing the heat evenly across the entire interposer layer 2 surface area through the lateral network, preventing heat from accumulating directly beneath the chip. For packaging solutions that integrate both GPU and HBM, the heat flux density in the GPU region is significantly higher than that in the HBM region. The lateral temperature uniformity of the heat dissipation matrix 7 effectively balances the temperature difference between different chip regions, preventing localized overheating from affecting the data access stability of the HBM and ensuring the continuous performance output of the entire computing system under high load.

[0057] In an optional embodiment, it further includes:

[0058] The substrate 3 is disposed on the side of the interposer layer 2 away from the computing chip 1, and the substrate 3 has metal heat diffusion pillars that are vertically aligned with the vertical heat via array.

[0059] It should be noted that the substrate 3 in this embodiment is an organic substrate.

[0060] In this embodiment, a metal heat diffusion pillar is provided inside the substrate 3, and the metal heat diffusion pillar is aligned vertically with the vertical heat via array in the interposer layer 2. After heat is conducted downward through the heat dissipation matrix 7 in the silicon carbide interposer layer, it enters the substrate 3 through the bottom outlet of the vertical heat via array. The metal heat diffusion pillar directly receives this heat and continues to transfer it downward, forming a continuous low thermal resistance heat conduction path from the chip to the bottom of the substrate 3. The introduction of the metal heat diffusion pillar compensates for the insufficient thermal conductivity of the substrate 3 body material, avoids heat accumulation at the interface between the interposer layer 2 and the substrate 3, and further improves the overall heat transfer efficiency of the package in the vertical direction. At the same time, the metal heat diffusion pillar is distributed in an array within the substrate 3, and is vertically connected with the heat dissipation matrix 7 in the interposer layer 2, so that heat can also be spread laterally to a certain extent within the substrate 3, further homogenizing the overall temperature distribution of the package.

[0061] In an optional embodiment, the interposer 2 is interconnected with the substrate 3 by thermo-press bonding, and the metal thermal diffusion pillars correspond one-to-one with the vias of the vertical thermal via array.

[0062] During the thermo-press bonding process, the lower surface of the interposer 2 and the upper surface of the substrate 3 form a tight atomic-level bonding interface under the combined action of temperature and pressure. The top of the metal thermal diffusion pillar directly abuts the bottom outlet of the vertical heat via. Heat is conducted from the silicon carbide via wall to the metal pillar without passing through solder or other intermediate dielectric layers, significantly reducing interface thermal resistance. This one-to-one correspondence structure ensures that the longitudinal heat conduction path from the chip to the substrate 3 is physically continuous and uninterrupted, allowing heat to be transferred downwards efficiently and with low loss in the vertical direction, avoiding heat flow congestion caused by alignment misalignment or interface gaps.

[0063] In an optional embodiment, the substrate 3 comprises a high thermal conductivity resin-based composite material doped with silicon carbide (SiC) whiskers, having a thermal conductivity ≥15 W / (m·K).

[0064] Silicon carbide whiskers themselves possess high thermal conductivity. When uniformly dispersed in the resin matrix, they form a continuous thermally conductive network, increasing the overall thermal conductivity of substrate 3 by several times compared to traditional organic substrates. After heat enters substrate 3 from the interposer 2 via the vertical thermal via array, substrate 3 itself can participate in both vertical heat transfer and lateral heat spread, no longer becoming a thermal resistance bottleneck in the heat dissipation path of the package. The entire package structure maintains low thermal resistance in the vertical heat conduction path. Simultaneously, the thermal expansion coefficients between the silicon carbide whiskers and the silicon carbide interposer are similar, resulting in lower thermal stress at the interface between substrate 3 and interposer 2 during temperature cycling, contributing to the connection reliability of the package structure during long-term operation.

[0065] In an optional embodiment, it further includes:

[0066] Heat sink 4 is attached to the side of the substrate 3 facing away from the intermediary layer 2. Heat is transferred downwards through the intermediary layer 2 and the substrate 3 and then enters the heat sink 4, where it is further spread and transferred to the external cooling environment.

[0067] Furthermore, the heat sink 4 is a silicon carbide-copper composite heat sink. The silicon carbide skeleton provides a high thermal conductivity channel and mechanical support, while the copper-filled network enhances lateral heat diffusion capability. The silicon carbide-copper composite allows the heat sink 4 to possess both high thermal conductivity and a thermal expansion coefficient that matches the upper substrate 3, resulting in low interfacial thermal stress during temperature cycling and high connection reliability. The surface of the heat sink 4 can also be processed with a micro-fin array to increase the heat exchange area with the external liquid cooling plate 5 or air-cooled airflow, improving the overall external heat dissipation efficiency of the package.

[0068] In an optional embodiment, it further includes:

[0069] A heat sink is disposed on the side of the computing chip 1 away from the interposer layer 2, and three-dimensional intersecting microchannels are etched inside the heat sink.

[0070] In this embodiment, the heat sink creates a second heat dissipation path from the top of the chip, which, together with the downward heat conduction path of the interposer layer 2, forms a bidirectional heat dissipation architecture. After coolant is introduced into the three-dimensional intersecting microchannels, the liquid forms forced convection heat transfer within the channel network, and the heat in the area on the back of the chip that directly contacts the bottom surface of the heat sink is quickly carried away by the coolant. The intersecting arrangement of the microchannels ensures that the channels cover the entire back area of ​​the chip, eliminating flow dead zones, and making the heat transfer intensity more uniform across the top of the chip, which helps to reduce the temperature difference on the chip surface.

[0071] Furthermore, the heat dissipation cover is a silicon carbide (SiC) microfluidic heat dissipation cover. Silicon carbide has high intrinsic thermal conductivity, and the inner wall of the microchannel itself can efficiently absorb and transfer heat to the coolant. Silicon carbide is also corrosion-resistant and has good chemical compatibility with the coolant, with no risk of corrosion or blockage on the channel wall during long-term operation. The silicon carbide heat dissipation cover and the silicon carbide interposer are made of the same material, and both have the same coefficient of thermal expansion, resulting in good deformation coordination of the overall package during temperature cycling and high structural stability. The SiC microfluidic heat dissipation cover is located above the chip, not inside the silicon carbide interposer or the organic substrate; below the chip are, in sequence, the silicon carbide interposer, the organic substrate, and the bottom SiC-Cu composite heat dissipation plate, forming a three-dimensional composite heat dissipation architecture combining top microchannel liquid cooling, middle silicon carbide thermal diffusion, and bottom heat dissipation plate heat conduction.

[0072] By way of example and not limitation, the CoPoS packaging structure may include: a silicon carbide microfluidic heat sink: single-crystal silicon carbide with a thermal conductivity of 480 W / (m·K), a microchannel width of 100 μm, and a depth of 80 μm; an AI chipset: one GPU with a heat flux density of 600 W / cm², and six HBMs arranged in a center-surround pattern; a silicon carbide interposer: a 300 mm square semi-insulating SiC layer with a thickness of 300 μm, vertical heat vias with a diameter of 30 μm and a spacing of 200 μm; an organic substrate: a silicon carbide whisker-reinforced resin-based composite material with a thermal conductivity of 18 W / (m·K); and a bottom heat dissipation layer: a SiC-Cu composite heat sink with microfins. Fabrication parameters: flip-chip bonding temperature 260 °C, pressure 80 N; nano-silver sintering temperature 200 °C, holding time 30 min.

[0073] The CoPoS packaging structure adopted in this embodiment reduces the total thermal resistance by more than 60%, lowers the main chip junction temperature by 25–35°C, and effectively eliminates local hot spots. The use of a square silicon carbide panel is compatible with the CoPoS "circle-to-square" architecture, increasing integration by 30% and reducing costs by 15–20%. The high mechanical strength of silicon carbide helps suppress warpage in large-size packages, while its high resistivity ensures low signal loss under high-density wiring. Interface bonding strength is improved by 40% in temperature cycling tests, making it suitable for the long-term high-load operating environment of AI data centers.

[0074] like Figure 2 As shown, this embodiment provides a method for fabricating a CoPoS packaging structure, including the following steps:

[0075] S1. Prepare an interposer layer 2, the interposer layer 2 being made of semi-insulating silicon carbide, and form a heat dissipation matrix 7 inside the interposer layer 2. The heat dissipation matrix 7 includes a vertical heat through-hole array and a lateral heat conduction network embedded inside the interposer layer 2. The vertical heat through-hole array and the lateral heat conduction network are intertwined. The vertical heat through-hole array is used for heat conduction.

[0076] Specifically, the heat dissipation matrix 7 is formed as follows: a 300mm square semi-insulating silicon carbide wafer is provided and mechanically ground and chemically mechanically polished to a thickness of 200μm–500μm; a vertical thermal via array is prepared using laser deep drilling and inductively coupled plasma etching processes, with via diameters of 20μm–50μm; silicon carbide material is deposited on the inner wall of the vias and inside the panel by chemical vapor deposition to form a lateral heat conduction network, which is integrated with the vertical thermal vias in the intersection area to form a heat diffusion matrix; subsequently, silicon vias and multilayer redistribution layers are prepared, and Cu / Co alloy wiring is used to complete the fabrication of the electrical interconnect structure 6.

[0077] S2. At least one computing chip 1 is flip-chip disposed on one side of the interposer layer 2, and the bottom of the chip and the interposer layer 2 are filled with a high thermal conductivity interface material to reduce contact thermal resistance.

[0078] Specifically, Cu / SnAg solder bumps are prepared on the surface of the chip 1, with a bump height of 20μm–30μm; a flip-chip bonding process is used, with a temperature of 250℃–280℃ and a pressure of 50N–100N, to precisely bond the chip assembly to the corresponding area of ​​the interposer layer 2; the bottom is filled with epoxy resin-based thermally conductive adhesive, and silicon carbide nanoparticles are added, with a thermal conductivity ≥5W / (m·K), which strengthens mechanical connection and thermal conduction after curing.

[0079] Through the above steps, the electrical interconnect structure 6 and the heat dissipation matrix 7 are constructed simultaneously during the preparation of the interposer layer 2. The vertical thermal via walls of the heat dissipation matrix 7 are directly formed from silicon carbide, without metal filling. The lateral network is embedded within the interposer layer 2. This process reduces the need for metal filling in the vias and the introduction of redundant interface layers, simplifying the process. The resulting interposer layer 2 possesses both high-speed signal transmission capabilities between chips and low thermal resistance three-dimensional thermal conductivity. Thermoelectric functions are integrated within the same component but physically separated. The overall package can meet the dual requirements of high-density interconnection and efficient heat dissipation, adapting to the heat dissipation requirements of high-performance chips under continuous high loads.

[0080] In an optional embodiment, the step of preparing the interposer layer 2 further includes: forming an electrical interconnect structure 6 in the interposer layer 2, and decoupling the electrical interconnect structure 6 from the vertical heat via array in terms of spatial location and transmission function.

[0081] In practical applications, the electrical interconnect structure 6 can be fabricated using conventional through-silicon vias (TSVs) and multilayer metal redistribution layers, and placed in the area of ​​the interposer 2 away from the thermal via array, with the two not overlapping in the layout. The vertical thermal via array only serves the function of vertical heat conduction; the via walls are made of silicon carbide and are not filled with metal. Electrical signals are transmitted between chips via independent metal-filled vias and wiring layers. Thus, the heat dissipation path and the signal path are physically completely separated. Thermoelectric functions are implemented in parallel within the same interposer 2 without interference. Signal integrity is not affected by the parasitic effects introduced by the thermal vias, and the size and distribution of the thermal vias are not constrained by wiring rules and can be freely optimized according to heat dissipation requirements.

[0082] In an optional embodiment, before interconnecting the interposer layer 2 with the substrate 3 in step S1, the method further includes:

[0083] A substrate 3 is provided, wherein a metal thermal diffusion pillar is provided in the substrate 3;

[0084] The interposer 2 is interconnected with the substrate 3 by hot-press bonding, so that the through holes of the vertical thermal via array correspond one-to-one with the metal thermal diffusion pillars in the substrate 3.

[0085] In this embodiment, during the thermo-press bonding process, the silicon carbide via wall and the metal pillar form a tight connection at the interface through atomic diffusion. This direct contact eliminates the need for intermediate layers such as solder, resulting in lower thermal resistance along the path of heat transfer from the via wall to the metal pillar. The introduction of the metal thermal diffusion pillar compensates for the limited thermal conductivity of the substrate 3, allowing heat transferred downwards from the interposer 2 to be efficiently injected into the substrate 3 and continue to be conducted longitudinally along the metal pillar. The entire package forms an uninterrupted, low-thermal-resistance thermal chain along the path from the chip to the substrate 3, improving longitudinal heat dissipation efficiency.

[0086] In an alternative embodiment, such as Figure 3 As shown, the fabrication method of the CoPoS packaging structure may further include the following steps:

[0087] S3. Fabrication of silicon carbide microfluidic heat dissipation cap;

[0088] Specifically, a single-crystal silicon carbide substrate is provided, and a three-dimensional cross-shaped microchannel array is prepared by photolithography and inductively coupled plasma deep etching; a nano-silicon carbide coating with a thickness of 1μm–5μm is deposited on the inner wall of the channel to improve thermal conductivity and corrosion resistance; the inlet / outlet ports are welded, and after a sealing test, the system is kept at 1MPa pressure for 30 minutes without leakage before being put into use.

[0089] S4. Package stacking and interface connection;

[0090] The silicon carbide interlayer is interconnected with the organic substrate by thermo-press bonding, and the metal thermal diffusion pillars are precisely aligned with the vertical thermal vias; the back of the computing chip 1 is coated with nano silver paste and sintered at low temperature (180℃–220℃) for 30 minutes to form a low thermal resistance interface; the bottom of the organic substrate is bonded with a silicon carbide-copper composite heat sink 4 using thermally conductive insulating adhesive to complete the overall encapsulation.

[0091] S5. Testing and Packaging.

[0092] Thermal performance tests are performed on the package structure, including thermal resistance and junction temperature tests; electrical tests are performed, including signal integrity and on-resistance tests; reliability tests are performed, including temperature cycling from -55℃ to 125℃ for 1000 cycles; after passing the tests, vacuum packaging is performed.

[0093] The CoPoS packaging structure fabrication method in this embodiment is based on silicon carbide high thermal conductivity material and achieves heat dissipation through solid-state heat conduction path, which is different from the solution that relies solely on fluid cooling.

[0094] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A CoPoS packaging structure, characterized in that, include: An interposer layer, wherein the interposer layer is made of semi-insulating silicon carbide; At least one computing chip is flip-chip mounted on one side of the interposer layer; A heat dissipation matrix is ​​formed inside the interposer layer. The heat dissipation matrix includes a vertical heat through-hole array and a lateral heat conduction network embedded inside the interposer layer. The vertical heat through-hole array and the lateral heat conduction network are intertwined. The vertical heat through-hole array is used for heat conduction. The walls of the vertical heat-conducting hole array are made of the intermediate layer body material, and the holes of the vertical heat-conducting hole array are not filled with metallic conductive material; the lateral heat-conducting network is formed of silicon carbide material and is integrally connected with the vertical heat-conducting holes in the vertical heat-conducting hole array in the intersection area.

2. The CoPoS packaging structure according to claim 1, characterized in that, The intermediate layer also forms an electrical interconnect structure, which is decoupled from the vertical heat via array in terms of spatial location and transmission function.

3. The CoPoS packaging structure according to claim 1, characterized in that, The resistivity of the intermediate layer is ≥10. 11 Ω·cm.

4. The CoPoS packaging structure according to claim 1, characterized in that, The diameter of the vertical heat-perforation array is 20μm-50μm, and the spacing between adjacent heat-perforations is 100μm-300μm.

5. The CoPoS packaging structure according to claim 4, characterized in that, The thickness of the transverse heat-conducting network is 10μm-30μm.

6. The CoPoS packaging structure according to claim 1, characterized in that, The computing chip includes at least one of a graphics processor, an application-specific integrated circuit (ASIC), and a high-bandwidth memory, and the operating heat flux density of the computing chip is ≥500W / cm³. 2 .

7. The CoPoS packaging structure according to claim 1, characterized in that, Also includes: A substrate is disposed on the side of the interposer layer opposite to the computing chip, and the substrate has metal heat diffusion pillars that are vertically aligned with the vertical heat via array.

8. The CoPoS packaging structure according to claim 7, characterized in that, The interposer is interconnected with the substrate by thermo-press bonding, and the metal thermal diffusion pillars correspond one-to-one with the through holes of the vertical thermal via array.

9. The CoPoS packaging structure according to claim 7, characterized in that, The substrate comprises a high thermal conductivity resin-based composite material doped with silicon carbide whiskers, with a thermal conductivity ≥15W / (m·K).

10. The CoPoS packaging structure according to claim 7, characterized in that, Also includes: A heat sink is attached to the side of the substrate away from the interlayer.

11. The CoPoS packaging structure according to claim 1, characterized in that, Also includes: A heat sink is disposed on the side of the computing chip away from the interposer layer, and three-dimensional intersecting microchannels are etched inside the heat sink.

12. A method for fabricating a CoPoS encapsulation structure, characterized in that, include: An interposer layer is prepared, the interposer layer being made of semi-insulating silicon carbide, and a heat dissipation matrix is ​​formed inside the interposer layer. The heat dissipation matrix includes a vertical heat via array and a lateral heat conduction network embedded inside the interposer layer. The vertical heat via array and the lateral heat conduction network are interwoven. The vertical heat via array is used for heat conduction. The walls of the holes in the vertical heat via array are made of the interposer layer body material, and the holes in the vertical heat via array are not filled with a metallic conductive material. The lateral heat conduction network is formed of silicon carbide material and is integrally connected with the vertical heat vias in the vertical heat via array in the intersection region. At least one computing chip is flip-chip mounted on one side of the interposer layer.

13. The preparation method according to claim 12, characterized in that, The step of preparing the intermediate layer further includes: forming an electrical interconnect structure in the intermediate layer, and decoupling the electrical interconnect structure from the vertical heat via array in terms of spatial location and transmission function.

14. The preparation method according to claim 12, characterized in that, Before interconnecting the interposer layer with the substrate, the method further includes: A substrate is provided, wherein a metal thermal diffusion pillar is disposed therein; The interlayer is interconnected with the substrate by a hot-press bonding process, so that the through-holes of the vertical thermal via array correspond one-to-one with the metal thermal diffusion pillars in the substrate.

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