A multilayer metal wiring structure inside a semiconductor or ceramic bulk material and a method of manufacture

Abstract

The application discloses a kind of semiconductor or ceramic bulk material internal multilayer metal wiring structure and preparation method, wherein structure includes sequentially bonded stacked multilayer stack structure, and the stack structure of each layer includes semiconductor or ceramic bulk material, the semiconductor or ceramic bulk material has groove inside, the groove is filled with metal material, the metal material forms metal wiring layer, the metal wiring layer is covered with bonding layer, the bonding layer is tiled on the surface of the semiconductor or ceramic bulk material for bonding with upper stack structure, and the semiconductor or ceramic bulk material, metal wiring layer and bonding layer constitute the stack structure of single layer.The application avoids using traditional powder co-firing process, avoids using high-temperature process, and solves the problem of excessively high process temperature in the process of forming multilayer metal wiring in existing semiconductor or ceramic.

Description

Technical Field

[0001] This invention relates to the field of semiconductor fabrication technology, and in particular to a multilayer metal wiring structure and fabrication method inside a semiconductor or ceramic bulk material. Background Technology

[0002] Implementing multilayer metal wiring within ceramic or semiconductor bulk materials is a key technology for manufacturing high-density, high-reliability electronic modules. Currently, the most widely used multilayer wiring processes in the industry mainly include low-temperature co-fired ceramic (LTCC) technology and high-temperature co-fired ceramic (HTCC) technology.

[0003] Both LTCC and HTCC belong to powder co-firing technology. The basic process is as follows: ceramic powder (such as Al2O3, AlN, glass ceramics, etc.) is mixed with organic binder to form green ceramic tape. Through drilling, filling (using metal paste, such as Ag, Pd, Ag / Pd, W, Mo, etc.), and printing circuits, multi-layer green ceramic tapes are stacked, hot-pressed, and finally co-fired at high temperature to form a ceramic substrate with a three-dimensional metal wiring structure inside.

[0004] Both HTCC and LTCC require co-firing temperatures above 600°C. Specifically, the sintering temperature for LTCC is typically between 850°C and 950°C, while HTCC requires temperatures above 1500°C. However, these known technologies have revealed the following significant drawbacks in long-term application:

[0005] 1. The internal material of the block is uneven.

[0006] Because ceramic powder and metal powder are mixed and co-fired, it is difficult to make the size, shape and distribution of powder particles completely consistent, resulting in material inhomogeneity inside the sintered block, which affects the structural consistency and electrical performance stability.

[0007] 2. Grooves exist between the powder particles.

[0008] During co-firing, the powder particles cannot be completely densified, leaving behind micron- or even submicron-sized grooves. These grooves reduce the material's mechanical strength, airtightness, and insulation reliability, and are particularly difficult to detect and repair within multilayer structures.

[0009] 3. Metal wires are prone to deterioration at high temperatures.

[0010] Both HTCC and LTCC processes require co-firing at temperatures above 600°C. High-temperature environments can easily lead to oxidation, diffusion, agglomeration, or adverse reactions between the metal conductors and the ceramic, resulting in increased conductor resistance, decreased adhesion, and even open circuits.

[0011] 4. The co-firing process generates enormous thermal stress, leading to abnormal film formation.

[0012] Due to the significant difference in the coefficient of thermal expansion (CTE) between ceramic and metal materials, enormous thermal stress accumulates at the interface during sintering at temperatures above 600°C and subsequent cooling. This stress can cause wrinkling, cracking, and peeling of the metal film, or cause interlayer misalignment, severely affecting the reliability and yield of multilayer wiring.

[0013] 5. During co-firing, oxides participate in the reaction, resulting in a decrease in thermal conductivity.

[0014] To achieve co-firing matching between ceramics and metals, it is usually necessary to introduce oxide additives or utilize the oxidation reaction of the ceramic itself to promote sintering. However, after these oxides participate in the reaction, they change the heat conduction path at the interface, forming a high thermal resistance layer, resulting in a significant decrease in overall thermal conductivity. This problem is particularly prominent for power modules that require efficient heat dissipation (such as substrates for SiC and GaN devices).

[0015] In summary, known LTCC and HTCC technologies are limited by the principle of powder co-firing and high-temperature processes above 600°C, making it difficult to simultaneously achieve material uniformity, density, metal wire integrity, low thermal stress, and high thermal conductivity. Summary of the Invention

[0016] Therefore, there is a need to provide a multilayer metal wiring structure and fabrication method inside semiconductor or ceramic bulk materials to solve the problem of excessively high fabrication temperature during the formation of multilayer metal wiring in existing semiconductors or ceramics.

[0017] To achieve the above objectives, the present invention provides a multilayer metal wiring structure inside a semiconductor or ceramic bulk material, comprising a multilayer stacked structure bonded sequentially. Each layer of the stacked structure includes a semiconductor or ceramic bulk material, the semiconductor or ceramic bulk material having trenches filled with a metal material forming a metal wiring layer. A bonding layer covers the metal wiring layer and is laid flat on the surface of the semiconductor or ceramic bulk material for bonding with the upper stacked structure. The semiconductor or ceramic bulk material, the metal wiring layer, and the bonding layer constitute a single-layer stacked structure. One layer of the stacked structure has a through-hole at its non-metallic wiring layer. The through-hole is located above the metal wiring layer of the next layer of the stacked structure. The bonding layer in the next layer of the stacked structure has a hole at the corresponding position of the through-hole. The hole and the through-hole are used to achieve electrical connection between layers.

[0018] Furthermore, the width of the metal wiring layer is 3μm to 100μm, and the height is 0.3μm to 10μm.

[0019] Furthermore, the minimum spacing between adjacent metal wiring layers is 10 μm to 50 μm.

[0020] Furthermore, the number of stacked layers in the multi-layer stacked structure is not less than 2; and / or: the groove is an inverted trapezoidal groove.

[0021] Furthermore, the metallic material comprises one or more of titanium, platinum, gold, copper, silver, and tin-silver alloy; and / or: the semiconductor in the semiconductor or ceramic block is one of silicon, aluminum nitride, gallium nitride, gallium arsenide, and indium phosphide; and / or: the ceramic in the semiconductor or ceramic block is one of aluminum nitride, diamond, alumina, and silicon nitride.

[0022] The present invention also provides a method for fabricating a multilayer metal wiring structure inside a semiconductor or ceramic bulk material as described in any one of the present invention, comprising the following steps:

[0023] Step 1: Provide a semiconductor or ceramic bulk material, form a mask layer and define a pattern on its surface, and form trenches inside the bulk material by etching;

[0024] Step 2: Deposit metallic material in the trench and on the surface of the block material using a physical deposition method;

[0025] Step 3: Use chemical mechanical polishing to flatten the surface, remove excess metal from the surface of the block material, leaving the metal only in the trenches to form a metal wiring layer;

[0026] Step 4: Deposit a bonding layer on the entire surface of the planarized block material;

[0027] Step 5: Perform patterned etching on the bonding layer to expose the underlying metal or form interlayer connection windows;

[0028] Step 6: Repeat steps 1 to 5 at least once to form a multi-layered stacked structure;

[0029] Step 7: Using an alignment and bonding process, and with the help of a positioning fixture, the multi-layer stacked structure is aligned and bonded to form a multi-layer metal wiring structure with multiple layers of metal wiring inside.

[0030] Furthermore, in step 1, SiN or SiO2 is used as a mask layer, and positive photoresist is used to define the pattern; the etching method is chemical wet etching or plasma dry etching.

[0031] Furthermore, in step 2, metal materials are deposited using electron beam evaporation or sputtering deposition methods; and patterns are defined using negative photoresist through a metal stripping process.

[0032] Further, in step 3, the surface roughness Ra after chemical mechanical polishing is <2 nm; and / or: in step 4, the bonding layer material is selected from one or more of AlN, SiO2, and Al2O3, and is prepared by plasma-enhanced chemical vapor deposition or physical deposition; and / or: in step 5, the bonding layer is etched by ICP, and the etching gas includes one or more of BCl3, Cl2, and Ar.

[0033] Furthermore, in step 7, the allowable error for alignment and bonding is less than 20 μm, the bonding temperature is below 300°C, and the bonding pressure is below 1 MPa.

[0034] Unlike existing technologies, the above-mentioned technical solution forms a metal wiring layer and a bonding layer separately in a single-layer stacked structure, and then bonds the multi-layer stacked structure together using the bonding layer to ultimately form a multi-layer metal wiring structure. This avoids the use of traditional powder co-firing processes and high-temperature processes, thus solving the problem of excessively high fabrication temperatures in the formation of multi-layer metal wiring in existing semiconductors or ceramics. Attached Figure Description

[0035] Figure 1 This is a flowchart of the method steps of the present invention;

[0036] Figure 2 This is a schematic diagram of the block material and the etched structure of the present invention;

[0037] Figure 3 This is a schematic diagram of the metal deposition and planarization process of the present invention;

[0038] Figure 4 This is a schematic diagram of the deposition bonding layer and the etching of the bonding layer in this invention;

[0039] Figure 5 This is a schematic diagram of the multilayer stacking and alignment bonding structure of the present invention.

[0040] Explanation of reference numerals in the attached figures:

[0041] 1. Semiconductor or ceramic bulk materials;

[0042] 2. Trench;

[0043] 3. Metallic materials;

[0044] 4. Metal wiring layer;

[0045] 5. Bonding layer;

[0046] 6. Through hole;

[0047] 7. Drilling holes. Detailed Implementation

[0048] To explain in detail the technical content, structural features, objectives, and effects of the technical solution, the following description is provided in conjunction with specific embodiments and accompanying drawings.

[0049] In this document, the term "embodiment" means that a specific feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The term "embodiment" appearing in various places throughout the specification does not necessarily refer to the same embodiment, nor does it specifically limit its independence or connection with other embodiments. In principle, in this application, as long as there are no technical contradictions or conflicts, the technical features mentioned in each embodiment can be combined in any way to form corresponding implementable technical solutions.

[0050] Unless otherwise defined, the technical terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains; the use of related terms herein is merely for the purpose of describing particular embodiments and is not intended to limit this application.

[0051] In the description of this application, the term "and / or" is used to describe the logical relationship between objects, indicating that three relationships can exist. For example, A and / or B means: A exists, B exists, and A and B exist simultaneously. Additionally, the character " / " in this document generally indicates that the preceding and following objects have an "or" logical relationship.

[0052] In this application, terms such as “first” and “second” are used only to distinguish one entity or operation from another, and do not necessarily require or imply any actual quantity, hierarchy or order relationship between these entities or operations.

[0053] Unless otherwise specified, the use of terms such as “comprising,” “including,” “having,” or other similar expressions in this application is intended to cover non-exclusive inclusion, which does not exclude the presence of additional elements in a process, method, or product that includes the stated elements, such that a process, method, or product that includes a list of elements may include not only those defined elements but also other elements not expressly listed, or elements inherent to such a process, method, or product.

[0054] Similar to the interpretation in the Patent Examination Guidelines, in this application, expressions such as "greater than," "less than," and "exceeding" are understood to exclude the stated number; expressions such as "above," "below," and "within" are understood to include the stated number. Furthermore, in the description of the embodiments in this application, "multiple" means two or more (including two), and similar expressions related to "multiple" are also interpreted in this way, such as "multiple groups" and "multiple times," unless otherwise explicitly specified.

[0055] In the description of the embodiments of this application, the space-related expressions used, such as "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "vertical," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," "axial," "radial," and "circumferential," indicate the orientation or positional relationship based on the orientation or positional relationship shown in the specific embodiments or drawings. They are only for the purpose of describing the specific embodiments of this application or for the reader's understanding, and do not indicate or imply that the device or component referred to must have a specific position, a specific orientation, or be constructed or operated in a specific orientation. Therefore, they should not be construed as limitations on the embodiments of this application.

[0056] Unless otherwise expressly specified or limited, the terms "installation," "connection," "linking," "fixing," and "setting," as used in the description of the embodiments of this application, should be interpreted broadly. For example, "connection" can be a fixed connection, a detachable connection, or an integral setting; it can be a mechanical connection, an electrical connection, or a communication connection; it can be a direct connection or an indirect connection through an intermediate medium; it can be the internal connection of two components or the interaction between two components. For those skilled in the art to which this application pertains, the specific meaning of the above terms in the embodiments of this application can be understood according to the specific circumstances.

[0057] Please see Figures 1 to 5 This invention provides a multilayer metal wiring structure and its fabrication method within a semiconductor or ceramic bulk material. The method includes:

[0058] Step 1: Groove etching of the block substrate.

[0059] A semiconductor or ceramic bulk material 1 is provided, the material of which is selected from any one of the following, but not limited to: Si, AlN, Al2O3, SiN, SiC, diamond, etc. Alternatively, if it is a semiconductor bulk material, the semiconductor bulk material is one of silicon, aluminum nitride, gallium nitride, gallium arsenide, and indium phosphide; or if it is a ceramic bulk material, the ceramic bulk material is one of aluminum nitride, diamond, alumina, and silicon nitride.

[0060] During etching, SiN or SiO2 is used as a mask layer, and a positive photoresist is used to define the pattern. Then, trenches 2 corresponding to the target wiring pattern are formed on the bulk material using chemical wet etching or plasma dry etching. In one embodiment (AlN bulk material): a 6 mol / L KOH solution is used, and etching is performed at 60°C for 10 minutes to obtain trenches 2 with a depth of 3 μm. In another embodiment (SiC bulk material): an etching gas of BCl3:Cl2:Ar = 15 sccm:20 sccm:10 sccm is used, with an ICP power of 300 W and a bias voltage of 100 W, and etching is performed for 30 minutes to obtain trenches 2 with a depth of 3 μm. This trench can be an inverted trapezoidal trench. In some embodiments, the width of the metal wiring layer is 3 μm to 100 μm, and the height is 0.3 μm to 10 μm. The minimum spacing between adjacent metal wiring layers is 10 μm to 50 μm.

[0061] Step 2: Metal deposition.

[0062] Patterning is defined using a negative photoresist via a metal lift-off process. A metal material 3 is grown as a conductive layer using physical deposition. In one embodiment, Ti / Pt / Au is deposited by electron beam evaporation (E-Beam) to thicknesses of 100 nm / 100 nm / 3000 nm. In another embodiment, Ti / Cu is deposited by sputtering to thicknesses of 100 nm / 3000 nm. In some embodiments, the metal material comprises one or more of titanium, platinum, gold, copper, silver, and a tin-silver alloy.

[0063] Step 3: Flattening process.

[0064] A chemical mechanical polishing (CMP) process is used to perform damascus planarization, removing excess metal from the surface of the bulk material, leaving only the metal within the trenches, and achieving a globally flat surface. The metal material 3 forms the metal wiring layer 4. In one embodiment, a CMP slurry based on colloidal silica is used, with a polishing pressure of 2 psi, a rotation speed of 60 rpm, a polishing time of 5 minutes, and a surface roughness Ra < 2 nm.

[0065] Step 4: Deposit the bonding layer.

[0066] A bonding layer 5 is deposited on the entire surface of the planarized bulk material for subsequent interlayer bonding and insulation. The bonding layer material includes, but is not limited to, AlN, SiO2, Al2O3, etc. For example, in one embodiment, a SiO2 bonding layer with a thickness of 1 μm is deposited by plasma-enhanced chemical vapor deposition (PECVD) at a deposition temperature of 200°C and a stress controlled within ±50 MPa.

[0067] Step 5: Patterning and etching of the bonding layer.

[0068] SiN or SiO2 is used as the mask layer, and a positive photoresist is used to define the pattern. The bonding layer is etched using ICP to expose the underlying metal or form interlayer connection windows. For example, in one embodiment (SiC bulk material): an etching gas of BCl3:Cl2:Ar = 15 sccm:20 sccm:10 sccm was used, with an ICP power of 300 W, a bias voltage of 100 W, and an etching time of 1 minute, resulting in a bonding layer etching depth of 0.1 μm.

[0069] Step 6: Through-hole etching.

[0070] Laser etching is used to achieve electrical connections between layers. In one embodiment, a picosecond ultraviolet laser with a wavelength of 355 nm, a pulse width of 10 ps, ​​a power of 5 W, and a repetition frequency of 100 kHz is used to form a 20 μm diameter via 6 in the bonding layer and the bulk material.

[0071] Step 7: Multi-layer stacking and alignment bonding.

[0072] Repeat steps 1 to 6 to prepare multilayer blocks with different wiring layouts, i.e., multiple single-layer stacked structures. A precise alignment and bonding process is employed, using a positioning fixture, allowing an alignment error of less than 20 μm. In one embodiment, the bonding layers of the upper and lower blocks are placed face-to-face in a positioning fixture and bonded for 30 minutes at 300°C, 1 MPa pressure, and a vacuum environment to achieve a multilayer interconnect structure. This forms a multilayer metal wiring structure.

[0073] The above embodiments form a metal wiring layer and a bonding layer in a single-layer stacked structure, and then bond the multi-layer stacked structure together using the bonding layer to form a multi-layer metal wiring structure. This avoids the use of traditional powder co-firing processes and high-temperature processes. The 300°C in the bonding process is also much lower than the 600°C in the co-firing process, thus solving the problem of excessively high fabrication temperatures in the formation of multi-layer metal wiring in existing semiconductors or ceramics.

[0074] Through the above process, a multilayer metal wiring structure is formed inside a semiconductor or ceramic bulk material, such as... Figure 5As shown, a multilayer stacked structure is included, with each layer comprising a semiconductor or ceramic bulk material 1. The semiconductor or ceramic bulk material 1 has trenches 2 internally, filled with a metal material 3. The metal material 3 forms a metal wiring layer 4, which is covered by a bonding layer 5. The bonding layer 5 is laid flat on the surface of the semiconductor or ceramic bulk material 1 for bonding with the upper stacked structure. The semiconductor or ceramic bulk material 1, the metal wiring layer 4, and the bonding layer 5 constitute a single-layer stacked structure. One layer of the stacked structure has a through-hole 6 at its non-metallic wiring layer 4, located above the metal wiring layer 4 of the next layer. The bonding layer 5 of the next layer has a hole 7 at the corresponding position of the through-hole 6. The hole 7 and the through-hole 6 are used to achieve electrical connections between layers. This forms a multilayer metal wiring structure. This avoids the use of traditional powder co-firing processes and high-temperature processes, solving the problem of excessively high fabrication temperatures in existing semiconductor or ceramic multilayer metal wiring processes.

[0075] It should be noted that although the above embodiments have been described herein, this does not limit the scope of patent protection of the present invention. Therefore, any changes and modifications made to the embodiments described herein based on the innovative concept of the present invention, or equivalent structural or procedural transformations made using the content of the present invention's specification and drawings, directly or indirectly applying the above technical solutions to other related technical fields, are all included within the scope of patent protection of the present invention.

Claims

1. A multilayer metal wiring structure inside a semiconductor or ceramic bulk material, characterized by: The structure includes a multilayer stacked structure bonded sequentially. Each layer of the stacked structure includes a semiconductor or ceramic block with trenches inside. The trenches are filled with a metal material that forms a metal wiring layer. A bonding layer covers the metal wiring layer and is laid flat on the surface of the semiconductor or ceramic block for bonding with the upper stacked structure. The semiconductor or ceramic block, the metal wiring layer, and the bonding layer constitute a single-layer stacked structure. One layer of the stacked structure has a through-hole at its non-metallic wiring layer. The through-hole is located above the metal wiring layer of the next layer of the stacked structure. The bonding layer in the next layer of the stacked structure has a hole at the corresponding position of the through-hole. The hole and the through-hole are used to achieve electrical connection between layers.

2. A multilayer metal wiring structure inside a semiconductor or ceramic bulk material according to claim 1, characterized in that: The width of the metal wiring layer is 3μm to 100μm, and the height is 0.3μm to 10μm.

3. A multilayer metal wiring structure inside a semiconductor or ceramic bulk material according to claim 1, characterized in that: The minimum spacing between adjacent metal wiring layers is 10 μm to 50 μm.

4. A multilayer metal wiring structure inside a semiconductor or ceramic bulk material according to claim 1, characterized in that: The number of stacked layers in the multi-layer stacked structure is not less than 2; and / or: the groove is an inverted trapezoidal groove.

5. A multilayer metal wiring structure inside a semiconductor or ceramic bulk material according to claim 1, characterized in that: The metallic material comprises one or more of titanium, platinum, gold, copper, silver, and tin-silver alloy; and / or: the semiconductor in the semiconductor or ceramic block is one of silicon, aluminum nitride, gallium nitride, gallium arsenide, and indium phosphide; and / or: the ceramic in the semiconductor or ceramic block is one of aluminum nitride, diamond, alumina, and silicon nitride.

6. A method of producing a multilayer metal wiring structure inside a semiconductor or ceramic block as claimed in any one of claims 1 to 5, characterized by, Includes the following steps: Step 1: Provide a semiconductor or ceramic bulk material, form a mask layer and define a pattern on its surface, and form trenches inside the bulk material by etching; Step 2: Deposit metallic material in the trench and on the surface of the block material using a physical deposition method; Step 3: Use chemical mechanical polishing to flatten the surface, remove excess metal from the surface of the block material, leaving the metal only in the trenches to form a metal wiring layer; Step 4: Deposit a bonding layer on the entire surface of the planarized block material; Step 5: Perform patterned etching on the bonding layer to expose the underlying metal or form interlayer connection windows; Step 6: Repeat steps 1 to 5 at least once to form a multi-layered stacked structure; Step 7: Using an alignment and bonding process, and with the help of a positioning fixture, the multi-layer stacked structure is aligned and bonded to form a multi-layer metal wiring structure with multiple layers of metal wiring inside.

7. The method of claim 6, wherein: In step 1, SiN or SiO2 is used as a mask layer, and positive photoresist is used to define the pattern; the etching method is chemical wet etching or plasma dry etching.

8. The method of claim 6, wherein: In step 2, metal materials are deposited using electron beam evaporation or sputtering deposition methods; and negative photoresist is used to define patterns through a metal stripping process.

9. The method of claim 6, wherein: In step 3, the surface roughness Ra after chemical mechanical polishing is less than 2 nm; and / or: in step 4, the bonding layer material is selected from one or more of AlN, SiO2, and Al2O3, and is prepared by plasma-enhanced chemical vapor deposition or physical deposition; and / or: in step 5, the bonding layer is etched by ICP, and the etching gas includes one or more of BCl3, Cl2, and Ar.

10. The method of claim 6, wherein: In step 7, the allowable error for alignment bonding is less than 20 μm, the bonding temperature is below 300°C, and the bonding pressure is below 1 MPa.

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