Package substrate with series-parallel laser hole cluster structure for high-speed serdes

Abstract

This application relates to the field of advanced packaging technology and discloses a packaging substrate with a series-parallel laser aperture cluster structure for high-speed SerDes. It includes a first interconnect structure connected to a die and a second interconnect structure connected to a printed circuit board. The first and second interconnect structures are connected via vias. Each of the first and second interconnect structures includes at least one interconnect unit, and each interconnect unit includes at least one interconnect layer. Each interconnect layer includes a cluster structure consisting of at least three laser apertures, which are connected in pairs by wires. The laser apertures are arranged in a polygonal pattern, and the laser apertures of adjacent interconnect layers are staggered vertically. In the horizontal direction, the laser apertures of adjacent interconnect units are connected to each other via pads. The first and second interconnect structures serve as transmission channels for high-speed SerDes signals between the die and the printed circuit board. This application solves the problem of signal transmission failure caused by cracking of the single laser aperture interconnect structure inside the existing packaging substrate.

Description

Technical Field

[0001] This invention relates to the field of advanced packaging technology, and more specifically, to the field of high-density interconnect (HDI) printed circuit board and integrated circuit packaging technology, and more specifically to a packaging substrate with a series-parallel laser aperture cluster structure for high-speed SerDes, and a flip chip including the packaging substrate. Background Technology

[0002] With the rapid development of data centers, artificial intelligence, and high-performance computing technologies, the transmission rate of high-speed serial interfaces (SerDes) has evolved from 56 / 112Gbps PAM4 to 224Gbps PAM4 and even higher. Such high-speed signals are extremely sensitive to the integrity of the transmission channel; any tiny impedance discontinuity or structural defect in the channel can lead to severe signal loss and an increase in bit error rate.

[0003] In flip-chip ball grid array (FC BGA) packages using high-density interconnect (HDI) technology, interlayer electrical interconnects are primarily achieved through micro-blind vias (hereinafter referred to as "laser vias") formed by laser drilling. Due to the thermal expansion coefficient (CTE) mismatch between the package substrate and the die, and the motherboard (or printed circuit board (PCB)), the edge region of the package substrate experiences the greatest mechanical stress under temperature cycling stress during packaging, testing, and long-term service. This makes the copper plating on the walls of the laser vias located in this region, which are used to transmit high-speed SerDes signals, extremely prone to fatigue cracking. Once cracked, it will directly lead to an open signal path, causing system-level data transmission failure.

[0004] Currently, industry solutions primarily focus on process optimization, such as improving laser drilling and electroplating processes to enhance the mechanical toughness of the copper plating on the hole walls, or employing through-hole plating technology. However, these methods cannot eliminate the inherent reliability risks caused by the intrinsic properties of materials and the stresses of the service environment. For SerDes channels employing point-to-point connections, the failure of any critical interconnect point (laser hole) means the interruption of the entire high-speed channel, posing a severe challenge to system reliability.

[0005] Therefore, there is an urgent need for an innovative solution that starts from the design architecture level to fundamentally improve the long-term reliability of high-speed signal interconnect structures. Summary of the Invention

[0006] The purpose of this application is to provide a packaging substrate with a series-parallel laser aperture cluster structure for high-speed SerDes and a flip chip including the packaging substrate, so as to solve the problem of system-level signal transmission failure caused by mechanical stress cracking and open circuit in the existing single laser aperture interconnect structure.

[0007] In a first aspect, this application provides a packaging substrate for high-speed SerDes, comprising: A first interconnect structure connected to a bare die and a second interconnect structure connected to a printed circuit board, wherein the first interconnect structure and the second interconnect structure are connected through vias; The first interconnect structure and the second interconnect structure each include at least two interconnect units, each interconnect unit includes at least one interconnect layer, and each interconnect layer includes a cluster structure composed of at least three laser holes connected in parallel. The at least three laser holes are connected in pairs by wires. The at least three laser holes in the cluster structure are arranged in a polygonal pattern. The laser holes in adjacent interconnect units are staggered in the vertical direction, and the laser holes of adjacent interconnect layers of adjacent interconnect units are connected in series by pads in the horizontal direction, so that the first interconnect structure and the second interconnect structure each form a series-parallel laser hole cluster structure. The first interconnect structure and the second interconnect structure serve as transmission channels for high-speed SerDes signals between the die and the printed circuit board.

[0008] In a preferred embodiment, each interconnect layer includes a cluster structure consisting of three laser apertures arranged in an equilateral triangle.

[0009] In a preferred embodiment, the first interconnect structure and the second interconnect structure each include two interconnect units, wherein the laser aperture of the first interconnect unit is rotated by 60° relative to the laser aperture of the second interconnect unit.

[0010] In a preferred embodiment, the via is connected to the laser via in the adjacent interconnect layer via a pad in the horizontal direction.

[0011] In a preferred embodiment, the motherboard is located above the packaging substrate, and the high-speed signal lines in the packaging substrate are connected to the motherboard through an interlayer.

[0012] In a preferred embodiment, the system further includes: the high-speed differential trace, which is connected to the first interconnect structure connected to the motherboard.

[0013] In a preferred embodiment, the printed circuit board is located below the packaging substrate, and the packaging substrate is connected to the printed circuit board via an array of solder balls.

[0014] In a preferred embodiment, the first interconnect structure and the second interconnect structure are surrounded by anti-pads of a quasi-elliptical shape.

[0015] In a preferred embodiment, the first interconnect structure has an anti-solder pad on the side closer to the motherboard, and the second interconnect structure has a metal solder pad on the side closer to the printed circuit board.

[0016] In a second aspect, this application provides a flip chip for high-speed SerDes, comprising: The aforementioned packaging substrate; The motherboard located above the packaging substrate; The printed circuit board located beneath the packaging substrate.

[0017] It should be understood that, within the scope of this invention, the above-described technical features of this invention and the technical features specifically described below (such as in the embodiments) can be combined with each other to form new or preferred technical solutions. Due to space limitations, they will not be described in detail here. Attached Figure Description

[0018] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the accompanying drawings used in the description of the embodiments or the prior art will be briefly introduced below. It should be understood that the accompanying drawings described below are merely some implementation examples of the present invention, and those skilled in the art can obtain other implementation examples based on these drawings without creative effort.

[0019] Figure 1 This is a schematic diagram of the structure of a flip-chip package according to one embodiment of this application.

[0020] Figure 2 and Figure 3 This is a schematic diagram of the structure of the packaging substrate according to one embodiment of this application.

[0021] Figure 4 This is a cross-sectional view of different layers of the packaging substrate according to one embodiment of this application.

[0022] Figure 5 Simulated S-parameters of a packaging substrate according to one embodiment of this application are shown.

[0023] Figure 6 The effect of laser hole cracking in different layers of the packaging substrate on simulated S-parameters is shown in one embodiment of this application. Detailed Implementation

[0024] In the following description, many technical details are presented to help the reader better understand this application. However, those skilled in the art will understand that the technical solutions claimed in this application can be implemented even without these technical details and various variations and modifications based on the following embodiments.

[0025] Through extensive and in-depth research, the inventors have addressed the reliability bottleneck in existing High-Density Interconnect (HDI) processes, where single laser vias are prone to fatigue cracking due to thermomechanical stress, leading to open circuits in high-speed signal paths. This invention proposes a packaging substrate for high-speed SerDes, where the interconnect structure employs a clustered design of series-parallel laser vias. This invention innovatively replaces single laser vias in the signal path with a clustered structure composed of multiple series-parallel micro-laser vias. By precisely optimizing the laser via diameter, spacing, layout, and corresponding ground anti-pad parameters, this structure exhibits excellent impedance continuity across a wide bandwidth from DC to 65GHz, fully supporting high-quality transmission of 224Gbps PAM4 high-speed signals. The core innovation of this invention lies in the introduction of a physical redundancy mechanism: when one laser via in the cluster fails, the remaining series-parallel via structures still ensure the integrity of the electrical connection, thus completely avoiding single-point failure and greatly enhancing the reliability of high-speed signal interconnects in long-term use. This design is flexible, fully compatible with existing packaging processes, and has significant engineering application value.

[0026] As used in this article, the term "SerDes" is short for SERializer / DESerializer. It is a mainstream time-division multiplexing (TDM) point-to-point (P2P) serial communication technology. At the transmitting end, multiple low-speed parallel signals are converted into high-speed serial signals, transmitted through a transmission medium (optical fiber or copper wire), and finally converted back into low-speed parallel signals at the receiving end. This point-to-point serial communication technology fully utilizes the channel capacity of the transmission medium, reduces the required transmission channels and the number of device pins, increases signal transmission speed, and thus significantly reduces communication costs.

[0027] The term "Flip Chip Ball Grid Array (FC BGA)" is an advanced integrated circuit packaging technology in which the active side of the chip (the side containing transistors and circuits) faces down, is directly connected to the package substrate through tiny bumps, and is connected to the motherboard (PCB) on the bottom of the substrate in the form of an array of solder balls.

[0028] The term "Printed Circuit Board (PCB)" refers to a device manufactured using electronic printing techniques. It serves as a support for electronic components and a carrier for the electrical interconnection of these components.

[0029] The term "via" (also known as a metallized via) refers to a metallized hole on a printed circuit board or package used to achieve electrical connections between different conductive layers. Its core function is to act as a vertical interconnect channel, allowing signals and current to be transmitted between layers of a multilayer board. Depending on the structure, vias are mainly classified as through-hole vias that penetrate all layers, blind vias that connect only the surface layer and inner layers, and buried vias located entirely between inner layers. Vias are manufactured through drilling and metallization (such as copper plating) processes. Besides electrical connections, they are also commonly used for heat dissipation and electromagnetic shielding.

[0030] The term "antipad" refers to a copper-free isolation area on the power or ground plane of a printed circuit board or package, surrounding a via, used to prevent accidental short circuits between the via and the plane layer and to provide electrical isolation. Its core function is to reduce parasitic capacitance by adjusting the size of the isolation area, and in high-speed designs, it is used to control impedance and improve signal integrity.

[0031] The term "simulated S-parameters (scattering parameters)" is a core tool for describing the reflection and transmission characteristics of linear networks at high frequencies. S-parameters represent the complex ratio of the incident wave to the reflected / transmitted wave, reflecting the reflection (e.g., S11, S22) and transmission (e.g., S21, S12) characteristics of the device at specific frequencies.

[0032] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in further detail below with reference to the accompanying drawings.

[0033] One embodiment of this application relates to a package substrate with a series-parallel laser aperture cluster structure for high-speed SerDes. (See reference...) Figure 1 As shown, the package substrate connects the die and the PCB, enabling high-speed SerDes signal transmission between the die and the PCB. The structure of the package substrate is shown in the reference diagram. Figure 2 and Figure 3 As shown, the packaging substrate includes a first interconnect structure 10 connected to a die (not shown) and a second interconnect structure 20 connected to a printed circuit board (not shown). The first interconnect structure 10 and the second interconnect structure 20 are connected through a via (core hole) 30. Each of the first interconnect structure 10 and the second interconnect structure 20 includes two interconnect structures for transmitting differential signals of high-speed SerDes.

[0034] It should be noted that the first interconnect structure 10 and the second interconnect structure 20 can be mutually symmetrical structures.

[0035] The first interconnect structure 10 and the second interconnect structure 20 each include at least one interconnect unit. Each interconnect unit includes at least one interconnect layer, and each interconnect layer includes at least three laser holes. The laser holes are connected in pairs via wires, meaning they are electrically connected in parallel. The at least three laser holes in each interconnect layer and the connecting wires together form a cluster structure. The at least three laser holes in the cluster structure are arranged in a polygonal pattern, forming a parallel laser hole cluster structure. The parallel laser hole cluster structures of adjacent interconnect units are then connected in series to form a series structure, thus making the interconnect structure a "series-parallel laser hole cluster structure". The laser holes in the same interconnect unit overlap in the vertical direction (e.g., the z-axis direction in the figure), and the projections of the laser holes in adjacent interconnect units in the vertical direction are staggered. Each laser hole has a pad at both ends. In the horizontal direction (e.g., the x-axis or y-axis direction in the figure), the pads of the laser holes in adjacent interconnect layers of adjacent interconnect units are connected in series. The first interconnect structure 10 and the second interconnect structure 20 serve as a transmission channel for high-speed SerDes signals between the die and the PCB. High-speed SerDes signals can be high-speed differential signals.

[0036] In one embodiment, the first interconnect structure 10 and the second interconnect structure 20 each include two interconnect units, and each interconnect unit includes two interconnect layers, namely, a first interconnect layer and a second interconnect layer. Each interconnect layer may include three laser apertures, which form a cluster structure. The three laser apertures are connected by wires and arranged in an equilateral triangle. The laser apertures in the two interconnect layers of the same interconnect unit overlap each other in the vertical direction, while the laser apertures of the first interconnect unit are rotated 60° relative to the laser apertures of the second interconnect unit. Specifically, the three laser apertures of the first interconnect unit form an equilateral triangle arrangement, and the three laser apertures of the second interconnect unit form another equilateral triangle arrangement. The triangle formed by the first interconnect unit can be obtained by rotating it by 60°. It is understood that the cluster structure is not limited to an equilateral triangle arrangement and can be other triangular arrangements.

[0037] Laser vias in the interconnect layers of the same interconnect unit are connected vertically via pads, and laser vias in adjacent interconnect layers of adjacent interconnect units are also interconnected horizontally via pads. It should be understood that the laser vias in the interconnect layers are connected to pads both above and below. Because the laser vias of adjacent interconnect units are staggered vertically, the pads of laser vias in adjacent interconnect layers of adjacent interconnect units are connected, for example, via metal wires.

[0038] In another embodiment, the first interconnect structure 10 and the second interconnect structure 20 each include two interconnect units, each interconnect unit including a first interconnect layer and a second interconnect layer. Each interconnect layer may include four laser holes forming a cluster structure, with the four laser holes connected by wires and arranged in a quadrilateral pattern. For example, they may be arranged in a square, rectangular, or other structural configurations. The laser holes in the two interconnect layers of the same interconnect unit overlap vertically, while the laser holes of the first interconnect unit are rotated 45° relative to the laser holes of the second interconnect layer. Specifically, the four laser holes of the first interconnect unit form a square arrangement, and the three laser holes of the second interconnect unit form another square arrangement. The square formed by the first interconnect unit can be obtained by rotating the square formed by the first interconnect unit by 45° to obtain the square formed by the second interconnect unit.

[0039] refer to Figures 2 to 4 As shown, Figure 2 and Figure 3 The diagram shows a cluster structure consisting of three laser apertures connected in series and parallel. Figure 4 yes Figure 2 and Figure 3 The image shows the optical patterns of each layer of the encapsulation structure. Note that... Figure 2 and Figure 3 The middle part is omitted Figure 4 The L1 layer in the optical pattern. The black areas of the optical pattern represent the metal structure that is retained after etching; the white areas of the optical pattern represent the metal structure that needs to be etched away; and the gray areas of the optical pattern represent the position and size of the connection between the current layer and the laser hole of the next layer.

[0040] The first interconnect structure 10 includes a first interconnect unit 101 and a second interconnect unit 102, wherein the first interconnect unit 101 includes Figure 3 The structure of L2 and L3 in the middle and Figure 3 The L4 portion of the structure, the second interconnect unit 102 includes Figure 3 The structure of L5 and L6 in the middle and Figure 3 The structure of L4 is shown below. L2 and L3, L3 and L4, L4 and L5, and L5 and L6 each constitute an interconnect layer. It should be understood that the laser holes of the first interconnect unit 101 and the second interconnect unit 102 are connected horizontally via pads (i.e., in the L4 layer). Since the laser holes in the L2 and L3 layers are offset from those in the L4 and L5 layers on the z-axis, the L4 layer in the xy-plane includes the pads of the laser holes from the previous interconnect layer as well as the pads of the laser holes from the next interconnect layer, and these pads are interconnected.

[0041] The second interconnection structure 20 includes a first interconnection unit 201 and a second interconnection unit 202, wherein the first interconnection unit 201 includes Figure 3The structure of L7 and L8 in the middle and Figure 3 The L9 portion of the structure, the second interconnect unit 202 includes Figure 3 The structure of L10 and L11 and Figure 3 The structure of L9 is shown below. L7 and L8, L8 and L9, L9 and L10, and L10 and L11 each constitute an interconnect layer. It should be understood that the laser holes of the first interconnect unit 201 and the second interconnect unit 202 are connected horizontally (i.e., in layer L9) via pads. Since the laser holes in layers L7 and L8 are staggered with those in layers L9 and L10 on the z-axis, layer L9 includes pads for laser holes from both the previous and next interconnect layers in the xy-plane, totaling six pads, which are interconnected. Furthermore, layer L12 consists of metal pads used for subsequent connection to solder balls, thereby further connecting to the PCB.

[0042] Via 30 is horizontally connected to laser vias in adjacent interconnect layers via pads. The die is located above the package substrate, and high-speed signal lines 40 in the package substrate are connected to the die via an interposer. The package substrate also includes high-speed differential traces 40, which are connected to a first interconnect structure 10 connected to the die. The PCB is located below the package substrate, and the package substrate is connected to the printed circuit board via a solder ball array.

[0043] like Figure 4 As shown, the first interconnect structure 10 and the second interconnect structure 20 are surrounded by anti-pads of a near-elliptical shape. The anti-pad is formed on the side of the first interconnect structure 10 closer to the die, and the metal pad is formed on the side of the second interconnect structure 20 closer to the printed circuit board.

[0044] To better understand the technical solution of this application, a specific example is provided below. The details listed in this example are mainly for ease of understanding and are not intended to limit the scope of protection of this application.

[0045] This invention relates to a micro-blind via structure and its design method for transmitting high-speed serial interface (SerDes) signals in flip-chip ball grid array (FC BGA) packages, to solve the problem of system-level signal transmission failure caused by mechanical stress-induced cracking and open circuits in existing single laser via interconnect structures. The core objective of this invention is to significantly improve the long-term reliability of high-speed signal transmission paths while ensuring excellent signal integrity.

[0046] To achieve the above objectives, this invention proposes a "serial-parallel laser aperture cluster" structure. Its core design concept is to abandon the traditional single laser aperture at the required interconnection locations on each layer of the packaging substrate for a single high-speed SerDes signal channel, and instead use a "aperture cluster" composed of multiple micro-laser apertures connected in series and parallel to achieve interlayer electrical connections. The specific technical solution includes the following two aspects.

[0047] 1. Series-Parallel Laser Via Cluster Structure: In a preferred embodiment, each interconnect layer has at least three laser via pads, which are interconnected in pairs by wires to form a series-parallel network. Electrical connection between adjacent layers is achieved through at least three series-parallel micro-laser vias, thus forming a redundant interconnect cluster spanning multiple layers.

[0048] 2. Ground (GND) Antipad Co-optimization: To ensure the continuity of high-speed signal impedance, the antipad size of each reference ground layer is co-optimized. By precisely controlling the shape and size of the antipad, the "series-parallel laser via cluster" structure and the reference ground plane maintain matched impedance characteristics within the target wideband (e.g., DC to 65GHz).

[0049] Simulation data demonstrates that the "serial-parallel laser aperture cluster" structure described in this invention exhibits excellent signal integrity performance. Within a DC~65GHz bandwidth, its reflection coefficient (S11) is below -15dB, and its insertion loss (S21) is better than -0.5dB. Crucially, simulation results confirm that even if individual laser apertures within the cluster crack, the impact on the overall channel signal integrity is negligible.

[0050] Figure 2 and Figure 3 This is a 3D rendering of a clustered series-parallel laser aperture. It includes a pair of high-speed differential lines, a pair of clustered series-parallel laser apertures above the core aperture, a pair of clustered series-parallel laser apertures below the core aperture, and a pair of core apertures connecting the clustered series-parallel laser apertures.

[0051] Figure 4 In the diagram, (a) to (l) correspond to the optical pattern of clustered serial-parallel laser vias and GND anti-pads in each layer (L1~L12) of the package, respectively. The black area of ​​the optical pattern represents the metal structure retained after etching; the white area of ​​the optical pattern represents the metal structure that needs to be etched away; and the gray area of ​​the optical pattern represents the position and size of the connection between the current layer and the laser via of the next layer.

[0052] Figure 5 These are the simulated S-parameters of the clustered series-parallel laser apertures and the surrounding GND overall structure. Figure 6 This relates to the impact of cracking in individual laser apertures within a clustered series-parallel laser aperture configuration on the simulated S-parameters. Figure 6(a) represents the simulated S-parameters of a clustered series-parallel laser aperture structure in L2-L3 and L10-L11, where a laser aperture crack exists (the simulation sets the aperture to be disconnected from the pad with a gap of 2µm). Figure 6 (b) represents the simulated S-parameters of the clustered series-parallel laser aperture structure in L2-L3 and L8-L9, where a laser aperture crack exists (the simulation sets the aperture to be disconnected from the disk with a gap of 2µm). Figure 6 (c) represents the simulated S-parameters of the clustered series-parallel laser aperture structure in L4-L5 and L10-L11, where one laser aperture cracks (the simulation sets the aperture to be separated from the disk with a gap of 2µm). Figure 6 Figure (d) shows the simulated S-parameters of the clustered series-parallel laser aperture structure when one laser aperture cracks in L4-L5 and L8-L8 (the simulation sets the aperture to be separated from the disk with a gap of 2µm). As can be seen from the figure, when one laser aperture cracks, the change in the simulation results is negligible, that is, the impact on the signal integrity of the entire channel is approximately negligible.

[0053] In summary, the present invention has the following outstanding advantages and effects: 1. Revolutionary reliability improvement: By introducing physical redundancy design, the traditional "single point failure" mode is transformed into a "fault-tolerant" mode. Even if individual laser holes in the cluster crack due to stress, the remaining series and parallel holes can still maintain electrical continuity, fundamentally eliminating the signal path open circuit caused by single hole failure, and significantly extending the service life of the product under harsh operating conditions.

[0054] 2. Superior signal integrity assurance: Through integrated electromagnetic simulation and collaborative optimization design, this cluster structure can achieve excellent impedance matching and low-loss transmission within the target high-speed bandwidth (supporting up to 224Gbps PAM4 and above), meeting the most stringent high-speed signal integrity requirements.

[0055] 3. Excellent design and process compatibility: This invention does not require changes to existing mainstream HDI manufacturing processes (such as laser drilling, pattern electroplating, etc.). It can be implemented simply by modifying the Gerber design file, which facilitates rapid mass production and has extremely high engineering practical value and cost-effectiveness.

[0056] Another embodiment of this application also includes a flip chip for high-speed SerDes, comprising: the aforementioned packaging substrate; a motherboard located above the packaging substrate; and a printed circuit board located below the packaging substrate. (See reference) Figure 1As shown, one or more dies are connected to the package substrate via an interposer. These dies serve as the control motherboard, and the package substrate is connected to the PCB via solder balls. High-speed differential signals are transmitted to the PCB through the interconnect structure in the package substrate.

[0057] The various technical features disclosed in the above-described invention, the various technical features disclosed in the following embodiments and examples, and the various technical features disclosed in the accompanying drawings can be freely combined to form various new technical solutions (all of which should be considered as having been recorded in this specification), unless such a combination of technical features is technically infeasible. For example, in one example, feature A+B+C is disclosed, and in another example, feature A+B+D+E is disclosed. Features C and D are equivalent technical means that serve the same function, and technically only one needs to be used; it is impossible to use both simultaneously. Feature E can be technically combined with feature C. Therefore, the solution A+B+C+D should not be considered as having been recorded because it is technically infeasible, while the solution A+B+C+E should be considered as having been recorded.

[0058] Several different embodiments have been described above according to different features of the present invention. Specific elements and arrangements in the present invention are for simplification, but the present invention is not limited to these embodiments. For example, the description of forming a first element on a second element may include embodiments where the first element and the second element are in direct contact, as well as embodiments where additional elements are formed between the first element and the second element, such that the first element and the second element are not in direct contact. Furthermore, for the sake of brevity, the present invention uses repeated element symbols and / or letters in different examples, but this does not imply a specific relationship between the various embodiments and / or structures.

[0059] Furthermore, spatial terms such as "above," "below," "higher," "lower," and similar terms may be used in the embodiments. These relational terms are used to facilitate the description of the relationship between one element(s) or feature(s) in the diagram(s). These spatial relational terms include different orientations of the device in use or operation, as well as the orientations described in the diagram. The device may be turned to different orientations (rotated 90 degrees or other orientations), and the spatially related adjectives used therein can be interpreted in the same way.

[0060] All references to this specification are considered to be incorporated integrally into the disclosure of this application so that they can serve as the basis for modifications if necessary. Furthermore, it should be understood that the above descriptions are merely preferred embodiments of this specification and are not intended to limit the scope of protection of this specification. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of one or more embodiments of this specification should be included within the scope of protection of one or more embodiments of this specification.

Claims

1. A packaging substrate with a series-parallel laser aperture cluster structure for high-speed SerDes, characterized in that, include: A first interconnect structure connected to a bare die and a second interconnect structure connected to a printed circuit board, wherein the first interconnect structure and the second interconnect structure are connected through vias; The first interconnect structure and the second interconnect structure each include at least two interconnect units, each interconnect unit includes at least one interconnect layer, and each interconnect layer includes a cluster structure composed of at least three laser holes connected in parallel. The at least three laser holes are connected in pairs by wires. The at least three laser holes in the cluster structure are arranged in a polygonal pattern. The laser holes in adjacent interconnect units are staggered in the vertical direction, and the laser holes of adjacent interconnect layers of adjacent interconnect units are connected in series by pads in the horizontal direction, so that the first interconnect structure and the second interconnect structure each form a series-parallel laser hole cluster structure. The first interconnect structure and the second interconnect structure serve as transmission channels for high-speed SerDes signals between the die and the printed circuit board.

2. The packaging substrate as described in claim 1, characterized in that, Each interconnect layer includes a cluster structure consisting of three laser apertures arranged in an equilateral triangle.

3. The packaging substrate as described in claim 2, characterized in that, The first interconnect structure and the second interconnect structure each include two interconnect units, and the laser aperture of the first interconnect unit is rotated by 60° relative to the laser aperture of the second interconnect unit.

4. The packaging substrate as described in claim 1, characterized in that, The vias in the horizontal direction are connected to the laser holes in the adjacent interconnect layers via pads.

5. The packaging substrate as described in claim 1, characterized in that, The die is located above the packaging substrate, and the high-speed signal lines in the packaging substrate are connected to the die through an interposer.

6. The packaging substrate as described in claim 5, characterized in that, Also includes: The high-speed differential trace is connected to the first interconnect structure that is connected to the die.

7. The packaging substrate as described in claim 1, characterized in that, The printed circuit board is located below the packaging substrate, and the packaging substrate is connected to the printed circuit board through an array of solder balls.

8. The packaging substrate as described in claim 1, characterized in that, The first interconnect structure and the second interconnect structure are surrounded by anti-pads of a near-elliptical shape.

9. The packaging substrate as described in claim 1, characterized in that, The first interconnect structure has an anti-pad on the side near the die, and the second interconnect structure has a metal pad on the side near the printed circuit board.

10. A flip chip for high-speed SerDes, characterized in that, include: The packaging substrate as described in any one of claims 1 to 9; The bare die located above the packaging substrate; The printed circuit board located beneath the packaging substrate.

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