Semiconductor devices

Abstract

One embodiment of the present disclosure relates to a semiconductor device having a substrate, first and second semiconductor chips. The first and second semiconductor chips each have at least one functional module and at least one module power control circuit. The first semiconductor chip further has a summarizing circuit that sums up a start-up request signal requesting the supply of power voltage from at least one module power control circuit, along with a score based on parasitic capacitance, and outputs a summed start-up request signal and a summed score. The second semiconductor chip further has a main arbitration circuit that, based on the summed start-up request signal and summed score from the summarizing circuit, and the start-up request signals requesting the supply of power voltage from multiple module power control circuits included in the second semiconductor chip, along with scores based on parasitic capacitance, outputs an authorization signal authorizing the supply of power voltage to one or more module power control circuits that have output start-up request signals to the first and second semiconductor chips.

Description

Technical Field

[0001] This disclosure relates to a semiconductor device. Background Technology

[0002] Previously, there were technologies that mounted multiple semiconductor chips on a single substrate or package to manufacture chiplet products or multi-chip packaged products. In such products with multiple semiconductor chips, controlling the power supply voltage of each semiconductor chip requires considering the power supply status of other semiconductor chips. For example, if multiple semiconductor chips sharing a power domain are simultaneously supplied with power to multiple functional modules, inrush current may cause malfunctions or failures.

[0003] Patent Document 1: US Patent No. 11,467,655

[0004] Patent Document 2: Japanese Patent Application Publication No. 2023-075588

[0005] However, in a power control circuit that controls the power supply voltage of a certain functional module, it is impossible to know the timing of the power supply voltage of other functional modules by other power supply voltage circuits. There is room for improvement in the timing control of power supply voltage across multiple semiconductor chips. Summary of the Invention

[0006] One of the purposes of this disclosure is to properly control the timing of the power supply voltage across multiple semiconductor chips.

[0007] One embodiment of this disclosure relates to a semiconductor device comprising a substrate, a first semiconductor chip disposed on the substrate, and a second semiconductor chip disposed on the substrate. The first semiconductor chip and the second semiconductor chip each have: at least one functional module; and at least one module power control circuit, electrically connected to one or more of the at least one functional module, controlling the supply of power voltage to each of the one or more functional modules. The first semiconductor chip further comprises a summarizing circuit, which summarizes the start-up request signals for requesting the supply of power voltage to the one or more functional modules respectively controlled by one or more of the module power control circuits included in the first semiconductor chip, and the summarizing signals based on parasitic capacitance, and outputs a summarized start-up request signal and a summarized score. The second semiconductor chip also has a main arbitration circuit, which outputs a permission signal to allow the supply of power voltage to begin to the first semiconductor chip and the first or more module power control circuits that have output the above-mentioned start-up request signal and the above-mentioned score from the above-mentioned summary circuit, and the start-up request signal for requesting to start supplying power voltage for the above-mentioned functional modules of the above-mentioned one or more of the plurality of module power control circuits included in the second semiconductor chip, based on the score of parasitic capacitance.

[0008] According to one embodiment of this disclosure, the timing of the power supply voltage across multiple semiconductor chips can be appropriately controlled. Attached Figure Description

[0009] Figure 1 This is a diagram illustrating an example of the structure of the semiconductor device according to the first embodiment.

[0010] Figure 2 It means Figure 1 A diagram showing an example of the structure of the main arbitration circuit.

[0011] Figure 3 It means Figure 1 A diagram illustrating an example of the structure of a split circuit and a summing circuit.

[0012] Figure 4 It means Figure 2 A flowchart of an example of the operation flow of the main arbitration circuit.

[0013] Figure 5 It means Figure 4 A flowchart of an example of the process of enqueuing an item using the action.

[0014] Figure 6 It means Figure 4 A flowchart of an example of the process of requesting storage action.

[0015] Figure 7 It means Figure 4 Here is a flowchart of an example of the process for simultaneously granting permission to determine an action.

[0016] Figure 8 It means Figure 3 The flowchart is an example of the process of summarizing the actions of the summary circuit.

[0017] Figure 9 It means Figure 3 The flowchart is an example of a process for summarizing the summary circuit using the request to store actions.

[0018] Figure 10 It means Figure 3 A flowchart of an example of the segmentation operation of a segmentation circuit.

[0019] Figure 11 This is a diagram illustrating an example of the structure of the semiconductor device according to the second embodiment.

[0020] Figure 12 This is a diagram illustrating an example of the structure of the semiconductor device according to the third embodiment.

[0021] Figure 13 This is a diagram illustrating an example of the structure of the semiconductor device according to the fourth embodiment.

[0022] Figure 14 This is a diagram illustrating an example of the structure of the semiconductor device according to the fifth embodiment.

[0023] Figure 15 This is a diagram illustrating an example of the structure of the semiconductor device according to the sixth embodiment.

[0024] Figure 16 This is a diagram illustrating an example of the structure of the semiconductor device according to the seventh embodiment.

[0025] Figure 17 This is a diagram illustrating an example of the structure of the semiconductor device according to the eighth embodiment.

[0026] Figure 18 This is a diagram illustrating an example of the structure of the semiconductor device according to the ninth embodiment. Detailed Implementation

[0027] Hereinafter, the semiconductor device of this embodiment will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to this embodiment.

[0028] In the following description, the same reference numerals are used to denote components with essentially the same function and structure, and repeated descriptions are only performed when necessary. Furthermore, the embodiments may be appropriately combined with other embodiments, modifications, and / or prior art.

[0029] Furthermore, in the description of this disclosure, constituent elements having the same or substantially the same function are sometimes distinguished by adding English letters or numbers to the end of the reference numerals. Alternatively, when multiple constituent elements having the same or substantially the same function are not distinguished, the English letters or numbers at the end of the reference numerals are sometimes omitted and described uniformly.

[0030] Furthermore, in the description of this disclosure, "determine whether it is A" can be "determine whether it is A", "determine whether it is not A", or "determine whether it is A".

[0031] Furthermore, in various embodiments of this disclosure, semiconductor devices, such as those comprising multiple semiconductor chips mounted on a substrate or package and referred to as SoC (System on a Chip) or SiP (System in Package), are exemplified as semiconductor devices.

[0032] (First Implementation)

[0033] Figure 1 This is a diagram illustrating an example of the structure of the semiconductor device 1a according to the first embodiment. (See diagram for example.) Figure 1 As shown, the semiconductor device 1a has a power management IC (Integrated Circuit) 3 and multiple semiconductor chips 5.

[0034] A power management IC 3 and multiple semiconductor chips 5 are disposed on a substrate 2. The substrate 2 is formed, for example, of silicon or resin. The substrate 2 is, for example, a Si interposer substrate, but other printed circuit boards or other circuit boards for semiconductor devices may also be used appropriately. The power management IC 3 is a composite power supply circuit that generates power supply voltages to the multiple semiconductor chips 5 respectively. Wiring patterns constituting a power supply domain 4 are formed on the substrate 2. The power supply domain 4 is a power supply group that receives power from the power management IC 3.

[0035] Figure 1Semiconductor chips 5a and 5b are illustrated as multiple semiconductor chips 5. Semiconductor chips 5a and 5b belong to a common power domain 4 and are electrically connected to a power management IC 3. Semiconductor chips 5a and 5b each have circuit groups 6a and 6b. Circuit groups 6a and 6b each have at least one switch 13, at least one functional module 15, and at least one module power control circuit 17. Additionally, semiconductor chip 5a also has a main arbitration circuit 18. Furthermore, semiconductor chip 5b also has a sub-arbitration circuit 19, a segmentation circuit 31, and a summarization circuit 33. Here, semiconductor chip 5a is an example of a second semiconductor chip disposed on a substrate. Furthermore, semiconductor chip 5b is an example of a first semiconductor chip disposed on a substrate.

[0036] At least one module power control circuit 17 is electrically connected to the main arbitration circuit 18. Figure 1 In the example, the power control circuits 17 of each module of semiconductor chip 5a are electrically connected to the main arbitration circuit 18 within the same semiconductor chip 5a. Additionally, the power control circuits 17 of each module of semiconductor chip 5b are electrically connected to the sub-arbitration circuits 19 within semiconductor chip 5b.

[0037] At least one module power control circuit 17 is located in normally open regions 9a and 9b that receive power voltage from power domain 4 at all times. At least one module power control circuit 17 is electrically connected to at least one functional module 15 within the same semiconductor chip 5. At least one module power control circuit 17 controls the power voltage supply from power management IC 3 for each corresponding at least one functional module 15.

[0038] Specifically, for each of the at least one functional module 15 connected to semiconductor chip 5a, the module power control circuit 17 outputs a power supply voltage turn-on request signal and a score to the main arbitration circuit 18 based on the operating state of that functional module 15. Furthermore, based on the power supply voltage turn-on permission signal from the main arbitration circuit 18, the module power control circuit 17 of semiconductor chip 5a controls the turn-on / turn-off of the power supply voltage to that functional module 15 and the power supply voltage supply sequence. Similarly, for each of the at least one functional module 15 connected to semiconductor chip 5b, the module power control circuit 17 outputs a power supply voltage turn-on request signal and a score to the aggregation circuit 33 based on the operating state of that functional module 15. Furthermore, based on the power supply voltage turn-on permission signal from the sub-arbitration circuit 19, the module power control circuit 17 of semiconductor chip 5b controls the turn-on / turn-off of the power supply voltage to that functional module 15 and the power supply voltage supply sequence. The score will be described later.

[0039] Furthermore, this disclosure illustrates, but is not limited to, the control of each of at least one functional module 15 transitioning from a power-off state to an on state. For example, this disclosure can also be applied to the control of each of at least one functional module 15 transitioning from a first operating mode to a second operating mode where the operating voltage (or operating frequency) is higher than that of the first operating mode, or to a combination of these applications.

[0040] At least one functional module 15 is electrically connected to a corresponding switch 13. Specifically, at least one functional module 15 is connected to the power domain 4 via a corresponding switch 13. At least one functional module 15 is at least one processor, driven by a power supply voltage from the power management IC 3.

[0041] As an example, at least one functional module 15 is a CPU (Central Processing Unit) core, but it can also be other processors. Furthermore, at least one functional module 15 can be either a processor that implements a predetermined function by executing a program loaded from ROM (internal memory) or the like into RAM (internal memory), or a processor constructed as a dedicated circuit to implement a predetermined function. Additionally, each circuit group 6 can also provide two or more functional modules 15 of two or more types. Moreover, the functions of the two or more functional modules 15 can be the same or different.

[0042] At least one switch 13 is controlled by the corresponding module power control circuit 17, switching the conduction / disconnection between the corresponding functional module 15 and the power management IC3 (power domain 4).

[0043] Figure 1 Examples include three module power control circuits 17 controlling the supply of power voltage to one functional module 15 for each semiconductor chip 5, and one module power control circuit 17 controlling the supply of power voltage to each of two functional modules 15. Furthermore, the number of module power control circuits 17 in each semiconductor chip 5 is arbitrary and can be appropriately designed. Additionally, the number of functional modules 15 controlled by one module power control circuit 17 is arbitrary and can be appropriately designed. Moreover, the number of functional modules 15 and module power control circuits 17 can be the same or different among two or more semiconductor chips 5.

[0044] The main arbitration circuit 18 is located in the normally open region 9a. The main arbitration circuit 18 has an internal register. Based on the thresholds for semiconductor chips 5a and 5b stored in the internal register, and the power supply voltage enable request signals and scores received from the power supply control circuits 17 of each module, the main arbitration circuit 18 outputs a power supply voltage enable permission signal to the power supply control circuits 17 of each module.

[0045] Here, the "fraction" is based on the parasitic capacitance of the functional module 15 receiving power and the resistance value of the switch 13 connected to the functional module 15. The fraction of each functional module 15 is, for example, predetermined and stored in the internal memory of each functional module 15 or the module power control circuit 17.

[0046] As an example, the value of the fraction can be designed such that the response time when switch 13 is turned on, i.e., the time until steady state is reached, becomes a time constant that meets the required specifications. This time constant "τ" is, for example, expressed as "τ = CR" when the capacitance of the parasitic capacitance of functional module 15 is "C" and the resistance of the corresponding switch 13 is "R". Here, in the transition state from the turn-on of switch 13 to the steady state of the parasitic capacitance of functional module 15, the surge current reaches its maximum at the point where the unit time change "dV / dt" of its potential "V" reaches its maximum. Therefore, the value of the fraction can be obtained by multiplying the maximum "dV / dt" in the transition state by "1 / R", i.e., the value of "dI / dt". This fractional value is an inherent value of the circuit, depending on the operating frequency, operating voltage, circuit size, etc.

[0047] Additionally, the "threshold" is the amount of drop in power supply voltage (or power supply current) that prevents each semiconductor chip 5 from malfunctioning, and the current tolerance value of the power management IC 3. This threshold is predetermined for the power management IC 3 and semiconductor chip 5 and stored in the internal registers (memory) of the main arbitration circuit 18 and the sub-arbitration circuit 19.

[0048] As an example, the dynamic voltage drop (DVD) is generated proportionally to the surge current. Therefore, the threshold value can be expressed as: when the dynamic voltage drop (≈ surge current) within the range specified by each process (approval condition) that prevents malfunction is set to "X", and the current tolerance value (current tolerance) specified in the power management IC3 is set to "Y", the threshold value can be expressed as "Min(X, Y)". Furthermore, the threshold value for the multiple semiconductor chips 5 sharing the power domain 4, for example, when the dynamic voltage drop "X" of semiconductor chip "A" and semiconductor chip "B" are "XA" and "XB" respectively, can be expressed as "Min("XA", "XB", Y)". For example, in the semiconductor device 1 according to this embodiment, the threshold value used by the sub-arbitration circuit 19 for semiconductor chip 5b is expressed as "Min("XB", Y)". Moreover, for example, the threshold value used by the main arbitration circuit 18 for the system, i.e., semiconductor chips 5a and 5b, is expressed as "Min("XA", "XB", Y)".

[0049] The main arbitration circuit 18 compares the total score (total score) of at least one functional module 15 with an enable request with a threshold. Then, when the total score is below the threshold, the main arbitration circuit 18 authorizes all received enable requests. On the other hand, when the total score is greater than the threshold, the main arbitration circuit 18 repeats the following process: authorizes predetermined high-priority enable requests within the range where the total score does not exceed the threshold, until the total score of the received enable requests falls below the threshold.

[0050] Figure 2 It means Figure 1 A diagram showing an example of the structure of the main arbitration circuit 18. (See diagram for example.) Figure 2 As shown, the main arbitration circuit 18 includes a request acceptance circuit 191, a request storage memory 193, a simultaneous permission determination circuit 195, and a simultaneous permission sending circuit 197.

[0051] The request receiving circuit 191 performs an enqueue entry operation. For example, the request receiving circuit 191 sequentially stores the activation requests and scores for at least one functional module 15 of semiconductor chips 5a and 5b, received sequentially from the power control circuit 17 of at least one module of semiconductor chips 5a and 5b, into the enqueue entry 201. Figure 2 As shown, the queuing entry 201 has a region for each of at least one functional module 15 for the controlled object.

[0052] Additionally, the request receiving circuit 191 performs a request storage operation. For example, the request receiving circuit 191 stores data stored in the enqueue entry 201 as enqueue data 203 into the request storage memory 193 at predetermined intervals. The request storage memory 193 is, for example, a FIFO (First In, First Out) memory. Figure 2 As shown, the enqueued data 203 has a region for each of at least one functional module 15 for the controlled object.

[0053] Furthermore, the priority of supplying power to the functional module 15 can be adjusted by determining the storage location in the request storage memory 193 based on a predetermined priority. That is, the calculation of the total score described later can be performed based on the priority set for each of the multiple functional modules 15 of the multiple semiconductor chips 5. This adjustment can be performed by setting the storage location in the enqueue entry 201 and the enqueue data 203, or by setting the starting position for reading (searching) from the enqueue data 203 in the simultaneous permission determination described later, or by a combination of these.

[0054] Simultaneous permission determination circuit 195 performs simultaneous permission determination. For example, upon receiving sequential power control requests from at least one module power control circuit 17 of semiconductor chips 5a and 5b for at least one functional module 15 of semiconductor chips 5a and 5b, simultaneous permission determination circuit 195 determines whether power supply to each functional module 15 is feasible. Specifically, simultaneous permission determination circuit 195 calculates a total score (total score) of at least one functional module 15 with power requests within a predetermined period based on the power requests and scores stored in request storage memory 193. Furthermore, simultaneous permission determination circuit 195 determines whether power supply to the functional module 15 with power requests is feasible based on a comparison of the total score with a threshold value for semiconductor chips 5a and 5b. Then, simultaneous permission determination circuit 195 stores the determination result in simultaneous permission flag 205. Figure 2 As shown, the license mark 205 also has a region for each of at least one functional module 15 for the controlled object.

[0055] Simultaneously, the simultaneous permission sending circuit 197 performs a simultaneous permission sending operation. For example, referring to the simultaneous permission flag 205, the simultaneous permission sending circuit 197 sends a permission related to at least one functional module 15 whose power supply has been permitted by the simultaneous permission determination circuit 195 to at least one of the module power control circuit 17 of semiconductor chip 5a and the partitioning circuit 31 of semiconductor chip 5b. Furthermore, the permission sent to the partitioning circuit 31 of semiconductor chip 5b relates to at least one module power control circuit 17 of semiconductor chip 5b.

[0056] Furthermore, the simultaneous permission determination circuit 195, when a priority is set, starts with the highest priority start request; when no priority is set, it repeatedly grants power supply within a range where the total score does not exceed a threshold, following the reading order. At this time, each time the simultaneous permission determination circuit 195 determines whether power supply is feasible, it stores the determination result in the simultaneous permission flag 205 and provides a start notification to the simultaneous permission sending circuit 197. Additionally, each time the simultaneous permission sending circuit 197 receives a start notification from the simultaneous permission determination circuit 195, it uses this start notification as a trigger and, referring to the simultaneous permission flag 205, sends out permission.

[0057] The summarizing circuit 33 is located in the normally open region 9b. The summarizing circuit 33 is electrically connected to the main arbitration circuit 18 of semiconductor chip 5a and at least one module power control circuit 17 of semiconductor chip 5b. The summarizing circuit 33 receives the turn-on request signal and score from each module power control circuit 17 of semiconductor chip 5b, and outputs the summarizing turn-on request signal and the summarizing score (the total value of the scores) to the main arbitration circuit 18.

[0058] The segmentation circuit 31 is located in the normally open region 9b. The segmentation circuit 31 is electrically connected to the main arbitration circuit 18 of semiconductor chip 5a and the sub-arbitration circuit 19 of semiconductor chip 5b. When a permission signal is input from the main arbitration circuit 18, the segmentation circuit 31 extracts the module power control circuit 17 of semiconductor chip 5b corresponding to the permission signal, and outputs the permission signal and score corresponding to the extracted module power control circuit 17 to the sub-arbitration circuit 19.

[0059] Sub-arbitration circuit 19 is located within normally open region 9b. Sub-arbitration circuit 19 is electrically connected to split circuit 31 and at least one module power control circuit 17. Sub-arbitration circuit 19 has the same structure as main arbitration circuit 18. For example, sub-arbitration circuit 19 has an internal register that outputs permission signals for enabling power voltage to each module power control circuit 17 of semiconductor chip 5b based on threshold values ​​stored in the internal register and power voltage enable request signals and fractions from split circuit 31 regarding the power supply voltage of each module power control circuit 17 of semiconductor chip 5b.

[0060] Figure 3 It means Figure 1 A diagram illustrating an example of the structure of the dividing circuit 31 and the summing circuit 33. (See diagram for example.) Figure 3As shown, the segmentation circuit 31 has a segmentation permission sending circuit 311. Additionally, the aggregation circuit 33 has a request acceptance circuit 331 and an aggregation request sending circuit 333. Furthermore, either the segmentation circuit 31 or the aggregation circuit 33 has an aggregation request storage memory 32. Alternatively, the aggregation request storage memory 32 may also be an external memory for both the segmentation circuit 31 and the aggregation circuit 33.

[0061] The request receiving circuit 331 performs a summary entry operation. For example, the request receiving circuit 331 sequentially stores the activation requests and scores for at least one functional module 15 of the semiconductor chip 5b, received sequentially from at least one module power control circuit 17 of the semiconductor chip 5b, into the summary entry 202. Figure 3 As shown, the summary entry 202 has a region for each of at least one functional module 15 of the semiconductor chip 5b for the controlled object.

[0062] Additionally, the request acceptance circuit 331 and the summary request sending circuit 333 perform a summary request storage operation. For example, the request acceptance circuit 331 stores data stored in the summary entry 202 as enqueue data 204 into the summary request storage memory 32 at predetermined intervals. Figure 3 As shown, the queuing data 204 has a region for each of at least one functional module 15 of the semiconductor chip 5b of the controlled object. In addition, the request acceptance circuit 331 stores the opening request and score in the summary request storage memory 32, and the summary request output circuit 333, referring to the summary entry 202, outputs the summary opening request and summary score (the total value of the scores) to the main arbitration circuit 18.

[0063] Furthermore, by determining the storage location in the summary request storage memory 32 based on a predetermined priority, the priority of the power supply to the functional modules 15 of the semiconductor chip 5b can be adjusted. That is, the calculation of the summary score, described later, can be performed based on the priority set for each of the at least one functional module 15 of the semiconductor chip 5b. This adjustment can be performed by setting the storage location in the summary entry 202 and the enqueue data 204, or by setting the starting position for reading (searching) from the summary entry 202 in the aforementioned summary request storage operation, or by setting the starting position for reading (searching) from the enqueue data 203 in the aforementioned simultaneous permission determination, or by a combination of these.

[0064] The segmentation circuit 31 performs a segmentation operation. For example, when a power supply voltage enable permission signal is input from the main arbitration circuit 18, the segmentation circuit 31 refers to the summary request storage memory 32, extracts at least one module power control circuit 17 of the semiconductor chip 5b corresponding to the permission signal, and outputs the enable request signal and score corresponding to the extracted module power control circuit 17 to the sub-arbitration circuit 19 through the segmentation permission output circuit 311.

[0065] Next, the flow of control processing performed in the semiconductor device 1a configured as described above will be explained.

[0066] Figure 4 This is a flowchart illustrating an example of the operation flow of the main arbitration circuit 18 involved in the implementation. Furthermore, in the semiconductor device 1a, it is assumed that the power control circuits 17 of the multiple modules of semiconductor chips 5a and 5b output, at desired timings, activation requests and scores for at least one functional module 15.

[0067] The main arbitration circuit 18 performs the enqueue entry action (S101). Figure 5 It means Figure 4 A flowchart of an example of the process of enqueuing an entry. The main arbitration circuit 18, for example, receives, in one cycle, the activation requests and scores of at least one functional module 15 directly or via the summarizing circuit 33 and stores them in the corresponding area of ​​the enqueuing entry 201 (S201).

[0068] The main arbitration circuit 18 performs a request to store data (S102). Figure 6 It means Figure 4 Here is a flowchart illustrating an example of the request storage operation process. The main arbitration circuit 18 determines, for example, at any interval of one cycle or more, whether there is at least one valid open request in the enqueue entry 201 (S301). When there is at least one valid open request in the enqueue entry 201 (S301: Yes), the main arbitration circuit 18 stores the data stored in the enqueue entry 201 as enqueue data 203 into the request storage memory 193 (S302). When there is no valid open request in the enqueue entry 201 (S301: No), or after processing in S302, the request storage operation ends.

[0069] The main arbitration circuit 18 performs a simultaneous permission determination action (S103). Figure 7 It means Figure 4 Here is a flowchart of an example of the process for simultaneously granting permission to determine an action.

[0070] The main arbitration circuit 18 determines whether the request storage memory 193 (e.g., a FIFO memory) is in an empty state where no enqueued data 203 is stored (S401). When the request storage memory 193 is empty (S401: Yes), the permission determination action ends and the process returns to S401. On the other hand, when the request storage memory 193 is not empty, that is, when enqueued data 203 is stored (S401: No), after initializing the total score and the simultaneous permission flag 205 (S402), the main arbitration circuit 18 scans the request storage memory 193 in any order, starting from the highest priority enable request, and repeatedly grants power supply within the range where the total score does not exceed the threshold, until the total score of the received enable requests becomes below the threshold (S403 to S408).

[0071] Specifically, the main arbitration circuit 18 refers to the request storage memory 193. When the valid request flag [i] in the scanned region "i" of the enqueued data 203 is "1" (S403: Yes), it determines whether the total score obtained by adding the score [i] of the scanned region "i" to the current total score is below the threshold (S404).

[0072] When the total score exceeds the threshold (S404: No), the main arbitration circuit 18 asserts (sets to valid) all permissions [* (* can be any)] in the simultaneous permission flag 205 at that time point that are "1", and sends them to the corresponding module power control circuit 17 or the split circuit 31 (S405). After assertion, the main arbitration circuit 18 initializes the total score and the simultaneous permission flag 205 (S406).

[0073] When the total score is below the threshold (S404: Yes), or after assertion and initialization, the main arbitration circuit 18 adds the current score [i] to update the total score and sets the simultaneous permission flag 205 of the scanned region "i", i.e., the simultaneous permission flag [i], to "1" (S407).

[0074] When the open request flag valid request [i] is not "1" (S403: No), or after processing in S407, the main arbitration circuit 18 updates the "i" representing the scanned region (S408) and processes the next scanned region "i+1" (or scanned region "i-1").

[0075] Then, the main arbitration circuit 18 determines whether there is no area in the simultaneous permission flag 205 at that time point where the simultaneous permission flag [*] is "1" (S409).

[0076] When there is a region where the simultaneous permission flag [*] is "1" (S409: No), the main arbitration circuit 18 asserts the permission [*] where the simultaneous permission flag [*] is "1" and sends it to the corresponding module power control circuit 17 or the split circuit 31 (S410).

[0077] When there is no region where the simultaneous permission flag [*] is "1" (S409: Yes), or after the processing in S410, the main arbitration circuit 18 outputs (discharges) the enqueue data 203 of the object being processed from the request storage memory 193 (S411). After that, the simultaneous permission determination action ends, and the process returns to S401.

[0078] Figure 8 It means Figure 3 A flowchart of an example of the operation of the summary entry of the summary circuit 33. For example, the summary circuit 33 sequentially stores and holds the turn-on requests and scores of at least one functional module 15 received from the power control circuit 17 of at least one module of semiconductor chip 5b in the corresponding area of ​​the summary entry 202 (S501).

[0079] Figure 9 It means Figure 3 Here is a flowchart of an example of the process of summarizing request storage operation of the summarizing circuit 33. For example, the summarizing circuit 33 determines, in any cycle more than one cycle, whether there is at least one valid open request in the summarizing entry 202 (S601). When there is at least one valid open request in the summarizing entry 202 (S601: Yes), the summarizing circuit 33 stores the data stored in the summarizing entry 202 as enqueue data 204 into the summarizing request storage memory 32 (S602). When there is no at least one valid open request in the summarizing entry 202 (S601: No), or after the processing in S602, the summarizing circuit 33 calculates the total score (summarizing score) of the valid open requests in the summarizing entry 202, and sends the summarizing score of the valid open requests, i.e., the summarized valid open requests and the summarizing score, as a summarized request (summarizing request) to the main arbitration circuit 18 (S603). Afterwards, this summarizing request storage operation ends.

[0080] Figure 10 It means Figure 3 A flowchart illustrating an example of the segmentation operation of the segmentation circuit 31. The segmentation circuit 31 determines whether to accept the segmentation operation. Figure 7The processing of S405 or S410 asserts the summary permission (summary permission) sent from the main arbitration circuit 18, which includes the permission signal and score (S701). When the summary permission is not accepted (S701: No), the splitting operation ends and returns to the processing of S701. On the other hand, when the summary permission is accepted (S701: Yes), the splitting circuit 31 asserts the valid requests in the summary entry 202 simultaneously and sends them to the sub-arbitration circuit 19 (S702). After assertion, the splitting circuit 31 outputs (removes) the enqueue data 204 of the current processing object from the summary request storage memory 32 (S703). After that, the splitting operation ends and returns to the processing of S701.

[0081] The operation of the sub-arbitration circuit 19 is the same as that of the main arbitration circuit 18 described above, so the description is omitted here.

[0082] As described above, the semiconductor device 1a according to this embodiment includes: a sub-arbitration circuit 19, which arbitrates turn-on request signals from at least one module power control circuit 17 within its own semiconductor chip 5b; and a main arbitration circuit 18, which arbitrates turn-on request signals from multiple module power control circuits 17 covering multiple semiconductor chips 5, including its own semiconductor chip 5a and other semiconductor chips 5b. Specifically, in the semiconductor device 1 according to this embodiment, the main arbitration circuit 18 outputs a permission signal to one or more module power control circuits 17 that have output turn-on request signals, based on turn-on request signals from one or more module power control circuits 17 included in semiconductor chips 5a and 5b, requesting to start supplying power voltage for one or more functional modules 15 of their respective controlled objects, and based on the fraction of parasitic capacitance. Furthermore, the sub-arbitration circuit 19 outputs an authorization signal to one or more module power control circuits 17 that have output an enable request signal, based on the authorization signals and scores from the main arbitration circuit 18 that are output from one or more module power control circuits 17 included in the semiconductor chip 5b, regarding one or more functional modules 15 of their respective controlled objects.

[0083] According to this structure, when a power supply voltage turn-on request is simultaneously made to supply power voltage to multiple functional modules 15 within multiple semiconductor chips 5a and 5b, the power supply voltage timing can be controlled across multiple semiconductor chips 5 based on their fractionation. This suppresses the drop in power supply voltage and the resulting malfunctions.

[0084] Furthermore, in the semiconductor device 1a according to this embodiment, a portion of the semiconductor chips 5b among the plurality of semiconductor chips 5 are provided with a summarizing circuit 33, which sums up power supply voltage turn-on requests from at least one functional module 15 within the semiconductor chip 5b. According to this structure, the number of signal lines between the plurality of semiconductor chips 5a and 5b can be reduced. Furthermore, even when the number of semiconductor chips 5 increases, the increase in processing load on the main arbitration circuit 18 can be suppressed.

[0085] Furthermore, in the semiconductor device 1a according to this embodiment, each of the plurality of semiconductor chips 5 is provided with either a main arbitration circuit 18 or a sub-arbitration circuit 19. The main arbitration circuit 18 performs simultaneous authorization determination related to multiple functional modules 15 across the plurality of semiconductor chips 5, while the sub-arbitration circuit 19 performs simultaneous authorization determination related to at least one functional module 15 within the semiconductor chip 5b. According to this structure, even when the number of semiconductor chips 5 increases, the increase in processing load on the main arbitration circuit 18, which controls the plurality of semiconductor chips 5 as a whole, can be suppressed.

[0086] (Second Implementation)

[0087] The semiconductor device 1 according to the second embodiment of this disclosure will be described. Here, the differences from the semiconductor device 1a according to the first embodiment will be mainly described, and repeated descriptions will be omitted as appropriate. Figure 11 This is a diagram illustrating an example of the structure of the semiconductor device 1b according to the second embodiment. The semiconductor device 1b according to the second embodiment has multiple power domains 4. Figure 11 Power domains 4a and 4b are illustrated as multiple power domains 4.

[0088] Power domains 4a and 4b are power domains with different power supply voltages. Here, power domain 4a is an example of a first power supply voltage region that operates with a first power supply voltage. Furthermore, power domain 4b is an example of a second power supply voltage region that operates with a second power supply voltage different from the first power supply voltage.

[0089] Figure 11 The semiconductor device 1b has semiconductor chips 5a and 5b as multiple semiconductor chips 5. Semiconductor chips 5a and 5b belong to the power domains 4a and 4b of two systems and are electrically connected to the power management IC 3 respectively.

[0090] Semiconductor chip 5a has circuit groups 6a and 6d. Circuit groups 6a and 6d are connected to power domains 4a and 4b, respectively. Furthermore, semiconductor chip 5b has circuit groups 6b and 6e. Circuit groups 6b and 6e are connected to power domains 4a and 4b, respectively.

[0091] Circuit groups 6a, 6b, 6d, and 6e each have at least one switch 13, at least one functional module 15, and at least one module power control circuit 17.

[0092] In circuit groups 6a and 6b, at least one module power control circuit 17 is located in normally open regions 9a and 9b that receive power supply voltage from power domain 4a at all times. Furthermore, in circuit groups 6d and 6e, at least one module power control circuit 17 is located in normally open regions 9d and 9e that receive power supply voltage from power domain 4b at all times.

[0093] In addition, semiconductor chip 5a has a main arbitration circuit 18 for each power domain 4. Figure 11 The semiconductor device 1b has main arbitration circuits 18a and 18d as the main arbitration circuits 18 for each power domain 4. The main arbitration circuits 18a and 18d are respectively located in normally open regions 9a and 9d.

[0094] In addition, semiconductor chip 5b has a sub-arbitration circuit 19, a splitting circuit 31 and a summarizing circuit 33 for each power domain 4. Figure 11 The semiconductor device 1b has sub-arbitration circuits 19b and 19e, splitting circuits 31b and 31e, and summing circuits 33b and 33e as sub-arbitration circuits 19, splitting circuits 31, and summing circuits 33 for each power domain 4. The sub-arbitration circuits 19b and 19e, splitting circuits 31b and 31e, and summing circuits 33b and 33e are respectively located in normally open regions 9b and 9e.

[0095] The main arbitration circuit 18a outputs an enable signal to each module power control circuit 17 of circuit group 6a based on a threshold stored in an internal register, the enable request signal and score of the power supply voltage received from each module power control circuit 17 of circuit group 6a, and the summarized enable request signal and summarized score received from the summarizing circuit 33b of semiconductor chip 5b, and outputs a summarized enable signal and summarized score to the sub-arbitration circuit 19b of semiconductor chip 5b. Additionally, the main arbitration circuit 18d outputs an enable signal to each module power control circuit 17 of circuit group 6d based on a threshold stored in an internal register, the enable request signal and score of the power supply voltage received from each module power control circuit 17 of circuit group 6d, and the summarized enable request signal and summarized score received from the summarizing circuit 33e of semiconductor chip 5b, and outputs a summarized enable signal and summarized score to the sub-arbitration circuit 19e of semiconductor chip 5b.

[0096] As described above, the semiconductor device 1 according to this embodiment has a main arbitration circuit 18, a sub-arbitration circuit 19, a segmentation circuit 31, and a summarization circuit 33 for each power domain 4. With this structure, it is possible to handle situations where power domains 4a and 4b have different power supply voltages, or situations where it is desirable to suppress power supply voltage fluctuations.

[0097] (Third implementation method)

[0098] The semiconductor device 1 according to the third embodiment of this disclosure will be described. Here, the differences from the semiconductor device 1a according to the first embodiment will be mainly described, and repeated descriptions will be omitted as appropriate. Figure 12 This is a diagram illustrating an example of the structure of the semiconductor device 1c according to the third embodiment. The semiconductor device 1c according to the third embodiment also includes at least one clock control circuit 21. Each of the at least one clock control circuit 21 has a frequency control circuit configured to change the frequency.

[0099] The circuit groups 7a and 7b of the semiconductor device 1c each have a structure in which at least one clock control circuit 21 is further provided in the circuit groups 6a and 6b according to the first embodiment. Specifically, at least one clock control circuit 21 is electrically connected between the functional module 15 and the module power control circuit 17, and outputs a clock signal CK to the connected functional module 15.

[0100] In the semiconductor device 1c, at least one module power control circuit, in addition to the connected functional module 15, also controls the connected clock control circuit 21. After the power supply voltage is supplied, each module power control circuit outputs a clock control signal to control the connected clock control circuit 21 based on the operating state of the connected functional module 15. Specifically, each module power control circuit controls the on / off state of the clock signal CK input to the controlled functional module 15 and the frequency of the input clock signal CK by controlling the connected clock control circuit 21.

[0101] According to this structure, after the power supply voltage is supplied, the clock signal CK can be turned on / off and its frequency can be controlled based on the operating state of the connected functional module 15, thereby reducing the power consumption of the functional module 15 of the controlled object.

[0102] (A variation of the third embodiment)

[0103] Furthermore, the structure involved in this embodiment can be appropriately combined with at least one of the semiconductor devices 1 involved in the above embodiments and variations.

[0104] For example, in the structure of a semiconductor device 1b that provides a main arbitration circuit 18 for each power domain 4, a clock control circuit 21 may also be provided between the functional module 15 and the module power control circuit 17.

[0105] (Fourth Implementation)

[0106] The semiconductor device 1 according to the fourth embodiment of this disclosure will be described. Here, the differences from the semiconductor device 1a according to the first embodiment will be mainly described, and repeated descriptions will be omitted as appropriate. Figure 13 This is a diagram illustrating an example of the structure of the semiconductor device 1d according to the fourth embodiment. In the semiconductor device 1d according to the fourth embodiment, the semiconductor chips 5a and 5b are similar to the semiconductor chip 5b of the semiconductor device 1a according to the first embodiment, and in addition to the circuit groups 6a and 6b, they also have sub-arbitration circuits 19a and 19b, splitting circuits 31a and 31b, and summarizing circuits 33a and 33b.

[0107] exist Figure 13 In the semiconductor device 1b, the main arbitration circuit 18 is electrically connected to the summing circuit 33a of semiconductor chip 5a and the summing circuit 33b of semiconductor chip 5b, respectively. Based on the threshold values ​​of semiconductor chips 5a and 5b stored in the internal register, the summing enable request signal and summing score received from the summing circuit 33a of semiconductor chip 5a, and the summing enable request signal and summing score received from the summing circuit 33b of semiconductor chip 5b, the main arbitration circuit 18 outputs an enable permission signal for the power supply voltage.

[0108] In the main arbitration circuit 18 of the semiconductor device 1a according to the first embodiment, the power-on request signals from the power control circuits 17 of each module in the semiconductor chip 5a and the aggregated power-on request signal from the aggregation circuit 33 of the semiconductor chip 5b are processed at the same level. On the other hand, in the semiconductor device 1b according to this embodiment, since the semiconductor chip 5a also outputs an aggregated power-on request signal to the main arbitration circuit 18, the aggregated power-on request signals from the two semiconductor chips 5a and 5b can be processed at the same level in the main arbitration circuit 18.

[0109] (A variation of the fourth embodiment)

[0110] Furthermore, the structure involved in this embodiment can be appropriately combined with at least one of the semiconductor devices 1 involved in the above embodiments and variations.

[0111] For example, in the structure of semiconductor device 1b, which provides a main arbitration circuit 18 on semiconductor chip 5a, a sub-arbitration circuit 19, a splitting circuit 31, and a summarizing circuit 33 for each power domain 4, it is also possible to further provide a sub-arbitration circuit 19, a splitting circuit 31, and a summarizing circuit 33 on semiconductor chip 5a for each power domain 4.

[0112] For example, in the structure of a semiconductor device 1c in which a clock control circuit 21 is provided between the functional module 15 and the module power control circuit 17, a sub-arbitration circuit 19, a splitting circuit 31 and a summarizing circuit 33 may also be provided on the semiconductor chip 5a.

[0113] For example, for each power domain 4, a main arbitration circuit 18, a sub-arbitration circuit 19, a splitting circuit 31, and a summarizing circuit 33 can be set in semiconductor chip 5a, and a sub-arbitration circuit 19, a splitting circuit 31, and a summarizing circuit 33 can be set in semiconductor chip 5b, and a clock control circuit 21 can be set between functional module 15 and module power control circuit 17.

[0114] (Fifth Implementation)

[0115] The semiconductor device 1 according to the fifth embodiment of this disclosure will be described. Here, the differences from the semiconductor device 1b according to the second embodiment will be mainly described, and repeated descriptions will be omitted as appropriate. Figure 14 This is a diagram illustrating an example of the structure of the semiconductor device 1e according to the fifth embodiment. The semiconductor device 1e according to the fifth embodiment also includes semiconductor chips 5c as a plurality of semiconductor chips 5. The semiconductor chips 5c have, for example, the same structure as the semiconductor chips 5b. Of course, in the circuit groups 6c, 6f of the semiconductor chips 5c, the number of functional modules 15 and module power control circuits 17 may be the same as or different from those of the other semiconductor chips 5.

[0116] Furthermore, the semiconductor device 1e according to the fifth embodiment has a time-division multiplexing circuit 25 for each power domain 4. Figure 14 In the example, time-division multiplexing circuits 25a and 25b are set up for power domains 4a and 4b, respectively.

[0117] The time-division multiplexing circuit 25a is located in the normally open region 9b of the semiconductor chip 5b, and is electrically connected to the main arbitration circuit 18a of the semiconductor chip 5a, as well as the segmentation circuits 31b, 31c and the summing circuits 33b, 33c of the semiconductor chips 5b and 5c. Additionally, the time-division multiplexing circuit 25b is located in the normally open region 9e of the semiconductor chip 5b, and is electrically connected to the main arbitration circuit 18d of the semiconductor chip 5a, as well as the segmentation circuits 31e, 31f and the summing circuits 33e, 33f of the semiconductor chips 5b and 5c.

[0118] Time-division multiplexing circuits 25a and 25b perform time-division multiplexing on the summation enable request signal and summation score signal output from each summation circuit 33 for each power domain 4.

[0119] As described above, the semiconductor device 1 according to this embodiment performs time-division multiplexing of communication between multiple semiconductor chips 5. According to this structure, when the number of semiconductor chips 5 to be controlled increases to three or more, although the number of connection wires between semiconductor chips 5 increases with each increase in the number of chips, it is possible to multiplex request signals and fractional signals from each semiconductor chip 5, thereby suppressing the increase in the number of signal wires to the semiconductor chip 5a having the main arbitration circuit 18.

[0120] (A variation of the fifth embodiment)

[0121] Furthermore, the structure involved in this embodiment can be appropriately combined with at least one of the semiconductor devices 1 involved in the above embodiments and variations.

[0122] For example, for multiple semiconductor chips 5a to 5c that are only connected to one power domain 4, the main arbitration circuit 18 of semiconductor chip 5a and the segmentation circuits 31b, 31c and the summing circuits 33b, 33c of semiconductor chips 5b and 5c can be connected via time-division multiplexing circuit 25 respectively.

[0123] For example, regarding multiple semiconductor chips 5a to 5c, in a structure in which semiconductor chip 5a is provided with a main arbitration circuit 18, a sub-arbitration circuit 19, a segmentation circuit 31, and a summarization circuit 33, the segmentation circuits 31a to 31c and the summarization circuits 33a to 33c of the multiple semiconductor chips 5a to 5c can be connected via a time-division multiplexing circuit 25 respectively.

[0124] For example, in the structure of a semiconductor device 1c in which a clock control circuit 21 is provided between the functional module 15 and the module power control circuit 17, the semiconductor chips can also be connected via a time-division multiplexing circuit 25.

[0125] (Sixth Implementation Method)

[0126] The semiconductor device 1 according to the sixth embodiment of this disclosure will be described. Here, the differences from the semiconductor device 1e according to the fifth embodiment will be mainly described, and repeated descriptions will be omitted as appropriate. Figure 15 This is a diagram illustrating an example of the structure of the semiconductor device 1f according to the sixth embodiment. Unlike the semiconductor device 1e according to the fifth embodiment, the semiconductor device 1f according to the sixth embodiment does not have a time-division multiplexing circuit 25, but instead has a communication master circuit 27 and at least one communication slave circuit 29.

[0127] exist Figure 15 In the example, as at least one communication slave circuit 29, communication slave circuit 29a disposed on semiconductor chip 5b and communication slave circuit 29b disposed on semiconductor chip 5c are illustrated. Communication master circuit 27, communication slave circuit 29a, and communication slave circuit 29b are connected in series using signal lines for serial communication. Here, communication master circuit 27 is an example of a second communication circuit. Furthermore, communication slave circuit 29a is an example of a first communication circuit.

[0128] Furthermore, the main communication circuit 27 is located in the normally open region 9a of the semiconductor chip 5a, and is electrically connected to the main arbitration circuit 18a in the normally open region 9a of the semiconductor chip 5a and the main arbitration circuit 18d in the normally open region 9d of the semiconductor chip 5a via serial communication signal lines. Furthermore, the slave communication circuit 29a is located in the normally open region 9b of the semiconductor chip 5b, and is electrically connected to the segmentation circuit 31b and the summarization circuit 33b in the normally open region 9b of the semiconductor chip 5b, and the segmentation circuit 31e and the summarization circuit 33e in the normally open region 9e of the semiconductor chip 5b via serial communication signal lines. Furthermore, the slave communication circuit 29b is located in the normally open region 9c of the semiconductor chip 5c, and is electrically connected to the segmentation circuit 31c and the summarization circuit 33c in the normally open region 9c of the semiconductor chip 5c, and the segmentation circuit 31f and the summarization circuit 33f in the normally open region 9f of the semiconductor chip 5f via serial communication signal lines.

[0129] Therefore, in Figure 15 In the example, the main communication circuit 27, multiple slave communication circuits 29a, 29b, segmentation circuits 31b, 31c, 31e, 31f, and summarization circuits 33b, 33c, 33e, 33f are connected in series using signal lines for serial communication.

[0130] Furthermore, in the semiconductor device 1f according to the sixth embodiment, each power domain 4 of each semiconductor chip 5 is assigned an ID for unique identification.

[0131] For example, in the internal memory of at least one module power control circuit 17, an ID for the semiconductor chip 5 and power domain 4 used to uniquely identify its own circuit is predetermined and stored. Then, at least one module power control circuit 17 outputs the ID assigned to its own circuit, along with an enable request signal and a score, to the next stage connected in series.

[0132] Alternatively, for example, the storage and output of the predetermined ID to the internal memory can be implemented by the aggregation circuit 33, which is the next stage of the module power control circuit 17 that outputs the enable request signal and the serial signal of the fraction, or by the communication master circuit 27, the communication slave circuit 29a, and the communication slave circuit 29b that receive the serial signal. In this case, the ID of the aggregation circuit 33, which uniquely identifies the serial signal outputting the enable request signal (or the aggregated enable request signal) and the fraction, can be used.

[0133] Alternatively, for example, the main arbitration circuit 18 temporarily holds the ID attached to the enable request signal (or the summative enable request signal) and the fraction, and outputs the held ID together with the grant signal (or the summative grant signal) to the next stage connected in series.

[0134] As described above, the semiconductor device 1 according to this embodiment connects the signal wiring for the activation request and division of each semiconductor chip 5 in series. Furthermore, in the semiconductor device 1 according to this embodiment, each semiconductor chip 5 sends the data along with its assigned ID to the next level when there is data to be transmitted (output), and forwards the data and ID from the previous level to the next level when there is no data to be transmitted (output). Specifically, the main communication circuit 27 and the multiple slave communication circuits 29a and 29b determine whether to receive or forward data based on the ID. Additionally, the ID can be a destination ID indicating the destination of transmission or a source ID indicating the source of transmission.

[0135] According to this structure, since the request signals and fractional serial signals between each semiconductor chip 5 can be transmitted and received via unidirectional serial communication signal lines, the increase in the number of signal wirings to the semiconductor chip 5a with the main arbitration circuit 18 can be suppressed, and the number of signal lines between the semiconductor chips 5 can be further reduced. Furthermore, when the number of semiconductor chips 5 to be controlled increases to three or more, although the number of connection wirings between semiconductor chips 5 increases with each increase in the number of chips, this increase can be suppressed.

[0136] (A variation of the sixth embodiment)

[0137] Furthermore, the structure involved in this embodiment can be appropriately combined with at least one of the semiconductor devices 1 involved in the above embodiments and variations.

[0138] (Seventh Implementation)

[0139] The semiconductor device 1 according to the seventh embodiment of this disclosure will be described. Here, the differences from the semiconductor device 1a according to the first embodiment will be mainly described, and repeated descriptions will be omitted as appropriate. Figure 16This is a diagram illustrating an example of the structure of the semiconductor device 1g according to the seventh embodiment.

[0140] exist Figure 16 In the semiconductor device 1g, a main arbitration circuit 18 may also be provided on the semiconductor chip 5a near the power management IC 3 on the substrate 2 (e.g., the closest position). The main arbitration circuit 18 provided on the semiconductor chip 5a receives the turn-on request signals and scores from the power control circuits 17 of each module of the semiconductor chip 5a, and the aggregate turn-on request signals and scores from the aggregation circuits 33 of each of the semiconductor chips 5b to 5d. Based on the scores of each power control circuit 17, it outputs an authorization signal and an aggregate authorization signal.

[0141] (A variation of the seventh embodiment)

[0142] Furthermore, the structure involved in this embodiment can be appropriately combined with at least one of the semiconductor devices 1 involved in the above embodiments and variations.

[0143] (Eighth Implementation)

[0144] The semiconductor device 1 according to the eighth embodiment of this disclosure will be described. Here, the differences from the semiconductor device 1g according to the seventh embodiment will be mainly described, and repeated descriptions will be omitted as appropriate. Figure 17 This is a diagram illustrating an example of the structure of the semiconductor device 1h according to the eighth embodiment.

[0145] exist Figure 17 In the semiconductor device 1g, multiple power management ICs 3a and 3b are disposed on the substrate 2. Thus, the semiconductor device 1g can also have different power management ICs 3 for each power domain 4. In this case, for example, a main arbitration circuit 18 can be disposed on semiconductor chips 5a and 5d near (e.g., the closest position) each of the power management ICs 3a and 3b. The main arbitration circuit 18a disposed on semiconductor chip 5a receives the enable request signals and scores from the power control circuits 17 of each module of semiconductor chip 5a, and the aggregate enable request signals and scores from the aggregation circuits 33 of each module of semiconductor chips 5b to 5d, and outputs an enable signal and an aggregate enable signal based on the scores of the power control circuits 17 of each module. Furthermore, the main arbitration circuit 18d disposed on semiconductor chip 5d receives the enable request signals and scores from the power control circuits 17 of each module of semiconductor chip 5d, and the aggregate enable request signals and scores from the aggregation circuits 33 of each module of semiconductor chip 5c, and outputs an enable signal and an aggregate enable signal based on the scores of the power control circuits 17 of each module.

[0146] (A variation of the eighth embodiment)

[0147] Furthermore, the structure involved in this embodiment can be appropriately combined with at least one of the semiconductor devices 1 involved in the above embodiments and variations.

[0148] (Ninth Implementation)

[0149] The semiconductor device 1 according to the ninth embodiment of this disclosure will be described. Here, the differences from the semiconductor device 1g according to the seventh embodiment will be mainly described, and repeated descriptions will be omitted as appropriate. Figure 18 This is a diagram illustrating an example of the structure of the semiconductor device 1i according to the ninth embodiment.

[0150] exist Figure 18 In the semiconductor device 1i, semiconductor chips 5a and 5c may be equipped with a main arbitration circuit 18 and a sub-arbitration circuit 19, and semiconductor chips 5b and 5d may be equipped with a sub-arbitration circuit 19. Power domain 4a supplies power voltage to a portion of semiconductor chip 5a and a portion of semiconductor chip 5b. Power domain 4b supplies power voltage to a portion of semiconductor chip 5a, a portion of semiconductor chip 5b, a portion of semiconductor chip 5c, and a portion of semiconductor chip 5d. Power domain 4c supplies power voltage to a portion of semiconductor chip 5c and a portion of semiconductor chip 5d. The main arbitration circuit 18a located in semiconductor chip 5a controls power domains 4a and 4b. Furthermore, the main arbitration circuit 18c located in semiconductor chip 5c controls power domain 4c.

[0151] (A variation of the ninth embodiment)

[0152] Furthermore, the structure involved in this embodiment can be appropriately combined with at least one of the semiconductor devices 1 involved in the above embodiments and variations.

[0153] Furthermore, regarding the above embodiments, some or all of each circuit can be constructed by hardware, or by information processing of software (programs) executed by a CPU or the like. Additionally, regarding the above embodiments, when multiple memories store data, each memory can store only a portion of the data, or it can store all of the data.

[0154] As described above, according to at least one embodiment of the present disclosure, the timing of the power supply voltage across multiple semiconductor chips can be appropriately controlled.

[0155] The embodiments of this disclosure have been described in detail above, but these embodiments are for illustrative purposes only and are not intended to limit the scope of these embodiments. Various additions, changes, substitutions, partial deletions, combinations, and other modifications can be made to each embodiment without departing from the technical spirit of the present invention. These embodiments and their modifications are included within the scope of the invention described in the technical solution and its equivalents.

[0156] Explanation of reference numerals in the attached figures

[0157] 1 Semiconductor device; 2 Substrate; 3 Power management IC; 4 Power domain; 5 Semiconductor chip; 6, 7 Circuit group; 9 Normally open area; 13 Switch; 15 Functional module; 17 Module power control circuit; 18 Main arbitration circuit; 19 Sub-arbitration circuit; 21 Clock control circuit; 25 Time division multiplexing circuit; 27 Communication master circuit; 29 Communication slave circuit; 31 Segmentation circuit; 32 Summary request storage memory; 33 Summary circuit; 191 Request acceptance circuit; 193 Request storage memory; 195 Simultaneous permission determination circuit; 197 Simultaneous permission sending circuit; 201 Enqueue entry; 202 Summary entry; 203 Enqueue data; 204 Enqueue data; 205 Simultaneous permission flag; 311 Segment permission sending circuit; 331 Request acceptance circuit; 333 Summary request sending circuit.

Claims

1. A semiconductor device comprising: substrate; The first semiconductor chip disposed on the aforementioned substrate; and The second semiconductor chip disposed on the aforementioned substrate, The first semiconductor chip and the second semiconductor chip each have: at least one functional module; and at least one module power control circuit, which is electrically connected to one or more of the at least one functional module to control the power supply voltage to each of the one or more functional modules. The first semiconductor chip also includes a summarizing circuit, which summarizes the start-up request signals for requesting the supply of power voltage from one or more of the multiple module power control circuits included in the first semiconductor chip, which are related to the control objects of the one or more functional modules, and the scores based on parasitic capacitance, and outputs a summarized start-up request signal and a summarized score. The second semiconductor chip also has a main arbitration circuit, which outputs a permission signal to allow the supply of power voltage to begin to the first semiconductor chip and the first or more module power control circuits that have output the above-mentioned start-up request signal and the above-mentioned score from the above-mentioned summary circuit, and the start-up request signal for requesting to start supplying power voltage for the above-mentioned functional modules of the above-mentioned one or more of the plurality of module power control circuits included in the second semiconductor chip, based on the score of parasitic capacitance.

2. The semiconductor device according to claim 1, wherein, The aforementioned first semiconductor chip also has: The segmentation circuit, receiving the license signal from the second semiconductor chip, outputs a license signal and the segmentation corresponding to the power control circuit of the licensed object included in the at least one power control circuit of the first semiconductor chip, based on the license signal; and The sub-arbitration circuit, based on the permission signal output from the above-mentioned segmentation circuit and the above-mentioned fraction, outputs a permission signal to allow the supply of power voltage to one or more module power control circuits that have output the above-mentioned start request signal contained in the first semiconductor chip.

3. A semiconductor device comprising: substrate; The first semiconductor chip disposed on the aforementioned substrate; and The second semiconductor chip disposed on the aforementioned substrate, The first semiconductor chip and the second semiconductor chip each have: at least one functional module; at least one module power control circuit, electrically connected to one or more of the functional modules respectively, controlling the supply of power voltage to each of the functional modules; and a summarizing circuit, which summarizes the start-up request signals for requesting the supply of power voltage to the functional modules respectively controlled by one or more of the module power control circuits, and the scores based on parasitic capacitance, and outputs a summarized start-up request signal and a summarized score. The second semiconductor chip also has a main arbitration circuit, which outputs a permission signal to allow the supply of power voltage to one or more module power control circuits that have output the above-mentioned start request signals and the above-mentioned summarization scores from the summarization start request signals from the first semiconductor chip and the second semiconductor chip, based on the summarization start request signals from the summarization score from the summarization circuits of each of the above-mentioned summarization circuits.

4. The semiconductor device according to claim 3, wherein, The first semiconductor chip and the second semiconductor chip mentioned above also respectively have: The segmentation circuit, receiving the permission signal from the main arbitration circuit, outputs a permission signal and a fraction corresponding to the power control circuit of the permissioned object in each of the at least one included module power control circuits; and The sub-arbitration circuit, based on the permission signal output from the above-mentioned segmentation circuit and the above-mentioned fraction, outputs a permission signal to allow the supply of power voltage to one or more module power control circuits that have output the above-mentioned start request signal contained in the first semiconductor chip.

5. The semiconductor device according to claim 1, wherein, The main arbitration circuit calculates the total value of the scores input within a set period, and outputs the permission signal based on the comparison result of the total value with a predetermined threshold.

6. The semiconductor device according to claim 5, wherein, The aforementioned main arbitration circuit calculates the aforementioned total value based on the priority set for the plurality of functional modules contained in the aforementioned first semiconductor chip and the aforementioned second semiconductor chip.

7. The semiconductor device according to claim 1, wherein, The first semiconductor chip and the second semiconductor chip respectively have a first power supply voltage region that operates with a first power supply voltage and a second power supply voltage region that operates with a second power supply voltage different from the first power supply voltage. The second semiconductor chip has the main arbitration circuit in the first power supply voltage region and the second power supply voltage region, respectively.

8. The semiconductor device according to claim 1, wherein, Each of the above-mentioned at least one module power control circuits has a clock control circuit, which controls the on / off state and frequency of the clock signal input to the above-mentioned functional modules based on the operating state of the above-mentioned functional modules that are the objects of control.

9. The semiconductor device according to claim 1, wherein, It also has a third semiconductor chip disposed on the aforementioned substrate. The aforementioned third semiconductor chip includes: at least one functional module; at least one module power control circuit electrically connected to one or more of the aforementioned functional modules to control the supply of power voltage to each of the aforementioned functional modules; and a summarizing circuit that summarizes the start-up request signals for requesting the supply of power voltage to the aforementioned functional modules, which are respectively controlled by one or more of the aforementioned module power control circuits included in the aforementioned third semiconductor chip, and the scores based on parasitic capacitance, and outputs a summarized start-up request signal and a summarized score. The first semiconductor chip also has a time-division multiplexing circuit, which is electrically connected between the aggregation circuit of the first semiconductor chip and the main arbitration circuit of the second semiconductor chip. The time-division multiplexing circuit performs time-division multiplexing on the aggregation start request signal and the aggregation score signal from the aggregation circuit of the first semiconductor chip and the second semiconductor chip and outputs them to the main arbitration circuit of the second semiconductor chip.

10. The semiconductor device according to claim 2, wherein, The first semiconductor chip also includes a first communication circuit, which is electrically connected to the aggregation circuit and forwards the aggregation enable request signal and the serial signal of the aggregation score from the aggregation circuit to the second semiconductor chip via a serial communication signal line. The second semiconductor chip also has a second communication circuit, which is electrically connected to the main arbitration circuit. The second communication circuit forwards the permission signal from the main arbitration circuit to the first semiconductor chip via the serial communication signal line, and receives the summary enable request signal and the serial signal of the summary score from the first semiconductor chip and outputs them to the main arbitration circuit.

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