Display panel, display device

Abstract

A display panel and a display device are disclosed. The display panel includes: a substrate, a plurality of light-emitting units, and a plurality of pixel driving circuits. The plurality of light-emitting units are located on one side of the substrate. The plurality of pixel driving circuits are located on one side of the substrate and are arrayed along a first direction and a second direction, the first direction and the second direction intersecting each other. The pixel driving circuits are used to drive the light-emitting units to emit light. The pixel driving circuits include a driving transistor, a ninth transistor, and a sixth transistor. The first electrode of the driving transistor is connected to a first power supply line, and the second electrode is connected to the first electrode of the ninth transistor. The first electrode of the sixth transistor is connected to the second electrode of the ninth transistor, and the second electrode is connected to the first electrode of the light-emitting unit. The ninth transistor is controlled by a constant voltage signal line, and a constant voltage signal on the constant voltage signal line can turn on the ninth transistor.

Description

Display panel, display device Technical Field

[0001] This disclosure relates to the field of display technology, and more particularly to a display panel and a display device. Background Technology

[0002] In related technologies, display panels include pixel driving circuits, which are used to drive light-emitting units to emit light. This application provides a new display panel with a new pixel driving circuit.

[0003] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this disclosure, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0004] According to one aspect of this disclosure, a display panel is provided, wherein the display panel includes:

[0005] Substrate;

[0006] Multiple light-emitting units are located on one side of the substrate.

[0007] Multiple pixel driving circuits are located on one side of the substrate. The multiple pixel driving circuits are arrayed along a first direction and a second direction, and the first direction and the second direction intersect. The pixel driving circuits are used to drive the light-emitting unit to emit light. The pixel driving circuits include a driving transistor, a ninth transistor, and a sixth transistor.

[0008] The first terminal of the driving transistor is connected to the first power supply line, and the second terminal is connected to the first terminal of the ninth transistor.

[0009] The first electrode of the sixth transistor is connected to the second electrode of the ninth transistor, and the second electrode is connected to the first electrode of the light-emitting unit.

[0010] The ninth transistor is controlled by a constant voltage signal line, and the constant voltage signal on the constant voltage signal line can turn on the ninth transistor.

[0011] In one exemplary embodiment of this disclosure, the ninth transistor is an N-type transistor, and the pixel driving circuit further includes an eighth transistor, wherein the first terminal of the eighth transistor is connected to the third initial signal line, and the second terminal is connected to the first terminal of the driving transistor;

[0012] The constant voltage signal line is one or more, and the one or more constant voltage signal lines include one or more of the first power line and the third initial signal line.

[0013] In one exemplary embodiment of this disclosure, the pixel driving circuit further includes a capacitor, the first electrode of the capacitor is connected to the gate of the driving transistor, the second electrode of the capacitor is connected to a first power supply line, and the constant voltage signal line includes the first power supply line;

[0014] The display panel also includes:

[0015] The second gate layer is located on one side of the substrate. The second gate layer includes a second conductive portion and a first connecting portion. The second conductive portion is used to form the second electrode of the capacitor. The first connecting portion is connected between two adjacent second conductive portions in the first direction.

[0016] The second active layer is located on the side of the second gate layer away from the substrate. The second active layer includes a ninth active portion, which is used to form the channel region of the ninth transistor.

[0017] Wherein, the orthographic projection of the first connection portion on the substrate covers the orthographic projection of the ninth active portion on the substrate, and at least a portion of the structure of the first connection portion is used to form the first gate of the ninth transistor.

[0018] In one exemplary embodiment of this disclosure, the pixel driving circuit further includes an eighth transistor, the first terminal of the eighth transistor is connected to a third initial signal line, the second terminal is connected to the first terminal of the driving transistor, and the constant voltage signal line includes the third initial signal line;

[0019] The display panel also includes:

[0020] The second active layer is located on the side of the second gate layer away from the substrate. The second active layer includes a ninth active portion, which is used to form the channel region of the ninth transistor.

[0021] The third gate layer is located on the side of the second active layer away from the substrate. The third gate layer includes the third initial signal line and the third conductive portion. The third conductive portion and the third initial signal line are connected in the same layer. The orthogonal projection of the third conductive portion on the substrate covers the orthogonal projection of the ninth active portion on the substrate. At least a portion of the structure of the third conductive portion is used to form the second gate of the ninth transistor.

[0022] In one exemplary embodiment of this disclosure, the pixel driving circuit further includes: a second transistor, wherein a first terminal of the second transistor is connected to the gate of the driving transistor, and a second terminal of the second transistor is connected to the second terminal of the driving transistor;

[0023] The display panel also includes:

[0024] A first gate line, the orthogonal projection of the first gate line on the substrate extends along the first direction, and a portion of the structure of the first gate line is used to form the second gate of the second transistor;

[0025] The third conductive portion is at least partially used to form the second gate of the ninth transistor;

[0026] An enable signal line, whose orthogonal projection on the substrate extends along the first direction, wherein a portion of the structure of the enable signal line is used to form the gate of the sixth transistor;

[0027] In the same pixel driving circuit, the orthogonal projection of the third conductive part on the substrate is located between the orthogonal projection of the first gate line on the substrate and the orthogonal projection of the enable signal line on the substrate.

[0028] In one exemplary embodiment of this disclosure, the pixel driving circuit further includes an eighth transistor, wherein the first terminal of the eighth transistor is connected to a third initial signal line, and the second terminal is connected to the first terminal of the driving transistor;

[0029] The third gate layer further includes a fourth conductive portion, the orthographic projection of the third conductive portion on the substrate extends along the first direction, the orthographic projection of the fourth conductive portion on the substrate extends along the second direction, and the fourth conductive portion is connected between the third conductive portion and the third initial signal line.

[0030] In one exemplary embodiment of this disclosure, the pixel driving circuit further includes an eighth transistor, wherein the first terminal of the eighth transistor is connected to a third initial signal line, and the second terminal is connected to the first terminal of the driving transistor;

[0031] The display panel also includes:

[0032] The second reset signal line extends along the first direction in the orthogonal projection on the substrate, and a portion of the structure of the second reset signal line is used to form the gate of the eighth transistor.

[0033] In the same pixel driving circuit: the orthographic projection of the second reset signal line on the substrate is located on the side of the orthographic projection of the enable signal line on the substrate away from the orthographic projection of the third conductive part on the substrate, and the orthographic projection of the second reset signal line on the substrate and the orthographic projection of the third initial signal line on the substrate at least partially overlap.

[0034] In one exemplary embodiment of this disclosure, the pixel driving circuit further includes a fifth transistor, wherein the first terminal of the fifth transistor is connected to the first power line, and the second terminal is connected to the first terminal of the driving transistor;

[0035] The display panel also includes:

[0036] A first active layer is located on one side of the substrate. The first active layer includes a fifth active portion and a sixth active portion. The fifth active portion is used to form the channel region of the fifth transistor, and the sixth active portion is used to form the channel region of the sixth transistor.

[0037] The second active layer is located on the side of the first active layer away from the substrate. The second active layer includes a ninth active portion, which is used to form the channel region of the ninth transistor.

[0038] In the first direction of the same pixel driving circuit, the orthographic projection of the sixth active part on the substrate is located between the orthographic projection of the ninth active part on the substrate and the orthographic projection of the fifth active part on the substrate.

[0039] In one exemplary embodiment of this disclosure, the pixel driving circuit further includes a second transistor and a seventh transistor;

[0040] The first terminal of the second transistor is connected to the gate of the driving transistor, and the second terminal is connected to the second terminal of the driving transistor;

[0041] The first terminal of the seventh transistor is connected to the second initial signal line, and the second terminal is connected to the second terminal of the sixth transistor.

[0042] The first active layer further includes a third active portion, a seventh active portion, a sixteenth active portion, a nineteenth active portion, and a twentieth active portion. The third active portion is used to form the channel region of the driving transistor, the seventh active portion is used to form the channel region of the seventh transistor, the sixteenth active portion is connected between the sixth active portion and the seventh active portion, the nineteenth active portion is connected to the end of the sixth active portion away from the seventh active portion, and the twentieth active portion is connected to the end of the third active portion away from the fifth active portion.

[0043] The second active layer further includes: a second active portion, a twenty-second active portion, and a twenty-third active portion. The second active portion is used to form the channel region of the second transistor. The twenty-second active portion is connected to the end of the ninth active portion away from the second active portion. The twenty-third active portion is connected between the second active portion and the ninth active portion.

[0044] The display panel also includes:

[0045] The fourteenth bridging section connects to the twentieth active section and the twenty-second active section respectively through vias;

[0046] The second bridging section connects the 23rd active section and the 16th active section respectively through vias.

[0047] In an exemplary embodiment of this disclosure, a plurality of pixel driving circuits form a plurality of pixel driving circuit groups, and the plurality of pixel driving circuit groups are arrayed along a first direction and a second direction. The pixel driving circuit group includes two adjacent pixel driving circuits in the first direction.

[0048] In the same pixel driving circuit group, the channel regions of the ninth transistors in two adjacent pixel driving circuits are mirror-symmetrically arranged on the substrate with respect to the axis of symmetry extending along the second direction.

[0049] The second active layer includes an active portion, a portion of which is used to form the channel region of the ninth transistor;

[0050] The display panel also includes:

[0051] A fourth conductive portion is connected between the third conductive portion and the third initial signal line. The orthographic projection of the fourth conductive portion on the substrate extends along the second direction, and the orthographic projection of the fourth conductive portion on the substrate is at least partially located between the orthographic projections of two adjacent active portions on the substrate in the same pixel driving circuit group.

[0052] In an exemplary embodiment of this disclosure, a plurality of pixel driving circuits form a plurality of pixel driving circuit groups, and the plurality of pixel driving circuit groups are arrayed along a first direction and a second direction. The pixel driving circuit group includes two adjacent pixel driving circuits in the first direction.

[0053] The orthographic projections of two adjacent pixel driving circuits in the same pixel driving circuit group onto the substrate are at least partially mirror-symmetrical with respect to an axis of symmetry extending along a second direction.

[0054] In one exemplary embodiment of this disclosure, the pixel driving circuit further includes a seventh transistor, the first electrode of the seventh transistor is connected to a second initial signal line, the second electrode is connected to a first electrode of the light-emitting unit, and the orthographic projection of the second initial signal line on the substrate extends along the first direction;

[0055] The display panel also includes:

[0056] The fourth bridging section is connected to the first electrode of the seventh transistor and the second initial signal line through vias;

[0057] The eleventh bridging section is connected to the two fourth bridging sections in the same pixel driving circuit group at the same layer.

[0058] The second initial connection line is located on a different conductive layer from the second initial signal line. The orthographic projection of the second initial connection line on the substrate extends along the second direction. The second initial connection line is connected to the eleventh bridging portion through a via.

[0059] In one exemplary embodiment of this disclosure, the pixel driving circuit further includes a first transistor, a first electrode of the first transistor is connected to a first initial signal line, a second electrode is connected to the second electrode of the driving transistor, and the orthographic projection of the first initial signal line on the substrate extends along the first direction;

[0060] The display panel also includes:

[0061] The third bridging section is connected to the first electrode of the first transistor and the first initial signal line through vias;

[0062] The twelfth bridging section is connected to the two third bridging sections in the same pixel driving circuit group at the same layer.

[0063] The first initial connection line is located on a different conductive layer from the first initial signal line. The orthographic projection of the first initial connection line on the substrate extends along the second direction. The first initial connection line is connected to the twelfth bridging portion through a via.

[0064] In one exemplary embodiment of this disclosure, the pixel driving circuit further includes a capacitor, the first electrode of the capacitor is connected to the gate of the driving transistor, the second electrode of the capacitor is connected to a first power supply line, and the constant voltage signal line includes the first power supply line;

[0065] The display panel also includes:

[0066] The second gate layer is located on one side of the substrate. The second gate layer includes a second conductive portion and a first connecting portion. The second conductive portion is used to form the second electrode of the capacitor. The first connecting portion is connected between two adjacent second conductive portions in the first direction.

[0067] The orthographic projection of the first connecting portion on the substrate and the orthographic projection of the ninth active portion on the substrate do not overlap.

[0068] In one exemplary embodiment of this disclosure, the first connecting portion includes:

[0069] The first sub-connecting portion extends along the second direction in its orthogonal projection onto the substrate.

[0070] The second sub-connecting portion extends along the second direction in its orthogonal projection onto the substrate.

[0071] A third sub-connecting portion is connected between the first sub-connecting portion and the second sub-connecting portion, and the orthographic projection of the third sub-connecting portion on the substrate extends along the first direction;

[0072] The orthographic projections of the third sub-connection portion and the third conductive portion on the substrate are arranged opposite to each other in the second direction, and the orthographic projections of the first sub-connection portion and the second sub-connection portion on the substrate are located between the orthographic projections of the third sub-connection portion and the third conductive portion on the substrate.

[0073] In one exemplary embodiment of this disclosure, the display panel further includes:

[0074] An enable signal line, the orthographic projection of which extends along a first direction on the substrate, and a portion of the structure of which is used to form the gate of the sixth transistor;

[0075] The enable signal line has a notch on the side facing the third sub-connection portion, and the orthographic projection of the notch on the substrate and the orthographic projection of the third sub-connection portion on the substrate are arranged opposite each other in the second direction.

[0076] In one exemplary embodiment of this disclosure, the pixel driving circuit further includes:

[0077] A first transistor, wherein the first terminal of the first transistor is connected to a first initial signal line, and the second terminal is connected to the second terminal of the driving transistor;

[0078] The second transistor has a first terminal connected to the gate of the driving transistor and a second terminal connected to the second terminal of the driving transistor.

[0079] The fourth transistor has its first terminal connected to the data line and its second terminal connected to the first terminal of the driving transistor.

[0080] The fifth transistor has its first terminal connected to the first power supply line and its second terminal connected to the first terminal of the driving transistor.

[0081] The seventh transistor has its first terminal connected to the second initial signal line and its second terminal connected to the light-emitting unit.

[0082] The eighth transistor has its first terminal connected to the third initial signal line and its second terminal connected to the first terminal of the driving transistor.

[0083] The capacitor has a first electrode connected to the gate of the driving transistor and a second electrode connected to the first power supply line.

[0084] Among them, the first transistor, the driving transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, and the eighth transistor are P-type transistors, and the second transistor and the ninth transistor are N-type transistors.

[0085] In one exemplary embodiment of this disclosure, the pixel driving circuit includes P-type transistors and N-type transistors, and the display panel further includes:

[0086] A first active layer is located on one side of the substrate, and a portion of the structure of the first active layer is used to form the channel region of the P-type transistor in the pixel driving circuit.

[0087] A first gate layer is located on the side of the first active layer away from the substrate, and a portion of the structure of the first gate layer is used to form the gate of the P-type transistor in the pixel driving circuit.

[0088] The second gate layer is located on the side of the first gate layer away from the substrate, and a portion of the structure of the second gate layer is used to form the first gate of at least a portion of the N-type transistors in the pixel driving circuit.

[0089] The second active layer is located on the side of the second gate layer away from the substrate, and a portion of the structure of the second active layer is used to form the channel region of the N-type transistor in the pixel driving circuit.

[0090] A third gate layer is located on the side of the second active layer away from the substrate, and a portion of the structure of the third gate layer is used to form the second gate of at least a portion of the N-type transistors in the pixel driving circuit.

[0091] The first source / drain layer is located on the side of the third gate layer opposite to the substrate, and a portion of the structure of the first source / drain layer is used to form a bridging portion connecting different transistors.

[0092] According to one aspect of this disclosure, a display device is provided, wherein the display device includes the display panel described above.

[0093] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0094] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0095] Figure 1 is a schematic diagram of an exemplary embodiment of the pixel driving circuit of this disclosure;

[0096] Figure 2 is a timing diagram of each node in a driving method of the pixel driving circuit shown in Figure 1;

[0097] Figure 3 is a structural layout of an exemplary embodiment of the display panel of this disclosure;

[0098] Figure 4 is a structural layout of the shielding layer in Figure 3;

[0099] Figure 5 shows the structural layout of the first active layer in Figure 3;

[0100] Figure 6 is a structural layout of the first gate layer in Figure 3;

[0101] Figure 7 is a structural layout of the second gate layer in Figure 3;

[0102] Figure 8 shows the structural layout of the second active layer in Figure 3;

[0103] Figure 9 shows the structural layout of the third gate layer in Figure 3;

[0104] Figure 10 shows the structural layout of the first source / drain layer in Figure 3;

[0105] Figure 11 is a structural layout of the second source / drain layer in Figure 3;

[0106] Figure 12 shows the structural layout of the shielding layer and the first active layer in Figure 3;

[0107] Figure 13 is a structural layout of the shielding layer, the first active layer, and the first gate layer in Figure 3;

[0108] Figure 14 is a structural layout of the shielding layer, the first active layer, the first gate layer, and the second gate layer in Figure 3;

[0109] Figure 15 is a structural layout of the shielding layer, the first active layer, the first gate layer, the second gate layer, and the second active layer in Figure 3;

[0110] Figure 16 is a structural layout of the shielding layer, the first active layer, the first gate layer, the second gate layer, the second active layer, and the third gate layer in Figure 3.

[0111] Figure 17 is a structural layout of the shielding layer, the first active layer, the first gate layer, the second gate layer, the second active layer, the third gate layer, and the first source / drain layer in Figure 3.

[0112] Figure 18 is a partial cross-sectional view of the display panel shown in Figure 3, cut along the dashed line AA;

[0113] Figure 19 is a schematic diagram of another exemplary embodiment of the display panel of this disclosure;

[0114] Figure 20 is a schematic diagram of the structure of the third gate layer in the display panel shown in Figure 19;

[0115] Figure 21 is a schematic diagram of another exemplary embodiment of the display panel of this disclosure;

[0116] Figure 22 is a schematic diagram of the structure of the first gate layer in the display panel shown in Figure 21;

[0117] Figure 23 is a schematic diagram of the structure of the second gate layer in the display panel shown in Figure 21;

[0118] Figure 24 is a schematic diagram of the structure of the shielding layer, the first active layer, the first gate layer, the second gate layer, and the second active layer in the display panel shown in Figure 21.

[0119] Figure 25 is a structural layout of another exemplary embodiment of the display panel of this disclosure;

[0120] Figure 26 is a structural layout of the first source / drain layer, the second source / drain layer, and the electrode layer in the display panel shown in Figure 25.

[0121] Figure 27 is a structural layout of the first source / drain layer and the second source / drain layer in the display panel shown in Figure 25;

[0122] Figure 28 is a structural layout of the first source / drain layer in the display panel shown in Figure 25;

[0123] Figure 29 is a structural layout of the electrode layer in the display panel shown in Figure 25. Detailed Implementation

[0124] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, they are provided so that this disclosure will be more comprehensive and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and therefore their detailed description will be omitted.

[0125] The terms “a,” “one,” and “” are used to indicate the existence of one or more elements / components / etc.; the terms “include” and “have” are used to indicate an open-ended meaning of inclusion and to mean that there may be other elements / components / etc. in addition to the listed elements / components / etc.

[0126] Figure 1 shows a schematic diagram of an exemplary embodiment of the pixel driving circuit of this disclosure. The pixel driving circuit may include: a driving transistor T3, a first transistor T1, a second transistor T2, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, a ninth transistor T9, and a capacitor C. Specifically, the first terminal of the fourth transistor T4 is connected to the data signal terminal Da, the second terminal of the fourth transistor T4 is connected to the first terminal of the driving transistor T3, and the gate of the fourth transistor T4 is connected to the second gate driving signal terminal G2; the first terminal of the fifth transistor T5 is connected to the first power supply terminal VDD, the second terminal of the fifth transistor T5 is connected to the first terminal of the driving transistor T3, and the gate of the fifth transistor T5 is connected to the enable signal terminal EM; the first terminal of the ninth transistor T9 is connected to the second terminal of the driving transistor T3, and the gate of the ninth transistor T9 is connected to the first power supply terminal VDD or the third initial signal terminal Vinit3; the first terminal of the second transistor T2 is connected to the gate of the driving transistor T3, the second terminal of the second transistor T2 is connected to the second terminal of the ninth transistor T9, and the gate of the second transistor T2 is connected to the first gate driving signal terminal G1; the first terminal of the sixth transistor T6 is connected to the ninth transistor T3. The second electrode of transistor T9 is connected to the second electrode of transistor T6, which is also connected to the second electrode of transistor T7. The gate of transistor T6 is connected to the enable signal terminal EM. The first electrode of transistor T7 is connected to the second initial signal terminal Vinit2, and its gate is connected to the second reset signal terminal Re2. The first electrode of transistor T1 is connected to the first initial signal terminal Vinit1, and its second electrode is connected to the second electrode of transistor T9. Its gate is connected to the first reset signal terminal Re1. The first electrode of transistor T8 is connected to the third initial signal terminal Vinit3, and its second electrode is connected to the first electrode of driving transistor T3. Its gate is connected to the second reset signal terminal Re2. The first electrode of capacitor C is connected to the gate of driving transistor T3, and its second electrode is connected to the first power supply terminal VDD. This pixel driving circuit can be used to drive an OLED unit. The first electrode of the OLED unit can be connected to the second electrode of transistor T6, and its second electrode can be connected to the second power supply terminal VSS. The first electrode of the OLED unit can be the anode, and the second electrode can be the cathode.

[0127] Among them, the second transistor T2 and the ninth transistor T9 can be N-type transistors, for example, the second transistor T2 and the ninth transistor T9 can be N-type metal-oxide transistors. At the same time, the first transistor T1, the driving transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 can be P-type transistors, for example, the driving transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 can be P-type low-temperature polycrystalline silicon transistors.

[0128] Figure 2 shows the timing diagram of each node in a driving method of the pixel driving circuit shown in Figure 1. Here, G1 represents the timing of the first gate driving signal terminal G1, G2 represents the timing of the second gate driving signal terminal G2, Re2 represents the timing of the second reset signal terminal Re2, Re1 represents the timing of the first reset signal terminal Re1, and EM represents the timing of the enable signal terminal EM.

[0129] As shown in Figure 2, the ninth transistor T9 is in a normally conducting state under the action of the first power supply terminal VDD or the third initial signal terminal Vinit3.

[0130] Figure 2 shows a timing diagram of some nodes in a driving method of the pixel driving circuit shown in Figure 1. Here, G1 represents the timing of the first gate driving signal terminal G1, G2 represents the timing of the second gate driving signal terminal G2, Re2 represents the timing of the second reset signal terminal Re2, Re1 represents the timing of the first reset signal terminal Re1, and EM represents the timing of the enable signal terminal EM.

[0131] The pixel driving circuit includes a first reset phase t1, a data writing phase t2, a second reset phase t3, and a light emission phase t4 during the high refresh rate driving period. In the first reset phase t1: the first gate driving signal terminal G1 and the second gate driving signal terminal G2 output high-level signals, the first reset signal terminal Re1 outputs a low-level signal, the first transistor T1, the second transistor T2, and the ninth transistor T9 are turned on, and the first initial signal terminal Vinit1 inputs a first initial signal to the first node N1 through the first transistor T1 and the second transistor T2. In the data writing phase t2: the first gate driving signal terminal G1 outputs a high-level signal, the second gate driving signal terminal G2 outputs a low-level signal, the fourth transistor T4, the second transistor T2, and the ninth transistor T9 are turned on, and the data signal terminal Da writes a compensation voltage Vdata+Vth to the first node N1 through the fourth transistor T4, the ninth transistor T9, and the second transistor T2, where Vdata is the voltage of the data signal at the data signal terminal, and Vth is the threshold voltage of the driving transistor T3. In the second reset phase t3: the second reset signal terminal Re2 outputs a low-level signal, turning on the seventh transistor T7 and the eighth transistor T8. The second initial signal terminal Vinit2 inputs a second initial signal to the first electrode of the OLED light-emitting unit, and the third initial signal terminal Vinit3 inputs a third initial signal to the first electrode of the driving transistor T3. The third initial signal can improve the hysteresis problem of the driving transistor T3. In the light-emitting phase t4: the enable signal terminal EM outputs a low-level signal, turning on the sixth transistor T6, the fifth transistor T5, and the ninth transistor T9. The driving transistor T3 drives the light-emitting unit to emit light under the action of the compensation voltage Vdata+Vth stored in capacitor C. The formula for the output current of the driving transistor is as follows: I=(μWCox / 2L)(Vgs-Vth) 2

[0132] Where I is the output current of the driving transistor; μ is the carrier mobility; Cox is the gate capacitance per unit area; W is the width of the driving transistor channel; L is the length of the driving transistor channel; Vgs is the gate-source voltage difference of the driving transistor; and Vth is the threshold voltage of the driving transistor. In the pixel driving circuit described above, the output current of the driving transistor I = (μWCox / 2L)(Vdata + Vth - Vdd - Vth) 2 This pixel driving circuit can avoid the influence of the driving transistor threshold on its output current.

[0133] This exemplary embodiment also provides a display panel, which may include a substrate, a shielding layer, a first active layer, a first gate layer, a second gate layer, a second active layer, a third gate layer, a first source / drain layer, and a second source / drain layer stacked sequentially. An insulating layer may be disposed between adjacent layers. As shown in Figures 3-17, Figure 3 is a structural layout diagram of an exemplary embodiment of the display panel of this disclosure; Figure 4 is a structural layout diagram of the shielding layer in Figure 3; Figure 5 is a structural layout diagram of the first active layer in Figure 3; Figure 6 is a structural layout diagram of the first gate layer in Figure 3; Figure 7 is a structural layout diagram of the second gate layer in Figure 3; Figure 8 is a structural layout diagram of the second active layer in Figure 3; Figure 9 is a structural layout diagram of the third gate layer in Figure 3; Figure 10 is a structural layout diagram of the first source / drain layer in Figure 3; Figure 11 is a structural layout diagram of the second source / drain layer in Figure 3; Figure 12 is a structural layout diagram of the shielding layer and the first active layer in Figure 3; Figure 13... Figure 3 shows the structural layout of the shielding layer, the first active layer, and the first gate layer. Figure 14 shows the structural layout of the shielding layer, the first active layer, the first gate layer, and the second gate layer in Figure 3. Figure 15 shows the structural layout of the shielding layer, the first active layer, the first gate layer, the second gate layer, and the second active layer in Figure 3. Figure 16 shows the structural layout of the shielding layer, the first active layer, the first gate layer, the second gate layer, the second active layer, and the third gate layer in Figure 3. Figure 17 shows the structural layout of the shielding layer, the first active layer, the first gate layer, the second gate layer, the second active layer, the third gate layer, and the first source / drain layer in Figure 3.

[0134] The display panel may include multiple pixel driving circuits as shown in FIG1. ​​As shown in FIG3, the display panel may include multiple pixel driving circuit groups Pz distributed in a first direction X and a second direction Y. Each pixel driving circuit group Pz may include two adjacent pixel driving circuits Pix distributed in the first direction X. At least a portion of the orthographic projection of the two pixel driving circuits Pix onto the substrate may be mirror-symmetrically arranged about an axis of symmetry extending along the second direction Y. The orthographic projections of the channel regions of the same type of transistors in the two pixel driving circuits with at least partially mirror-symmetrical structures onto the substrate are mirror-symmetrically arranged. For example, the orthographic projections of the channel regions of the first transistors in the two pixel driving circuits Pix onto the substrate are mirror-symmetrically arranged along an axis of symmetry. The first direction X and the second direction Y intersect; for example, the first direction X may be a row direction, and the second direction Y may be a column direction.

[0135] As shown in Figures 3, 4, and 12, the shielding layer includes multiple shielding parts 81 distributed in an array along the first direction X and the second direction Y, and the shielding parts 81 are interconnected.

[0136] As shown in Figures 3, 5, 12, and 13, the first active layer may include: a first active section 71, a third active section 73, a fourth active section 74, a fifth active section 75, a sixth active section 76, a seventh active section 77, an eighth active section 78, a tenth active section 710, an eleventh active section 711, a twelfth active section 712, a thirteenth active section 713, a fourteenth active section 714, a fifteenth active section 715, a sixteenth active section 716, a seventeenth active section 717, an eighteenth active section 718, a nineteenth active section 719, and a twentieth active section 720. The first active portion 71 is used to form the channel region of the first transistor T1; the third active portion 73 can be used to form the channel region of the driving transistor T3; the fourth active portion 74 can be used to form the channel region of the fourth transistor T4; the fifth active portion 75 can be used to form the channel region of the fifth transistor T5; the sixth active portion 76 can be used to form the channel region of the sixth transistor T6; the seventh active portion 77 can be used to form the channel region of the seventh transistor T7; the eighth active portion 78 can be used to form the channel region of the eighth transistor T8; the tenth active portion 710 and the twelfth active portion 712 are connected to the two ends of the eighth active portion 78; the eleventh active portion 711 is connected between the fourth active portion 74 and the third active portion 73; the thirteenth active portion 713 is connected to the fourth active portion 74 is located on the side away from the third active part 73; the fourteenth active part 714 is connected to the side of the seventh active part 77 away from the sixth active part 76; the fifteenth active part 715 is connected to the side of the fifth active part 75 away from the third active part 73, and is located in adjacent pixel driving circuit groups in the first direction X, with the two adjacent pixel driving circuits sharing the same fifteenth active part 715; the sixteenth active part 716 is connected between the seventh active part 77 and the sixth active part 76; the seventeenth active part 717 and the eighteenth active part 718 are connected to both ends of the first active part 71; the nineteenth active part 719 is connected to the end of the sixth active part 76 away from the seventh active part 77; and the twentieth active part 720 is connected to the end of the third active part 73 away from the fourth active part 74. The first active layer can be formed of polycrystalline silicon material. Correspondingly, the first transistor T1, the driving transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 can be P-type low-temperature polycrystalline silicon thin-film transistors.

[0137] The orthographic projection of the shielding portion 81 on the substrate can at least partially overlap with the orthographic projection of the third active portion 73 on the substrate. The shielding portion 81 can block light from the third active portion 73 to improve the stability of the output characteristics of the driving transistor. The shielding layer can be a conductive structure and can be connected to a stable voltage terminal. The shielding layer can act as a signal shield for the pixel driving circuit. For example, the stable voltage terminal can be any one of the first power supply terminal, the second power supply terminal, the first initial signal terminal, the second initial signal terminal, and the third initial signal terminal in FIG1.

[0138] As shown in Figures 3, 6, and 13, the first gate layer may include: a first conductive portion 11, a second gate line G2, an enable signal line EM, a first reset signal line Re1, and a second reset signal line Re2. The second gate line G2 can be used to provide the second gate drive signal terminal in Figure 1; the enable signal line EM can be used to provide the enable signal terminal in Figure 1; the first reset signal line Re1 can be used to provide the first reset signal terminal in Figure 1; and the second reset signal line Re2 can be used to provide the second reset signal terminal in Figure 1. The orthographic projections of the second gate line G2, the enable signal line EM, the first reset signal line Re1, and the second reset signal line Re2 onto the substrate can all extend along the first direction X. The orthographic projection of the second gate line G2 onto the substrate covers the orthographic projection of the fourth active portion 74 onto the substrate, and a portion of the structure of the second gate line G2 is used to form the gate of the fourth transistor. The orthographic projection of the enable signal line EM onto the substrate covers the orthographic projections of the fifth active portion 75 and the sixth active portion 76 onto the substrate. A portion of the structure of the enable signal line EM can be used to form the gates of the fifth transistor T5 and the sixth transistor T6, respectively. The orthographic projection of the first reset signal line Re1 onto the substrate covers the orthographic projection of the first active portion 71 onto the substrate. A portion of the structure of the first reset signal line Re1 is used to form the gate of the first transistor T1. The orthographic projection of the second reset signal line Re2 onto the substrate covers the orthographic projections of the seventh active portion 77 and the eighth active portion 78 onto the substrate. A portion of the structure of the second reset signal line Re2 can be used to form the gates of the seventh transistor T7 and the eighth transistor T8, respectively. The orthographic projection of the first conductive portion 11 onto the substrate covers the orthographic projection of the third active portion 73 onto the substrate. The first conductive portion 11 can be used to form the gate of the driving transistor T3 and the first electrode of the capacitor C. The display panel can use the first gate layer as a mask to conduct the first active layer, that is, the area of ​​the first active layer covered by the first gate layer can form the channel region of the transistor, and the area of ​​the first active layer not covered by the first gate layer forms a conductor structure.

[0139] As shown in Figures 3, 7, and 14, the second gate layer may include: a third gate line 2G1, a second conductive portion 22, a first connection portion 21, and a first initial signal line Vinit1. The orthographic projections of the third gate line 2G1 and the first initial signal line Vinit1 on the substrate extend along the first direction X. The third gate line 2G1 can be used to provide the first gate drive signal terminal in Figure 1. The first initial signal line Vinit1 can be used to provide the first initial signal terminal in Figure 1. The orthographic projections of the second conductive portion 22 and the first conductive portion 11 on the substrate at least partially overlap. The second conductive portion 22 is used to form the second electrode of the capacitor C. The first connection portion 21 connects two adjacent second conductive portions 22 in the first direction X.

[0140] As shown in Figures 3, 8, and 15, the second active layer may include an active portion 9, which may include: a second active portion 92, a ninth active portion 99, a twenty-first active portion 921, a twenty-second active portion 922, and a twenty-third active portion 923. The twenty-first active portion 921 is connected to the side of the second active portion 92 away from the ninth active portion 99, the twenty-second active portion 922 is connected to the side of the ninth active portion 99 away from the second active portion 92, and the twenty-third active portion 923 is connected between the second active portion 92 and the ninth active portion 99. The second active portion 92 is used to form the channel region of the second transistor T2, and the ninth active portion 99 is used to form the channel region of the ninth transistor T9. The second active layer may be formed of indium gallium zinc oxide (IGGaZN), and correspondingly, the second transistor T2 and the ninth transistor T9 may be N-type metal-oxide thin-film transistors. The orthographic projection of the third gate line 2G1 on the substrate can cover the orthographic projection of the second active portion 92 on the substrate, and a portion of the structure of the third gate line 2G1 can be used to form the first gate of the second transistor T2. The orthographic projection of the first connection portion 21 on the substrate covers the orthographic projection of the ninth active portion 99 on the substrate, and a portion of the structure of the first connection portion 21 is used to form the first gate of the ninth transistor T9.

[0141] As shown in Figures 3, 9, and 16, the third gate layer may include a first gate line 3G1, a second initial signal line Vinit2, a third initial signal line Vinit3, a third conductive portion 33, and a fourth conductive portion 34. The orthographic projections of the first gate line 3G1, the second initial signal line Vinit2, and the third initial signal line Vinit3 onto the substrate can all extend along the first direction X. The first gate line 3G1 can be used to provide the first gate drive signal terminal in Figure 1. The orthographic projection of the first gate line 3G1 onto the substrate can cover the orthographic projection of the second active portion 92 onto the substrate. A portion of the structure of the first gate line 3G1 can be used to form the second gate of the second transistor T2. Simultaneously, the first gate line 3G1 can be connected to the third gate line 2G1 through a via located in the display panel bezel area. The second initial signal line Vinit2 can be used to provide the second initial signal terminal in Figure 1, and the third initial signal line Vinit3 can be used to provide the third initial signal terminal in Figure 1. The orthographic projection of the third conductive portion 33 on the substrate extends along the first direction X, and the orthographic projection of the fourth conductive portion 34 on the substrate extends along the second direction Y. The fourth conductive portion 34 connects the third conductive portion 33 and the third initial signal line Vinit3. The orthographic projection of the third conductive portion 33 on the substrate covers the orthographic projection of the ninth active portion 99 on the substrate, and at least a portion of the structure of the third conductive portion 33 is used to form the second gate of the ninth transistor T9. In the two pixel driving circuits in the same pixel driving circuit group, the orthographic projections of the two ninth active portions 99 on the substrate are covered by the orthographic projection of the same third conductive portion 33 on the substrate. This display panel can use the third gate layer as a mask to perform conductor processing on the second active layer, that is, the area of ​​the second active layer covered by the third gate layer can form the channel region of the transistor, and the area of ​​the second active layer not covered by the third gate layer forms a conductor structure.

[0142] As shown in Figures 3, 10, and 17, the first source / drain layer may include a first bridging section 41, a second bridging section 42, a third bridging section 43, a fourth bridging section 44, a fifth bridging section 45, a sixth bridging section 46, a seventh bridging section 47, an eighth bridging section 48, a ninth bridging section 49, a tenth bridging section 410, an eleventh bridging section 411, a twelfth bridging section 412, a fourteenth bridging section 414, and a first fan-out line FIPH. The first bridging section 41 is connected to the twelfth active section 712 and the third initial signal line Vinit3 via vias, thereby connecting the third initial signal terminal and the first terminal of the eighth transistor T8. Pixel driving circuit groups located adjacent to each other in the first direction X share the same first bridging section 41. The second bridging section 42 connects to the twenty-third active section 923, the nineteenth active section 719, and the seventeenth active section 717 via vias, connecting the second terminal of the second transistor T2, the second terminal of the first transistor T1, the second terminal of the ninth transistor T9, and the first terminal of the sixth transistor T6. The third bridging section 43 connects to the eighteenth active section 718 and the first initial signal line Vinit1 via vias, connecting the first terminal of the first transistor T1 and the first initial signal terminal. Two pixel driving circuits in the same pixel driving circuit group share the same third bridging section 43. The fourth bridging section 44 connects to the fourteenth active section 714 and the second initial signal line Vinit2 via vias, connecting the first terminal of the seventh transistor T7 and the second initial signal terminal. The fifth bridging section 45 connects to the thirteenth active section 713 via vias, connecting the first terminal of the fourth transistor T4. The sixth bridging portion 46 connects to the eleventh active portion 711 and the tenth active portion 710 via vias, connecting the second electrode of the eighth transistor T8 and the first electrode of the driving transistor T3. The seventh bridging portion 47 connects to the first connecting portion 21 and the fifteenth active portion 715 via vias, connecting the second electrode of the capacitor C and the first electrode of the fifth transistor T5. Adjacent pixel driving circuit groups located in the first direction X share the same seventh bridging portion 47. The eighth bridging portion 48 connects to the sixteenth active portion 716 via vias, connecting the second electrode of the seventh transistor T7 and the second electrode of the sixth transistor T6. The ninth bridging portion 49 connects to the twenty-first active portion 921 and the first conductive portion 11 via vias, connecting the gate of the driving transistor T3 and the first electrode of the second transistor T2. An opening 221 may be formed on the second conductive portion 22, and a via connecting the ninth bridging portion 49 and the first conductive portion 11 passes through the opening 221. The eleventh bridging section 411 is connected between the two fourth bridging sections 44 in the partial pixel driving circuit group. The twelfth bridging section 412 is connected to the third bridging section 43 in the partial pixel driving circuit group.The fourteenth bridging section 414 connects to the twentieth active section 720 and the twenty-second active section 922 via vias, respectively, to connect the first electrode of the ninth transistor T9 and the second electrode of the driving transistor T3. The orthogonal projection of the first fan-out line FIPH on the substrate can extend along the first direction X. The first fan-out line FIPH can serve as a first-direction fan-out line connecting data lines in the FIP (Fanout In Pixel). In addition, the first fan-out line FIPH can also be provided outside the fan-out area. The first fan-out line FIPH outside the fan-out area can be connected to other signal lines or conductive blocks to reduce the voltage difference of signals at different positions on the display panel. For example, the first fan-out line FIPH outside the fan-out area can be connected to the common electrode layer of the display panel, which is located on the side of the light-emitting unit away from the substrate.

[0143] As shown in Figures 3 and 11, the second source / drain layer may include: a first power line VDD, a data line Da, a first initial connection line 5Vinit1, a second initial connection line 5Vinit2, a second fan-out line FIPV, and a thirteenth bridge section 513. The orthographic projections of the first power line VDD, the data line Da, the first initial connection line 5Vinit1, the second initial connection line 5Vinit2, and the second fan-out line FIPV onto the substrate all extend along the second direction Y. The first power line VDD provides the first power terminal in Figure 1. The first power line VDD is connected to the seventh bridge section 47 via a via to connect the first electrode of the fifth transistor and the first power terminal. The data line Da provides the data signal terminal in Figure 1. The data line Da is connected to the fifth bridge section 45 via a via to connect the data signal terminal and the first electrode of the fourth transistor T4. The first initial connection line 5Vinit1 is connected to the twelfth bridging section 412 via a via to connect to the intersecting first initial signal line Vinit1. Multiple first initial connection lines 5Vinit1 and multiple first initial signal lines Vinit1 can form a grid structure. The grid structure of the first initial signal lines Vinit1 can reduce the voltage difference of the first initial signal lines Vinit1 at different locations on the display panel, thereby improving the display uniformity of the display panel. The second initial connection line 5Vinit2 can be connected to the eleventh bridging section 411 via a via to connect to the intersecting second initial signal line Vinit2. Multiple second initial connection lines 5Vinit2 and multiple second initial signal lines Vinit2 can form a grid structure. The grid structure of the second initial signal lines Vinit2 can also improve the display uniformity of the display panel. The second fan-out line FIPV can serve as a second-direction fan-out line connecting data lines in the FIP (Fanout In Pixel). The second fan-out line FIPV can include multiple fan-out segments spaced apart in the second direction, and adjacent fan-out segments can be bridged through the tenth bridging section 410. Furthermore, a second fan-out line FIPV can be provided outside the fan-out area. This second fan-out line FIPV can be connected to other signal lines or conductive blocks to reduce voltage differences between different locations on the display panel. For example, the second fan-out line FIPV outside the fan-out area can be connected to the common electrode layer of the display panel, which is located on the side of the light-emitting unit facing away from the substrate. The thirteenth bridging portion 513 can be connected to the eighth bridging portion 48 via a via, and the thirteenth bridging portion 513 can be used to connect to the first electrode of the light-emitting unit.

[0144] In other exemplary embodiments, the second source / drain layer may further include a third initial connection line. The orthographic projection of the third initial connection line on the substrate also extends along the second direction Y. The third initial connection line can be connected to the first bridging portion 41 via vias to connect to the intersecting third initial signal line Vinit3. Multiple third initial connection lines and multiple third initial signal lines Vinit3 can form a mesh structure. The orthographic projections of the first initial connection line 5Vinit1, the second initial connection line 5Vinit2, and the third initial connection line on the substrate can be alternately distributed along the first direction X.

[0145] Figure 18 shows a partial cross-sectional view of the display panel shown in Figure 3, cut along the dashed line AA. The display panel may further include a buffer layer 101, a second insulating layer 102, a third insulating layer 103, a fourth insulating layer 104, a fifth insulating layer 105, a first dielectric layer 106, a passivation layer 107, and a first planarization layer 108. The substrate 100, shielding layer, buffer layer 101, first active layer, second insulating layer 102, first gate layer, third insulating layer 103, second gate layer, fourth insulating layer 104, second active layer, fifth insulating layer 105, third gate layer, first dielectric layer 106, first source / drain layer, passivation layer 107, first planarization layer 108, and second source / drain layer are sequentially stacked. The buffer layer 101, the second insulating layer 102, the third insulating layer 103, the fourth insulating layer 104, and the fifth insulating layer 105 can be single-layer or multi-layer structures, and the materials of the buffer layer 101, the second insulating layer 102, the third insulating layer 103, the fourth insulating layer 104, and the fifth insulating layer 105 can be at least one of silicon nitride, silicon oxide, and silicon oxynitride; the first dielectric layer 106 can be a silicon nitride layer; the material of the first planarization layer 108 can be an organic material, such as polyimide (PI), polyethylene terephthalate (PET), polyethylene naphthalate (PEN), silicon-glass bonded structure (SOG), etc. The passivation layer 107 can be a silicon oxide layer. The substrate 100 can include a glass substrate, a barrier layer, and a polyimide layer stacked sequentially, and the barrier layer can be an inorganic material. The materials of the first gate layer, the second gate layer, and the third gate layer can be one of molybdenum, aluminum, copper, titanium, niobium, or an alloy thereof, or a molybdenum / titanium alloy or a stacked conductive layer. The materials of the first and second source / drain layers can include metallic materials, such as molybdenum, aluminum, copper, titanium, niobium, or alloys thereof, or molybdenum / titanium alloys or stacks, or conductive layers such as titanium / aluminum / titanium stacks. The sheet resistance of any one of the first and second source / drain layers can be less than the sheet resistance of any one of the first, second, and third gate layers.

[0146] As shown in Figures 19 and 20, Figure 19 is a structural schematic diagram of another exemplary embodiment of the display panel of this disclosure, and Figure 20 is a structural schematic diagram of the third gate layer in the display panel shown in Figure 19. Compared with the display panel shown in Figure 3, the ninth transistor T9 in the display panel shown in Figure 19 adopts a single-gate structure, that is, the ninth transistor T9 only uses the first connection portion 21 to form its first gate, and the ninth transistor T9 does not have a second gate. Other structures of the display panel shown in Figure 19 can be the same as those of the display panel shown in Figure 3.

[0147] As shown in Figures 21-24, Figure 21 is a structural schematic diagram of another exemplary embodiment of the display panel of this disclosure, Figure 22 is a structural schematic diagram of the first gate layer in the display panel shown in Figure 21, Figure 23 is a structural schematic diagram of the second gate layer in the display panel shown in Figure 21, and Figure 24 is a structural schematic diagram of the shielding layer, the first active layer, the first gate layer, the second gate layer, and the second active layer in the display panel shown in Figure 21. The main difference between the display panel shown in Figure 21 and the display panel shown in Figure 3 is that the ninth transistor T9 in the display panel shown in Figure 21 adopts a single-gate structure, that is, the ninth transistor T9 only uses the third conductive part 33 to form its second gate, and the ninth transistor T9 does not have a first gate. As shown in Figures 21-24, the first connecting part 21 needs to be bent downward to avoid the active part 9. Specifically, the first connecting part 21 may include: a first sub-connecting part 211, a second sub-connecting part 212, and a third sub-connecting part 213. The orthographic projection of the first sub-connecting portion 211 on the substrate extends along the second direction Y; the orthographic projection of the second sub-connecting portion 212 on the substrate extends along the second direction Y; the third sub-connecting portion 213 is connected between the first sub-connecting portion 211 and the second sub-connecting portion 212, and the orthographic projection of the third sub-connecting portion 213 on the substrate extends along the first direction X; the orthographic projection of the third sub-connecting portion 213 on the substrate and the orthographic projection of the third conductive portion 23 on the substrate are arranged opposite to each other in the second direction Y, and the orthographic projections of the first sub-connecting portion 211 and the second sub-connecting portion 212 on the substrate are located between the orthographic projections of the third sub-connecting portion 213 and the third conductive portion 23 on the substrate. Simultaneously, a notch EM1 is formed on the side of the enable signal line EM projected onto the substrate, facing the projection of the first connection portion 21 onto the substrate, to prevent the projections of the enable signal line EM onto the substrate and the projection of the first connection portion 21 onto the substrate from overlapping. Specifically, the projections of the notch EM1 onto the substrate and the projection of the third sub-connection portion 213 onto the substrate are positioned opposite each other in the second direction Y. This avoids the formation of a large parasitic capacitance between the enable signal line and the first connection portion 21. It should be noted that the structures A and B are positioned opposite each other in the second direction, which can be understood as the regions traversed by structure A and structure B when moving infinitely in the second direction at least partially overlapping.

[0148] As shown in Figures 25-29, Figure 25 is a structural layout diagram of another exemplary embodiment of the display panel of this disclosure, Figure 26 is a structural layout diagram of the first source / drain layer, the second source / drain layer, and the electrode layer in the display panel shown in Figure 25, Figure 27 is a structural layout diagram of the first source / drain layer and the second source / drain layer in the display panel shown in Figure 25, Figure 28 is a structural layout diagram of the first source / drain layer in the display panel shown in Figure 25, and Figure 29 is a structural layout diagram of the electrode layer in the display panel shown in Figure 25.

[0149] As shown in Figures 25-29, the display panel further includes an electrode layer located on the side of the second source / drain layer facing away from the substrate. The electrode layer includes multiple electrode portions, which may include a first electrode portion R, a second electrode portion B, and a third electrode portion G. The first electrode portion R can be used to form the first electrode of a red light-emitting unit, the second electrode portion B can be used to form the first electrode of a blue light-emitting unit, and the third electrode portion G can be used to form the first electrode of a green light-emitting unit. The display panel may also include a pixel defining layer located on the side of the electrode layer facing away from the substrate. Multiple pixel openings are formed on the pixel defining layer, and the pixel openings are correspondingly disposed with the electrode portions. The orthographic projection of the electrode portion on the substrate coincides with the orthographic projection of its corresponding pixel opening on the substrate.

[0150] As shown in Figures 25-29, among the multiple electrode portions connected to the same row pixel driving circuit, the first electrode portion, the third electrode portion, the second electrode portion, and the third electrode portion are alternately distributed in the row direction; in two adjacent column pixel driving circuits, multiple first electrode portions and multiple second electrode portions are connected to the same column pixel driving circuit, and the first electrode portions and second electrode portions connected to the same column pixel driving circuit are alternately distributed in the column direction, and multiple third electrode portions are connected to another column pixel driving circuit.

[0151] As shown in Figures 25-29, the display panel can also include a first initial connecting line, a second initial connecting line, and a third initial connecting line, which together form the initial connecting line. The orthographic projections of the ninth bridging portions 49 located on both sides of the initial connecting line in the first direction X on the substrate and the orthographic projections of the third electrode portion G on the substrate overlap, and the orthographic projections of the two ninth bridging portions 49 on the substrate and the orthographic projections of the third electrode portion G on the substrate overlap on both sides of the first direction. Similarly, the orthographic projections of the second bridging portions 42 located on both sides of the initial connecting line in the first direction X on the substrate and the orthographic projections of the third electrode portion G on the substrate overlap, and the orthographic projections of the two second bridging portions 42 on the substrate and the orthographic projections of the third electrode portion G on the substrate overlap on both sides of the first direction. This arrangement allows the third electrode portion G to be relatively flat.

[0152] As shown in Figures 25-29, the electrode layer also includes a first electrode connection portion R1. The first electrode connection portion R1 and the first electrode portion R are connected in the same layer and are connected to the thirteenth bridging portion 513 via a via. As shown in Figure 25, in a local area BB, the overlapping area of ​​the orthographic projection of the first electrode connection portion R1 on the substrate and the orthographic projection of the enable signal line EM on the substrate overlaps with the eleventh bridging portion 411. The eleventh bridging portion 411 can shield the signal interference between the enable signal line EM and the first electrode connection portion R1.

[0153] As shown in Figures 25-29, the via connecting the second source / drain layer to the conductive layer facing the substrate can be called a second source / drain via. Compared to the display panel shown in Figure 3, the thirteenth bridging portion 513 connected to the second conductive portion B extends downward, and correspondingly, the via connecting the second conductive portion B and the thirteenth bridging portion 513 moves downward. The thirteenth bridging portion 513 connected to the third conductive portion G extends downward, and correspondingly, the via connecting the third conductive portion G and the thirteenth bridging portion 513 moves downward. This arrangement allows the four corner regions of the orthographic projection of the second conductive portion B onto the substrate to overlap with the orthographic projections of the four second source / drain vias onto the substrate, thereby improving the flatness of the second conductive portion B.

[0154] It should be noted that, as shown in Figure 3-29, the black squares with chamfers drawn on the side of the first source / drain layer away from the substrate represent vias connecting the first source / drain layer to other layers facing the substrate; the black rectangles with chamfers drawn on the side of the second source / drain layer away from the substrate represent vias connecting the second source / drain layer to other layers facing the substrate; and the black circles drawn on the side of the electrode layer away from the substrate represent vias connecting the electrode layer to other layers facing the substrate. Vias at different positions can penetrate different insulating layers.

[0155] It should be noted that the scale of the accompanying drawings in this disclosure can be used as a reference in actual processes, but is not limited thereto. For example, the aspect ratio of the channels, the thickness and spacing of each film layer, and the width and spacing of each signal line can be adjusted according to actual needs. The number of pixels in the display substrate and the number of sub-pixels in each pixel are not limited to the quantities shown in the figures. The accompanying drawings described in this disclosure are only schematic diagrams of the structure. In addition, the terms "first," "second," etc., are only used to define different structural names and do not have a specific order meaning. The same structural layer can be formed by the same patterning process. In this exemplary embodiment, the orthographic projection of a certain structure on the substrate extends along a certain direction, which can be understood as the orthographic projection of the structure on the substrate extending in a straight line or bending along that direction.

[0156] This exemplary embodiment also provides a display device, which includes the display panel described above. The display device can be a mobile phone, tablet computer, television, or other display device.

[0157] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the disclosure herein. This application is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the claims.

[0158] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the disclosure herein. This application is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the claims.

[0159] It should be understood that this disclosure is not limited to the precise structures described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this disclosure is defined only by the appended claims.

Claims

1. A display panel, wherein, The display panel includes: Substrate; Multiple light-emitting units are located on one side of the substrate. Multiple pixel driving circuits are located on one side of the substrate. The multiple pixel driving circuits are arrayed along a first direction and a second direction, and the first direction and the second direction intersect. The pixel driving circuits are used to drive the light-emitting unit to emit light. The pixel driving circuits include a driving transistor, a ninth transistor, and a sixth transistor. The first terminal of the driving transistor is connected to the first power supply line, and the second terminal is connected to the first terminal of the ninth transistor. The first electrode of the sixth transistor is connected to the second electrode of the ninth transistor, and the second electrode is connected to the first electrode of the light-emitting unit. The ninth transistor is controlled by a constant voltage signal line, and the constant voltage signal on the constant voltage signal line can turn on the ninth transistor.

2. The display panel according to claim 1, wherein, The ninth transistor is an N-type transistor. The pixel driving circuit also includes an eighth transistor, the first terminal of which is connected to the third initial signal line, and the second terminal of which is connected to the first terminal of the driving transistor. The constant voltage signal line is one or more, and the one or more constant voltage signal lines include one or more of the first power line and the third initial signal line.

3. The display panel according to claim 1, wherein, The pixel driving circuit also includes a capacitor, the first electrode of which is connected to the gate of the driving transistor, and the second electrode of which is connected to a first power supply line. The constant voltage signal line includes the first power supply line. The display panel also includes: The second gate layer is located on one side of the substrate. The second gate layer includes a second conductive portion and a first connecting portion. The second conductive portion is used to form the second electrode of the capacitor. The first connecting portion is connected between two adjacent second conductive portions in the first direction. The second active layer is located on the side of the second gate layer away from the substrate. The second active layer includes a ninth active portion, which is used to form the channel region of the ninth transistor. Wherein, the orthographic projection of the first connection portion on the substrate covers the orthographic projection of the ninth active portion on the substrate, and at least a portion of the structure of the first connection portion is used to form the first gate of the ninth transistor.

4. The display panel according to claim 1, wherein, The pixel driving circuit further includes an eighth transistor, the first terminal of which is connected to the third initial signal line and the second terminal of which is connected to the first terminal of the driving transistor. The constant voltage signal line includes the third initial signal line. The display panel also includes: The second active layer is located on one side of the substrate. The second active layer includes a ninth active portion, which is used to form the channel region of the ninth transistor. The third gate layer is located on the side of the second active layer away from the substrate. The third gate layer includes the third initial signal line and the third conductive portion. The third conductive portion and the third initial signal line are connected in the same layer. The orthogonal projection of the third conductive portion on the substrate covers the orthogonal projection of the ninth active portion on the substrate. At least a portion of the structure of the third conductive portion is used to form the second gate of the ninth transistor.

5. The display panel according to claim 1, wherein, The pixel driving circuit further includes: a second transistor, wherein a first terminal of the second transistor is connected to the gate of the driving transistor, and a second terminal of the second transistor is connected to the second terminal of the driving transistor; The display panel also includes: A first gate line, the orthogonal projection of the first gate line on the substrate extends along the first direction, and a portion of the structure of the first gate line is used to form the first gate of the second transistor; The third conductive portion is at least partially used to form the first gate of the ninth transistor; An enable signal line, whose orthogonal projection on the substrate extends along the first direction, wherein a portion of the structure of the enable signal line is used to form the gate of the sixth transistor; In the same pixel driving circuit, the orthogonal projection of the third conductive part on the substrate is located between the orthogonal projection of the first gate line on the substrate and the orthogonal projection of the enable signal line on the substrate.

6. The display panel according to claim 5, wherein, The pixel driving circuit further includes an eighth transistor, the first terminal of which is connected to the third initial signal line, and the second terminal of which is connected to the first terminal of the driving transistor. The display panel further includes a third gate layer, the third gate layer further includes the third conductive portion and the fourth conductive portion, the orthographic projection of the third conductive portion on the substrate extends along the first direction, the orthographic projection of the fourth conductive portion on the substrate extends along the second direction, and the fourth conductive portion is connected between the third conductive portion and the third initial signal line.

7. The display panel according to claim 5, wherein, The pixel driving circuit further includes an eighth transistor, the first terminal of which is connected to the third initial signal line, and the second terminal of which is connected to the first terminal of the driving transistor. The display panel also includes: The second reset signal line extends along the first direction in the orthogonal projection on the substrate, and a portion of the structure of the second reset signal line is used to form the gate of the eighth transistor. In the same pixel driving circuit: the orthographic projection of the second reset signal line on the substrate is located on the side of the orthographic projection of the enable signal line on the substrate away from the orthographic projection of the third conductive part on the substrate, and the orthographic projection of the second reset signal line on the substrate and the orthographic projection of the third initial signal line on the substrate at least partially overlap.

8. The display panel according to claim 1, wherein, The pixel driving circuit further includes a fifth transistor, wherein the first terminal of the fifth transistor is connected to the first power line and the second terminal is connected to the first terminal of the driving transistor. The display panel also includes: A first active layer is located on one side of the substrate. The first active layer includes a fifth active portion and a sixth active portion. The fifth active portion is used to form the channel region of the fifth transistor, and the sixth active portion is used to form the channel region of the sixth transistor. The second active layer is located on the side of the first active layer away from the substrate. The second active layer includes a ninth active portion, which is used to form the channel region of the ninth transistor. In the first direction of the same pixel driving circuit, the orthographic projection of the sixth active part on the substrate is located between the orthographic projection of the ninth active part on the substrate and the orthographic projection of the fifth active part on the substrate.

9. The display panel according to claim 8, wherein, The pixel driving circuit also includes a second transistor and a seventh transistor; The first terminal of the second transistor is connected to the gate of the driving transistor, and the second terminal is connected to the second terminal of the driving transistor; The first terminal of the seventh transistor is connected to the second initial signal line, and the second terminal is connected to the second terminal of the sixth transistor. The first active layer further includes a third active portion, a seventh active portion, a sixteenth active portion, a nineteenth active portion, and a twentieth active portion. The third active portion is used to form the channel region of the driving transistor, the seventh active portion is used to form the channel region of the seventh transistor, the sixteenth active portion is connected between the sixth active portion and the seventh active portion, the nineteenth active portion is connected to the end of the sixth active portion away from the seventh active portion, and the twentieth active portion is connected to the end of the third active portion away from the fifth active portion. The second active layer further includes: a second active portion, a twenty-second active portion, and a twenty-third active portion. The second active portion is used to form the channel region of the second transistor. The twenty-second active portion is connected to the end of the ninth active portion away from the second active portion. The twenty-third active portion is connected between the second active portion and the ninth active portion. The display panel also includes: The fourteenth bridging section connects to the twentieth active section and the twenty-second active section respectively through vias; The second bridging section connects the 23rd active section and the 19th active section respectively through vias.

10. The display panel according to claim 4, wherein, The plurality of pixel driving circuits form a plurality of pixel driving circuit groups, and the plurality of pixel driving circuit groups are arrayed along the first direction and the second direction. The pixel driving circuit group includes two adjacent pixel driving circuits in the first direction. In the same pixel driving circuit group, the channel regions of the ninth transistors in two adjacent pixel driving circuits are mirror-symmetrically arranged on the substrate with respect to the axis of symmetry extending along the second direction. The second active layer includes an active portion, a portion of which is used to form the channel region of the ninth transistor; The display panel also includes: A fourth conductive portion is connected between the third conductive portion and the third initial signal line. The orthographic projection of the fourth conductive portion on the substrate extends along the second direction, and the orthographic projection of the fourth conductive portion on the substrate is at least partially located between the orthographic projections of two adjacent active portions on the substrate in the same pixel driving circuit group.

11. The display panel according to claim 1, wherein, The plurality of pixel driving circuits form a plurality of pixel driving circuit groups, and the plurality of pixel driving circuit groups are arrayed along the first direction and the second direction. The pixel driving circuit group includes two adjacent pixel driving circuits in the first direction. The orthographic projections of two adjacent pixel driving circuits in the same pixel driving circuit group onto the substrate are at least partially mirror-symmetrical with respect to an axis of symmetry extending along a second direction.

12. The display panel according to claim 11, wherein, The pixel driving circuit further includes a seventh transistor, the first electrode of which is connected to a second initial signal line, the second electrode of which is connected to a first electrode of the light-emitting unit, and the orthogonal projection of the second initial signal line on the substrate extends along the first direction. The display panel also includes: The fourth bridging section is connected to the first electrode of the seventh transistor and the second initial signal line through vias; The eleventh bridging section is connected to the two fourth bridging sections in the same pixel driving circuit group at the same layer. The second initial connection line is located on a different conductive layer from the second initial signal line. The orthographic projection of the second initial connection line on the substrate extends along the second direction. The second initial connection line is connected to the eleventh bridging portion through a via.

13. The display panel according to claim 11, wherein, The pixel driving circuit further includes a first transistor, the first terminal of the first transistor is connected to a first initial signal line, the second terminal is connected to the second terminal of the driving transistor, and the orthogonal projection of the first initial signal line on the substrate extends along the first direction. The display panel also includes: The third bridging section is connected to the first electrode of the first transistor and the first initial signal line through vias; The twelfth bridging section is connected to the two third bridging sections in the same pixel driving circuit group at the same layer. The first initial connection line is located on a different conductive layer from the first initial signal line. The orthographic projection of the first initial connection line on the substrate extends along the second direction. The first initial connection line is connected to the twelfth bridging portion through a via.

14. The display panel according to claim 4, wherein, The pixel driving circuit also includes a capacitor, the first electrode of which is connected to the gate of the driving transistor, and the second electrode of which is connected to a first power supply line. The constant voltage signal line includes the first power supply line. The display panel also includes: The second gate layer is located on one side of the substrate. The second gate layer includes a second conductive portion and a first connecting portion. The second conductive portion is used to form the second electrode of the capacitor. The first connecting portion is connected between two adjacent second conductive portions in the first direction. The orthographic projection of the first connecting portion on the substrate and the orthographic projection of the ninth active portion on the substrate do not overlap.

15. The display panel according to claim 14, wherein, The first connecting part includes: The first sub-connecting portion extends along the second direction in its orthogonal projection onto the substrate. The second sub-connecting portion extends along the second direction in the orthographic projection onto the substrate. A third sub-connecting portion is connected between the first sub-connecting portion and the second sub-connecting portion, and the orthographic projection of the third sub-connecting portion on the substrate extends along the first direction; The orthographic projections of the third sub-connection portion and the third conductive portion on the substrate are arranged opposite to each other in the second direction, and the orthographic projections of the first sub-connection portion and the second sub-connection portion on the substrate are located between the orthographic projections of the third sub-connection portion and the third conductive portion on the substrate.

16. The display panel according to claim 15, wherein, The display panel also includes: An enable signal line, the orthographic projection of which extends along a first direction on the substrate, and a portion of the structure of which is used to form the gate of the sixth transistor; The enable signal line has a notch on the side facing the third sub-connection portion, and the orthographic projection of the notch on the substrate and the orthographic projection of the third sub-connection portion on the substrate are arranged opposite each other in the second direction.

17. The display panel according to claim 1, wherein, The pixel driving circuit also includes: A first transistor, wherein the first terminal of the first transistor is connected to a first initial signal line, and the second terminal is connected to the second terminal of the driving transistor; A second transistor, wherein the first terminal of the second transistor is connected to the gate of the driving transistor, and the second terminal of the second transistor is connected to the second terminal of the driving transistor; The fourth transistor has its first terminal connected to the data line and its second terminal connected to the first terminal of the driving transistor. The fifth transistor has its first terminal connected to the first power supply line and its second terminal connected to the first terminal of the driving transistor. The seventh transistor has its first terminal connected to the second initial signal line and its second terminal connected to the light-emitting unit. The eighth transistor has its first terminal connected to the third initial signal line and its second terminal connected to the first terminal of the driving transistor. The capacitor has a first electrode connected to the gate of the driving transistor and a second electrode connected to the first power supply line. Among them, the first transistor, the driving transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, and the eighth transistor are P-type transistors, and the second transistor and the ninth transistor are N-type transistors.

18. The display panel according to claim 1, wherein, The pixel driving circuit includes P-type transistors and N-type transistors, and the display panel further includes: A first active layer is located on one side of the substrate, and a portion of the structure of the first active layer is used to form the channel region of the P-type transistor in the pixel driving circuit. A first gate layer is located on the side of the first active layer away from the substrate, and a portion of the structure of the first gate layer is used to form the gate of the P-type transistor in the pixel driving circuit. The second gate layer is located on the side of the first gate layer away from the substrate, and a portion of the structure of the second gate layer is used to form the first gate of at least a portion of the N-type transistors in the pixel driving circuit. The second active layer is located on the side of the second gate layer away from the substrate, and a portion of the structure of the second active layer is used to form the channel region of the N-type transistor in the pixel driving circuit. A third gate layer is located on the side of the second active layer away from the substrate, and a portion of the structure of the third gate layer is used to form the second gate of at least a portion of the N-type transistors in the pixel driving circuit. The first source / drain layer is located on the side of the third gate layer opposite to the substrate, and a portion of the structure of the first source / drain layer is used to form a bridging portion connecting different transistors.

19. A display device, wherein, The display device includes the display panel as described in any one of claims 1-18.

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