Low power and low noise continuous time comparator

Abstract

The comparator (205) is provided with an always-on current source (Ibias) that conducts bias current through the comparator. The comparator asserts an output signal (out) in response to a ramp signal greater than a threshold voltage (Vth). To increase comparator speed while maintaining relatively low power consumption, the comparator includes a boost current source (Iboost) that conducts boost current through the comparator only during an enable cycle that begins when the ramp signal is greater than a duty cycle voltage (Figures 2 and 3: V duty cycle) less than the threshold voltage (Vth).

Description

Cross-referencing

[0001] This application claims priority and benefit to U.S. nonprovisional patent application No. 18 / 421,852, filed January 24, 2024, the entire contents of which are incorporated herein by reference, as fully set forth below and for all applicable purposes. Technical Field

[0002] This application relates generally to comparators, and more specifically to low-power and low-noise continuous-time comparators. Background Technology

[0003] A continuous-time comparator is an analog device that detects when a signal exceeds a threshold voltage and is a fundamental building block in many circuit applications. Because continuous-time comparators are so common and fundamental, for simplicity, the following discussion will simply refer to them as comparators. An important operating parameter of a comparator is its propagation delay, which is the delay between the input signal to the comparator and the output signal from the comparator. It can be shown that the propagation delay is a function of the bias current conducted through the comparator, such that the larger the bias current, the smaller the propagation delay. Furthermore, a relatively large bias current reduces transistor noise within the comparator. Conversely, the smaller the bias current, the greater the propagation delay and transistor noise. Therefore, comparator designers face the choice between reducing power consumption but resulting in relatively large propagation delay and increased transistor noise, or increasing power consumption at the expense of relatively small propagation delay and reduced transistor noise. Summary of the Invention

[0004] According to one aspect of this disclosure, a comparator system is provided, comprising: a ramp signal generator configured to periodically generate a ramp signal; an auxiliary comparator configured to assert an enable signal in response to the ramp signal being greater than a duty cycle voltage; and a main comparator configured to assert a comparator output signal in response to the ramp signal being greater than a threshold voltage, the threshold voltage being greater than the duty cycle voltage, wherein the main comparator includes: an always-on current source configured to conduct a bias current throughout the entire cycle of the ramp signal; and a boost current source configured to conduct a boost current only when the enable signal is asserted.

[0005] According to another aspect of this disclosure, a method for operating a comparator is provided, the method comprising: periodically generating a ramp signal; conducting a bias current through the comparator throughout the entire period of the ramp signal; conducting a boost current through the comparator in response to the ramp signal being greater than a duty cycle voltage; and asserting an output signal of the comparator in response to the ramp signal being greater than a threshold voltage, the threshold voltage being greater than the duty cycle voltage.

[0006] Finally, according to yet another aspect of this disclosure, a comparator is provided, comprising: a power node for a power supply voltage; a always-on current source coupled to the power node; a first switch coupled to the power node; a boost current source coupled to the first switch; a first PMOS transistor having a source coupled to both the always-on current source and the boost current source; and a first NMOS transistor having a drain coupled to the drain of the first PMOS transistor, wherein the gate of the first PMOS transistor is coupled to the first PMOS transistor. The transistor comprises: a gate of an NMOS transistor; a second PMOS transistor having a source coupled to a constantly on current source and a boost current source; a second NMOS transistor having a drain coupled to the drain of the second PMOS transistor, wherein the gate of the second PMOS transistor is coupled to the gate of the second NMOS transistor; and a third NMOS transistor having a source coupled to ground, a gate coupled to the drain of the second NMOS transistor, and a drain coupled to the source of the first NMOS transistor and the source of the second NMOS transistor.

[0007] These and other advantageous features can be better understood through the detailed description below. Attached Figure Description

[0008] Figure 1 This is a diagram of a Σ-Δ analog-to-digital converter including a current-to-analog converter according to one aspect of the present disclosure, wherein the current-to-analog converter is clock-controlled by a system including a low-power and low-noise comparator.

[0009] Figure 2 This is a diagram of a system including a low-noise and low-power comparator according to one aspect of this disclosure.

[0010] Figure 3 It is based on one aspect of this disclosure. Figure 2 The diagram shows several operating waveforms of the system.

[0011] Figure 4 This is a circuit diagram of a low-noise and low-power comparator according to one aspect of this disclosure.

[0012] Figure 5 This is a flowchart of an operation method for a low-power and low-noise comparator according to one aspect of this disclosure.

[0013] Figure 6 Some example electronic systems including low-noise and low-power comparators according to one aspect of this disclosure are illustrated.

[0014] The specific embodiments of this disclosure and its advantages can be best understood by referring to the following detailed description. It should be understood that the same reference numerals are used to identify the same elements illustrated in one or more of the figures. Detailed Implementation

[0015] This paper discloses a comparator that is high-speed and low-noise, yet has relatively low power consumption. The resulting low-power and low-noise comparator can be used in any system employing comparators. An example system benefiting from this comparator is as follows: Figure 1 The Σ-Δ analog-to-digital converter (ADC) 100 is shown. The first integrating stage 105 is a continuous-time integrating stage that integrates based on the resistor-capacitor (RC) time constant. The input resistor Rin serves as R in the RC time constant. The quantized input signal (such as an audio signal from a microelectromechanical system (MEMS) microphone 140) drives the input terminal 135 of the input resistor, while the other terminal of the input resistor is coupled to the inverting terminal of a differential amplifier (such as an operational transconductance amplifier (OTA) 125). The integrating capacitor, serving as C in the RC time constant, is coupled between the inverting terminal and the output terminal of the OTA 125. Therefore, the time constant is equal to Rin. Cint, where Rin is the resistance of the input resistor and Cint is the capacitance of the integrating capacitor. The feedback current digital-to-analog converter (IDAC) 110 also drives the inverting terminal. To reduce jitter sensitivity, it is advantageous to form the IDAC as a return-to-zero IDAC, which pulses the current according to the integral pulse width (Tp) within the cycle of the IDAC clock signal (IDAC clk).

[0016] Discrete-time integrator 120 integrates the output signal from first integrator stage 105 to provide an integrated signal, which is then quantized by quantizer 115 to provide a digital output signal. After processing by dynamic element matching function 130, the digital output signal is fed back to the inverting node of OTA 125 via IDAC. To improve the performance of Σ-Δ ADC 100, the IDAC clock signal that clocks IDAC 110 should have relatively low jitter.

[0017] like Figure 2The comparator system 200 shown advantageously provides a low-jitter IDAC clock signal by using a low-power and low-noise comparator 205 as disclosed herein. However, the comparator system 200 can be used in any suitable comparator application. Comparator 205 receives a ramp signal from ramp signal generator 210 at its non-inverting input terminal. Comparator 205 compares the ramp signal with a threshold voltage (Vth) received at its inverting input terminal to generate a reset pulse to set-reset (SR) latch 220. Conventionally, comparator 205 will have to choose between relatively low propagation delay at the cost of higher power consumption with reduced transistor noise or lower power consumption but relatively large propagation delay and increased transistor noise, as previously discussed. However, comparator 205 also receives an enable signal from auxiliary comparator 215 at its enable input terminal. As will be further explained herein, comparator 205 is configured to conduct a relatively small bias current until the enable signal is asserted. Therefore, in addition to conducting the bias current, comparator 205 also conducts a significantly larger boost current to achieve improved performance and operating speed at the transition point where the ramp signal rises to and becomes equal to and greater than the threshold voltage. Comparator 205 is also referred to herein as the master comparator.

[0018] The delay between the enable signal assertion and the switching point of comparator 205 is sufficiently large to allow the boost current in comparator 205 to begin conducting well before the switching point, without the delay being excessive and thus limiting the resulting power consumption. The increased bias current advantageously reduces transistor noise, allowing comparator 205 to generate a comparator output signal with reduced jitter. The delay between the enable signal assertion and the switching point is determined by the time between the switching point of auxiliary comparator 215 and the switching point of comparator 205. In one embodiment, the ramp signal frequency can range from 500 kHz to several MHz (e.g., greater than 6 MHz), such that the delay can be approximately 20 nanoseconds; however, it should be understood that other ramp signal frequencies and delay values ​​can be used in alternative embodiments. Regarding the switching point of auxiliary comparator 215, auxiliary comparator 215 receives the ramp signal at the non-inverting input terminal and the duty cycle voltage signal (V_duty_cycle) at the inverting input terminal. Therefore, when the ramp signal increases to exceed the duty cycle voltage signal, the switching point of the auxiliary comparator 215 occurs.

[0019] The duty cycle voltage signal is sufficiently smaller than the threshold voltage signal, providing the desired delay between the switching points of the auxiliary comparator 215 and the main comparator 205. The faster the ramp signal frequency, the greater the difference between the voltage threshold and the duty cycle voltage. Conversely, as the ramp signal frequency decreases, the difference between the voltage threshold and the duty cycle voltage can decrease.

[0020] Before the main comparator 205 resets the SR latch 220, the internal clock signal sets the SR latch 220 so that the SR latch pulses the IDAC clock signal to the IDAC 125. When the main comparator 205 reaches its transition point and asserts the reset signal, the SR latch resets (discharges) the IDAC clock signal. To better understand the comparator system 200, in Figure 3 The diagram shows some of its operating waveforms. In the first cycle of the IDAC clock signal, the internal clock (clk) signal ( Figure 2 The internal clock signal is asserted, which causes the IDAC clock signal to be set at time t0. The internal clock signal also triggers the ramp signal generator 210 to ramp the signal from a default value (such as zero volts) at time t0. The ramp signal increases to exceed the duty cycle voltage, which causes the auxiliary comparator 215 to assert the enable signal at time t1. The ramp signal continues to increase until it reaches or exceeds the threshold voltage at time t2, which causes the main comparator 205 to pulse the reset signal. The pulse of the reset signal resets both the ramp signal and the enable signal (discharges them to their default values), and also resets the IDAC clock signal. These waveforms are repeated in the second cycle of the ramp signal starting at time t3 and in the third cycle of the ramp signal starting at time t4.

[0021] The pulse width of the enable signal is equal to the delay between the switching points of auxiliary comparator 215 and main comparator 205. This pulse width can also be expressed as the duty cycle, determined by the difference between the threshold voltage and the duty cycle voltage. If the ramp signal frequency increases, the ramp signal slope (the amount of ramp signal increase per given unit time) will increase accordingly. Figure 3 It can be seen that the difference between the threshold voltage and the duty cycle voltage should then be increased to maintain the desired duty cycle of the enable signal. Conversely, if the ramp signal frequency decreases, the difference between the threshold voltage and the duty cycle voltage can be decreased to maintain the desired duty cycle of the enable signal.

[0022] Referring again to comparator system 200, the auxiliary comparator 215 is conventional because it is both low-power and has a relatively large propagation delay and increased transistor noise. Conversely, the main comparator 205 is low-power but has a relatively small propagation delay and reduced transistor noise. Figure 4The diagram shows a circuit diagram of an example specific implementation of the main comparator 205 that provides these advantages. A current source (Ibias) that is always on the power supply side is coupled between the power node of the power supply voltage VDD and the sources of p-type metal-oxide-semiconductor (PMOS) transistors P1 and PMOS transistor P2. The drain of transistor P1 is coupled to the drain of n-type metal-oxide-semiconductor (NMOS) transistor M1. Similarly, the drain of transistor P2 is coupled to the drain of NMOS transistor M2. The sources of transistors M1 and M2 are coupled to ground through NMOS transistor M3.

[0023] The node for the ramp signal is coupled to the gates of transistors P1 and M1. Similarly, the node for the threshold voltage (Vth) is coupled to the gates of transistors P2 and M2. Inverter 305 inverts the drain voltages of transistors P1 and M1 to generate the comparator output signal (out). In comparator system 200, the comparator output signal from the master comparator 205 is used as a reset pulse to reset the SR latch 220. However, it should be understood that the master comparator 205 can be used in any system using a low-power and low-noise continuous-time comparator. Regarding the operation of the master comparator 205, it is assumed that the ramp signal has not yet risen to equal the duty cycle voltage (in Figure 2 Before time t1. Since the ramp signal will be significantly less than the threshold voltage, the bias current conducted by the always-on current source will primarily flow through transistors P2 and M2 compared to transistors P1 and M1. Therefore, the drain of transistor P1 will charge towards the supply voltage VDD, causing the comparator output signal to ground (binary zero in the binary high implementation). The drain voltages of transistors P2 and M2 will rise to substantially equal to the voltage Vb. The drains of transistors P2 and M2 are coupled to the gate of transistor M3. Therefore, the gate of transistor M3 is charged to voltage Vb to fully turn on transistor M3. Therefore, transistor M3 can also be referred to herein as a first self-biased transistor. Since transistor M3 is self-biased by voltage Vb, the bias current from the always-on current source is conducted substantially to ground through transistors P2 and M2 and transistor M3 before time t1.

[0024] The always-on current source is configured or set to a size that results in a relatively small bias current to save power. However, recall that the transistor noise of the comparator increases as the bias current decreases. Therefore, if the main comparator 205 only includes the always-on current source, the jitter in the output signal of the main comparator 205 may be undesirably large. To reduce propagation delay and transistor noise, the main comparator 205 includes a power-side boost current source (Iboost) that supplies a relatively large boost current. However, unlike the always-on current source, the boost current source is coupled to the power node via a switch S1 that closes only when the enable signal is asserted. Before time t1, switch S1 is open, preventing the boost current source from supplying boost current. From time t1 to time t2, switch S1 closes, allowing the boost current source to drive the boost current to the sources of transistors P1 and P2. Therefore, the sources of transistors P1 and P2 are coupled to the shared current source output node 405 of the always-on current source and the boost current source. In an alternative implementation, switch S1 can be grounded between the boost current source and the sources of transistors P1 and P2.

[0025] It should be noted that transistor M3 is relatively small and therefore may be overloaded due to the sudden conduction of both bias current and boost current. The sources of transistors M3 and M4 are therefore coupled to the drain of NMOS transistor M4, which is larger than transistor M3. The source of transistor M4 is coupled to ground via switch S2, which is configured to turn on upon assertion of an enable signal. In an alternative embodiment, switch S2 may instead be ground-coupled between the drain of transistor M4 and the sources of transistors M1 and M2. Before time t1, switch S2 is off, preventing transistor M4 from conducting any current. However, from time t1 to time t2, switch S2 turns on to allow transistor M4 to conduct. The gate of transistor M4 is coupled to the drains of transistors P2 and M2 to charge the gate of transistor M4 to the common-mode voltage Vb. Therefore, transistor M4 can also be referred to herein as a second self-biased transistor, as it is biased by the common-mode voltage Vb. From time t1 to time t2, transistors M4 and M3 conduct the sum of the bias current and boost current to ground. As the ramp signal rises above the threshold voltage, the drain voltage of transistor M1 drops below the switching point of inverter 305, causing the comparator output signal to be asserted. This assertion of the comparator output signal resets both the ramp signal and the enable signal. The reset of the enable signal opens switches S1 and S2, stopping the boost current from conducting to ground. The reset of the ramp signal resets the comparator output signal (discharges to ground), allowing another ramp signal cycle to repeat.

[0026] Transistors P1 and M1 can also be represented herein as a first pair of transistors coupled between the current source output node 405 and the drains of transistors M3 and M4. Similarly, transistors P2 and M2 can also be represented herein as a second pair of transistors coupled between the current source output node 405 and the drains of transistors M3 and M4.

[0027] The relatively short pulse of the boost current from time t1 to time t2 results in limited power consumption, while the comparator speed is advantageously increased before the switching point of the main comparator 205. The bias current is also relatively small to reduce power consumption, but to keep the voltage Vb at an appropriate level for accurate operation.

[0028] Now refer to Figure 5 The flowchart discusses the operation method of the low-noise and low-power comparator disclosed herein. This method includes an action 500 that periodically generates a ramp signal. Figure 2 The example shown is that the ramp generator 210 periodically generates a ramp signal, which is an example of operation 500. The method also includes operation 505, which conducts a bias current through the comparator throughout the entire cycle of the ramp signal. An example of operation 505 is that the bias current is generated by a constantly on current source Ibias in the main comparator 205. Furthermore, the method includes operation 510, which conducts a boost current through the comparator in response to a ramp signal greater than the duty cycle voltage. An example of operation 510 is that the boost current is conducted through the main comparator 205 when an enable signal is asserted. Finally, the method includes operation 515, which asserts the output signal of the comparator in response to a ramp signal greater than a threshold voltage greater than the duty cycle voltage. (See below for...) Figure 3 The assertion of the reset signal discussed is an example of action 515.

[0029] Low-power and low-noise comparators, such as the master comparator 205 disclosed herein, can be incorporated into a variety of electronic systems. For example, such as Figure 6 As shown, a cellular phone 600, a laptop computer 605, and a tablet PC 610 may each include a MEMS microphone that generates an audio signal, which is digitized by an analog-to-digital converter including a low-power and low-noise comparator according to the present disclosure. Other exemplary electronic systems such as music players, video players, communication devices, and personal computers may also be configured with a low-power and low-noise comparator constructed according to the present disclosure.

[0030] This disclosure will now be summarized by the following example clauses: Clause 1. A comparator system, the comparator system comprising: A ramp signal generator, the ramp signal generator being configured to periodically generate ramp signals; An auxiliary comparator is configured to assert an enable signal in response to the ramp signal being greater than the duty cycle voltage. A master comparator configured to assert a comparator output signal in response to a ramp signal being greater than a threshold voltage, the threshold voltage being greater than the duty cycle voltage, wherein the master comparator includes: A constantly on current source, configured to conduct bias current throughout the entire cycle of the ramp signal; and A boost current source, which is configured to conduct boost current only when the enable signal is asserted.

[0031] Clause 2. The comparator system according to Clause 1, wherein the main comparator further comprises: Power nodes for power supply voltage; and A first switch is configured to be coupled to the power node and configured to close only when the enable signal is asserted, wherein the always-on current source is coupled to the power node, and wherein the first switch is coupled between the power node and the boost current source.

[0032] Clause 3. The comparator system according to Clause 2, wherein the main comparator further comprises: A first self-biased transistor, the first self-biased transistor having a source coupled to ground; The first pair of transistors is connected in series between the output node of both the always-on current source and the boost current source and the drain of the first self-biased transistor; and A second pair of transistors is connected in series between the current source output node and the drain of the first self-biased transistor, wherein the gate of the first self-biased transistor is coupled to the node between the transistors in the second pair of transistors.

[0033] Clause 4. A comparator system according to any one of Clauses 2 to 3, wherein the main comparator further comprises: A second self-biased transistor has a drain coupled to the drain of the first self-biased transistor and a gate coupled to the node between the transistors in the second pair of transistors; and A second switch is coupled between the source of the second self-biased transistor and ground, wherein the second switch is configured to close only when the enable signal is asserted.

[0034] Clause 5. The comparator system according to any one of Clauses 2 to 4, wherein the first pair of transistors comprises: A first p-type metal-oxide-semiconductor (PMOS) transistor, the first p-type metal-oxide-semiconductor (PMOS) transistor having a source coupled to the output node of the current source; and The first n-type metal-oxide-semiconductor (NMOS) transistor has a drain coupled to the drain of the first PMOS transistor and a source coupled to the drain of the first self-biased transistor and the drain of the second self-biased transistor.

[0035] Clause 6. The comparator system according to any one of Clauses 4 to 5, wherein the second pair of transistors comprises: A second PMOS transistor, the second PMOS transistor having a source coupled to the output node of the current source; and The second NMOS transistor has a drain coupled to the drain of the second PMOS transistor and a source coupled to the drain of the first self-biased transistor and the drain of the second self-biased transistor.

[0036] Clause 7. The comparator system according to Clause 5, wherein both the gate of the first PMOS transistor and the gate of the first NMOS transistor are coupled to a node for the ramp signal.

[0037] Clause 8. The comparator system according to Clause 6, wherein both the gate of the second PMOS transistor and the gate of the second NMOS transistor are coupled to a node for the duty cycle voltage.

[0038] Clause 9. The comparator system according to Clause 5, wherein the main comparator further comprises: An inverter configured to invert the voltage at the drain of the first PMOS transistor to provide the comparator output signal.

[0039] Clause 10. The comparator system according to any one of Clauses 1 to 9, wherein the comparator system further comprises: A set-reset latch is configured to reset a clock signal to a current-to-analog converter in response to an assertion of the comparator output signal.

[0040] Clause 11. The comparator system according to Clause 10, wherein the current digital-to-analog converter is included in a Σ-Δ analog-to-digital converter.

[0041] Clause 12. A comparator system according to any one of Clauses 1 to 11, wherein the comparator system is included within an analog-to-digital converter configured to digitize an audio signal from a microelectromechanical system (MEMS) microphone.

[0042] Clause 13. A method for operating a comparator, the method comprising: Ramp signals are generated periodically; Bias current is conducted through the comparator throughout the entire cycle of the ramp signal; In response to the ramp signal being greater than the duty cycle voltage, a boost current is conducted through the comparator; and The output signal of the comparator is asserted in response to the ramp signal being greater than a threshold voltage, wherein the threshold voltage is greater than the duty cycle voltage.

[0043] Clause 14 The method described in Clause 13 further includes: The clock is reset to the current digital-to-analog converter in the Σ-Δ analog-to-digital converter in response to the assertion of the output signal of the comparator.

[0044] Clause 15. The method according to any one of Clauses 13 to 14, the method further comprising: In response to the ramp signal being greater than the threshold voltage, the conduction of the boost current through the comparator is stopped.

[0045] Clause 16. The method according to any one of Clauses 13 to 15, wherein the boost current is greater than the bias current.

[0046] Clause 17. A comparator comprising: Power nodes used for power supply voltage; A constantly connected current source, which is coupled to the power supply node; A first switch, the first switch being coupled to the power node; A boost current source, wherein the boost current source is coupled to the first switch; A first PMOS transistor, the first PMOS transistor having a source coupled to the always-on current source and the boost current source; A first NMOS transistor, the first NMOS transistor having a drain coupled to the drain of a first PMOS transistor, wherein the gate of the first PMOS transistor is coupled to the gate of the first NMOS transistor. A second PMOS transistor having a source coupled to the always-on current source and the boost current source; A second NMOS transistor, the second NMOS transistor having a drain coupled to the drain of a second PMOS transistor, wherein the gate of the second PMOS transistor is coupled to the gate of the second NMOS transistor; and The third NMOS transistor has a source coupled to ground, a gate coupled to the drain of the second NMOS transistor, and a drain coupled to the source of the first NMOS transistor and the source of the second NMOS transistor.

[0047] Clause 18. The comparator according to Clause 17, the comparator further comprising: An inverter configured to invert the voltage at the drain of the first PMOS transistor to provide a comparator output signal.

[0048] Clause 19. The comparator according to any one of Clauses 17 to 18, the comparator further comprising: A fourth NMOS transistor having a drain coupled to the source of the first NMOS transistor and the source of the second NMOS transistor, and a gate coupled to the drain of the second NMOS transistor; and The second switch is coupled between the source of the fourth NMOS transistor and ground.

[0049] Clause 20. The comparator according to Clause 19, wherein the size of the fourth NMOS transistor is greater than the size of the third NMOS transistor.

[0050] As those skilled in the art will understand to date and depending on the specific application at hand, many modifications, substitutions, and variations may be made to the materials, apparatus, configurations, and methods of using the device as defined by the appended claims, without departing from the scope of this disclosure. Therefore, the scope of this disclosure should not be limited to the specific embodiments illustrated and described herein (as they are merely examples), but should be fully equivalent to the appended claims and their functional equivalents.

Claims

1. A comparator system, the comparator system comprising: A ramp signal generator, the ramp signal generator being configured to periodically generate ramp signals; An auxiliary comparator is configured to assert an enable signal in response to the ramp signal being greater than the duty cycle voltage. A master comparator configured to assert a comparator output signal in response to a ramp signal being greater than a threshold voltage, the threshold voltage being greater than the duty cycle voltage, wherein the master comparator includes: A constantly on current source, configured to conduct bias current throughout the entire cycle of the ramp signal; and A boost current source, which is configured to conduct boost current only when the enable signal is asserted.

2. The comparator system according to claim 1, wherein the main comparator further comprises: Power nodes used for power supply voltage; and A first switch is configured to be coupled to the power node and configured to close only when the enable signal is asserted, wherein the always-on current source is coupled to the power node, and wherein the first switch is coupled between the power node and the boost current source.

3. The comparator system according to claim 2, wherein the main comparator further comprises: A first self-biased transistor, the first self-biased transistor having a source coupled to ground; The first pair of transistors is connected in series between the current source output node of both the always-on current source and the boost current source and the drain of the first self-biased transistor. and A second pair of transistors is connected in series between the current source output node and the drain of the first self-biased transistor, wherein the gate of the first self-biased transistor is coupled to the node between the transistors in the second pair of transistors.

4. The comparator system of claim 3, wherein the main comparator further comprises: The second self-biased transistor has a drain coupled to the drain of the first self-biased transistor and a gate coupled to the node between the transistors in the second pair of transistors. and A second switch is coupled between the source of the second self-biased transistor and ground, wherein the second switch is configured to close only when the enable signal is asserted.

5. The comparator system of claim 4, wherein the first pair of transistors comprises: A first p-type metal-oxide-semiconductor (PMOS) transistor, the first p-type metal-oxide-semiconductor (PMOS) transistor having a source coupled to the output node of the current source; and The first n-type metal-oxide-semiconductor (NMOS) transistor has a drain coupled to the drain of the first PMOS transistor and a source coupled to the drain of the first self-biased transistor and the drain of the second self-biased transistor.

6. The comparator system of claim 4, wherein the second pair of transistors comprises: A second PMOS transistor, the second PMOS transistor having a source coupled to the output node of the current source; and The second NMOS transistor has a drain coupled to the drain of the second PMOS transistor and a source coupled to the drain of the first self-biased transistor and the drain of the second self-biased transistor.

7. The comparator system of claim 5, wherein both the gate of the first PMOS transistor and the gate of the first NMOS transistor are coupled to a node for the ramp signal.

8. The comparator system of claim 6, wherein both the gate of the second PMOS transistor and the gate of the second NMOS transistor are coupled to a node for the duty cycle voltage.

9. The comparator system of claim 5, wherein the main comparator further comprises: An inverter configured to invert the voltage at the drain of the first PMOS transistor to provide the comparator output signal.

10. The comparator system according to claim 1, further comprising: A set-reset latch is configured to reset a clock signal to a current-to-analog converter in response to an assertion of the comparator output signal.

11. The comparator system of claim 10, wherein the current digital-to-analog converter is included in a Σ-Δ analog-to-digital converter.

12. The comparator system of claim 1, wherein the comparator system is included within a cellular phone.

13. A method for operating a comparator, the method comprising: Ramp signals are generated periodically; Bias current is conducted through the comparator throughout the entire cycle of the ramp signal; In response to the ramp signal being greater than the duty cycle voltage, a boost current is conducted through the comparator; and The output signal of the comparator is asserted in response to the ramp signal being greater than a threshold voltage, wherein the threshold voltage is greater than the duty cycle voltage.

14. The method according to claim 13, further comprising: The clock is reset to the current digital-to-analog converter in the Σ-Δ analog-to-digital converter in response to the assertion of the output signal of the comparator.

15. The method according to claim 13, further comprising: In response to the ramp signal being greater than the threshold voltage, the conduction of the boost current through the comparator is stopped.

16. The method of claim 13, wherein the boost current is greater than the bias current.

17. A comparator, the comparator comprising: Power nodes used for power supply voltage; A constantly connected current source, which is coupled to the power supply node; A first switch, the first switch being coupled to the power node; A boost current source, wherein the boost current source is coupled to the first switch; A first PMOS transistor, the first PMOS transistor having a source coupled to the always-on current source and the boost current source; A first NMOS transistor, the first NMOS transistor having a drain coupled to the drain of a first PMOS transistor, wherein the gate of the first PMOS transistor is coupled to the gate of the first NMOS transistor. A second PMOS transistor having a source coupled to the always-on current source and the boost current source; The second NMOS transistor has a drain coupled to the drain of the second PMOS transistor, wherein the gate of the second PMOS transistor is coupled to the gate of the second NMOS transistor. and The third NMOS transistor has a source coupled to ground, a gate coupled to the drain of the second NMOS transistor, and a drain coupled to the source of the first NMOS transistor and the source of the second NMOS transistor.

18. The comparator of claim 17, further comprising: An inverter configured to invert the voltage at the drain of the first PMOS transistor to provide a comparator output signal.

19. The comparator of claim 17, further comprising: A fourth NMOS transistor having a drain coupled to the source of the first NMOS transistor and the source of the second NMOS transistor, and having a gate coupled to the drain of the second NMOS transistor; and The second switch is coupled between the source of the fourth NMOS transistor and ground.

20. The comparator of claim 19, wherein the size of the fourth NMOS transistor is larger than the size of the third NMOS transistor.

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