Constant power active discharge of energy storage circuit

Abstract

In some examples, a circuit (200) includes a reference signal generator (204), a comparator (205), a one-shot circuit (210), and a gate driver (202). The reference signal generator has a first input terminal and a second input terminal and an output terminal, the first input terminal of the reference signal generator configured to receive a discharge time selection value, and the second input terminal of the reference signal generator configured to receive a stop voltage selection value. The comparator has a first input terminal and a second input terminal and an output terminal, the first input terminal of the comparator configured to receive a sensed voltage, and the second input terminal of the comparator coupled to the output terminal of the reference signal generator. The one-shot circuit has a first input terminal and a second input terminal and an output terminal, the first input terminal coupled to the output terminal of the comparator, and the second input terminal configured to receive a on-time value. The gate driver has an input terminal and an output terminal, the input terminal of the gate driver coupled to the output terminal of the one-shot circuit.

Description

Background Technology

[0001] Various electric systems may include energy storage circuits, such as capacitors. In some applications, these energy storage circuits may pose a risk to the user, for example, by holding a charge under certain operating conditions or holding a charge for a period of time exceeding a threshold amount under certain operating conditions. Summary of the Invention

[0002] In some examples, a circuit includes a reference signal generator, a comparator, a single-shot circuit, and a gate driver. The reference signal generator has a first input terminal, a second input terminal, and an output terminal. The first input terminal of the reference signal generator is configured to receive a discharge time selection value, and the second input terminal is configured to receive a stop voltage selection value. The comparator has a first input terminal, a second input terminal, and an output terminal. The first input terminal of the comparator is configured to receive a sensed voltage, and the second input terminal of the comparator is coupled to the output terminal of the reference signal generator. The single-shot circuit has a first input terminal, a second input terminal, and an output terminal. The first input terminal is coupled to the output terminal of the comparator, and the second input terminal is configured to receive an on-time value. The gate driver has an input terminal and an output terminal, and the input terminal of the gate driver is coupled to the output terminal of the single-shot circuit.

[0003] In some instances, a circuit is configured to receive a sensed voltage representing the voltage of an energy storage circuit. The circuit is also configured to compare the sensed voltage with a reference signal representing a discharge profile of the energy storage circuit. The circuit is further configured to control a gate driver to provide a control signal in response to the sensed voltage having a value greater than the reference signal. This control signal is configured to discharge the energy storage circuit for a constant on-time period, the constant on-time period being determined such that the power discharge rate of the energy storage circuit remains constant.

[0004] In some examples, a system includes a switch, a capacitor, a voltage sensing circuit, a high-side drive circuit, a first transistor, a low-side drive circuit, and a second transistor. The switch has a first terminal and a second terminal, the second terminal of which is coupled to a positive power supply terminal. The capacitor has a first terminal and a second terminal, the first terminal of which is coupled to the first terminal of the switch, and the second terminal of the capacitor is coupled to a ground terminal. The voltage sensing circuit has a first terminal, a second terminal, and an output terminal, the first terminal of which is coupled to the first terminal of the switch, and the second terminal of the voltage sensing circuit is coupled to the ground terminal. The high-side drive circuit has an input terminal and an output terminal. The first transistor has a first terminal, a second terminal, and a control terminal, the first terminal of which is coupled to the first terminal of the switch, and the control terminal of the first transistor is coupled to the output terminal of the high-side drive circuit. The low-side drive circuit has a first input terminal, a second input terminal, and an output terminal, the first input terminal of which is coupled to the output terminal of the voltage sensing circuit. The second transistor has a first terminal, a second terminal, and a control terminal. The first terminal of the second transistor is coupled to the second terminal of the first transistor, the second terminal of the second transistor is coupled to the ground terminal, and the control terminal of the second transistor is coupled to the output terminal of the low-side drive circuit. Attached Figure Description

[0005] Figure 1 Block diagrams of the system in various instances.

[0006] Figure 2 Block diagrams of the drive circuits in various examples.

[0007] Figure 3 Graphs of signal waveforms in various examples.

[0008] Figure 4 Graphs of signal waveforms in various examples.

[0009] Figure 5 Graphs of signal waveforms in various examples.

[0010] Figure 6 The flowcharts are for the methods in various instances. Detailed Implementation

[0011] As described above, various electric systems may include energy storage circuits, such as capacitors. Examples of such electric systems include electric vehicles, hybrid vehicles, electric subsystems of vehicles, etc. As used herein, a vehicle may include automobiles, trucks, boats, aircraft, helicopters, industrial (e.g., construction, farm, etc.) equipment, or any other suitable wheeled or tracked land, sea, or air vehicles. In some application environments, these energy storage circuits may pose a risk to the user, for example, by holding a charge under certain operating conditions or holding a charge for a period exceeding a threshold time under certain operating conditions. For example, a vehicle traction inverter system in a battery-powered or hybrid vehicle may include a DC link capacitor. The DC link capacitor can improve the stability of the DC voltage supplied to the load (e.g., the vehicle traction inverter system) by supplementing the power supplied by the battery or other power source to cope with intermittent or transient heavy load conditions imposed on the power supply by the vehicle traction inverter system. Even after the DC link capacitor is decoupled from the vehicle's power source (e.g., battery), the DC link capacitor can retain its charge and the voltage it generates. In some instances, voltages can reach 800 volts (V) or greater. DC link capacitor voltages can pose a risk to users in certain operating conditions, such as in the event of a vehicle collision, during vehicle maintenance, or other service. Therefore, safety regulations, rules, laws, standards, or industry practices may specify the duration and / or discharge rate of DC link capacitors. For example, the duration and / or discharge rate may specify that the voltage of the DC link capacitor should decrease (e.g., discharge) to below a threshold voltage within an permissible timeframe. In instances, this timeframe may be from about 1 to about 5 seconds. In some instances, the threshold voltage may be about 60 V, about 40 V, between about 60 V and about 40 V, or any other suitable level or range. Some methods of discharging DC link capacitors involve releasing the stored energy through a resistor. However, such methods can generate significant heat, may require relatively large resistors (e.g., in terms of physical size and / or resistance), or may be undesirable or unsuitable for certain application environments.

[0012] Examples of active discharge of an energy storage circuit are provided in this specification. In these examples, the energy storage circuit is a capacitor, such as a DC link capacitor. In some examples, active discharge provides a constant power discharge rate. This involves observing a smaller voltage change over time at high voltages and a larger voltage change over time at low voltages. A constant power discharge rate reduces the peak junction temperature of power switches (e.g., transistors) in the discharge critical path compared to a constant current discharge rate. In some examples, a voltage sensing circuit can provide a sensed signal indicating or otherwise representing the DC link voltage (e.g., the voltage of the DC link capacitor). In some examples, the voltage sensing circuit can be a voltage divider coupled in parallel with the DC link capacitor. The sensed signal can be compared to a reference signal. Based on this comparison, the DC link capacitor can be discharged. For example, the reference signal can be a reference waveform representing the discharge waveform of the DC link capacitor. In response to the sensed signal having a value greater than the reference signal and a clock signal having an asserted value, a gate driver drives a switch (e.g., a transistor) to discharge the DC link capacitor. In some instances, the gate driver drives the switch based on a pulse input signal that is deasserted after a programmed time interval. In this way, the discharge rate of the DC link capacitor is controlled. By controlling the discharge rate of the DC link capacitor, the thermal characteristics of the system (e.g., power switches, passive components, etc. in the discharge critical path) can be better controlled, thereby improving system performance and making the system suitable for implementation in a wider range of application environments. In some instances, to discharge the DC link capacitor, the switch (or switches) is configured to create a path to ground (e.g., a short circuit to ground) between the DC link capacitor and a ground terminal providing a ground voltage potential. The switch (or switches) can be controlled based on the control applied by the gate driver to create this path to ground.

[0013] By adjusting the control voltage (e.g., gate voltage) of the switch, multiple short-circuit events can be generated, thereby discharging the DC link capacitor in a controlled manner. Pulse frequency modulation (PFM) control is implemented by adjusting the control voltage based on a comparison between a sensed signal and a reference signal. For example, the frequency of short-circuit events increases as the DC link voltage decreases.

[0014] Figure 1This is a block diagram of system 100 in various examples. In these examples, system 100 includes a power supply 102 (e.g., a battery, battery array, battery cell, etc.), a switch 103, a high-side drive circuit 104, a transistor 106, a low-side drive circuit 108, a transistor 110, a high-side drive circuit 112, a transistor 114, a low-side drive circuit 116, a transistor 118, a high-side drive circuit 120, a transistor 122, a low-side drive circuit 124, a transistor 128, a capacitor 130, a voltage sensing circuit 131, and a motor 132. In some examples, capacitor 130 is a DC link capacitor. In some examples, motor 132 is a three-phase motor with phase A, phase B, and phase C terminals. High-side drive circuit 104, transistor 106, low-side drive circuit 108, and transistor 110 can form a first branch for driving the first phase of motor 132; high-side drive circuit 112, transistor 114, low-side drive circuit 116, and transistor 118 can form a second branch for driving the second phase of motor 132; and high-side drive circuit 120, transistor 122, low-side drive circuit 124, and transistor 128 can form a third branch for driving the third phase of motor 132. In some embodiments, system 100 also includes controller 134. In these embodiments, controller 134 controls the operation of other components of system 100 (e.g., high-side drive circuits 104, 112, 120, low-side drive circuits 108, 116, 124, and / or switch 103).

[0015] In the example architecture of system 100, power supply 102 has a positive terminal and a negative (or ground) terminal. Switch 103 has a first terminal and a second terminal, the second terminal of switch 103 being coupled to the positive terminal of power supply 102. Capacitor 130 has a first terminal and a second terminal, the first terminal of capacitor 130 being coupled to the first terminal of switch 103, and the second terminal of capacitor 130 being coupled to the ground terminal of power supply 102. Voltage sensing circuit 131 has an output terminal as well as a first terminal and a second terminal, the first terminal of voltage sensing circuit 131 being coupled to the first terminal of switch 103, and the second terminal of voltage sensing circuit 131 being coupled to the ground terminal of power supply 102. High-side drive circuit 104 has a first input terminal providing a low-voltage power supply (LV_BAT), a second input terminal coupled to controller 134, a third input terminal, and an output terminal, the low-voltage power supply being from power supply 102 or any other suitable source. Transistor 106 has a first terminal coupled to a first terminal of switch 103, a second terminal coupled to a third input terminal of high-side drive circuit 104, and a control terminal coupled to an output terminal of high-side drive circuit 104. Low-side drive circuit 108 has a first input terminal coupled to a positive terminal of power supply 102, a second input terminal coupled to controller 134, a third input terminal coupled to ground terminal of power supply 102, a fourth input terminal coupled to an output terminal of voltage sensing circuit 131, and an output terminal. Transistor 110 has a first terminal coupled to a second terminal of transistor 106, a second terminal coupled to ground terminal of power supply 102, and a control terminal coupled to an output terminal of low-side drive circuit 108. In this example, the second terminal of transistor 106 is coupled to phase A terminal of motor 132.

[0016] The high-side drive circuit 112 has a first input terminal providing LV_BAT, a second input terminal coupled to the controller 134, a third input terminal, and an output terminal. Transistor 114 has a first terminal coupled to the first terminal of switch 103, a second terminal coupled to the third input terminal of the high-side drive circuit 112, and a control terminal coupled to the output terminal of the high-side drive circuit 112. The low-side drive circuit 116 has a first input terminal coupled to the positive terminal of power supply 102, a second input terminal coupled to the controller 134, a third input terminal coupled to the ground terminal of power supply 102, a fourth input terminal coupled to the output terminal of voltage sensing circuit 131, and an output terminal. Transistor 118 has a first terminal coupled to the second terminal of transistor 114, a second terminal coupled to the ground terminal of power supply 102, and a control terminal coupled to the output terminal of the low-side drive circuit 116. In this example, the second terminal of transistor 114 is coupled to the phase B terminal of motor 132.

[0017] The high-side drive circuit 120 has a first input terminal providing LV_BAT, a second input terminal coupled to the controller 134, a third input terminal, and an output terminal. Transistor 122 has a first terminal coupled to the first terminal of switch 103, a second terminal coupled to the third input terminal of the high-side drive circuit 120, and a control terminal coupled to the output terminal of the high-side drive circuit 120. The low-side drive circuit 124 has a first input terminal coupled to the positive terminal of power supply 102, a second input terminal coupled to the controller 134, a third input terminal coupled to the ground terminal of power supply 102, a fourth input terminal coupled to the output terminal of voltage sensing circuit 131, and an output terminal. Transistor 126 has a first terminal coupled to the second terminal of transistor 122, a second terminal coupled to the ground terminal of power supply 102, and a control terminal coupled to the output terminal of the low-side drive circuit 124. In this example, the second terminal of transistor 122 is coupled to the phase C terminal of motor 132.

[0018] As described above, the first, second, and third branches are coupled in parallel with capacitor 130, and each branch can be controlled to discharge capacitor 130 individually or in combination with another branch. For clarity, the operation of discharging capacitor 130 in system 100 will be described with respect to the first branch, which includes high-side drive circuit 104, transistor 106, low-side drive circuit 108, and transistor 110. However, in other instances, the second or third branch may alternatively or additionally be controlled to discharge capacitor 130, and the description herein of the first branch discharging capacitor 130 is equally applicable to the second and / or third branches.

[0019] In an example of the operation of system 100, controller 134 controls high-side drive circuits 104, 112, 120, low-side drive circuits 108, 116, 124, and / or switch 103 to supply power from power source 102 to motor 132, thereby controlling or otherwise driving motor 132. In this example, control may be performed based on pulse-width modulated signals received from any suitable source (e.g., controller 134), the range of which is not limited herein. Therefore, controlling high-side drive circuits 104, 112, 120, low-side drive circuits 108, 116, 124, and / or switch 103 to supply power to motor 132 may be outside the scope of this specification, and its description is omitted herein.

[0020] In response to the opening of switch 103 (e.g., decoupling the high-side drive circuits 104, 112, 120 and the low-side drive circuits 108, 116, 124 from the positive terminal of power supply 102), controller 134 can control one or more of the high-side drive circuits 104, 112, 120 and the low-side drive circuits 108, 116, 124 to discharge capacitor 130. Discharging can be performed according to PFM such that capacitor 130 discharges at a substantially constant power rate, wherein the voltage of the capacitor varies with time, and the voltage variation increases as the capacitor voltage decreases.

[0021] For example, in response to an assertion by controller 134 of a safety state enable signal, switch 103 can be disconnected. The safety state enable signal can be asserted by controller 134 in response to any suitable event, such as a system 100 shutdown or cutoff event, system 100 entering maintenance or service mode, detection of a collision in system 100, detection of a fault or other abnormal condition in system 100, etc. Also in response to the assertion of the safety state enable signal, high-side drive circuitry 104 can control transistor 106 to remain in a conductive or on state.

[0022] In response to the opening of switch 103, controller 134 may assert an active discharge enable signal. In some instances, asserting the active discharge enable signal includes providing an active discharge enable signal with a logic 1 value (e.g., an active high signal). In other instances, asserting the active discharge enable signal includes providing an active discharge enable signal with a logic 0 value (e.g., an active low signal). In response to the assertion of the active discharge enable signal, low-side drive circuitry 108 may modulate a control signal provided at the control terminal of transistor 110. By modulating the control voltage, low-side drive circuitry 108 controls transistor 110 to be in alternating conductive and non-conductive states, thereby creating a short-circuit event between the first terminal of capacitor 130 and the ground terminal of power supply 102. During these short-circuit events while transistor 110 is conductive, a portion of the charge stored in capacitor 130 is released, thereby reducing the voltage of capacitor 130. In some instances, each conductive period of transistor 110 and therefore each short-circuit event is a constant on-time event. In this way, each discharge period may have approximately the same duration. However, the frequency of short-circuit events and therefore the frequency of discharge periods can increase as the voltage of capacitor 130 decreases. In this way, the low-side drive circuit 108 provides a control signal at the control terminal of transistor 110 based on PFM modulation.

[0023] In some instances, the low-side drive circuit 108 modulates a control signal based on a comparison of the sensed voltage (VSENSE) provided by the voltage sensing circuit 131 with a reference voltage. In other instances, the low-side drive circuit 108 modulates a control signal based on a discharge control signal received from any suitable source (e.g., controller 134), the range of which is not limited herein. In some instances, the voltage sensing circuit 131 includes or is implemented as a resistor-based voltage divider (or any other suitable architecture) such that the sensed voltage is proportional to the voltage of capacitor 130. The low-side drive circuit 108 may compare the sensed voltage with a reference voltage or a reference signal. In some instances, the reference signal is a waveform provided by a signal generator. The signal generator may generate the waveform based on a discharge time and a stop voltage, which may be received by the low-side drive circuit 108 from the controller 134, received by the low-side drive circuit 108 as an externally provided user input, retrieved by the low-side drive circuit 108 from a register or other storage device or location, or hard-coded into the low-side drive circuit 108. In response to a sensed voltage having a value greater than or equal to a reference voltage, the low-side drive circuit 108 may provide a control signal to the transistor 110, the control signal having a pulse asserted within a programmed time period (e.g., "on-time"). As described above, the pulse may be a high-level active pulse or a low-level active pulse, depending on the process technology of the transistor 110.

[0024] In some instances, the programmed time quantity may be received by the low-side drive circuit 108 from the controller 134, received by the low-side drive circuit 108 as an externally provided user input, retrieved by the low-side drive circuit 108 from a register or other storage device or location, or hard-coded into the low-side drive circuit 108. In some instances, the low-side drive circuit 108 may limit the modulation frequency of the control signal. In such instances, in response to a sensed voltage having a value greater than or equal to a reference voltage and a clock signal having an asserted value, the low-side drive circuit 108 may provide a control signal to the transistor 110, the control signal having pulses asserted within the programmed time quantity (e.g., "on-time"). In some instances, the clock signal may be provided by a clock generator based on the sensed voltage and a clock frequency limit value. The clock frequency limit value can be received by the low-side drive circuit 108 from the controller 134, received by the low-side drive circuit 108 as an externally provided user input, retrieved by the low-side drive circuit 108 from a register or other storage device or location, or hard-coded into the low-side drive circuit 108. In some instances, the average discharge current is proportional to the clock signal. At high voltages, a lower frequency clock signal is provided to maintain constant power discharge, as described herein. To mitigate excessive average discharge current during fault scenarios, the frequency of the clock signal can be scaled inversely to the sensed voltage.

[0025] In some instances, the low-side drive circuit 108 can monitor for the presence of a fault during the discharge process. For example, the low-side drive circuit 108 can compare the sensed voltage with a fault reference voltage that includes a reference voltage plus a fault offset value. The fault offset value can be received by the low-side drive circuit 108 from the controller 134, received by the low-side drive circuit 108 as an externally provided user input, retrieved by the low-side drive circuit 108 from a register or other storage device or location, or hard-coded into the low-side drive circuit 108. In response to the sensed voltage exceeding the fault reference value, the low-side drive circuit 108 can assert a fault signal. In response to the assertion of the fault signal, the low-side drive circuit 108 can disable the discharge of the capacitor 130. Disabling the discharge of the capacitor 130 by the low-side drive circuit 108 in response to the assertion of the fault signal can be performed according to any suitable process and via any additional support components (not shown), the scope of which is not limited herein. In some instances, the low-side drive circuit 108 may provide a fault signal to the controller 134 for transmission to any or more of the high-side drive circuits 104, 112, 120, low-side drive circuits 116, 124, and / or any other suitable means. In other instances, the low-side drive circuit 108 itself may provide a fault signal to any or more of the high-side drive circuits 104, 112, 120, low-side drive circuits 116, 124, and / or any other suitable means.

[0026] In some instances, in response to the low-side drive circuit 108 determining and reporting a fault and thus disabling the discharge of capacitor 130 by the low-side drive circuit 108, one or more of the low-side drive circuits 116, 124 may attempt to discharge capacitor 130 in a manner substantially similar to that described above with respect to low-side drive circuit 108. In some instances, in response to the low-side drive circuit 108 determining and reporting a fault, a notification may be provided to a user or another circuit, component, or device. The notification may take any form, such as a visual notification, an auditory notification, a text notification, a notification transmitted via a network interface, an analog or digital signal transmitted between electrical components, etc.

[0027] Figure 2This is a schematic diagram of the drive circuit 200 in various examples. In various examples, the drive circuit 200 is suitable for implementation as any or more of low-side drive circuits 108, 116, and 124. In examples, the drive circuit 200 includes a gate driver 202, a reference signal generator 204, a comparator 205, a clock generator 206, an AND logic circuit 208, a single-shot circuit 210, and a comparator 212. The reference signal generator 204 and the clock generator 206 can each be implemented according to any suitable architecture, the range of which is not limited herein. In some examples, the reference signal generator 204 is implemented as a lookup table that provides the time spent at each voltage level. For example, across the time range t0 to t1, the reference signal generator 204 provides a voltage having a value that decreases from V1 and increases over time from t0 to t1, decreasing to V0 in multiple discrete voltage levels. In some instances, clock generator 206 is implemented using a combination of a lookup table and a PWM generator, the lookup table providing an increasing pulse width modulation (PWM) frequency as the voltage decreases, and the PWM generator generating a PWM signal at the PWM frequency for each voltage level. In some instances, single-electrode circuit 210 may be implemented as a multivibrator, such as a monostable multivibrator. In other instances, single-electrode circuit 210 may be implemented according to any suitable architecture, or as any suitable circuit capable of generating or providing a constant on-time pulse signal in response to a received signal. Gate driver 202 may be implemented according to any suitable architecture, the range of which is not limited herein.

[0028] In one example, the reference signal generator 204 has an output terminal and a first input terminal configured to receive a safety state enable signal, a second input terminal configured to receive an active discharge enable signal, a third input terminal configured to receive a discharge time selection value, and a fourth input terminal configured to receive a stop voltage selection value. In various examples, any one or more of the first to fourth input terminals of the reference signal generator 204 may be coupled to a corresponding output terminal of the controller 134 or any other suitable signal source, as described elsewhere herein. The comparator 205 has a first input terminal configured to receive a sensed voltage, a second input terminal coupled to the output terminal of the reference signal generator 204, and an output terminal. In some examples, the first input terminal of the comparator 205 is coupled to the output terminal of the voltage sensing circuit 131 to receive the sensed voltage from the voltage sensing circuit 131. In some examples, the drive circuit 200 does not limit the frequency of the PFM control of the transistor 110 implemented by the drive circuit. In such examples, the output terminal of the comparator 205 may be coupled to an input terminal of the single-shot circuit 210.

[0029] In other examples, clock generator 206 has a first input terminal configured to receive a sensed voltage (e.g., coupled to the output terminal of voltage sensing circuit 131 to receive the sensed voltage from voltage sensing circuit 131), a second input terminal configured to receive a clock frequency limit value, and an output terminal. In some examples, the second input terminal of clock generator 206 may be coupled to the output terminal of controller 134 or any other suitable signal source, as described elsewhere herein. AND logic circuit 208 has a first input terminal coupled to the output terminal of comparator 205, a second input terminal coupled to the output terminal of clock generator 206, and an output terminal. Single-shot circuit 210 has a first input terminal coupled to the output terminal of AND logic circuit 208, a second input terminal configured to receive an on-time value, and an output terminal coupled to gate driver 202. In some examples, the second input terminal of single-shot circuit 210 may be coupled to the output terminal of controller 134 or any other suitable signal source, as described elsewhere herein.

[0030] This document describes the operation of drive circuit 200 in the case where both the safety state enable signal and the active discharge enable signal have asserted values, as described above. In such an example of the operation of drive circuit 200, reference signal generator 204 provides a reference signal based on a discharge time selection value (e.g., specifying t1) and a stop voltage selection value (e.g., specifying V0), which specify the discharge time selection value for discharging capacitor 130 and the voltage discharged to by capacitor 130 during the discharge time. Comparator 205 receives a sensed voltage representing the voltage of capacitor 130 from voltage sensing circuit 131 and a reference signal from reference signal generator 204. In this example, the reference signal simulates the voltage waveform of a capacitor discharging at a constant power. In response to a sensed voltage having a value greater than the reference signal, comparator 205 provides a comparison result with a logic 1 value. In response to a sensed voltage not having a value greater than the reference signal, comparator 205 provides a comparison result with a logic 0 value.

[0031] Clock generator 206 provides a clock signal (CLOCK) based on a clock frequency limit value, which specifies the highest frequency of the control signal used to control transistor 110. CLOCK can vary from a first frequency f0 to a second frequency f1 as the sensed voltage changes. In response to a comparison result having a logic 1 value and the clock signal provided by clock generator 206 having a logic 1 value, AND logic circuit 208 provides a logic result with a logic 1 value. In response to a comparison result having a logic 0 value or the clock signal provided by clock generator 206 having a logic 0 value, AND logic circuit 208 provides a logic result with a logic 0 value. In response to a logic result having a logic 1 value, single-pole circuit 210 provides a signal pulse to gate driver 202. The signal pulse can have a pulse width specified according to the on-time value received by single-pole circuit 210.

[0032] In response to a signal pulse provided by single-transmitter circuit 210 having an asserted value, gate driver 202 provides a control signal to transistor 110 to conduct transistor 110. The conducting transistor 110 then generates a short-circuit event from capacitor 130 through transistor 106 and transistor 110 to ground (e.g., the ground terminal of power supply 102) to partially discharge capacitor 130. This operation can be repeated until the sensed voltage drops to approximately equal to or less than the stop voltage selection value.

[0033] As described above, in some instances, the drive circuit 200 includes fault detection, at least in part, implemented by comparator 212. For example, a reference signal is added to a fault offset value to form a fault reference signal. Although Figure 2 A discrete summing component is included to add the reference signal and the fault offset value, but the summation can alternatively be inherent and implemented by coupling two analog signal lines together. Comparator 212 receives the sensed voltage and the fault reference signal. In response to the sensed voltage having a value greater than the fault reference signal, comparator 205 provides a comparison result with a logic 1 value. In response to the sensed voltage not having a value greater than the fault reference signal, comparator 205 provides a comparison result with a logic 0 value. In response to the fault signal having a logic 0 value, drive circuit 200 determines that there is no fault condition associated with the discharge of capacitor 130. In response to the fault signal having a logic 1 value, drive circuit 200 determines that there is a fault condition associated with the discharge of capacitor 130. In response to determining that a fault condition exists, drive circuit 200 may stop discharging capacitor 130 or attempt to discharge the capacitor. In various instances, in response to other events, such as determining that the temperature of transistor 110 or any other component of drive circuit 200 or system 100 exceeds a threshold, drive circuit 200 may stop discharging capacitor 130 or attempt to discharge the capacitor.

[0034] Figure 3 Figure 300 shows signal waveforms in various examples. In one example, the signal in Figure 300 may be provided in a system such as System 100. In another example, Figure 300 includes a signal V representing the gate-to-source voltage of transistor 110. GS The signal I represents the drain current of transistor 110. DRAIN The signal V represents the voltage across capacitor 130. DC_LINK and the signal E representing the amount of energy released from capacitor 130 DIS As shown in Figure 300, in response to V GS and I DRAIN The increase of V DC_LINK The value decreases by ΔV, and E DIS Increase. As further shown in Figure 300, based on the pulse signal provided by the single-shot circuit 210, the conduction time of transistor 110 is t. on In this example, the maximum voltage of the control signal supplied to transistor 110 can be selected to control the peak drain current (Id) of transistor 110. PEAK ), so as to be compatible with t on Together, they control the amount of energy (EPP) released from capacitor 130 for each signal pulse provided to single-transmitter circuit 210.

[0035] Figure 4 Figure 400 shows signal waveforms in various examples. In one example, the signals in Figure 400 may be provided in a system such as System 100. In another example, Figure 400 includes the signal AD_EN, representing an active signal discharge enable signal, and the signal V, representing the maximum value of a control signal. LDO V GS The signal envelope, the signal representing the control signal frequency (Freq), I DRAIN V DC_LINK and E DIS The signal envelope. As shown in Figure 400, in response to the assertion of AD_EN, at setup time t AD_SU During this period, V LDO The value is reduced in order to limit the I of transistor 110. PEAK As described above. Upon completion of the setup time, the drive circuit 200 controls transistor 110 according to the PFM, as described above, to discharge capacitor 130. When the drive circuit 200 controls transistor 110 to discharge capacitor 130, V GS and I DRAIN The value increases, such as V. GS and I DRAINThe signal envelope is shown. As shown in the signal envelope of Freq, the pulse frequency of the control signal of the control circuit 200 to control transistor 110 is dynamically increased to provide a roughly constant power discharge, such as when V DC_LINK The value of E decreases approximately linearly. DIS As shown. Figure 4 Furthermore, the active discharge of capacitor 130 can be sustained for an active discharge time (t). AD ), until V DC_LINK It has been reduced to approximately equal to the stop voltage selection value. Capacitor 130 can be used at t AD After it ends, it continues to discharge passively.

[0036] Figure 5 Figure 500 shows signal waveforms in various examples. In one example, the signal in Figure 500 may be provided in a system such as System 100. In another example, Figure 500 includes the signal of Figure 400 and a fault reference signal V. REF As described above. As shown in Figure 500, in response to the assertion of AD_EN, at setup time t AD_SU During this period, V LDO The value is reduced in order to limit the I of transistor 110. PEAK As described above. Upon completion of the setup time, the drive circuit 200 controls transistor 110 according to the PFM, as described above, to discharge capacitor 130. When the drive circuit 200 controls transistor 110 to discharge capacitor 130, V GS and I DRAIN The value increases, such as V. GS and I DRAIN The signal envelope is shown. As shown in the signal envelope of Freq, the pulse frequency of the control signal of the control transistor 110 controlled by the drive circuit 200 dynamically increases to provide a discharge of approximately constant power. However, at time t1, VSENSE and V REF The difference between the values ​​exceeds the offset value, as described above. This is in response to VSENSE and V. REF The difference between the values ​​exceeds the offset value (in Figure 5 The fault offset level (shown in the diagram) asserts or provides a fault signal (FLT) with a logic 0 value. In response to the assertion of the fault signal, active discharge of capacitor 130 by low-side drive circuit 108 (or more generally, drive circuit 200, as described above) can be disabled. In some instances, the drive circuit that disables active discharge may retry active discharge after a programmed amount of time, or another drive circuit (e.g., one or both of low-side drive circuits 116, 124 when active discharge is disabled for low-side drive circuit 108) may attempt to actively discharge capacitor 130.

[0037] Figure 6 Flowcharts are provided for various instances of method 600. In these instances, method 600 represents at least some operations performed by a drive circuit (e.g., drive circuit 200). For example, method 600 may represent at least some operations performed by drive circuit 200, implemented as low-side drive circuits 108, 116, 124, as described above herein. In at least some instances, method 600 is implemented to discharge a capacitor (e.g., capacitor 130) via a series of short-circuit events. In some instances, the discharge is performed according to a PFM to provide a substantially constant or linear power discharge rate.

[0038] At operation 602, a sensed voltage is received. In some instances, the sensed voltage is received from a voltage sensing circuit (e.g., a voltage divider). The sensed voltage may represent, be proportional to, or otherwise indicate the voltage value of a capacitor (e.g., a DC link capacitor).

[0039] At operation 604, the sensed voltage is compared with a reference voltage to provide a comparison result. In some instances, the reference voltage is a reference signal waveform indicating a discharge curve of the capacitor. In some instances, the reference voltage can be determined at a specific time point based on a discharge time selection value and a stop voltage selection value, which can be obtained from any suitable source.

[0040] At operation 606, a pulse signal is provided in response to the comparison result having an asserted value and the clock signal having an asserted value. In some instances, the clock signal is provided based on a clock frequency limit value that limits the frequency of the pulse signal. The pulse signal may, for example, be provided by a single-shot circuit with a constant on-time.

[0041] At operation 608, the control transistor is made to conduct during the conduction time according to the pulse signal, so as to partially discharge the capacitor. In some instances, the control transistor becoming conductive will produce a short-circuit event, during which energy is released from the capacitor, thereby reducing the voltage of the capacitor (and thus reducing the sensed voltage).

[0042] In this specification, the term "coupled" may encompass a connection, communication, or signal path that achieves a functional relationship consistent with this specification. For example, if device A generates a signal to control device B to perform an action, then: (a) in a first instance, device A is coupled to device B via a direct connection; or (b) in a second instance, device A is coupled to device B via an intermediate component C, provided that the intermediate component C does not alter the functional relationship between device A and device B, such that device B is controlled by device A via a control signal generated by device A.

[0043] A device “configured” to perform a task or function may be configured (e.g., programmed and / or hardwired) to perform the function during manufacturing by the manufacturer, and / or may be configured (or reconfigured) by the user after manufacturing to perform the function and / or other additional or alternative functions. Configuration may be achieved through firmware and / or software programming of the device, through the construction and / or layout of the device’s hardware components and interconnects, or a combination thereof.

[0044] The circuits or devices described herein that include certain components may alternatively be coupled to those components used to form the described circuit system or device. For example, a structure described as including one or more semiconductor elements (e.g., transistors), one or more passive elements (e.g., resistors, capacitors, and / or inductors), and / or one or more sources (e.g., voltage sources and / or current sources) may alternatively include only semiconductor elements within a single physical device (e.g., a semiconductor die and / or integrated circuit (IC) package) and may be coupled to at least some of the passive elements and / or sources to form the described structure, for example, during or after manufacturing by an end user and / or a third party.

[0045] While some components may be described herein as belonging to a particular process technology, these components may be interchangeable with components from other process technologies. The circuits described herein can be reconfigured to include the replaced components, thereby providing functionality at least partially similar to that available prior to the component replacement. Unless otherwise stated, components shown as resistors generally represent any one or more elements coupled in series and / or parallel to provide the impedance represented by the resistor shown. For example, a resistor or capacitor shown and described herein as a single component may alternatively be multiple resistors or capacitors coupled in parallel between the same nodes. For example, a resistor or capacitor shown and described herein as a single component may alternatively be multiple resistors or capacitors coupled in series between the same two nodes as the single resistor or capacitor.

[0046] The use of the phrase "ground voltage potential" in the foregoing description includes chassis grounding, ground wire grounding, floating grounding, virtual grounding, digital grounding, common grounding, and / or any other form of grounding connection applicable to or suitable for the teachings of this specification. In this specification, unless otherwise stated, "about," "approximately," or "generally" preceding a parameter means within + / - 10% of said parameter. Modifications may be made to the described examples, and other examples may exist within the scope of the claims.

[0047] As used herein, the terms “terminal,” “node,” “interconnect,” “pin,” and “lead” are used interchangeably. Unless specifically stated otherwise, these terms are generally used to refer to interconnections or the ends of device elements, circuit elements, integrated circuits, devices, or semiconductor components. Additionally, a voltage rail, or more simply a “rail,” may also be referred to as a voltage terminal and may generally mean a common node or a set of coupled nodes at the same potential in a circuit.

Claims

1. A circuit comprising: A reference signal generator having a first input terminal, a second input terminal, and an output terminal, wherein the first input terminal of the reference signal generator is configured to receive a discharge time selection value, and the second input terminal of the reference signal generator is configured to receive a stop voltage selection value; A comparator having a first input terminal, a second input terminal, and an output terminal, wherein the first input terminal of the comparator is configured to receive a sensed voltage, and the second input terminal of the comparator is coupled to the output terminal of the reference signal generator; A single-transmitter circuit having a first input terminal, a second input terminal, and an output terminal, wherein the first input terminal is coupled to the output terminal of the comparator, and the second input terminal is configured to receive an on-time value; as well as A gate driver having an input terminal and an output terminal, the input terminal of the gate driver being coupled to the output terminal of the single-shot circuit.

2. The circuit according to claim 1, further comprising: An AND logic circuit having a first input terminal, a second input terminal, and an output terminal, wherein the first input terminal of the AND logic circuit is coupled to the output terminal of the comparator, and the output terminal of the AND logic circuit is coupled to the first input terminal of the single-shot circuit; as well as A clock generator having an output terminal coupled to the second input terminal of the AND logic circuit.

3. The circuit of claim 1, further comprising a second comparator having a first input, a second input, and an output terminal, the first input terminal of the second comparator being coupled to the first input terminal of the comparator, the second input terminal being configured to receive a fault reference signal formed by adding a fault offset level value to a reference signal provided by the reference signal generator, and the output terminal of the second comparator being coupled to the second input terminal of the gate driver.

4. The circuit of claim 1, further comprising a voltage sensing circuit having a first terminal, a second terminal, and an output terminal, the second terminal of the voltage sensing circuit being coupled to a ground terminal, and the output terminal of the voltage sensing circuit being coupled to the first input terminal of the comparator.

5. The circuit of claim 4, wherein the voltage sensing circuit includes a voltage divider having an output coupled to the first input terminal of the comparator.

6. The circuit of claim 4, further comprising a capacitor having a first terminal and a second terminal, the first terminal of the capacitor being coupled to the first terminal of the voltage sensing circuit, and the second terminal of the capacitor being coupled to the ground terminal.

7. The circuit of claim 4, further comprising a transistor having a first terminal and a second terminal and a control terminal, the first terminal of the transistor being coupled to the first terminal of the voltage sensing circuit, the second terminal of the transistor being coupled to the ground terminal, and the control terminal of the transistor being coupled to the output terminal of the gate driver.

8. A circuit configured as follows: Receive the sensed voltage representing the voltage of the energy storage circuit; The sensed voltage is compared with a reference signal representing the discharge curve of the energy storage circuit; and In response to the sensed voltage having a value greater than the reference signal, a gate driver is controlled to provide a control signal configured to discharge the energy storage circuit for a constant on-time period, the constant on-time period being determined such that the power discharge rate of the energy storage circuit remains constant.

9. The circuit of claim 8, wherein the control signal is a pulse frequency modulation (PFM) signal having a frequency determined to keep the power discharge rate of the energy storage circuit constant.

10. The circuit of claim 8, wherein the circuit is configured to control the gate driver to provide the control signal in response to the sensed voltage having a value greater than the reference signal and in response to a clock signal having an asserted value, wherein the clock signal limits the frequency of the control signal.

11. The circuit of claim 8, wherein the circuit is configured to compare the sensed voltage with a fault reference signal and, in response to the sensed voltage exceeding the fault reference signal, provide a fault signal indicating that a fault related to the discharge of the energy storage circuit has occurred.

12. The circuit of claim 8, wherein the circuit is configured to provide the control signal at the control terminal of the transistor to make the transistor conductive, thereby creating a short circuit between the energy storage circuit and the ground terminal.

13. The circuit of claim 12, wherein the energy storage circuit is a DC link capacitor of an electric vehicle power system.

14. The circuit of claim 8, wherein the circuit is configured to determine the discharge curve of the energy storage circuit based on a discharge time selection value and a stop voltage selection value, such that the energy storage circuit discharges to a voltage less than or equal to the stop voltage selection value within a time period specified by the discharge time selection value.

15. A system comprising: A switch having a first terminal and a second terminal, the second terminal of the switch being coupled to a positive power supply terminal; A capacitor having a first terminal and a second terminal, the first terminal of the capacitor being coupled to the first terminal of the switch, and the second terminal of the capacitor being coupled to a ground terminal; A voltage sensing circuit having a first terminal, a second terminal, and an output terminal, wherein the first terminal of the voltage sensing circuit is coupled to the first terminal of the switch, and the second terminal of the voltage sensing circuit is coupled to the ground terminal; A high-side drive circuit, which has input terminals and output terminals; A first transistor has a first terminal, a second terminal, and a control terminal, the first terminal of the first transistor being coupled to the first terminal of the switch, and the control terminal of the first transistor being coupled to the output terminal of the high-side drive circuit. A low-side driving circuit having a first input terminal, a second input terminal, and an output terminal, wherein the first input terminal of the low-side driving circuit is coupled to the output terminal of the voltage sensing circuit; as well as The second transistor has a first terminal, a second terminal, and a control terminal. The first terminal of the second transistor is coupled to the second terminal of the first transistor, the second terminal of the second transistor is coupled to the ground terminal, and the control terminal of the second transistor is coupled to the output terminal of the low-side drive circuit.

16. The system of claim 15, wherein, In response to receiving a security state enable signal with an asserted value at the input terminal of the high-side drive circuit, the high-side drive circuit is configured to control the first transistor to remain in a conductive state.

17. The system of claim 15, wherein, In response to receiving an active discharge enable signal with an asserted value at the second input terminal of the low-side drive circuit, the low-side drive circuit is configured to discharge the capacitor by modulating a control signal provided at the control terminal of the second transistor according to pulse frequency modulation (PFM).

18. The system of claim 17, wherein the low-side drive circuit is configured to discharge the capacitor at a constant power discharge rate by generating a series of short-circuit events between the capacitor and a ground voltage potential, the short-circuit events having a constant on-time.

19. The system of claim 17, wherein the low-side drive circuit is configured to: The sensed voltage is received from the voltage sensing circuit, the sensed voltage representing the voltage of the capacitor; and In response to the sensed voltage exceeding the value of a reference signal, a signal pulse is provided to control the second transistor to conduct within a constant on-time period.

20. The system of claim 17, wherein the low-side drive circuit is configured to: The sensed voltage is received from the voltage sensing circuit, the sensed voltage representing the voltage of the capacitor; and In response to the sensed voltage exceeding the value of the reference signal and the clock signal having an asserted value, a signal pulse is provided to control the second transistor to conduct during a constant on-time period.

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