Transmitter implemented with inverter buffers

Abstract

Certain aspects of this disclosure relate to transmitters implemented with inverter buffers and techniques for wireless transmission using such transmitters. An example transmitter typically includes: an upconverter circuit including one or more inputs coupled to one or more transmission chains of the transmitter; an inverter buffer including an input coupled to a first output of the upconverter circuit; and at least one amplifier coupled to the first output of the inverter buffer.

Description

Cross-references to related applications

[0001] This application claims priority to U.S. Patent Application No. 18 / 418,484, filed January 22, 2024, which is incorporated herein by reference. Technical Field

[0002] Certain aspects of this disclosure generally relate to electronic circuits, and more specifically to transmitters implemented using inverter buffers. Background Technology

[0003] Wireless communication devices are widely deployed to provide a variety of communication services, such as telephone, video, data, messaging, broadcasting, and so on. These wireless communication devices can transmit and / or receive radio frequency (RF) signals via any of a variety of suitable radio access technologies (RATs), including but not limited to 5G New Radio (NR), LTE, CDMA, TDMA, WCDMA, GSM, GSM, Bluetooth, Bluetooth Low Energy (BLE), ZigBee, WLAN RATs (e.g., WiFi), etc.

[0004] A wireless communication network may include multiple base stations capable of supporting communication with multiple mobile stations. A mobile station (MS) may communicate with a base station (BS) via downlink and uplink. A downlink (or forward link) is the communication link from the base station to the mobile station, while an uplink (or reverse link) is the communication link from the mobile station to the base station. The base station may transmit data and control information to the mobile station on the downlink and / or receive data and control information from the mobile station on the uplink. The base station and / or the mobile station may include one or more transmitters and receivers. Summary of the Invention

[0005] The systems, methods, and apparatuses of this disclosure each have several aspects, none of which are solely responsible for their desired properties. Without limiting the scope of this disclosure as set forth in the following claims, some features will now be briefly discussed. Upon consideration of this discussion, and particularly after reading the section entitled "Detailed Description," one will understand how the features of this disclosure provide advantages including reduced power consumption and area consumption, and facilitate operation at higher frequencies.

[0006] Some aspects of this disclosure relate to a transmitter. The transmitter typically includes: an upconverter circuit including one or more inputs coupled to one or more transmit chains of the transmitter; an inverter buffer including an input coupled to a first output of the upconverter circuit; and at least one amplifier coupled to the first output of the inverter buffer.

[0007] Some aspects of this disclosure relate to a method for wireless communication. The method typically includes: generating an up-converted signal using an up-converter circuit of a transmitter; generating a buffered signal based on the up-converted signal using an inverter buffer; generating an amplified signal based on the buffered signal via at least one amplifier of the transmitter; and performing signal transmission using the amplified signal.

[0008] Some aspects of this disclosure relate to a wireless device. The wireless device typically includes: an antenna and a transmitter coupled to the antenna and including: an upconverter circuit including one or more inputs to one or more transmission chains coupled to the transmitter; an inverter buffer including an input coupled to a first output of the upconverter circuit; and a first amplifier coupled to the first output of the inverter buffer and including an output coupled to the antenna.

[0009] To achieve the foregoing and related objectives, one or more aspects include the features fully described below and specifically pointed out in the claims. The following description and drawings illustrate some exemplary features of one or more aspects in detail. However, these features indicate only some of the various ways in which the principles of the various aspects may be employed, and this description is intended to include all such aspects and their equivalents. Attached Figure Description

[0010] To gain a more detailed understanding of the foregoing features of this disclosure, a more specific description, which has been briefly summarized above, can be obtained by referring to various aspects, some of which are illustrated in the accompanying drawings. However, it should be noted that the drawings illustrate only certain typical aspects of this disclosure and are therefore not to be construed as limiting its scope, as other equally valid aspects may be acknowledged in this description.

[0011] Figure 1 This is a diagram illustrating an example wireless communication network in which various aspects of the present disclosure can be practiced.

[0012] Figure 2 It is a block diagram conceptually illustrating the design of an example base station (BS) and user equipment (UE) in which various aspects of this disclosure can be practiced.

[0013] Figure 3This is a block diagram of an example radio frequency (RF) transceiver in which various aspects of this disclosure can be practiced.

[0014] Figure 4 An example transmitter according to certain aspects of this disclosure is illustrated.

[0015] Figure 5 Example circuits for implementing an inverter buffer according to certain aspects of this disclosure are illustrated.

[0016] Figure 6 This is a flowchart illustrating example operations for wireless communication according to certain aspects of this disclosure.

[0017] For ease of understanding, the same reference numerals have been used where possible to denote common elements in the figures. It is conceivable that elements disclosed in one aspect may be usefully applied to other aspects without specific description. Detailed Implementation

[0018] Some aspects of this disclosure relate to a transmitter designed to achieve lower current and area consumption while maintaining performance across a range of process / temperature / power variations. The transmitter may be designed to support a wide frequency range and share at least one transmit chain for different operating modes (e.g., WiFi operating at 2.4 GHz (2G) and 5 GHz (5G)), but some aspects of this disclosure are applicable to transmitters that do not share between operating modes. Due to the low-power and low-area-consumption design of the transmitter, one or more components of the transmit chain (e.g., digital-to-analog converter (DAC), baseband filter (BBF), and / or passive mixer) may not be able to drive the driver amplifier (DA) to operate at output power levels that enable operation at higher frequencies. Some aspects of this disclosure address the use of an inverter buffer (e.g., coupled to the output of the passive mixer) to provide sufficient power to one or more PAs, thereby contributing to supporting higher frequencies with a lower power and area-consumption design.

[0019] Various aspects of this disclosure are described more fully below with reference to the accompanying drawings. However, this disclosure may be embodied in many different forms and should not be construed as limited to any particular structure or function presented throughout this disclosure. Rather, these aspects are provided so that this disclosure will be comprehensive and complete, and will fully convey the scope of this disclosure to those skilled in the art. Based on the teachings herein, those skilled in the art will understand that the scope of this disclosure is intended to cover any aspect of the disclosure herein, whether implemented independently or in combination with any other aspect of this disclosure. For example, any number of aspects set forth herein may be used to implement an apparatus or method of practice. Furthermore, the scope of this disclosure is intended to cover such apparatus or methods implemented using structures, functions, or structures and functions other than or different from the various aspects of the disclosure set forth herein. It should be understood that any aspect of the disclosure herein may be embodied by one or more elements of the claims.

[0020] The word “exemplary” is used in this document to mean “serving as an example, instance, or illustration.” Any aspect described as “exemplary” in this document is not necessarily to be construed as preferred or superior to other aspects.

[0021] As used in this article, the term "connected with" in various tenses of the verb "connect" can refer to an element. A Directly connected to the component B Or other components can be connected to the component. A With components B Between (i.e., elements) A With components B Indirect connection). In the context of electronic components, the term "connected to..." may also be used herein to refer to leads, traces, or other conductive materials used to connect components. A and components B Electrical connections (and any components that are electrically connected between them). Example wireless system

[0022] Figure 1Example wireless communication network 100 is illustrated in which various aspects of this disclosure can be practiced. For example, wireless communication network 100 may be a new radio (NR) system (e.g., a fifth-generation (5G) NR network), an evolved universal terrestrial radio access (E-UTRA) system (e.g., a fourth-generation (4G) network), a universal mobile telecommunications system (UMTS) (e.g., a second-generation / third-generation (2G / 3G) network), or a code division multiple access (CDMA) system (e.g., a 2G / 3G network), or may be configured to communicate according to IEEE standards such as one or more standards in the 802.11 standard.

[0023] like Figure 1 As illustrated, the wireless communication network 100 may include multiple base stations (BS) 110a to 110z (each individually referred to herein as BS 110 or collectively as BS 110) and other network entities. BS may also be referred to as access point (AP), evolved Node B (eNodeB or eNB), next-generation Node B (gNodeB or gNB), or some other terminology.

[0024] BS 110 can provide communication coverage for a specific geographic area (sometimes referred to as a "cell"), which can be stationary or mobile depending on the location of the mobile BS. In some examples, BS 110 can use any suitable transport network, interconnected with each other through various types of backhaul interfaces (e.g., direct physical connection, wireless connection, virtual network, etc.) and / or connected to one or more other BSs or network nodes (not shown) in the wireless communication network 100. Figure 1 In the example shown, BS 110a, 110b, and 110c can be macro BSs for macro cells 102a, 102b, and 102c, respectively. BS 110x can be a pico BS for pico cell 102x. BS 110y and 110z can be femto BSs for femto cells 102y and 102z, respectively. A BS can support one or more cells.

[0025] BS 110 communicates with one or more user equipment (UEs) 120a to 120y (each individually referred to herein as "UE 120" or collectively as "UE 120") in the wireless communication network 100. The UE can be fixed or mobile and can also be referred to as a user terminal (UT), mobile station (MS), access terminal, station (STA), client, wireless device, mobile device, or some other term. The user terminal can be a wireless device such as a cellular phone, smartphone, personal digital assistant (PDA), handheld device, wearable device, wireless modem, laptop computer, tablet computer, personal computer, etc.

[0026] BS 110 is considered a transmitting entity for downlink and a receiving entity for uplink. UE 120 is considered a transmitting entity for uplink and a receiving entity for downlink. As used herein, a “transmitting entity” is a separately operating apparatus or device capable of transmitting data via a frequency channel, and a “receiving entity” is a separately operating apparatus or device capable of receiving data via a frequency channel. In the following description, the subscript “…” dn " indicates the downlink, subscript " up "Indicates uplink. You can select..." N up Each UE is used for simultaneous transmission on the uplink, and can be selected. N dn Each UE is used for simultaneous transmission on the downlink. N up It can be equal to or not equal to N dn ,and N up and N dn It can be a static value or it can change for each scheduling interval. Beam control or some other spatial processing techniques can be used at BS 110 and / or UE 120.

[0027] UEs 120 (e.g., 120x, 120y, etc.) may be distributed throughout the wireless communication network 100, and each UE 120 may be stationary or mobile. The wireless communication network 100 may also include relay stations (e.g., relay station 110r) (also referred to as repeaters, etc.) that receive transmissions of data and / or other information from upstream stations (e.g., BS 110a or UE 120r) and transmit the transmissions of data and / or other information to downstream stations (e.g., UE 120 or BS 110), or relay transmissions between UEs 120 to facilitate communication between devices.

[0028] BS 110 can communicate with one or more UE 120s on both the downlink and uplink at any given time. The downlink (i.e., the forward link) is the communication link from BS 110 to UE 120, while the uplink (i.e., the reverse link) is the communication link from UE 120 to BS 110. UE 120 can also communicate peer-to-peer with another UE 120.

[0029] Wireless communication network 100 can use multiple transmit antennas and multiple receive antennas to transmit data on the downlink and uplink. BS 110 can be equipped with several ( N ap (Number) antennas to achieve transmit diversity for downlink transmission and / or receive diversity for uplink transmission. A set of (N u Each UE 120 can receive downlink transmissions and send uplink transmissions. Each UE 120 can send user-specific data to and / or receive user-specific data from the BS 110. Typically, each UE 120 may be equipped with one or more antennas. N u Each UE 120 can have the same or different number of antennas.

[0030] The wireless communication network 100 can be a time-division duplex (TDD) system or a frequency-division duplex (FDD) system. In a TDD system, the downlink and uplink share the same frequency band. In an FDD system, the downlink and uplink use different frequency bands. The wireless communication network 100 can also utilize a single carrier or multiple carriers for transmission. Each UE 120 can be equipped with a single antenna (e.g., to reduce cost) or multiple antennas (e.g., where additional cost can be supported).

[0031] Network controller 130 (sometimes referred to as a "system controller") can communicate with a group of BSs 110 and (e.g., via backhaul) provide coordination and control for these BSs 110. In some cases (e.g., in a 5G NR system), network controller 130 may include centralized units (CUs) and / or distributed units (DUs). In some aspects, network controller 130 can communicate with core network 132 (e.g., a 5G core network (5GC)) that provides various network functions such as access and mobility management, session management, user plane functions, policy control functions, authentication server functions, unified data management, application functions, network openness functions, network repository functions, network slice selection functions, etc.

[0032] In certain aspects of this disclosure, BS 110 and / or UE 120 may include transceivers implemented using inverter buffers, as described in more detail herein.

[0033] Figure 2 Examples of BS 110a and UE 120a in which aspects of this disclosure may be implemented (e.g., from...) Figure 1 Example components of a wireless communication network 100.

[0034] On the downlink, at BS 110a, the transmitting processor 220 can receive data from data source 212, control information from controller / processor 240, and / or other data (e.g., from scheduler 244). Various types of data can be transmitted on different transport channels. For example, control information can be designated for the Physical Broadcast Channel (PBCH), Physical Control Format Indicator Channel (PCFICH), Physical Hybrid Automatic Repeat Request (HARQ) Indicator Channel (PHICH), Physical Downlink Control Channel (PDCCH), Group Common PDCCH (GC PDCCH), etc. Data can be designated for the Physical Downlink Shared Channel (PDSCH), etc. The Media Access Control (MAC)-Control Element (MAC-CE) is a MAC layer communication structure that can be used for exchanging control commands between wireless nodes. The MAC-CE can be carried in shared channels such as PDSCH, Physical Uplink Shared Channel (PUSCH), or Physical Sidelink Shared Channel (PSSCH).

[0035] Processor 220 can process (e.g., encode and symbol map) data and control information to obtain data symbols and control symbols, respectively. Transmitter processor 220 can also generate reference symbols such as those for primary synchronization signal (PSS), secondary synchronization signal (SSS), PBCH demodulation reference signal (DMRS), and channel state information reference signal (CSI-RS).

[0036] The transmit (TX) multiple-input multiple-output (MIMO) processor 230 can perform spatial processing (e.g., pre-decoding) on ​​data symbols, control symbols, and / or reference symbols where applicable, and can provide the output symbol stream to the modulators (MODs) in transceivers 232a to 232t. Each modulator in transceivers 232a to 232t can process the corresponding output symbol stream (e.g., for orthogonal frequency division multiplexing (OFDM), etc.) to obtain an output sample stream. In some implementations, non-OFDM modulation schemes can be used to provide reduced power consumption. Each transceiver in transceivers 232a to 232t can further process (e.g., convert to analog, amplify, filter, and up-convert) the output sample stream to obtain a downlink signal. The downlink signal from transceivers 232a to 232t can be transmitted via antennas 234a to 234t, respectively.

[0037] At UE 120a, antennas 252a to 252r can receive downlink signals from BS 110a and can provide the received signals to transceivers 254a to 254r respectively. Transceivers 254a to 254r can adjust (e.g., filter, amplify, downconvert, and digitize) the corresponding received signals to obtain input samples. Each demodulator (DEMOD) in transceivers 232a to 232t can further process the input samples (e.g., for OFDM, etc.) to obtain received symbols. MIMO detector 256 can obtain the received symbols from all demodulators in transceivers 254a to 254r, perform MIMO detection on the received symbols (where applicable), and provide the detected symbols. Receiver processor 258 can process (e.g., demodulate, deinterleave, and decode) the detected symbols, provide the decoded data for UE 120a to data sink 260, and provide the decoded control information to controller / processor 280.

[0038] On the uplink, at UE 120a, the transmit processor 264 can receive and process data from data source 262 (e.g., for the Physical Uplink Shared Channel (PUSCH)) and control information from controller / processor 280 (e.g., for the Physical Uplink Control Channel (PUCCH)). The transmit processor 264 can also generate reference symbols for reference signals (e.g., for the Sounding Reference Signal (SRS)). Symbols from the transmit processor 264 can be pre-decoded (if applicable) by the TX MIMO processor 266, further processed by modulators (MODs) in transceivers 254a to 254r (e.g., for Single Carrier Frequency Division Multiplexing (SC-FDM), etc.), and transmitted to BS 110a. At BS 110a, the uplink signal from UE 120a can be received by antenna 234, processed by demodulators in transceivers 232a to 232t, detected by MIMO detector 236 where applicable, and further processed by receiver processor 238 to obtain decoded data and control information transmitted by UE 120a. Receiver processor 238 can provide the decoded data to data sink 239 and the decoded control information to controller / processor 240.

[0039] Memory 242 and 282 can store data and program code for BS 110a and UE 120a, respectively. Memory 242 and 282 can also interface with controller / processor 240 and 280, respectively. Scheduler 244 can schedule the UE for data transmission on the downlink and / or uplink.

[0040] In some aspects of this disclosure, transceiver 232 and / or transceiver 254 may be implemented using an inverter buffer, as described in more detail herein.

[0041] NR can use Orthogonal Frequency Division Multiplexing (OFDM) with a cyclic prefix (CP) on both the uplink and downlink. NR can use Time Division Duplex (TDD) to support half-duplex operation. OFDM and Single-Carrier Frequency Division Multiplexing (SC-FDM) divide the system bandwidth into multiple orthogonal subcarriers, which are often referred to as tones, frequency bands, etc. Each subcarrier can be modulated with data. Modulation symbols can be transmitted in the frequency domain using OFDM and in the time domain using SC-FDM. The spacing between adjacent subcarriers can be fixed, and the total number of subcarriers can depend on the system bandwidth. The system bandwidth can also be divided into subbands. For example, a subband can cover multiple resource blocks (RBs). Example RF transceiver

[0042] Figure 3 This is a block diagram of an example radio frequency (RF) transceiver circuit 300 according to certain aspects of this disclosure. The RF transceiver circuit 300 includes at least one transmit (TX) path 302 (also referred to as a "transmit chain") for transmitting signals via one or more antennas 306 and at least one receive (RX) path 304 (also referred to as a "receive chain") for receiving signals via antenna 306. When the TX path 302 and RX path 304 share antenna 306, these paths can be connected to the antenna via an interface 308, which may include any of a variety of suitable RF devices, such as switches, duplexers, double-ended converters, multiplexers, etc.

[0043] Receiving in-phase (I) and / or quadrature (Q) baseband analog signals from a digital-to-analog converter (DAC) 310, the TX path 302 may include a baseband filter (BBF) 312, a mixer 314, a driver amplifier (DA) 316, and a power amplifier (PA) 318. The BBF 312, mixer 314, DA 316, and PA 318 may be included in a radio frequency integrated circuit (RFIC). In some respects, the PA 318 may be external to the RFIC.

[0044] BBF 312 filters the baseband signal received from DAC 310, and mixer 314 mixes the filtered baseband signal with the transmit local oscillator (LO) signal to convert the baseband signal of interest to a different frequency (e.g., up-convert from baseband to RF). This frequency conversion process produces a sum and difference frequency between the LO frequency and the frequency of the baseband signal of interest. This sum and difference frequency is referred to as the "beat frequency". The beat frequency is typically in the RF range, such that the signal output from mixer 314 is typically an RF signal, which can be amplified by DA 316 and / or PA 318 before being transmitted by antenna 306. When a mixer 314 is exemplified, several mixers can be used to up-convert the filtered baseband signal to one or more intermediate frequencies and subsequently up-convert the intermediate frequency (IF) signal to the frequency used for transmission. In some respects, an inverter buffer can be used to drive DA 316 with sufficient linearity (e.g., to meet linearity specifications), as described in more detail herein.

[0045] The RX path 304 may include a low-noise amplifier (LNA) 324, a mixer 326, and a baseband filter (BBF) 328. The LNA 324, mixer 326, and BBF 328 may be included in one or more RFICs, which may be the same RFIC as the RFIC including the TX path components, or may not be the same RFIC as the RFIC including the TX path components. The RF signal received via antenna 306 may be amplified by the LNA 324, and the mixer 326 mixes the amplified RF signal with a received local oscillator (LO) signal to convert the RF signal of interest to a different baseband frequency (e.g., down-conversion). The baseband signal output from the mixer 326 may be filtered by the BBF 328 before being converted to digital I and / or Q signals by an analog-to-digital converter (ADC) 330 for digital signal processing.

[0046] Some transceivers may employ a frequency synthesizer with a variable-frequency oscillator (e.g., a voltage-controlled oscillator (VCO) or a digitally controlled oscillator (DCO)) to generate a stable, tunable LO with a specific tuning range. Thus, the transmit LO may be generated by the TX frequency synthesizer 320, which may be buffered or amplified by amplifier 322 before being mixed with the baseband signal in mixer 314. Similarly, the receive LO may be generated by the RX frequency synthesizer 332, which may be buffered or amplified by amplifier 334 before being mixed with the RF signal in mixer 326. In some aspects, a single frequency synthesizer may be used for both TX path 302 and RX path 304. In some aspects, the TX frequency synthesizer 320 and / or the RX frequency synthesizer 332 may include a frequency multiplier (such as a doubler) driven by an oscillator (e.g., a VCO) in the frequency synthesizer.

[0047] Controller 336 (e.g., Figure 2 The controller / processor 280 in the controller can direct the operation of the RF transceiver circuit 300A, such as transmitting signals via TX path 302 and / or receiving signals via RX path 304. The controller 336 can be a processor, digital signal processor (DSP), application-specific integrated circuit (ASIC), field-programmable gate array (FPGA) or other programmable logic device (PLD), discrete gate or transistor logic, discrete hardware components, or any combination thereof. Memory 338 (e.g., Figure 2 The memory 282 in the memory can store data and / or program code used to operate the RF transceiver circuit 300. The controller 336 and / or the memory 338 may include control logic (e.g., complementary metal-oxide-semiconductor (CMOS) logic).

[0048] although Figures 1 to 3 Wireless communication is provided as an example application in which certain aspects of this disclosure can be implemented to facilitate understanding, but certain aspects described herein can be used in any of a variety of other suitable systems. Example transmit chain with self-biased inverter buffer

[0049] Certain aspects of this disclosure provide a transmitter that implements shared in-phase and quadrature (I / Q) digital-to-analog converters (DACs) and transmit baseband (TXBB) filters for 2.4 GHz (2G) and 5 GHz (5G). These DACs and filters can be coupled to an upconverter (UPC) (e.g., a passive mixer) for upconversion to facilitate transmission. The transmitter can be implemented for Internet of Things (IoT) devices and / or wearable devices (e.g., headphones), and therefore may have stringent power consumption and area specifications. These DACs, filters, and UPCs can be implemented in a low-power and low-area manner.

[0050] When operating in 2G mode, the signal from the UPC may be able to drive the transmitter's driver amplifier (DA) with sufficient linearity. However, when operating in 5G mode (e.g., at high frequencies such as the 5G band, which in some implementations can be up to 6.4 GHz), the signal from the UPC may not be able to drive the DA with sufficient linearity for transmission. Designing these DACs, filters, and UPCs to drive the DA with sufficient linearity in 5G mode can lead to increased power consumption and area, making it challenging to meet the stringent power and area specifications of IoT applications while maintaining system specifications. Certain aspects of this disclosure relate to the use of a self-biased inverter buffer with variable capacitive and inductive elements in the transmission path, thereby allowing the transmission path to provide power to the DA with sufficient linearity for transmission when operating in 5G mode.

[0051] Figure 4 An example transmitter 400 according to certain aspects of this disclosure is illustrated. Transmitter 400 includes an in-phase (I) DAC 402 and a quadrature (Q) DAC 406, which receive corresponding I and Q signals for conversion from the digital domain to the analog domain. These I and Q analog signals are provided to corresponding I and Q BBFs 404, 408 for filtering. A UPC 410 may be coupled to the outputs of BBFs 404, 408 to up-convert the filtered signal using a local oscillator (LO) signal. As shown, the up-converted signal from UPC 410 may be provided to a buffer circuit 412 (e.g., including a self-biased inverter buffer 434), wherein the output of buffer circuit 412 is provided to one or more PAs for amplification of the signal transmitted through antenna 432.

[0052] In some aspects, a driver amplifier (DA) (also known as a preamplifier PA (PPA)) can be used, which can correspond to Figure 3 DA316) and the main PA (MPA) (e.g., corresponding to Figure 3(PA 318). For example, the output of buffer circuit 412 can be received at the input of DA 422 (e.g., the buffered signal from buffer circuit 412 can be provided to the gate of the transconductance transistor of DA 422). The differential output of DA 422 can be provided to the primary winding of transformer 424, wherein the secondary winding of transformer 424 is coupled to the input of MPA 426. The signal from the secondary winding of transformer 424 can be provided to MPA 426 for amplification. The amplified signal from MPA 426 is provided to the primary winding of transformer 428 (e.g., a balun). For example, the differential output of MPA 426 can be coupled to a corresponding terminal of the primary winding of transformer 428. As shown, the terminal of the secondary winding of transformer 428 can be coupled to a reference potential node (e.g., electrically grounded), while another terminal of transformer 428 can be coupled to antenna 432 via AC coupling capacitive element 430.

[0053] As shown, the buffer circuit 412 may include a self-biased inverter buffer 434 having differential outputs (e.g., providing different voltages Vop and Von) coupled to corresponding terminals of an inductive element 420 via respective AC-coupled capacitive elements 414, 416. In some aspects, a capacitive element 418 (e.g., a variable capacitive element) may be coupled between these terminals of the inductive element 420. The capacitive element 418 and the inductive element 420 can be used to extend the load effect on the inverter buffer 434. For example, by means of the inductive element 420 and the tuning of the capacitive element 418, the bandwidth associated with the inverter buffer 434 is extended (e.g., providing a widened bandwidth centered on the LO frequency (e.g., 5.5 GHz), thereby enabling this bandwidth to support transmit bands for 5G modes (e.g., 4.9 GHz to 6.4 GHz). The midpoint (e.g., a tap) of the inductive element can also be used to set the DC bias for the DA 422. In other words, a bias voltage (Vbias) can be generated at the tap of the inductive element 420 to bias DA 422.

[0054] Figure 5 Examples of implementations of inverter buffers (e.g., according to certain aspects of this disclosure) are illustrated. Figure 4 An example circuit of an inverter buffer 434 is shown. As illustrated, the inverter buffer 434 may include an inverter 502 that receives a positive input voltage (Vip) via a capacitive element 506 (e.g., an AC-coupled capacitive element), and an inverter 504 that receives a negative input voltage (Vin) via a capacitive element 514. Vip and Vin can be received from the inverter buffer at the Vip and Vin nodes, respectively. Figure 4 The UPC410 receives it.

[0055] Inverter 502 may include a p-type metal-oxide-semiconductor (PMOS) transistor 510 and an n-type metal-oxide-semiconductor (NMOS) transistor 512, the drains of which are coupled to the negative output voltage (Von) node of the inverter buffer. The source of transistor 510 may be coupled to a voltage rail (Vdd), and the source of transistor 512 may be coupled to a reference potential node (e.g., electrically grounded). The gates of transistors 510 and 512 may be coupled together and to a first terminal of capacitive element 506, wherein a second terminal of capacitive element 506 is coupled to the Vip node. In some aspects, a resistive element 508 may be coupled between the Von node and the gates of transistors 510 and 512 to bias inverter 502 with a certain gain (e.g., to provide self-biasing for inverter 502). Similarly, inverter 504 may include a PMOS transistor 518 and an NMOS transistor 520, the drains of which are coupled to the positive output voltage (Vop) node of the inverter buffer. The gates of transistors 518 and 520 may be coupled together and coupled to the first terminal of capacitive element 514, wherein the second terminal of capacitive element 514 is coupled to Vin node. In some aspects, resistive element 516 may be coupled between Vop node and the gates of transistors 518 and 520, thereby biasing inverter 504 with a certain gain.

[0056] Figure 6 This is a flowchart illustrating an example operation 600 for wireless communication according to certain aspects of this disclosure. Operation 600 may be performed, for example, by a transmitter (such as...) Figure 4 The transmitter 400 is used to execute this.

[0057] At box 602, the transmitter uses the transmitter's up-converter circuitry (e.g., Figure 4 The up-converter signal is generated by UPC 410. At block 604, the transmitter generates a buffered signal based on the up-converted signal using an inverter buffer (e.g., inverter buffer 434). At block 606, the transmitter generates an amplified signal based on the buffered signal via at least one amplifier of the transmitter (e.g., DA 422 and / or MPA 426). At block 608, the transmitter uses the amplified signal for signal transmission. In some aspects, when transmitting using the first frequency band, the maximum output power capability of the up-converter circuit is less than the power consumption of the at least one amplifier. The transmitter can support the first frequency band (e.g., a band for 5G) and a second frequency band (e.g., a band for 2G) with a center frequency lower than the center frequency of the first frequency band.

[0058] In some aspects, a first terminal of an inductive element (e.g., inductive element 420) is coupled to a first output of an inverter buffer. Taps of the inductive element may be coupled to an input of the at least one amplifier. The inductive element may include a second terminal coupled to a second output of the inverter buffer. The transmitter may set the capacitance of a capacitive element (e.g., capacitive element 418) to adjust the bandwidth of the inverter buffer. The capacitive element may be coupled between the first and second terminals of the inductive element.

[0059] In some aspects, the inverter buffer may include a first transistor (e.g., Figure 5 The transistor 510, whose source is coupled to a voltage rail (e.g., Vdd) and whose drain is coupled to the output of the inverter buffer; and the second transistor (e.g., Figure 5 The source of transistor 512 is coupled to a reference potential node, and the drain is coupled to the output of the inverter buffer. A resistive element (e.g., resistive element 508) may be coupled between the output of the inverter buffer and the gates of the first transistor and the second transistor. The resistive element may provide DC bias for the inverter buffer.

[0060] In some aspects, the amplified signal may be generated via a first amplifier (e.g., DA 422) of the at least one amplifier. The transmitter may generate another amplified signal based on the amplified signal using a second amplifier (e.g., MPA426) of the at least one amplifier. This other amplified signal may be used to transmit the signal. Example

[0061] In addition to the various aspects described above, specific combinations of these aspects are also within the scope of this disclosure, some of which are detailed below:

[0062] Aspect 1: A transmitter comprising: an upconverter circuit including one or more inputs coupled to one or more transmission chains of the transmitter; an inverter buffer including an input coupled to a first output of the upconverter circuit; and at least one amplifier coupled to the first output of the inverter buffer.

[0063] Aspect 2: The transmitter according to aspect 1, wherein when transmitting using the first frequency band, the maximum output power capability of the upconverter circuit is less than the power consumption of the at least one amplifier.

[0064] Aspect 3: The transmitter according to aspect 2, wherein the transmitter is configured to support the first frequency band and a second frequency band with a center frequency lower than the first frequency band.

[0065] Aspect 4: A transmitter according to any one of Aspects 1 to 3, wherein the inverter buffer includes a resistive element coupled between the input terminal of the inverter buffer and the first output terminal of the inverter buffer.

[0066] Aspect 5: The transmitter according to any one of Aspects 1 to 4, the transmitter further comprising an inductive element having a first terminal coupled to the first output terminal of the inverter buffer and a tap coupled to the input terminal of the at least one amplifier.

[0067] Aspect 6: The transmitter according to aspect 5, wherein: the inductive element includes a second terminal coupled to a second output of the inverter buffer; and the transmitter further includes a capacitive element coupled between the first terminal and the second terminal of the inductive element.

[0068] Aspect 7: The transmitter according to aspect 6, wherein the capacitive element includes a variable capacitive element.

[0069] Aspect 8: The transmitter according to any one of Aspects 5 to 7 further includes an AC-coupled capacitive element coupled between the first output terminal of the inverter buffer and the first terminal of the inductive element.

[0070] Aspect 9: A transmitter according to any one of Aspects 1 to 8, wherein the inverter buffer comprises: a first transistor having a source coupled to a voltage rail and a drain coupled to a first output terminal of the inverter buffer; a second transistor having a source coupled to a reference potential node and a drain coupled to the first output terminal of the inverter buffer; and a resistive element coupled between the first output terminal of the inverter buffer and the gates of the first transistor and the second transistor.

[0071] Aspect 10: The transmitter according to aspect 9, wherein the inverter buffer further includes an AC-coupled capacitive element coupled between the first output terminal of the upconverter circuit and the gates of the first transistor and the second transistor.

[0072] Aspect 11: The transmitter according to any one of Aspects 1 to 10, wherein the upconverter circuit includes a passive mixer.

[0073] Aspect 12: A transmitter according to any one of Aspects 1 to 11, wherein the at least one amplifier comprises: a first amplifier including an input coupled to a first output of the inverter buffer; a transformer including a primary winding coupled to an output of the first amplifier; a second amplifier including an input coupled to a secondary winding of the transformer; and another transformer including a primary winding coupled to an output of the second amplifier.

[0074] Aspect 13: A transmitter according to any one of aspects 1 to 12, wherein the one or more transmission chains include a first transmission chain for in-phase (I) signals and a second transmission chain for quadrature (Q) signals.

[0075] Aspect 14: A transmitter according to any one of aspects 1 to 13, wherein each of the one or more transmission chains includes a digital-to-analog converter (DAC) and a baseband filter.

[0076] Aspect 15: A method for wireless communication, the method comprising: generating an up-converted signal using an up-converter circuit of a transmitter; generating a buffered signal based on the up-converted signal using an inverter buffer; generating an amplified signal based on the buffered signal via at least one amplifier of the transmitter; and performing signal transmission using the amplified signal.

[0077] Aspect 16: According to the method of aspect 15, wherein when transmitting using the first frequency band, the maximum output power capability of the upconverter circuit is less than the power consumption of the at least one amplifier.

[0078] Aspect 17: The method according to aspect 16, wherein the transmitter supports the first frequency band and a second frequency band with a center frequency lower than the first frequency band.

[0079] Aspect 18: The method according to any one of Aspects 15 to 17, wherein a first terminal of the inductive element is coupled to a first output terminal of the inverter buffer, and wherein a tap of the inductive element is coupled to an input terminal of the at least one amplifier.

[0080] Aspect 19: The method according to aspect 18, wherein: the inductive element includes a second terminal coupled to a second output of the inverter buffer; and the method further includes setting a capacitance of a capacitive element to adjust the bandwidth of the inverter buffer, the capacitive element being coupled between the first terminal and the second terminal of the inductive element.

[0081] Aspect 20: The method according to any one of Aspects 15 to 19, wherein the inverter buffer comprises: a first transistor having a source coupled to a voltage rail and a drain coupled to an output terminal of the inverter buffer; a second transistor having a source coupled to a reference potential node and a drain coupled to the output terminal of the inverter buffer; and a resistive element coupled between the output terminal of the inverter buffer and the gates of the first transistor and the second transistor.

[0082] Aspect 21: The method according to any one of aspects 15 to 20, wherein: the amplified signal is generated via a first amplifier of the at least one amplifier; the method further includes generating another amplified signal based on the amplified signal using a second amplifier of the at least one amplifier; and using the other amplified signal to transmit the signal.

[0083] Aspect 22: A wireless device comprising: an antenna; and a transmitter coupled to the antenna and including: an upconverter circuit including one or more inputs of one or more transmission chains coupled to the transmitter; an inverter buffer including an input coupled to a first output of the upconverter circuit; and a first amplifier coupled to a first output of the inverter buffer and including an output coupled to the antenna.

[0084] The above description provides examples and is not intended to limit the scope, applicability, or examples set forth in the claims. Changes may be made to the function and arrangement of the elements discussed without departing from the scope of this disclosure. Various processes or components may be omitted, substituted, or added as appropriate in various examples. For example, the described method may be performed in a different order than described, and various steps may be added, omitted, or combined. Furthermore, features described with respect to some examples may be combined in some other examples. For example, any number of aspects set forth herein may be used to implement an apparatus or practice. Moreover, the scope of this disclosure is intended to cover such apparatuses or methods implemented using structures, functionalities, or structures and functionalities other than those set forth herein or different from the various aspects of the disclosure set forth herein. It should be understood that any aspect of the disclosure herein may be embodied by one or more elements of the claims.

[0085] The various operations of the methods described above can be performed by any suitable component capable of performing the corresponding function. This component can include various hardware and / or software components and / or modules, including but not limited to circuits, application-specific integrated circuits (ASICs), or processors. Generally, in the presence of operations illustrated in the accompanying drawings, these operations can have corresponding components plus functional elements.

[0086] As used in this article, the phrase "at least one of" in a list of items refers to any combination of these items, including a single member. For example, " a , b or c "At least one of" is intended to cover: a , b , c , ab , ac , bc and abc and any combination having multiple identical elements (e.g., a - a , a - a - a , a - a - b , a - a - c , a - b - b , a - c - c , b - b , b - b - b , b - b - c , c - c and c - c - c or a , b and c (any other sorting).

[0087] The methods disclosed herein include one or more steps or actions for implementing the described methods. The steps and / or actions of the methods may be interchanged without departing from the scope of the claims. In other words, unless a specific order of steps or actions is specified, the order and / or use of a particular step and / or action may be modified without departing from the scope of the claims.

[0088] It should be understood that the claims are not limited to the precise configurations and components illustrated above. Various modifications, variations, and alterations may be made to the arrangement, operation, and details of the methods and apparatus described above without departing from the scope of the claims.

Claims

1. A transmitter, the transmitter comprising: An upconverter circuit, the upconverter circuit including one or more input terminals coupled to one or more transmission chains of the transmitter; An inverter buffer, the inverter buffer including an input terminal coupled to a first output terminal of the up-converter circuit; and At least one amplifier coupled to the first output of the inverter buffer.

2. The transmitter according to claim 1, wherein when transmitting using the first frequency band, the maximum output power capability of the upconverter circuit is less than the power consumption of the at least one amplifier.

3. The transmitter of claim 2, wherein the transmitter is configured to support the first frequency band and a second frequency band with a center frequency lower than the first frequency band.

4. The transmitter of claim 1, wherein the inverter buffer includes a resistive element coupled between the input terminal of the inverter buffer and the first output terminal of the inverter buffer.

5. The transmitter of claim 1, further comprising an inductive element having a first terminal coupled to the first output of the inverter buffer and a tap coupled to the input of the at least one amplifier.

6. The transmitter according to claim 5, wherein: The inductive element includes a second terminal coupled to the second output of the inverter buffer; and The transmitter also includes a capacitive element coupled between the first terminal and the second terminal of the inductive element.

7. The transmitter of claim 6, wherein the capacitive element comprises a variable capacitive element.

8. The transmitter of claim 5, further comprising an AC-coupled capacitive element coupled between the first output terminal of the inverter buffer and the first terminal of the inductive element.

9. The transmitter of claim 1, wherein the inverter buffer comprises: A first transistor having a source coupled to a voltage rail and a drain coupled to the first output terminal of the inverter buffer; The second transistor has a source coupled to a reference potential node and a drain coupled to the first output terminal of the inverter buffer; and A resistive element coupled between the first output terminal of the inverter buffer and the gates of the first transistor and the second transistor.

10. The transmitter of claim 9, wherein the inverter buffer further comprises an AC-coupled capacitive element coupled between the first output terminal of the upconverter circuit and the gates of the first transistor and the second transistor.

11. The transmitter of claim 1, wherein the upconverter circuit includes a passive mixer.

12. The transmitter of claim 1, wherein the at least one amplifier comprises: A first amplifier, the first amplifier including an input coupled to a first output terminal of the inverter buffer; A transformer, the transformer including a primary winding coupled to the output of the first amplifier; A second amplifier, the second amplifier including an input terminal coupled to the secondary winding of the transformer; and Another transformer, the other transformer including a primary winding coupled to the output of the second amplifier.

13. The transmitter of claim 1, wherein the one or more transmission chains include a first transmission chain for in-phase (I) signals and a second transmission chain for quadrature (Q) signals.

14. The transmitter of claim 1, wherein each of the one or more transmission chains comprises a digital-to-analog converter (DAC) and a baseband filter.

15. A method for wireless communication, the method comprising: The upconverter circuit of the transmitter generates the upconverted signal; Based on the up-converted signal, an inverter buffer is used to generate a buffered signal; At least one amplifier of the transmitter generates an amplified signal based on the buffered signal; as well as The amplified signal is used to perform signal transmission.

16. The method of claim 15, wherein when transmitting using the first frequency band, the maximum output power capability of the upconverter circuit is less than the power consumption of the at least one amplifier.

17. The method of claim 16, wherein the transmitter supports the first frequency band and a second frequency band with a center frequency lower than the first frequency band.

18. The method of claim 15, wherein a first terminal of the inductive element is coupled to a first output of the inverter buffer, and wherein a tap of the inductive element is coupled to an input of the at least one amplifier.

19. The method of claim 18, wherein: The inductive element includes a second terminal coupled to the second output of the inverter buffer; and The method further includes setting the capacitance of a capacitive element to adjust the bandwidth of the inverter buffer, the capacitive element being coupled between the first terminal and the second terminal of the inductive element.

20. A wireless device, the wireless device comprising: antenna; and A transmitter, coupled to the antenna, includes: An upconverter circuit, the upconverter circuit including one or more input terminals coupled to one or more transmission chains of the transmitter; Inverter buffer, the inverter buffer including an input terminal coupled to a first output terminal of the up-converter circuit; and A first amplifier is coupled to a first output of the inverter buffer and includes an output coupled to the antenna.

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