A method for spectral spreading of a data transmission clock and a device for using the method.

Abstract

An apparatus according to this disclosure includes: a PLL configured to modulate and output a frequency of a clock used for synchronizing communication data according to an adjustment signal applied to the PLL; and a controller configured to generate an adjustment signal according to a modulated waveform and apply the adjustment signal to the PLL, the modulated waveform being a successive form of a plurality of modulated wave units determined by a set modulation profile. A modulated wave unit is a signal whose sum of signal values ​​first becomes zero during its duration, and at least two consecutive modulated wave units among the plurality of modulated wave units differ from each other in at least one of duration and signal form.

Description

Technical Field

[0001] This invention relates to the technical field of spectrum spreading of a clock used to synchronize a data stream when transmitting and receiving data streams between communication devices. Background Technology

[0002] Clock data recovery (CDR) refers to recovering the clock from the received data stream and using it for data demodulation. However, a fixed-frequency square wave is typically used as the clock, and its spectrum has characteristics such as... Figure 1 The energy concentration is illustrated in form 1. Therefore, electromagnetic waves generated strongly in a specific frequency band can cause electromagnetic interference (EMI) problems to the signals, circuits, etc. of other surrounding electronic components.

[0003] Furthermore, since electromagnetic energy increases with frequency, the necessity of eliminating the negative effects of EMI also increases with the improvement of communication speed. The technology proposed to address this need is spread spectrum clock (SSC).

[0004] The essence of spread spectrum clock technology lies in the fact that the clock frequency is periodically rotated around the nominal frequency F0 (T SSC ) changes, such as Figure 2a As illustrated, this causes spectrum 2 to expand, such as Figure 2b As illustrated, this reduces the peak energy (ΔdE). pk ).

[0005] In addition, in order to effectively expand the clock spectrum, besides Figure 2a In addition to the illustrated target modulation pattern, various other target modulation patterns were used, and Figure 2c and Figure 2d These patterns and the resulting spread spectrum of the clock are illustrated.

[0006] However, as can be seen from the illustrated spread spectrum pattern, if the modulation pattern is changed, only the intensity of the harmonic components at the nominal frequency fluctuates, while the peak value of the spread spectrum (pkE) remains constant. ssc1 pkE ssc2 pkE ssc3 No significant difference was observed. In other words, modulating the frequency with any pattern only slightly shifts the specific spectrum that causes the greatest EMI problems, without having any effect on further reducing the intensity of electromagnetic waves within that spectrum. Summary of the Invention

[0007] Technical issues

[0008] One object of the present invention is to provide a clock spectrum spreading method and an apparatus for further reducing the maximum intensity of electromagnetic waves.

[0009] Another object of the present invention is to provide a method for extending the clock spectrum by using a non-repetitive modulation waveform to frequency modulate the clock, and an apparatus for using the method.

[0010] Another object of the present invention is to provide a modulation / demodulation method for using spread spectrum clocks between transmitting / receiving devices that employ loop timing, and an apparatus for using the method.

[0011] The purpose of this invention is not limited to the purposes explicitly described above, but also includes the purpose of achieving effects that can be derived from the following specific and exemplary description of the invention.

[0012] Solution to the problem

[0013] According to one aspect of this disclosure, an apparatus is provided for performing data communication with a peer device via a transmission channel, the apparatus comprising: a PLL (phase-locked loop) configured to modulate and output a frequency of a clock used for synchronizing communication data according to an adjustment signal applied to the PLL; a first controller configured to generate an adjustment signal according to a modulation waveform and apply the adjustment signal to the PLL, the modulation waveform being a continuous form of a plurality of modulation wave units determined by a set modulation profile; and a main controller configured to control the first controller to initiate the application of the adjustment signal to the PLL.

[0014] In an embodiment according to this disclosure, the main controller is configured such that modulation wave units, each corresponding to a series of modulation wave unit identifiers, are set to waveforms in a sequential form according to their identifier order as a modulation profile in the first controller. Furthermore, the series of modulation wave unit identifiers are confirmed based on data encoded by components provided in the device, or information is received from a peer device.

[0015] The device may have a configuration for the receiver. That is, the clock may be a clock used to capture and receive signals carried on the transmission channel as digital signals.

[0016] In an embodiment where the device is a receiver, the master controller controls the first controller to apply an adjustment signal to the PLL at a predetermined time point elapsed from the time point at which a specific pattern is detected on the transmission channel. Alternatively, the master controller may control the first controller to apply an adjustment signal to the PLL at a predetermined time point elapsed from the time point at which a message containing specific information is received from the peer device. In this case, the specific information may be information notifying that information about the plurality of modulation wave units has been successfully received. Furthermore, the device may be configured such that a clock can also be used to transmit a data stream to the transmission channel for transmission to the peer device. In this case, the device may further include: a second PLL configured to modulate and output the frequency of a second clock used for synchronizing the data stream transmitted to the peer device according to the adjustment signal applied to the second PLL; and a MUX (multiplexer) that selects one of the clock and the second clock according to a specified mode and outputs the latter for synchronizing the data stream transmitted to the transmission channel. The mode may be specified by a component circuitically configured in the device and capable of selectively setting specific values.

[0017] The device may have configurations for the transmitter. That is, the clock may be a clock used to send a data stream to the transmission channel, which is then sent to the peer device.

[0018] In one embodiment of this disclosure, the device may further include: a second PLL configured to modulate and output the frequency of a second clock recovered from a digital signal according to a second adjustment signal applied to the second PLL, the second clock being used to capture and receive digital signals from signals carried on a transmit channel; and a second controller configured to generate the second adjustment signal according to the modulated waveform and apply it to the second PLL. In this case, when a loop time has elapsed from the time point at which the first controller initiates the application of the adjustment signal to the PLL, the master controller controls the second controller to initiate the application of the second adjustment signal to the second PLL, and the master controller determines the loop time based on the time gap from the time immediately following the transmission of a message to the peer device to the time point at which the reception of the message from the peer device begins. More specifically, the master controller may determine the loop time as the time obtained by subtracting the previously confirmed receive / transmit switching time of the peer device from the time gap.

[0019] In one embodiment of the present disclosure, the device further includes: a second PLL configured to modulate and output the frequency of a second clock recovered from a digital signal according to a second adjustment signal applied to the second PLL, the second clock being used to capture and receive digital signals from signals carried on a transmission channel; a delay unit configured to delay the adjustment signal by a delay time according to a delay control signal applied to the delay unit, and output the delay signal as a second adjustment signal; and a tracker configured to adjust the delay time of the adjustment signal in the delay unit according to the signal-to-noise ratio (SNR) of the data stream recovered from the digital signal, and apply a delay control signal corresponding to the adjusted delay time to the delay unit. In this embodiment, the tracker is configured to: confirm the SNR of the recovered data stream for each specified interval, and when the currently confirmed second SNR is lower than the previously confirmed first SNR, reapply the delay control signal applied to the delay unit when the first SNR was obtained, and complete the adjustment of the delay time of the delay unit. Furthermore, the tracker can apply an initial delay time to the delay unit as the time gap immediately following the sending of a message to the peer device until the start of receiving messages from the peer device, and then adjust the delay time to be shorter than the previous delay time each time the delay time is adjusted. Alternatively, the tracker can apply a predetermined time as the initial delay time to the delay unit, and then adjust the delay time to be longer than the previous delay time each time the delay time is adjusted.

[0020] In an implementation where the device is a transmitter, the main controller may apply a control signal to the first controller, which causes an adjustment signal to be applied to the PLL at a predetermined time point after the point at which a signal of a specific pattern is transmitted through the transmission channel.

[0021] According to another aspect of this disclosure, a method for transmitting data with a peer device via a transmission channel is provided, the method comprising: step 1: confirming set modulation wave data; step 2: setting a modulation waveform as a modulation profile, the modulation waveform being in the form of a plurality of modulation wave units indicated by the confirmed modulation wave data being formed consecutively; and step 3: generating an adjustment signal based on the modulation waveform and applying the adjustment signal to a PLL, the PLL being configured to modulate and output a frequency of a clock used for synchronizing communication data. Furthermore, the PLL is configured to modulate the frequency of the clock according to the adjustment signal.

[0022] In the above-described apparatus, method, and implementation, the modulation wave unit is a signal whose sum of signal values ​​first becomes zero within its time length, and at least two consecutive modulation wave units among the plurality of modulation wave units may differ from each other in at least one of time length and signal form.

[0023] According to another aspect of this disclosure, an apparatus for performing data communication with a peer device via a transmission channel, in addition to a PLL and a first controller, further includes: a second PLL configured to modulate and output the frequency of a second clock recovered from a digital signal according to a second adjustment signal applied to the second PLL, the second clock being used to capture and receive digital signals from signals carried on the transmission channel; a delay unit configured to delay the first adjustment signal by a delay time according to a delay control signal applied to the delay unit, and output it as the second adjustment signal; a tracker configured to adjust the delay time of the first adjustment signal in the delay unit according to the signal-to-noise ratio of the data stream recovered from the digital signal, and apply a delay control signal corresponding to the adjusted delay time to the delay unit; and a main controller configured to control the first controller to initiate the application of the first adjustment signal to the first PLL, and configured to include a signal in which the modulation wave unit is a signal whose sum of signal values ​​first becomes zero during its time length, and configured to include the main controller being configured to control the tracker to initiate the adjustment of the delay time for the first adjustment signal.

[0024] Beneficial effects of the invention

[0025] The method for extending the spectrum of a data transmission clock according to the present invention, as described above, or at least one embodiment of the present invention described in detail below in conjunction with the accompanying drawings, further extends the spectrum of the clock necessary for data communication, thereby reducing the maximum intensity of the electromagnetic waves generated by the clock, and the method is applicable to both one-way and two-way communication between two communication devices.

[0026] Furthermore, one embodiment of the present invention can even be applied to two communication devices that use a single clock for data communication with each other by applying loop timing, thereby reducing the maximum intensity of electromagnetic waves generated by the clock even for communication devices that apply loop timing, which can reduce the impact of electromagnetic waves on surrounding devices.

[0027] Furthermore, even when configuring a communication system using communication devices whose characteristics are unpredictable during state transitions between receiving and transmitting, embodiments of the present invention offer a solution that can apply the clock spectrum extension method according to the present invention, which may be more conducive to embodying the present invention in a product. Attached Figure Description

[0028] Figure 1 The spectrum of a commonly used square wave clock is shown.

[0029] Figure 2a and Figure 2bAn example of a modulation waveform used for frequency modulation of a clock is shown, along with the spectrum of a clock spread according to the frequency modulation of the waveform, shown together with the unspread spectrum.

[0030] Figure 2c and Figure 2d These are diagrams illustrating different types of modulation waveforms used for frequency modulation of a clock and the resulting spread spectrum of the clock.

[0031] Figure 3a An example is illustrated of a modulation wave unit set for a modulation profile for clock frequency modulation applicable to an embodiment of the present invention.

[0032] Figure 3b and Figure 3c Different types of modulation wave units are illustrated for modulation profiles applicable to another embodiment of the present invention.

[0033] Figure 4a and Figure 4b This is a diagram illustrating the configuration and determination method for determining and applying a modulation profile from a predetermined set of modulation waves.

[0034] Figure 5a and Figure 5b These are block diagrams illustrating the configurations of a data transmitter and a receiver according to embodiments of the present invention.

[0035] Figure 6 An example of timing according to an embodiment of the invention is provided when a modulation profile for extending the clock spectrum is applied to the transmission and reception of data.

[0036] Figure 7 The application timing of the modulation profile in transmission and reception according to an embodiment of the present invention, as well as the sharing process of the corresponding modulation profile, are illustrated.

[0037] Figure 8 This is an example of a transceiver configuration according to an embodiment of the present invention, which transmits and receives data by incorporating clock frequency modulation.

[0038] Figure 9 This is an example in Figure 8 A diagram showing the sharing of modulation profiles used for frequency modulation of the transmit and receive clocks in the transceiver, and the timing of frequency modulation using those modulation profiles.

[0039] Figure 10 This is an example of a transceiver configuration according to an embodiment of the present invention, wherein a clock recovered from the received data stream is used for synchronization of data transmission.

[0040] Figure 11This is a diagram illustrating the timing of the transceiver providing the clock in two transceivers with loop timing applied, according to an embodiment of the present invention, when the transceiver begins to frequency modulate the received clock.

[0041] Figure 12 This is a block diagram of a transceiver according to another embodiment of the invention, which is configured such that two transceivers with loop timing applied can be selectively used as a master transceiver or a slave transceiver, while having the same circuit configuration.

[0042] Figure 13 This is a block diagram of a transceiver according to another embodiment of the present invention, which can search for and apply frequency modulation timing of the received clock without knowing the characteristic values ​​of the peer transceiver operating in a loop timing manner.

[0043] Figure 14 This is an example Figure 13 The timing diagram shows the state of the transceiver search and application frequency modulation timing that matches the received clock returned by the loop timing. The mode of the present invention Detailed Implementation

[0045] Various embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0046] In the following description and drawings of embodiments according to the present invention, unless otherwise stated, the same numbers denote the same components. Of course, for ease of explanation and understanding, the same components may also be represented by different numbers if necessary.

[0047] In this invention, to further expand the clock spectrum, the target modulation pattern of the clock frequency is given a non-repetitive characteristic. Furthermore, to obtain this target modulation pattern, the signal controlling the clock frequency is also made to have a non-repetitive characteristic, and this specification uses the term "modulation profile" to refer to this signal.

[0048] The modulation profile consists of modulation wave units with different characteristics. Here, a "modulation wave unit" refers to a signal of arbitrary waveform that satisfies the following requirement: within the time length of the waveform, the sum of the corresponding signal values ​​(i.e., the signal values ​​processed by the corresponding waveform at any given moment) first becomes zero (in the case of continuous signals, the term "sum" can refer to the integral value, and is used in a similar sense in the following description and claims); this characteristic can be the time length of the modulation wave unit or the form of the modulation signal.

[0049] The fact that the sum of the signal values ​​becomes zero for the first time within the aforementioned time period means that at the point when the modulation wave is applied, the clock frequency, which had changed due to the modulation wave, will revert to its value before the modulation wave was applied. In other words, the total phase change of the clock becomes 0, and the phase returns to and becomes fixed to the phase immediately preceding the application of the modulation wave.

[0050] Figure 3a An example of a modulation wave unit set 10 suitable for a modulation profile according to an embodiment of the present invention is illustrated. For each type of modulation wave unit (k1, k=1, ..., N), a set of modulation wave units with multiple time lengths (T) is provided. 1Cy_i Modulation wave units (k, i=1, 2, 3...) of the same type j (j=2, 3...), to form modulation wave group 30. And each modulation wave unit in this set is assigned a unique identifier.

[0051] Figure 3a The illustrated modulation wave units all represent continuous signal forms, but the technical ideas and principles of the present invention can not be realized only when signal continuity is guaranteed. Even if the modulation wave unit has discontinuities, the waveform up to the specified time length can also correspond to the modulation wave unit referred to in this specification and claims, provided that the sum of each signal value first becomes 0 at a specific time length. Figure 3b A simple example of this type of modulation wave unit is given.

[0052] Furthermore, in embodiments according to the present invention, the modulation wave unit can be formed as a set of discrete signals. Figure 3c The form of such a modulation wave unit is illustrated. Figure 3c The illustrated modulation wave unit is in the form of continuous discrete signals with the same signal value but different signs. A clock frequency diagram (f) modulated by a clock frequency modulation device according to the order of signal values ​​is also illustrated. mod This figure illustrates the cumulative effect of the applied discrete signal on frequency modulation.

[0053] In this way, even in the case of a modulated wave composed of continuous discrete signal values ​​of the same magnitude but different signs, the length (T) at which the sum of the accumulated signal values ​​from the starting point first becomes 0 can be determined, as illustrated in the figure. 1cy_x And when that length ends, the corresponding frequency modulation amount (total phase change) becomes 0 again, making the length up to that length (T) 0. 1cy_x A series of signal values ​​can be called a modulation wave unit.

[0054] Figure 3aThe illustrated modulated wave set 30 includes all modulated wave units with different time lengths and signal formats, but the modulated wave set can also be configured to differ only in time length or only in signal format; the technical concept and spirit of the present invention can also be realized through such an embodiment. Furthermore, although not illustrated in the modulated wave set 30, Figure 3b or Figure 3c The modulation wave unit described as an example in the example can naturally also be included in this set. Alternatively, the modulation wave set 30 can be configured as follows: Figure 3b or Figure 3c The modulated wave unit is described as an example in the text.

[0055] Therefore, the set of modulated waves 30 mentioned in the following description is based on those with Figures 3a to 3c The example described above allows for the selection of multiple arbitrary modulation waves within the modulation wave unit.

[0056] Figure 4a and Figure 4b This is a diagram illustrating the configuration and method for determining and applying a modulation profile from a modulated wave set 30. The configuration for determining and applying the modulation profile is implemented on the side that provides the transmission clock in the data communication between the two levels, and includes a profile determiner 11, an SSC controller 10, and a modulation controller 12.

[0057] The configuration file determiner 11 can be data recorded in the circuit or data manually set and encoded externally for components such as DIP switches. This data corresponds to the identifiers of a series of modulation wave units in the modulation wave set 30. The term "modulation sequence" is used herein to refer to the data 11a corresponding to the identifiers of a series of modulation wave units.

[0058] When including Figure 4a When the device in the illustrated configuration is started, the SSC controller 10 refers to the modulation wave data of the configuration file determiner 11, reads the modulation wave units corresponding to the identifiers in the order specified in the modulation wave data, and sets them in the modulation controller 12. Figure 4b Suppose that the series of modulation wave unit identifiers indicated by the modulation wave data of the configuration file determiner 11 are “11, N3, 21, N2, 13…” (11a), and through the operation of the SSC controller 10 described above, the signal 40, which is sequentially created by the modulation wave units corresponding to each identifier, is set as the modulation configuration file in the modulation controller 12.

[0059] like Figure 4bAs illustrated in the example, unlike conventional methods that spread the spectrum of repeating modulated wave units, the modulation profile applied to the modulation controller 12 according to this embodiment repeats the modulation period in units of modulated wave unit groups specified by the modulation sequence determined by the profile determiner 11. Furthermore, since the modulated signal fluctuates irregularly within this modulation period, the spread of the clock in the spectrum can be greatly increased compared to conventional spread spectrum clocks that apply repeating modulated wave units.

[0060] The following section will describe in detail the application. Figure 4a and Figure 4b The data transmission and reception configuration illustrated in the example uses a non-repetitive modulation profile to extend the clock spectrum.

[0061] Figure 5a This is a block diagram illustrating the configuration of a data transmitter 100 according to an embodiment of the present invention. The illustrated transmitter 100 includes a profile determiner 11 and a modulation wave set 30 as described above, and these components perform setting operations as described above for expanding the clock spectrum into a non-repetitive modulation profile. The modulation controller 112 and SSC controller 110 constituting the transmitter 100 perform the setting operations described above for expanding the clock spectrum, and according to the embodiment, further perform other operations. These operations are described in detail in the corresponding sections.

[0062] The illustrated transmitter 100 includes: a PLL 310 that generates a clock whose phase matches a control signal applied from a modulation controller 112; a channel modulator 40 that modulates an input bitstream in a predetermined manner to match the channel for transmission; a transmit driver 30 that captures and outputs the output signal of the channel modulator 40 in synchronization with the output clock of the PLL 310; and a MUX 113 that selects one of a plurality of inputs and applies it to an input terminal of the channel modulator 40.

[0063] Furthermore, the PLL 310 includes: a phase interpolator 311 that adjusts the clock phase according to a control signal applied to the phase interpolator; and a clock generator 312 that generates a clock whose phase has been adjusted by the phase interpolator 311. The channel modulator 40 includes: a pseudo-random encoder 41 that is synchronized with the output clock of the PLL 310 and pseudo-randomizes the input bit stream based on an arbitrarily set pseudo-random sequence; and a PAM mapper 42 that is synchronized with the output clock of the PLL 310 and amplitude modulates the encoded bits output by the pseudo-random encoder 41 with a predetermined symbol unit.

[0064] The channel modulator 40 of transmitter 100 is illustrated together as an example to facilitate understanding of the specific description of embodiments of the invention and is not configured to have a direct relationship with the spread spectrum clock to which the technical principles and concepts of the invention are applied. Therefore, any configuration of the channel modulator that is configured to transmit input data to another party can be applied to transmitter 100 illustrated for the purpose of explaining the invention.

[0065] According to an embodiment of the present invention, the receiver corresponding to the transmitter 100 can be as follows: Figure 5b The illustrated configuration is as follows. The illustrated receiver 200 is also configured to include a modulation controller 212 and an SSC controller 210, and these controllers directly perform the modulation profile setting operations for extending the clock spectrum as described above using the profile determiner 11 and the modulation set 30 provided with the receiver.

[0066] In addition to these configurations, receiver 200 also includes PLL 320, which is configured similarly to PLL 310 of transmitter 100 and performs similar functions. The only difference between PLL 320 and PLL 310 of transmitter 100 is that the internal phase interpolator 321 performs phase adjustment with a clock that is phase-synchronized with the clock recovered from the received signal.

[0067] The receiver 200 is also configured to include: an AD converter 50 that converts signals on the transmission channel into digital signals in sync with the output clock of the PLL 320; an equalizer 60 that compensates for amplitude and phase distortion of the digitally converted signals; and a clock / data recovery unit 70 that recovers the clock and data from the equalized digital signals.

[0068] According to an embodiment of the invention, when the transmitter 100 and receiver 200 configured as described above are powered on and started, each of the SSC controllers 110 and 210 sets the configured modulation profile in the modulation controllers 112 and 212 by referring to the modulation sequence set by the profile determiner 11 as described above.

[0069] Upon completion of the modulation profile setup, the SSC controller 110 of transmitter 100 activates the channel modulator 40. The channel modulator 40 can be activated regardless of the modulation profile settings. When the channel modulator 40 is activated, the pseudo-random encoder 41 generates a pseudo-random sequence from the set code, and this sequence is modulated by the PAM mapper 42 and begins to be transmitted to the transmission channel. The pseudo-random sequence transmitted in this manner includes a special bit stream agreed upon as a synchronization pattern in the transmission channel.

[0070] In this initial state, since a modulation start signal has not yet been applied from the SSC controller 110, the modulation controller 112 does not apply a control signal (hereinafter referred to as the "phase adjustment signal") to the phase interpolator 311 for adjusting the clock phase. That is, the phase adjustment signal remains 0. Therefore, the clock of the PLL 310 remains at the set frequency (F...). o ).

[0071] The pseudo-random sequence signal 113 transmitted by the transmission channel experiences a delay (T) that depends on the length of the transmission channel. TD (This delay is referred to as the "propagation delay"), and then reaches receiver 200. The signal is recovered into a digital signal by AD converter 50. Synchronization detector 80 determines the correlation of a predetermined synchronization pattern signal with the recovered digital signal and searches for synchronization pattern segments accordingly. When a segment is found, it notifies SSC controller 210 of the segment.

[0072] Meanwhile, the SSC controller 110 of transmitter 100 synchronizes the pattern transmission at the time point (t) when the pattern transmission is completed. S_E A modulation start signal is applied to the modulation controller 112 (which can be determined from the activation time of the channel modulator 114). Therefore, the modulation controller 112 applies a phase adjustment signal to the phase interpolator 311 of the PLL 310 according to the modulation waveform 401 determined by a previously set modulation profile. The phase interpolator 311 adjusts the rate of change of the clock phase lead or lag according to the signal value of the phase adjustment signal and notifies the clock generator 312 of the time point corresponding to the phase determined according to the current rate of change, so that the clock is output at that time point. According to this method, a clock with a frequency varying according to the modulation waveform is output from the PLL 310.

[0073] In receiver 200, when synchronization detector 80 notifies a synchronization pattern segment, SSC controller 210 at the time point corresponding to the completion of that segment (t... R_E A modulation start signal is applied to the modulation controller 212. Therefore, frequency modulation of the clock is started in the same manner as that of the transmitter 100.

[0074] In the modulation of the clock frequency initiated from transmitter 100 and receiver 200, a propagation delay time (T) exists due to the signal delay of the transmission channel. TD The time difference. However, since the bit stream 124 transmitted from transmitter 100 in sync with the frequency-varying transmission clock experiences the same propagation delay time (T) in the transmission channel. TD The signal then reaches receiver 200, and the time difference is canceled out by the modulation waveform 402 of the modulation profile used to modulate the clock in the receiver.

[0075] Therefore, at any point in time (t) during the reception of the bit streamDR ), due to the modulation point (S) used for frequency modulation PMW The change in clock frequency caused by ) is related to the time point (t) when the data bit stream is transmitted. Ds Modulation waveform used for frequency modulation 40 I The resulting frequency change (Δf) Sp The same as the clock frequency used in the transmitter 100 for the bit stream. That is, in the receiver 200, the exact same clock frequency (=F0+Δf) is used. Sp The clock signal is used to obtain the data bit stream signal from the transmission channel.

[0076] Frequency modulation of the clocks in the transmitter and receiver may not begin from the point in time when the synchronization pattern is completed, but rather from the point in time immediately following the synchronization pattern after a specified time interval has elapsed.

[0077] In the above embodiment, the receiver 200 is also provided with a profile determiner 11, which, similar to the transmitter 100, sets the same modulation sequence as the transmitter for expanding the clock spectrum. In another embodiment according to the invention, a receiver without a profile determiner 11 can be configured. In this embodiment, a modulation sequence for determining the modulation profile is received from and used by the peer transmitter 100. The following will be based on... Figure 5b The prerequisite for removing the configuration file determiner 11 from the receiver block diagram is described in detail below.

[0078] Figure 7 The process of sending information about the modulation profile to the receiver according to this embodiment is illustrated schematically.

[0079] When powered on, the SSC controller 110 of transmitter 100 activates at a specified time point (t). NgSt The modulation sequence confirmed by the configuration file determiner will be configured as configuration file information 61. This time point is within the period from the transmission of synchronization pattern 60 to the transmission channel after the activation of channel modulator 40 as described above until the completion of channel training operation (LS). T This time (referred to as the "link establishment time") is recorded, and the configuration file information is input into MUX 113 so that it can be sent to the transmit channel via channel modulator 40. This initiates the modulation configuration file sharing operation.

[0080] The signal carrying the configuration information 61 on the transmission channel has a propagation delay time (T). TDThe signal then reaches receiver 200 and is restored to a digital signal by AD converter 50. Distortion in the transmission channel is compensated by equalizer 60 and converted into a data stream by data decision unit 90. The data stream determined by data decision unit 90 is even sent to SSC controller 210.

[0081] The receiver's SSC controller 210 confirms the modulation sequence of the configuration file information from the received data stream, and sequentially reads the corresponding modulation wave unit from its own modulation wave set 30 according to the confirmed modulation sequence, and sets the modulation configuration file in the modulation controller 212. Simultaneously, it configures a response message 62 notifying normal receipt of the configuration file information and sends it to the transmission channel. Of course, the transmission of the response message is based on the premise that the transmission channel supports bidirectional communication in full-duplex or half-duplex mode.

[0082] The transmission of response information 62 is based on the following premise: receiver 200 is equipped with components for data transmission, such as channel modulator 40, transmit driver 20, etc., as in transmitter 100, and transmitter 100 is equipped with components for data reception, such as equalizer 60, data decision unit 90, clock / data recovery unit 70, etc., as in receiver 200. If receiver 200 and transmitter 100 are not equipped with these components, SSC controller 110 sends configuration file information to the transmit channel, and SSC controller 210 sets the modulation configuration file to modulation controller 212 according to the received modulation sequence, thereby completing the modulation configuration file sharing operation.

[0083] If the SSC controller 110 of transmitter 100 receives the response sent for the configuration file information normally, it records that the sharing of the modulation configuration file is successful and completes the modulation configuration file sharing operation.

[0084] Even if modulation profile sharing is successfully completed, the corresponding SSC controllers of transmitter 100 and receiver 200 will not initiate clock frequency modulation, but will wait until the link establishment time (LST) ends. T When ) is completed, at that time point (t) i Each SSC controller applies a modulation start signal to the modulation controller of the corresponding device, thereby initiating frequency modulation of the clock in each of the transmitter 100 and the receiver 200 based on the same modulation profile.

[0085] Link establishment time (LS) T The time (LS) is the same in both the transmitter and receiver, and the time (LS) is the same. T The start is based on synchronization pattern 60. During the propagation delay time (T... TDThe receiver 200, which subsequently receives the synchronization pattern, has a reference time that is delayed by the propagation delay time (T) compared to the transmitter 100. TD In other words, the time point at which clock frequency modulation is initiated is also delayed by the propagation delay time (T) compared to the time at which the transmitter is activated. TD (t2=t1+T) TD Therefore, when the bit stream emitted from transmitter 100, synchronized with the transmission clock 601 of the modulation frequency at any point in time, undergoes a propagation delay time (T), TD When the signal reaches the receiver, the receive clock 602, which is modulated at the same frequency as the transmit clock, is used to restore the signal of the bit stream on the transmit channel to a digital signal.

[0086] As mentioned above, data communication can be unidirectional, from transmitter to receiver, but it can also be bidirectional. For bidirectional communication, all components for sending and receiving must be included, and in this specification, a device configured in this way is referred to as a "transceiver". Figure 8 This is a block diagram illustrating the configuration of a transceiver according to an embodiment of the present invention.

[0087] The transceiver 400's Tx modulation controller 411 (its configuration is as follows) Figure 8 The transceiver 100 (as shown) performs the same function as the modulation controller 112 of the transmitter 100 described above, the Rx modulation controller 412 performs the same function as the modulation controller 212 of the receiver 200 described above, and the SSC controller 410 performs the combined function of each SSC controller of the transmitter 100 and the receiver 200. That is, it controls the initiation of frequency modulation of the transmit clock (T-clock) of the Tx modulation controller 411 and the initiation of frequency modulation of the receive clock (R-clock) of the Rx modulation controller 412, respectively. When both transceivers communicating with each other include a profile determiner 11, as shown in the reference... Figure 6 As explained, a modulation start signal is applied to each of the Tx modulation controller 411 and the Rx modulation controller 412. When only one of the two transceivers includes the profile determiner 11, the process described in the reference is also executed. Figure 7 The explained modulation profile sharing operation.

[0088] Furthermore, the modulation sequence set by the configuration file determiner 11 or the modulation configuration file determined based on the shared configuration file information is publicly set to the Tx modulation controller 411 and the Rx modulation controller 412, and together they are used to modulate the transmit clock (T-clock) and the receive clock (R-clock).

[0089] One of the two transceivers performs the function of controlling the channel used for data transmission. In this specification, the transceiver having this channel control function is referred to as the "master transceiver," and the other transceiver not having this function is referred to as the "sub-transceiver." If only one of the two transceivers sharing a modulation profile between them via communication includes the profile determiner 11, it is assumed that the profile determiner is located in the master transceiver. This assumption is only for ease of explanation. Considering the changes due to differences in the entities providing and receiving profile information, the following description of embodiments of the invention based on the above assumption can also be directly applied to embodiments where the profile determining unit is located in the sub-transceiver.

[0090] If two transceivers are 400 (with the following configuration) Figure 8 (As shown) If the transmission channels used for communication between the two transceivers support full-duplex transmission mode, then for each of the channels transmitted from the master transceiver to the slave transceiver and from the slave transceiver to the master transceiver, the initiation of transmit clock and receive clock modulation can be determined by whether the configuration file determiners of the two transceivers are set to reference. Figure 6 or Figure 7 Perform in the same manner as described.

[0091] In an implementation where communication between two transceivers must be performed in half-duplex mode, the modulation initiation of the transmit and receive clocks (T-clock, R-clock) for the time slot channel (hereinafter referred to as "downlink time slot") transmitted from the master transceiver to the slave transceiver and the time slot transmitted from the slave transceiver to the master transceiver (hereinafter referred to as "uplink time slot") is as follows. Figure 9 This is illustrated schematically.

[0092] For reference Figure 7 The same manner described is used to perform configuration file sharing between the SSC controller 410 of the master transceiver and the SSC controller 410 of the slave transceiver, which are equipped with configuration file determiners, and modulation initiation based on the shared modulation configuration file for the master transceiver's transmit clock (T-clock) and the slave transceiver's receive clock (R-clock).

[0093] For the transmit clock (T-clock) of the sub-transceiver, the SSC controller 410 of the sub-transceiver has elapsed a specified waiting time (T) since the point in time when it transmitted the response information 621 for the configuration file information received from the master transceiver via the uplink channel. ST_INT ) time point (t) 22 ), and apply a modulation start signal to the Tx modulation controller 411 to start modulation.

[0094] The master transceiver's receive clock (R-clock) is activated based on receiving response information 621 from the slave transceiver. When the master transceiver's SSC controller 410 receives response information 621 from the time the reception was completed, a waiting time (T) has elapsed since the time of reception completion. ST_INT ) time point (t) 12 ), and apply a modulation start signal to the Rx modulation control unit 412 to start modulation.

[0095] Waiting time (T) ST_INT ) can be set to any value, such that the time point at which this time ends (t) 22 The point in time that coincides with the end of the aforementioned link establishment time (LST) and the time slot (TS) of the uplink channel in the half-duplex transmission channel. UP Between the start time points.

[0096] In addition, the waiting time (T) ST_INT It can also be determined based on other types of messages besides response message 621. For example, the waiting time (T) ST_INT It can be specified based on the link state transition progress message sent to the master transceiver to notify it when the sub-transceiver completes link establishment.

[0097] Since the modulation of the receive clock (R-clock) in the master transceiver, as described above, is determined based on the timing of the data received from the sub-transceiver, this modulation start time is delayed by the propagation delay time (T0) relative to the modulation start time of the sub-transceiver's transmit clock (T-clock). TD However, when an uplink time slot (TS) is generated... UP ) time (t) 23 The modulation profile (mP) applied at that point in time to perform frequency modulation on the transmit clock used by the sub-transceiver to transmit the bit stream. u_Tx The points on the main transceiver are the modulation profiles (mP) used in the main transceiver for receiving clock frequency modulation. u_Rx In the propagation delay time (T) TD This occurs afterward. Therefore, a clock 902 with the same frequency as the clock 901 used for transmitting the corresponding bit stream is used to receive the bit stream.

[0098] The above implementation scheme is configured such that the transmit clock of the sub-transceiver for transmitting bit streams operates independently of the receive clock.

[0099] Not limited to these embodiments, the method for extending the clock spectrum according to the present invention can also be applied to sub-transceivers that use a receive clock recovered from the received bit stream as a transmit clock. The method of using the receive clock as the transmit clock is called "loop timing," and the following describes the application of the method for extending the clock spectrum to transceiver pairs employing this loop timing.

[0100] According to an embodiment of the present invention, the configuration of the master transceiver with loop timing is applied. Figure 8 The transceiver 400 illustrated has the same configuration. However, some functions of the SSC controller 410, more specifically, the determination of the timing for applying the modulation start signal to the Rx modulation controller 412, are different. This will be described below.

[0101] According to an embodiment of the present invention, a sub-transceiver employing loop timing can, as follows: Figure 10 The configuration is illustrated. In this embodiment, the sub-transceiver 510 does not have a PLL for the transmit clock and is configured to directly use the receive clock (more specifically, a clock synchronized with its own receive clock) recovered from the clock / data recovery unit 70 for data transmission. That is, it is configured such that the recovered receive clock is also applied to the channel modulator 40 and the transmit driver 20.

[0102] The method for determining the timing of the SSC controller 410 of the sub-transceiver 510 setting the modulation profile and applying the clock modulation start signal to the modulation controller 212 is the same as described above. That is, at a specific time point determined based on the time point at which the synchronization pattern is detected from the transmit channel, the modulation start signal is applied to the modulation controller 212.

[0103] like Figure 11 As shown, the SSC controller 410 of the main transceiver 400 (its configuration is as follows) Figure 8 As shown, the start time point (t) of frequency modulation based on the transmit clock (T-clock) st_T The modulation start time of the receive clock (R-clock) is determined by [the following]. The frequency modulation start time of the transmit clock (T-clock) is [the following]. st_T The determination of ) shall be carried out in the same manner as the above implementation plan.

[0104] For the receive clock (R-clock), the loop time (T) has elapsed since the time point at which the modulation start signal is applied to the Tx modulation controller 411. IP When ), the SSC controller 410 is at time point (t) st_R A modulation start signal is applied to the Rx modulation controller 412. As illustrated in the figure, the loop time (T) IPDIt is determined by two time elements, one of which is the interval time between signals (T). TR_Gap The other is the state transition time (T) of the sub-transmitter 510. st_Tr More specifically, the transition time from receiving to sending.

[0105] like Figure 11 As illustrated, for the interval time (T) between signals TR_Gap SSC controller 410 measures the time point (t) from the completion of transmission of any message 11011 sent to sub-transceiver 510 during the link establishment time. TE ), until the time point when message 11012 (more specifically, the frame that sent the message) begins to be received (t Rs The time interval between signals. If half-duplex bidirectional communication is used between the master transceiver and the slave transceiver, the time from the end of the downlink time slot for sending any message to the receipt of that message on the uplink channel can be used as the interval time (T) between signals. TR_Gap ).

[0106] Furthermore, the value set in the master transceiver 400 is used as the state transition time (T). st_Tr This value can be recorded as data in the device's SSC controller 410, or it can be a value set in components such as DIP switches. Alternatively, it indicates the state transition time (T). st_Tr The value of ) can be set in the sub-transceiver 510 and sent to the SSC controller 410 of the master transceiver 400 through information messages that are mutually communicated during the link establishment time.

[0107] State transition time (T) stm This corresponds to the processing time immediately following the detection of the end of the downlink time slot by the sub-transmitter 510 on the transmission channel until it begins transmitting its own data stream to the transmission channel. Therefore, the time required for data to travel purely round trip on the transmission channel (i.e., the loop time (T)) 1pD This is achieved by analyzing the signal gap time (T). TR_Gap Subtract the state transition time (T) from the original text. St_Tr The time is obtained by using the master transceiver 400's transmit clock (T-clock) as a delay relative to the transmit clock (T-clock) by the time it takes for the clock to be recovered through loop timing and returned to the sub-transmitter 510 (T). 1pD ).

[0108] Therefore, when the SSC controller 410 calculates the loop time (T) as described above before initiating frequency modulation of the transmit clock (T-clock), 1pD Then, when a modulation start signal is applied to the Tx modulation controller 411, it starts from that point (t). st_TThe calculated loop time (T) has elapsed since then. lpD ) time (t) st_E Apply a modulation start signal to the Rx modulation controller 412.

[0109] By starting the frequency modulation of the receive clock (R clock) in this way, even a master transceiver 400 with loop timing can receive the bit stream as a clock whose frequency is completely synchronized with the clock synchronized during transmission.

[0110] In the above description of the method of extending the clock spectrum by applying loop timing, the master transceiver 400 and the slave transceiver 510 are configured differently from each other, but for the manufacturing efficiency of the communication equipment, the two transceivers can be configured in the same way. Figure 12 This is a block diagram of the transceiver 500 configured according to this implementation scheme.

[0111] Figure 12 The transceiver 500 can be used as a master transceiver or a slave transceiver with loop timing applied, and also includes a MUX 115, which selects one of two input clocks (clock1, clock2) and outputs it as the transmit clock (T-clock), thus being selectively applied to the transmit clock (T-clock) applied to the channel modulator 40 and the transmit driver 20. In the MUX 115, a first clock (clock1) is input to the PLL 310, which phase-modulates an oscillating clock recovered from the received data stream and synchronized with that clock according to the modulation profile, and outputs the phase-modulated oscillating clock.

[0112] In addition, a selection signal is applied to the MUX 115 to select the input terminal. This selection signal uses an operating mode value to set whether the transceiver operates as a master transceiver or a slave transceiver. This operating mode value can be specified by components such as jumpers configured in the transceiver 500 circuitry, which can selectively set specific values ​​for the transceiver. If the operating mode value is specified as "master mode," the MUX 115 is configured to output a first clock (clock1); if it is specified as "slave mode," the transceiver 500 is configured to output a second clock (clock2).

[0113] Furthermore, the transceiver 500 is also equipped with circuitry that allows operating mode values ​​set by components to be applied to the SSC controller 410. Therefore, if the applied operating mode value corresponds to "master mode," the SSC control unit 410 executes actions such as... Figure 11 The operation of applying a modulation start signal to the Rx modulation controller 412 is explained based on loop time calculation and the calculated loop time; if it is a "sub-mode", it is configured not to perform this operation.

[0114] Meanwhile, in the above implementation scheme, in the master transceiver that uses loop timing, the loop time (T) 1PD ) is from the preset state transition time (T) St_Tr The state transition time (T) is determined in advance and is used to determine the application timing of the modulation start signal of the receive clock (R-clock). However, in another embodiment of the invention, even if the state transition time (T) is unknown in advance... St_Tr It can also perform clock frequency modulation based on the delay time of the clock returned from the sub-transceiver via loop timing. Figure 13 This is an example of a block diagram of the master transceiver 600 configured for this implementation scheme.

[0115] The main transceiver 600 further includes: a modulation delay unit 612 configured to dynamically delay and output a phase adjustment signal for frequency modulation output from the Tx modulation controller 411 according to a delay control signal applied to the modulation delay unit; and an SCC tracker 611 configured to adjust the delay control signal according to the signal-to-noise ratio of the received data stream, wherein the SSC controller 610 also has the function of controlling the SSC tracker 611.

[0116] Figure 14 This is an example of frequency modulation timing for the receive clock (R-clock) in the master transceiver 600 according to an embodiment of the present invention, and illustrates finding and applying frequency modulation timing that matches the receive clock (R-clock) returned via loop timing. This modulation timing search process can be performed during the link establishment time described above.

[0117] The SSC controller 610 first, as described above, determines the time interval (T) between signals. TR_Gap Then, when the interval time between signals (T) was confirmed... TR_Gap At the same time, a modulation start signal (t) is applied to both the Tx modulation controller 411 and the SSC tracker 611. st When a modulation start signal is applied to the SSC tracker 611, the time interval between the obtained signals (T) is... TR_Gap The information was sent.

[0118] When a modulation start signal is applied, the SSC tracker 611 will record the interval time (T) between signals transmitted during the application period. TR_Gap ) as the initial delay time (D oThe modulation delay unit 612 is set, and dynamic delay operation is initiated. Therefore, the phase adjustment signal for frequency modulation of the transmit clock (T-clock) output by the Tx modulation controller 411 is delayed by an initial delay time (D0) by the modulation delay unit 612, and then the phase of the PLL 320 (t) applied to the synchronous receive clock (R-clock) is started. d_st0 ).

[0119] Furthermore, the SSC tracker 611, from the initial delay time (D... o The preset test period (T) starts from a past point in time. test Within this period, equalizer 60 is used to confirm the signal-to-noise ratio of the data stream received from the peer transceiver, and the corresponding period (T) is recorded. test The average value (SNR0) (14111). Simultaneously, it applies a delay time setting of the modulation delay unit 612 to the delay time (D) after reducing the preset resolution gap (ΔdT). i The delay control signal of the phase control signal output by the Tx modulation controller 411 is shortened by the delay amount of the resolution gap (ΔdT) and begins to be applied to the PLL 320 (t). d_st1 ).

[0120] After adjusting the delay time of the modulation delay unit 612, the SSC tracker 611 performs the following test cycle (T). test During this period, confirmation is received from equalizer 60 (i DNR The signal-to-noise ratio (SNR) of the received data stream is recorded, and the average value (SNR1) within that period 14112 is recorded. Then, if an average value of the previously recorded SNR exists, the average value (SNR1) is calculated. o The signal-to-noise ratio (SNR) is compared with the average value (SNR1) just obtained. In this comparison, if it is confirmed that the average value (SNR1) of the currently obtained signal-to-noise ratio is higher than the previous average value (SNR0), the SSC tracker 611 further performs the above test method in the next test cycle.

[0121] The above description of each test cycle (T) test During the operation, if the currently obtained average signal-to-noise ratio (SNR) is confirmed... k () lower than the previously obtained average signal-to-noise ratio (1412) k+1 Then the SSC tracker 611 will modulate the delay time (D) set by the modulation delay unit 612. k-1 Reset to a time longer than the current delay (D) kA certain resolution gap (ΔdT) is defined (1413). Thus, the modulation profile of the clock used for synchronously transmitting the data stream is applied to the frequency modulation of the received clock to perfectly match the delayed clock returned according to the loop timing.

[0122] In an embodiment of the present invention, the search for modulation delay time described above can be repeated multiple times, and the modulation delay time with the highest frequency is finally applied to the modulation delay unit 612 to complete the modulation timing search process.

[0123] In the above implementation scheme, the signal gap time (T) is set in the initial stage. TR_Gap The initial delay time is set as the delay time in the modulation delay unit 612, and then the delay time is reduced by the resolution gap (ΔdT) to find the modulation delay time. However, the modulation delay time can also be found in the reverse way. That is, after setting an arbitrarily set initial delay time (which can be zero) for the modulation delay unit 612, in each test cycle (T... test The modulation delay time can be found by adding the delay time of the resolution gap (ΔdT) of the modulation delay unit 612.

[0124] Meanwhile, when a pair of transceivers is configured to use loop timing, even if the transceiver that generates its own transmit clock performs frequency modulation on the transmit clock using a repetitive modulation wave unit, the modulation timing search process described above can naturally be applied to find and set the modulation timing of the receive clock.

[0125] The method for extending the spectrum of the data transmission clock according to the present invention, various embodiments of the device for the method, and the configurations and operations described in the embodiments (as specifically described so far) can be selectively combined and implemented in various ways, provided that they do not contradict each other.

[0126] The embodiments of the present invention described above are for illustrative purposes. Those skilled in the art will understand that various improvements, modifications, substitutions or additions can be made to the embodiments without departing from the technical spirit and scope of the invention as disclosed in the appended claims.

[0127] Explanation of reference numerals in the attached figures

[0128] 10, 110, 210, 410, 610: SSC controller

[0129] 11: Configuration File Determiner

[0130] 11a: Modulation sequence

[0131] 12, 112, 212, 312: Modulation controller

[0132] 20: Send driver

[0133] 40: Channel modulator

[0134] 41: Pseudo-random encoder

[0135] 42: PAM Mapper

[0136] 50: AD converter

[0137] 60: Equalizer

[0138] 70: Clock / Data Recovery Unit

[0139] 80: Synchronization Detector

[0140] 90: Data Decision Unit

[0141] 100: Transmitter

[0142] 113: MUX

[0143] 200: Receiver

[0144] 310, 320: PLL

[0145] 311, 321: Phase interpolators

[0146] 312, 322: Clock generator

[0147] 400: Transceiver

[0148] 411: Tx Modulation Controller

[0149] 412: Rx modulation controller

[0150] 500: Transceiver

[0151] 510: Sub-transceiver

[0152] 600: Master transceiver

[0153] 611: SSC Tracker

[0154] 612: Modulation Delay Unit

Claims

1. A device that performs data communication with a peer device via a transmission channel, the device comprising: a PLL configured to modulate a frequency of a clock used for synchronizing communication data according to a modulation signal applied to the PLL and output, a first controller configured to generate the modulation signal according to a modulation waveform that is a successive form of a plurality of modulation pulses determined by a modulation profile set, and apply the modulation signal to the PLL, a main controller configured to control the first controller so that applying the modulation signal to the PLL is initiated, wherein the modulation pulse is a signal whose sum of signal values becomes zero for the first time within a time length thereof, and wherein at least two successive modulation pulses of the plurality of modulation pulses differ from each other in at least one of the time length and the form of the signal.

2. The device according to claim 1, wherein: the main controller is configured so that a waveform having a successive form in order of modulation pulse identifiers each corresponding to a series of modulation pulse identifiers is set as the modulation profile in the first controller.

3. The device according to claim 2, wherein: the main controller is configured to confirm the series of modulation pulse identifiers from data encoded by a component provided in the device.

4. The device according to claim 2, wherein: the main controller is configured to receive information on the series of modulation pulse identifiers from the peer device.

5. The device according to claim 1, wherein: the clock is a clock used for capturing and receiving a signal carried on the transmission channel as a digital signal.

6. The device according to claim 5, wherein: the main controller is configured to control the first controller so that applying the modulation signal to the PLL is initiated at a point of time that elapses a predetermined time from a point of time at which a specific pattern is detected on the transmission channel.

7. The device according to claim 5, wherein: the main controller is configured to control the first controller so that applying the modulation signal to the PLL is initiated at a point of time that elapses a predetermined time from a point of time at which a message of specific information is received from the peer device.

8. The device according to claim 7, wherein: the specific information is information that informs that information on the plurality of modulation pulses has been successfully received.

9. The device according to claim 5, wherein: the device is configured so that the clock is also available for transmitting a data stream to the transmission channel, the data stream being used for transmission to the peer device.

10. The device according to claim 9, the device further comprising: a second PLL configured to modulate a frequency of a second clock used for synchronizing the data stream transmitted to the peer device according to a modulation signal applied to the second PLL and output, and The MUX selects one of the clock and the second clock according to a specified mode and outputs the selected clock for synchronizing the data stream sent to the transmission channel. The mode is specified by a component in the device that is configured by circuitry and can selectively set specific values.

11. The device according to claim 1, wherein: The clock is used to send a data stream to the transmission channel, and the data stream is used to send to the peer device.

12. The device according to claim 11, further comprising: A second PLL, configured to modulate and output the frequency of a second clock recovered from a digital signal according to a second modulation signal applied to the second PLL, the second clock being used to capture and receive digital signals from signals carried on the transmission channel, and A second controller is configured to generate the second adjustment signal based on the modulation waveform and apply the second adjustment signal to the second PLL. The main controller is further configured to control the second controller such that, after a loop time has elapsed since the first controller initiated the application of the adjustment signal to the PLL, the second adjustment signal is initiated to be applied to the second PLL, and... The master controller is configured to determine the loop time based on the time interval from the moment a message is sent to the peer device to the moment the message is started being received from the peer device.

13. The device according to claim 12, wherein: The master controller is configured to determine the loop time as the time obtained by subtracting the previously confirmed receive / transmit switching time of the peer device from the time gap.

14. The device according to claim 11, further comprising: A second PLL, configured to modulate and output the frequency of a second clock recovered from a digital signal according to a second modulation signal applied to the second PLL, the second clock being used to capture and receive digital signals from signals carried on the transmission channel. Delay unit, configured to delay the adjustment signal by a delay time according to a delay control signal applied to the delay unit, and output it as the second adjustment signal, and A tracker configured to adjust the delay time of the adjustment signal in the delay unit based on the signal-to-noise ratio of the data stream recovered from the digital signal, and to apply a delay control signal corresponding to the adjusted delay time to the delay unit.

15. The device according to claim 14, wherein: The tracker is configured to: confirm the signal-to-noise ratio of the recovered data stream for each specified interval, and when the currently confirmed second signal-to-noise ratio is lower than the previously confirmed first signal-to-noise ratio, reapply the delay control signal applied to the delay unit when the first signal-to-noise ratio was obtained, and complete the adjustment of the delay time of the delay unit.

16. The device according to claim 14, wherein: The tracker is configured to apply an initial delay time to the delay unit from the time interval immediately following the sending of a message to the peer device to the time when the message is first received from the peer device, and then adjust the delay time to be shorter than the previous delay time each time the delay time is adjusted.

17. The device according to claim 14, wherein: The tracker is configured to apply a predetermined time as an initial delay time to the delay unit, and then adjust the delay time to a longer delay time each time the delay time is adjusted.

18. The apparatus according to claim 11, wherein: The main controller is configured to apply the control signal to the first controller, the control signal causing the adjustment signal to be applied to the PLL at a predetermined time point after the time point from the time point when the signal of the specific pattern is transmitted through the transmission channel.

19. An apparatus for performing data communication with a peer device via a transmission channel, the apparatus comprising: The PLL is configured to modulate and output the frequency of a clock used for synchronizing communication data according to an adjustment signal applied to the PLL. A second PLL, configured to modulate and output the frequency of a second clock recovered from a digital signal according to a second modulation signal applied to the second PLL, the second clock being used to capture and receive digital signals from signals carried on the transmission channel. A first controller is configured to generate a first adjustment signal based on a modulation waveform and apply the first adjustment signal to a first PLL, wherein the modulation waveform is a continuous form of multiple modulation wave units determined by a set modulation profile. A delay unit is configured to delay the first adjustment signal by a delay time according to a delay control signal applied to the delay unit, and output the delay signal as the second adjustment signal. A tracker configured to adjust the delay time of a first adjustment signal in a delay unit based on the signal-to-noise ratio of a data stream recovered from the digital signal, and to apply a delay control signal corresponding to the adjusted delay time to the delay unit. A main controller is configured to control the first controller to initiate the application of the first adjustment signal to the first PLL, and is configured to include the signal in which the sum of the signal values ​​first becomes zero within its time length, and is configured to include the main controller being configured to control the tracker to initiate adjustment of the delay time for the first adjustment signal.

20. A method for transmitting data with a peer device via a transmission channel, the method comprising: Step 1: Confirm the set modulation wave data. Step 2: Set the modulation waveform as a modulation profile, wherein the modulation waveform is a form in which multiple modulation wave units indicated by the confirmed modulation wave data are continuously formed, and Step 3: Generate an adjustment signal based on the modulation waveform, and apply the adjustment signal to the PLL, wherein the PLL is configured to modulate and output the frequency of the clock used for synchronizing communication data. The PLL is configured to modulate the frequency of the clock according to the adjustment signal. The modulation wave unit is the signal whose sum of signal values ​​first becomes zero within a time period, and At least two consecutive modulation wave units among the plurality of modulation wave units are different from each other in at least one of the time length and the form of the signal.

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