Dynamic color data format conversion

Abstract

Various embodiments include methods for image compression and decompression. Some embodiments can include identifying a location of image color data of a portion of an image in an interleaved format within a portion of memory; and encoding metadata with a location identifier that describes the location of the image color data of the portion of the image in the interleaved format within the portion of memory, which can be image data format independent. Some embodiments can include decoding metadata with a location identifier configured to describe a location of image color data of a portion of an image in an interleaved format within a portion of memory; and identifying the location of the image color data of the portion of the image in the interleaved format within the portion of memory according to the location identifier.

Description

Background Technology

[0001] Power efficiency is a critical aspect of the operation of many computing devices, especially battery-powered devices with limited power supplies. In some computing devices, image data shared between processing devices can be allocated to static random access memory (SRAM) instead of dynamic random access memory (DRAM). However, image data is formatted, and not all processing devices can efficiently handle all image buffer formats. Summary of the Invention

[0002] Various aspects include systems and methods for image compression that can be performed by a processing system of a computing device. These aspects may include: identifying the location of image color data in an interleaved format within a portion of memory for a part of an image; and encoding metadata with a location identifier configured to describe that location of the image color data in the interleaved format within that portion of memory for that part of the image. In some aspects, encoding the metadata may include encoding image data format-independent metadata.

[0003] Some aspects may also include generating the location identifier based on the location of the image color data in the interlaced format within the portion of the memory for that portion of the image.

[0004] In some aspects, the location identifier may be configured to indicate to the image decoder device that a component of the image color data is one of the following: compressed into a portion of a previous block, begins a block of a first size, begins a block of a second size, or is a first constant value or a second constant value. In some aspects, the location identifier may be configured to indicate to the image decoder device that all components of the image color data are constant values. In some aspects, the location identifier may be configured to indicate to the image decoder device that the first component of the image color data begins a block of a first size, begins a block of a second size, or is a first constant value or a second constant value.

[0005] In some aspects, the image color data of that portion of the image in that portion of the memory in the interlaced format may include compressed image color data for at least one component of the image color data. In some aspects, the image color data of that portion of the image in that portion of the memory in the interlaced format may include multiple components of the image color data, such that each of the multiple components represents either a color value or a transparency value.

[0006] Various aspects include systems and methods for image decompression that can be performed by a processing system of a computing device. These aspects may include: decoding metadata using location identifiers configured to describe the location of image color data in an interleaved format within a portion of memory for a portion of the image; and identifying the location of image color data in an interleaved format within a portion of memory for a portion of the image based on the location identifiers. In some aspects, the metadata may be image data format independent.

[0007] In some aspects, identifying the location of the image color data of the portion of the image in the interlaced format within the portion of the memory according to the location identifier may include: identifying the location of the image color data of the portion of the image in the interlaced format within the portion of the memory according to a value associated with the location identifier, wherein each of the values ​​is configured to represent the location of one of a plurality of components of the image color data of the portion of the image in the interlaced format within the portion of the memory.

[0008] In some aspects, decoding the metadata using a location identifier that is configured to describe the location of the image color data in the interleaved format within the portion of the memory for that part of the image may include: locating values ​​based on the location identifier to determine the positions of multiple components of the image color data in the interleaved format within the portion of the memory for that part of the image.

[0009] In some aspects, decoding the metadata using a location identifier of the location of the image color data in the interleaved format within the portion of the memory, which is configured to describe that part of the image, may include: generating, based on the location identifier, values ​​of the locations of multiple components of the image color data in the interleaved format within the portion of the memory, which are configured to represent that part of the image.

[0010] In some aspects, the location identifier may be configured to indicate to the image decoder device that a component of the image color data is one of the following: compressed into a portion of a previous block, begins a block of a first size, begins a block of a second size, or is a first constant value or a second constant value. In some aspects, the location identifier may be configured to indicate to the image decoder device that all components of the image color data are constant values. In some aspects, the location identifier may be configured to indicate to the image decoder device that the first component of the image color data begins a block of a first size, begins a block of a second size, or is a first constant value or a second constant value.

[0011] In some aspects, the image color data of that portion of the image in that portion of the memory, in the interlaced format, includes compressed image color data for at least one component of the image color data. In some aspects, the image color data of that portion of the image in that portion of the memory, in the interlaced format, may include multiple components of the image color data, such that each of the multiple components represents either a color value or a transparency value.

[0012] Another aspect may include a computing device having a processor configured to perform one or more operations of any of the methods outlined above. Another aspect may include a non-transitory processor-readable storage medium storing processor-executable instructions thereon configured to cause the processor of the computing device to perform operations of any of the methods outlined above. Another aspect includes a computing device having components for performing any of the methods outlined above. Another aspect includes a system-on-a-chip used in a computing device, the system-on-a-chip including a processor configured to perform one or more operations of any of the methods outlined above. Attached Figure Description

[0013] The accompanying drawings, incorporated herein and forming part of this specification, illustrate exemplary embodiments of the claims and, together with the general description given above and the detailed description given below, serve to interpret the features of the claims.

[0014] Figure 1 This is a system block diagram illustrating an example communication system suitable for implementing any of the various implementation schemes.

[0015] Figure 2 This is a component block diagram of an example computing and wireless modem system applicable to any implementation of various implementation schemes.

[0016] Figure 3 This is a component block diagram illustrating a software architecture, including a radio protocol stack for the user plane and control plane in wireless communication, applicable to any implementation of various implementation schemes.

[0017] Figure 4A and Figure 4B This is a block diagram illustrating components of a system configured for image compression and image decompression according to various implementation schemes.

[0018] Figure 5A and Figure 5B It is a component block diagram of example image data formats in memory according to various implementation schemes.

[0019] Figure 6 This is a component block diagram of examples of compressed image data in different image data formats in memory according to some implementation schemes.

[0020] Figure 7 It is a tabular diagram that maps the location identifiers of encoded metadata to values ​​configured to represent the locations of components of image color data, according to some implementation schemes.

[0021] Figure 8 This is a component block diagram of an example of compressed image data, including image data format-independent metadata, in a memory according to some implementation schemes.

[0022] Figure 9 This is a flowchart illustrating a method for image compression that can be executed by a processing system of a computing device according to some implementation schemes.

[0023] Figure 10 This is a flowchart illustrating a method for image decompression that can be executed by a processing system of a computing device according to some implementation schemes.

[0024] Figure 11A This is a flowchart illustrating a method for image compression that can be executed by a processor of a computing device according to some implementation schemes.

[0025] Figure 11B This is a conceptual block diagram illustrating an example of an image data compression mode according to some implementation schemes.

[0026] Figure 11C This is a conceptual block diagram illustrating an example of metadata encoding according to some implementation schemes.

[0027] Figure 11D This is a conceptual block diagram illustrating an example of metadata encoding according to some implementation schemes.

[0028] Figure 12 This is a flowchart illustrating operations that can be executed by a processor of a computing device as part of a method for image compression, according to some implementation schemes.

[0029] Figure 13A This is a flowchart illustrating a method for image decompression that can be executed by a processor of a computing device according to some implementation schemes.

[0030] Figure 13B This is a conceptual block diagram illustrating an example of an image decompression operation according to some implementation schemes.

[0031] Figure 14 It is a component block diagram applicable to network computing devices used with some implementation schemes.

[0032] Figure 15 It is a component block diagram applicable to wireless devices used with some implementation schemes. Detailed Implementation

[0033] Various embodiments will be described in detail with reference to the accompanying drawings. Where possible, the same reference numerals will be used throughout the drawings to refer to the same or similar parts. References to specific examples and embodiments are for illustrative purposes and are not intended to limit the scope of the claims.

[0034] Various implementations include systems and methods for managing data compression and decompression of image data to facilitate access to image data by different processing systems configured for different image data formats. Various implementations can improve the efficiency and utility of computing devices by reducing the processes and energy required by different processors and / or processing systems of a computing device to access stored image data in different image data formats. Various implementations may include image data format-independent metadata (referred to as image data format-independent metadata) having location identifiers configured to describe the location of image color data of a portion of an image in an interleaved format within a portion of memory. Some implementations may include location identifiers configured to describe the location of image color data of a portion of an image in an interleaved format within a portion of memory. Some implementations may include interpreting the location identifiers according to the image data format of the processing system to retrieve image color data of a portion of the image, regardless of the image data format of the image color data of the portion of the image within a portion of memory.

[0035] The term "computing device" as used herein refers to any or all of the following: wireless or wired router devices, server devices and other components of communication networks, wireless or wired electrical appliances, cellular phones, smartphones, portable computing devices, personal or mobile multimedia players, laptop computers, tablet computers, smartbooks, ultrabooks, handheld computers, wireless email receivers, internet-enabled multimedia cellular phones, medical devices and equipment, biosensors / devices, wearable devices (including smartwatches, smart clothing, smart glasses, smart wristbands, smart jewelry (e.g., smart rings, smart bracelets, etc.)), entertainment devices (e.g., wireless game controllers, music and video players, satellite radio components, etc.), wireless network-enabled Internet of Things (IoT) devices (including smart meters / sensors, industrial manufacturing equipment, large and small machines and appliances for home or business use), wireless communication components within autonomous and semi-autonomous vehicles, wireless devices attached to or incorporated into various mobile platforms, GPS devices, and similar electronic devices including memory, wireless communication components, and programmable processors.

[0036] The term "System-on-a-Chip" (SOC) is used herein to refer to a single integrated circuit (IC) chip containing multiple resources and / or processors integrated on a single substrate. A single SOC may contain circuitry for digital, analog, mixed-signal, and radio frequency functions. A single SOC may also include any number of general-purpose and / or special-purpose processors (digital signal processors, modem processors, video processors, etc.), memory blocks (e.g., ROM, RAM, flash memory, etc.), and resources (e.g., timers, voltage regulators, oscillators, etc.). A SOC may also include software for controlling the integrated resources and processors, as well as software for controlling peripheral devices.

[0037] The term "System-in-Package" (SIP) may be used herein to refer to a single module or package containing multiple resources, computing units, cores and / or processors on two or more IC chips, a substrate, or a System-on-a-Chip (SoC). For example, a SIP may include a single substrate on which multiple IC chips or semiconductor dies are stacked in a vertical configuration. Similarly, a SIP may include one or more multi-chip modules (MCMs) on which multiple ICs or semiconductor dies are packaged into a single substrate. A SIP may also include multiple independent SoCs coupled together and packaged in close proximity via high-speed communication circuitry, such as on a single motherboard or in a single wireless device. The proximity of the SoCs facilitates high-speed communication and the sharing of memory and resources.

[0038] The term "packaging" is used herein to refer to a data compression technique used to reduce the number of bits in a data stream of digital information (such as image data or multimedia data) to be stored and / or transmitted, so that the original digital information can be recovered via decompression (sometimes referred to herein as "unpacking") without significantly degrading the quality or fidelity of the original data. Image compression (i.e., image data packing) is widely used in the telecommunications industry, and various data compression or packing techniques are known and used. Several known data packing techniques exist, and the reference herein to "packing type" refers to a specific packing or data compression used for data chunking, which may include tile-based packing techniques that compress data according to tiles or linear-based packing techniques that compress data in a linear manner.

[0039] Power efficiency is a critical aspect of the operation of many computing devices, especially battery-powered devices with limited power supplies. In some computing devices, image data shared between processing devices can be allocated to SRAM instead of DRAM. However, image data is formatted, and not all processing devices in a computing device can efficiently handle all types of image buffer formats.

[0040] The inability to directly process image data formats not configured for a processing device may require additional processing by a device that would otherwise not be configured for those formats. For example, a processing device not configured for an image data format requires a process to convert image data in an unsupported format to a supported format configured for that format. As another example, multiple accesses to image data can be performed by a processing device not configured for an image data format to retrieve all required image data, whereas a processing device configured for an image data format can retrieve all required image data in a single access. Any additional processes required by a processing device not configured for an image data format incur additional costs in terms of power efficiency and execution speed compared to a processing device configured for an image data format.

[0041] Various implementations address and overcome the aforementioned problems by implementing metadata with location identifiers (such as image data format-independent metadata), which can be configured to describe the location of image color data in an interleaved format within a portion of memory for a part of an image. The metadata can be format-independent because it can be configured to represent interleaved image data in a manner usable by any processing system configured for interleaved or non-interleaved image data. The location identifier can be configured to describe the location of image color data in an interleaved format within a portion of memory for a part of an image. Using the location identifier from the metadata, processing systems not configured for interleaved format image data can access the image color data of a part of an image within a portion of memory without considering the interleaved image data format. In other words, image data in an interleaved format may not need to be converted to an image data format supported by a processing system not configured for interleaved format image data. Furthermore, processing systems not configured for interleaved format image data can avoid multiple accesses to retrieve specific image color data by accessing the location of the specific image color data indicated by the location identifier.

[0042] Various implementations enable processing systems (e.g., GPUs) configured for interleaved image data formats (e.g., RGBA) to write interleaved image data to and / or read interleaved image data from memory. Various implementations also enable processing systems (e.g., digital processing units (DPUs)) configured for non-interleaved image data formats (such as component image data formats (e.g., red-green-blue (RGB) planar format) to read individual components from interleaved image data at memory. Processing systems configured for interleaved image data formats can maintain efficient access to interleaved image data during read and write operations. Processing systems configured for non-interleaved image data formats can directly read individual components from interleaved image data. Traditional conversion processes, such as copying operations that read interleaved format and output non-interleaved format, can be avoided. By avoiding the need to store non-interleaved format image data converted from interleaved format image data, less memory is required for image data.

[0043] Various implementations can be implemented in software, firmware, hardware (e.g., circuitry), or a combination of software and hardware configured to perform specific operations or functions. Some implementations can be implemented in hardware configured to perform operations or functions, whether or not instructions are executed. Some implementations can be implemented in a processing system, a system-on-a-chip (SOC), a network-on-a-chip (NOC), or another suitable specific implementation.

[0044] While the following examples and implementations are described with reference to specific data volumes or data group sizes, such volumes or sizes are examples for illustrative purposes and, while useful in many applications and specific implementations, are not intended to be limiting. For example, a processing system of a computing device may write and / or read 256 bytes of image color data. The image color data may include 64-byte blocks for each component of the image color data (e.g., red, green, blue, alpha), and each 64-byte block may be compressed or decompressed individually. In some cases, the 64-byte blocks may not be compressed. In such implementations, the computing device may store the image color data in 32-byte blocks for encoding and decoding. Various implementations can be used to enable processing systems of a computing device configured for different image data formats to efficiently access the same image data.

[0045] Figure 1 This is a system block diagram illustrating an example communication system 100 applicable to any implementation of various implementation schemes. Communication system 100 may be a 5G New Radio (NR) network, or any other suitable network such as a Long Term Evolution (LTE) network.

[0046] Communication system 100 may include a heterogeneous network architecture, which includes a core network 140 and various wireless devices ( Figure 1 The following are examples of wireless devices 120a-120e. Wireless devices 120a-120e are examples of computing devices. The communication system 100 may also include multiple base stations (exemplified as BS 110a, BS 110b, BS 110c, and BS 110d) and other network entities. A base station is an entity that communicates with the wireless devices and may also be referred to as a Node B, an LTE evolution node B (eNB), an access point (AP), a radio headend, a transmit / receive point (TRP), a new radio base station (NR BS), a 5G Node B (NB), a next-generation Node B (gNB), and so on. Each base station can provide communication coverage for a specific geographic area. In 3GPP, the term "cell" can refer to the coverage area of ​​a base station, a base station subsystem serving that coverage area, or a combination thereof, depending on the context in which the term is used.

[0047] Base stations 110a-110d can provide communication coverage for macrocells, picocells, femtocells, another type of cell, or combinations thereof. A macrocell covers a relatively large geographic area (e.g., a radius of several kilometers) and allows unrestricted access by wireless devices with a service subscription. A picocell covers a relatively small geographic area and allows unrestricted access by wireless devices with a service subscription. A femtocell covers a relatively small geographic area (e.g., a home) and allows restricted access by wireless devices associated with that femtocell (e.g., wireless devices in a closed subscriber group (CSG)). A base station used for a macrocell may be referred to as a macro BS. A base station used for a picocell may be referred to as a pico BS. A base station used for a femtocell may be referred to as a femtocell BS or a home BS. Figure 1 In the illustrated example, base station 110a may be a macro BS for macro cell 102a, base station 110b may be a pico BS for pico cell 102b, and base station 110c may be a femto BS for femto cell 102c. Base stations 110a-110d may support one or more (e.g., three) cells. The terms “eNB,” “base station,” “NR BS,” “gNB,” “TRP,” “AP,” “Node B,” “5G NB,” and “cell” may be used interchangeably herein.

[0048] In some examples, the cell may not be stationary, and the geographical area of ​​the cell may move depending on the location of the mobile base station. In some examples, base stations 110a-110d may interconnect with each other using any suitable transport network through various types of backhaul interfaces (such as direct physical connections, virtual networks, or combinations thereof), and interconnect to one or more other base stations or network nodes (not illustrated) in the communication system 100.

[0049] Base stations 110a-110d can communicate with the core network 140 via wired or wireless communication link 126. Wireless devices 120a-120e can communicate with base stations 110a-110d via wireless communication link 122.

[0050] The wired communication link 126 can use a variety of wired networks (e.g., Ethernet, TV cable, telephone, fiber optic and other forms of physical network connection) that can use one or more wired communication protocols (such as Ethernet, point-to-point protocol, high-level data link control (HDLC), advanced data communication control protocol (ADCCP) and transmit control protocol / Internet protocol (TCP / IP)).

[0051] The communication system 100 may also include a relay station (e.g., relay BS 110d). A relay station is an entity capable of receiving data transmissions from an upstream station (e.g., a base station or wireless device) and transmitting that data to a downstream station (e.g., a wireless device or base station). A relay station can also be a wireless device capable of relaying transmissions for other wireless devices. Figure 1 In the illustrated example, relay station 110d can communicate with macro base station 110a and wireless device 120d to facilitate communication between base station 110a and wireless device 120d. A relay station may also be referred to as a relay base station, relay, relay, etc.

[0052] Network controller 130 can be coupled to a set of base stations and can provide coordination and control over these base stations. Network controller 130 can communicate with the base stations via backhaul. Base stations can also communicate with each other directly or indirectly, for example, via wireless or wired backhaul.

[0053] Wireless devices 120a, 120b, and 120c can be distributed throughout the communication system 100, and each wireless device can be stationary or mobile. Wireless devices can also be referred to as access terminals, terminals, mobile stations, user units, stations, etc.

[0054] Macro base station 110a can communicate with communication network 140 via wired or wireless communication link 126. Wireless devices 120a, 120b, and 120c can communicate with base stations 110a-110d via wireless communication link 122.

[0055] Figure 2 This is a component block diagram illustrating an example processing system 200 suitable for implementing any of the various implementation schemes. Various implementation schemes may be implemented on several single-processor and multi-processor computer systems, including system-on-a-chip (SOC) or system-in-package (SIP) components.

[0056] refer to Figure 1 and Figure 2The illustrated example processing system 200 (which may be a SIP in some embodiments) includes two SOCs 202 and 204 coupled to a clock 206, a voltage regulator 208, and a wireless transceiver 266 configured to transmit and receive wireless communications to and from a wireless device (such as base station 110a) via an antenna (not shown). In some embodiments, the first SOC 202 operates as the central processing unit (CPU) of the wireless device, which executes instructions by performing arithmetic, logic, control, and input / output (I / O) operations specified by instructions from a software application. In some embodiments, the second SOC 204 may operate as a dedicated processing unit. For example, the second SOC 204 may operate as a dedicated 5G processing unit responsible for managing high-capacity, high-speed (e.g., 5Gbps) and / or ultra-high frequency short-wavelength (e.g., 28GHz millimeter-wave spectrum) communications.

[0057] The first SOC 202 may include one or more processing systems, each of which may be one or more of the following: a digital signal processor (DSP) 210, a modem processor 212, a graphics processor 214, an application processor 216, one or more coprocessors 218 (e.g., vector coprocessors) connected to one or more of these processors, memory 220, custom circuitry 222, system components and resources 224, interconnect / bus modules 226, one or more temperature sensors 230, a thermal management unit 232, and a thermal power envelope (TPE) component 234. The second SOC 204 may include one or more processing systems, each of which may be one or more of the following: a 5G modem processor 252, a power management unit 254, an interconnect / bus module 264, multiple millimeter-wave transceivers 256, memory 258, and various additional processors 260 (such as application processors, packet processors, etc.).

[0058] Each processing system 210, 212, 214, 216, 218, 252, 260 may include one or more processors / cores, and each processor / core may perform operations independently of the other processors / cores. For example, the first SOC 202 may include a processing system running a first type of operating system (e.g., FreeBSD, LINUX, OS X, etc.) and a processing system running a second type of operating system (e.g., MICROSOFT WINDOWS 10). Furthermore, any one or all of the processing systems 210, 212, 214, 216, 218, 252, 260 may be included as part of a processor cluster architecture (e.g., synchronous processor cluster architecture, asynchronous or heterogeneous processor cluster architecture, etc.).

[0059] The first SOC 202 and the second SOC 204 may include various system components, resources, and custom circuitry for managing sensor data, analog-to-digital conversion, wireless data transmission, and performing other specialized operations, such as decoding data packets and processing encoded audio and video signals for rendering in a web browser. For example, the system components and resources 224 of the first SOC 202 may include power amplifiers, voltage regulators, oscillators, phase-locked loops, peripheral bridges, data controllers, memory controllers, system controllers, access ports, timers, and other similar components for supporting processing systems and software clients running on wireless devices. System components and resources 224 and / or custom circuitry 222 may also include circuitry for engaging peripheral devices such as cameras, electronic displays, wireless communication devices, external memory chips, etc.

[0060] The first SOC 202 and the second SOC 204 can communicate via interconnect / bus module 250. Various processors 210, 212, 214, 216, and 218 within the processing system 200 can be interconnected via interconnect / bus module 226 to one or more memory elements 220, system components and resources 224, custom circuitry 222, and thermal management unit 232. Similarly, processor 252 can be interconnected via interconnect / bus module 264 to power management unit 254, millimeter-wave transceiver 256, memory 258, and various additional processing systems 260. Interconnect / bus modules 226, 250, and 264 may include arrays of reconfigurable logic gates and / or implement bus architectures (e.g., CoreConnect, AMBA, etc.). Communication can be provided by advanced interconnects such as high-performance on-chip networks (NoC).

[0061] The processing system 200 may also include input / output modules (not illustrated) for communicating with resources outside the SOC, such as clock 206 and voltage regulator 208. Resources outside the processing system 200 (e.g., clock 206, voltage regulator 208) may be shared by two or more of the internal SOC processing systems 202, 204.

[0062] In addition to the example SIP 200 discussed above, various implementations can be implemented in a wide variety of computing systems, which may include processing systems that may include a single processor, multiple processors, multi-core processors, or any combination thereof.

[0063] Figure 3 This is a component block diagram illustrating a software architecture 300, including a radio protocol stack for the user plane and control plane in wireless communication, applicable to any of the various implementation schemes. Reference Figures 1 to 3Wireless device 320 may implement software architecture 300 to facilitate communication between wireless device 320 (e.g., wireless devices 120a-120e, 200) and base station 350 (e.g., base station 110a) of communication system (e.g., 100). In various embodiments, layers in software architecture 300 may form logical connections with corresponding layers in the software of base station 350. Software architecture 300 may be distributed among one or more processors (e.g., processors 212, 214, 216, 218, 252, 260) within processing system (e.g., 200). Although an example of a single radio protocol stack has been given, in multi-SIM (Subscriber Identity Module) wireless devices, software architecture 300 may include multiple protocol stacks, each of which may be associated with a different Subscriber Identity Module (SIM) (e.g., in a dual-SIM wireless communication device, the two protocol stacks are associated with two SIMs respectively). Although the following description refers to the LTE communication layer, the software architecture 300 may support any of the various standards and protocols used for wireless communication, and / or may include additional protocol stacks that support any of the various standards and protocols used for wireless communication.

[0064] Software architecture 300 may include a Non-Access Layer (NAS) 302 and an Access Layer (AS) 304. NAS 302 may include functions and protocols supporting packet filtering, security management, mobility control, session management, and traffic and signaling between a wireless device's SIM (e.g., SIM 204) and its core network 140. AS 304 may include functions and protocols supporting communication between the SIM (e.g., SIM 204) and entities (e.g., base stations) of the supported access network. Specifically, AS 304 may include at least three layers (Layer 1, Layer 2, and Layer 3), each of which may contain various sublayers.

[0065] In the user plane and control plane, Layer 1 (L1) of AS 304 can be Physical Layer (PHY) 306, which supervises the functions of transmitting and / or receiving over the air interface via a radio transceiver (e.g., 256). Examples of such Physical Layer 306 functions may include Cyclic Redundancy Check (CRC) appendices, decoding blocks, scrambling and descrambling, modulation and demodulation, signal measurement, MIMO, etc. The Physical Layer may include various logical channels, including the Physical Downlink Control Channel (PDCCH) and the Physical Downlink Shared Channel (PDSCH).

[0066] In the user plane and control plane, Layer 2 (L2) of AS 304 can be responsible for the link between wireless device 320 and base station 350 on physical layer 306. In various implementations, Layer 2 may include a Media Access Control (MAC) sublayer 308, a Radio Link Control (RLC) sublayer 310, and a Packet Data Convergence Protocol (PDCP) sublayer 312, each of which forms a logical connection terminating at base station 350.

[0067] In the control plane, Layer 3 (L3) of AS 304 may include a Radio Resource Control (RRC) sublayer 3. Although not shown, software architecture 300 may include additional Layer 3 sublayers, as well as various upper layers above Layer 3. In various embodiments, RRC sublayer 313 may provide functions including broadcasting system information, paging, and establishing and releasing RRC signaling connections between radio device 320 and base station 350.

[0068] In various implementations, PDCP sublayer 312 provides uplink functions including multiplexing between different radio bearers and logical channels, sequence numbering, handover data processing, integrity protection, encryption, and header compression. In the downlink, PDCP sublayer 312 provides functions including in-order delivery of data packets, duplicate data packet detection, integrity verification, decryption, and header decompression.

[0069] In the uplink, RLC sublayer 310 can provide segmentation and concatenation of upper-layer data packets, retransmission of lost data packets, and Automatic Repeat Request (ARQ). In the downlink, RLC sublayer 310 functions may include data packet reordering to compensate for out-of-order reception, reassembly of upper-layer data packets, and ARQ.

[0070] In the uplink, MAC sublayer 308 provides functions including multiplexing between logical and transport channels, random access procedures, logical channel prioritization, and hybrid ARQ (HARQ) operation. In the downlink, MAC layer functions may include intra-cell channel mapping, demultiplexing, discontinuous reception (DRX), and HARQ operation.

[0071] While the software architecture 300 provides the ability to transmit data over a physical medium, it may further include at least one host layer 314 to provide data delivery services to various applications within the wireless device 320. In some embodiments, application-specific functionality provided by at least one host layer 314 may provide an interface between the software architecture and the general-purpose processing system 260.

[0072] In other embodiments, software architecture 300 may include one or more higher logical layers (e.g., transport, session, presentation, application, etc.) that provide host layer functionality. For example, in some embodiments, software architecture 300 may include a network layer (e.g., Internet Protocol (IP) layer) where logical connections terminate at a packet data network (PDN) gateway (PGW). In some embodiments, software architecture 300 may include an application layer where logical connections terminate at another device (e.g., end-user equipment, server, etc.). In some embodiments, software architecture 300 may also include a hardware interface 316 in AS 304 between physical layer 306 and communication hardware (e.g., one or more radio frequency (RF) transceivers).

[0073] Figure 4A and Figure 4B This is a component block diagram illustrating a system 400 configured for image compression and image decompression according to various implementation schemes. Reference Figures 1 to 4B System 400 may include computing devices 402 and 404 (e.g., 110a-110d, 120a-120e, 200, 320, 350). In some embodiments, computing devices 402 and 404 may be the same computing device and include all modules 408, 410, 412, 436, 438, 440, 442 described for each example of computing devices 402 and 404. For example, computing device 402 may be a computing device exemplifying a configuration for image data compression and metadata encoding, and computing device 404 may be the same computing device exemplifying concurrent and / or subsequent configurations for image data decompression and metadata decoding. Components of computing devices 402 and 404 further described herein may be the same components exemplifying concurrent and / or subsequent configurations similar to those of computing devices 402 and 404. In some implementations, computing devices 402 and 404 can be connected via wired or wireless communication links 122, 124, 126 (in various aspects thereof). Figure 1 (Example) Separate computing devices 402 and 404 communicating. Unless otherwise indicated, the examples and descriptions herein may be similarly applied to embodiments in which computing devices 402, 404 are a single computing device or computing devices 402 and 404 are separate computing devices.

[0074] Computing devices 402, 404 may include one or more processing systems 428, 432 coupled to electronic storage devices 426, 430 and a wireless transceiver (e.g., 266). Wireless transceiver 266 may be configured to receive messages transmitted in downlink transmission from wireless communication network 424 and pass such messages to processing systems 428, 432 for processing. Similarly, processing systems 428, 432 may be configured to transmit messages for uplink transmission to wireless transceiver 266 for transmission to wireless communication network 424. In some embodiments, computing device 402 may be a computing device configuration for image data compression and metadata encoding, and computing device 404 may be a computing device configuration for image data decompression and metadata decoding. In some embodiments, computing device 402 may be a transmitting computing device, and computing device 404 may be a receiving wireless device for receiving compressed image data chunks and associated metadata.

[0075] Referring to computing device 402, processing system 428 can be configured by machine-readable instructions 406. Machine-readable instructions 406 may include one or more instruction modules. Instruction modules may include computer program modules. In some embodiments, the functionality of the instruction modules may be implemented in software, firmware, hardware (e.g., circuitry), or a combination of software and hardware configured to perform specific operations or functions. Instruction modules may include one or more of image data analysis module 408, metadata generation module 410, image data packaging module 412, transmit / receive (TX / RX) module 414, or other instruction modules.

[0076] Image data analysis module 408 may be configured to analyze image data and identify the location of components of image color data (e.g., compressed and / or uncompressed red, green, blue, and / or alpha components stored in memory (e.g., memory 220, 258, electronic storage device 426)). For example, image data analysis module 408 may be configured to analyze image data and identify which block of image data each component of image color data begins in. In some embodiments, image data analysis module 408 may also be configured to determine the packing type used for image data chunks. For example, image data analysis module 408 may be configured to analyze image data chunks and determine their compressibility.

[0077] Metadata generation module 410 can be configured to generate metadata with location identifiers configured to describe the location of image color data components in an interleaved format within a portion of memory for a portion of the image. Metadata generation module 410 can generate location identifiers and encode the metadata with these location identifiers. The metadata may be independent of the image data format, as it can be configured to represent interleaved image data in a manner usable by any processing system 432 configured for interleaved or non-interleaved format image data. In some embodiments, metadata generation module 410 may also be configured to generate metadata describing the packing type used for image data chunking.

[0078] The image data packaging module 412 can be configured to package image data chunks according to a determined packaging type.

[0079] The transmit / receive (TX / RX) module 414 can be configured to transmit the packaged image data chunks and metadata to a second computing device (e.g., computing device 404).

[0080] Referring to computing device 404, processing system 432 can be configured by machine-readable instructions 434. Machine-readable instructions 406 may include one or more instruction modules. Instruction modules may include computer program modules. Instruction modules may include one or more of the following: metadata decoding module 436, packet analysis module 438, image unpacking module 440, TX / RX module 442, or other instruction modules.

[0081] Metadata decoding module 436 can be configured to decode metadata using location identifiers, which are configured to describe the location of image color data components in an interleaved format within a portion of memory (e.g., memory 220, 258, electronic storage device 426) for a portion of the image. Metadata decoding module 436 can be configured to decode the location identifiers and, based on the location identifiers, identify the location of image color data in an interleaved format within a portion of memory for a portion of the image. In some embodiments, metadata decoding module 436 can be configured to decode metadata describing the packing type used for image data chunking.

[0082] Packaging analysis module 438 can be configured to determine the packaging type for image data chunking based on decoded metadata.

[0083] The image unpacking module 440 can be configured to unpack image data blocks according to the determined packing type used for image data blocks.

[0084] The TX / RX module 442 can be configured to communicate with the wireless communication network 424.

[0085] In some implementations, computing devices 402, 404 may be operatively linked via one or more electronic communication links (such as wired or wireless communication link 122 or some other communication medium).

[0086] Electronic storage devices 426 and 430 may include non-transitory storage media that electronically store information. The electronic storage media of electronic storage devices 426 and 430 may include one or both of system storage devices integrated with (i.e., substantially non-removable) computing devices 402 and 404 and removable storage devices removably connected to computing devices 402 and 404 via, for example, a port (e.g., a Universal Serial Bus (USB) port, a FireWire port, etc.) or a drive (e.g., a disk drive, etc.). Electronic storage devices 426 and 430 may include one or more of the following: optically readable storage media (e.g., optical discs, etc.), magnetically readable storage media (e.g., magnetic tape, magnetic hard disk drives, floppy disk drives, etc.), charge-based storage media (e.g., EEPROM, RAM, etc.), solid-state storage media (e.g., flash drives, etc.), and / or other electronically readable storage media. Electronic storage devices 426 and 430 may include one or more virtual storage resources (e.g., cloud storage devices, virtual private networks, and / or other virtual storage resources). Electronic storage devices 426 and 430 may store software algorithms, information determined by processing systems 428 and 432, information received from computing devices 402 and 404, or other information that enables computing devices 402 and 404 to function as described herein.

[0087] Processing systems 428 and 432 may be configured to provide information processing capabilities within computing devices 402 and 404. Thus, processing systems 428 and 432 may include one or more of a digital processor, an analog processor, digital circuitry designed to process information, analog circuitry designed to process information, a state machine, and / or other mechanisms for electronically processing information. Although processing systems 428 and 432 are illustrated as a single entity, this is merely for illustrative purposes. In some embodiments, processing systems 428 and 432 may include multiple processing units and / or processor cores. Processing units may be physically located within the same device, or processing systems 428 and 432 may represent the processing functionality of multiple devices operating collaboratively. Processing systems 428 and 432 may be configured to execute modules 408 to 414 and modules 436 to 442 and / or other modules by: software; hardware; firmware; a combination of software, hardware, and / or firmware; and / or other mechanisms for configuring the processing capabilities on processing systems 428 and 432. As used herein, the term "module" may refer to any component or set of components that performs the functionality attributable to that module. This may include one or more physical processors, processor-readable instructions, circuitry, hardware, storage media, or any other component during the execution of processor-readable instructions.

[0088] The description below of the functionality provided by the various modules 408-414 and 436-442 is for illustrative purposes and not intended to be limiting, as any of modules 408-414 and 436-442 may provide more or less functionality than described. For example, one or more of modules 408-414 and 436-442 may be eliminated, and some or all of their functionality may be provided by other modules 408-414 and 436-442. As another example, processing systems 428, 432 may be configured to execute one or more additional modules that can perform some or all of the functionality attributable to one of modules 408-414 and 436-442.

[0089] Figure 5A and Figure 5B These are illustrations of example image data formats 500a and 500b in memories (e.g., memories 220, 258, electronic storage device 426) according to various implementation schemes. Reference Figures 1 to 5AThe memory can be a component of a computing device (e.g., 110a-110d, 120a-120e, 200, 320, 350, 402, 404), such as non-volatile and / or volatile memory, such as local memory, notepad memory, cache memory, main memory, random access memory (e.g., DRAM and / or SRAM). Image data formats 500a and 500b can be representations of image data, including components of image color data, such as red component 502, green component 504, blue component 506, and / or alpha (or transparency) component 508.

[0090] Image data format 500a can be a representation of an interleaved image data format (e.g., RGBA) in memory. For example, each column of image data format 500a can represent a single component of image color data 502-508. Each row of image data format 500a can represent multiple sets of image color data, each set having each of the components of image color data 502-508. In various examples, a combination of consecutive positions in image data format 500a can represent image color data for a portion of an image (such as a tile of the image). For a non-limiting example, four rows of image data format 500a can represent a tile of the image.

[0091] Image data format 500b can be a representation of a non-interleaved image data format (e.g., RGB planar format) in memory. For example, each segment of image data format 500b (e.g., consecutive positions on consecutive lines in memory) can represent a single component of image color data 502-506. In some examples, image data format 500b may exclude the alpha (or transparency) component 508. In various examples, combinations of non-consecutive positions in image data format 500b can represent image color data for a portion of the image, such as pixels of the image. In a non-limiting example, a position within a segment of each component of image color data 502-506 in image data format 500b can represent a pixel of the image.

[0092] Various processing systems and / or processors of the computing device (e.g., 210, 212, 214, 216, 218, 252, 260, 428, 432) may be configured to write to and / or read from memory one of image data formats 500a and 500b, and are not configured to read from memory the other of image data formats 500a and 500b. For example, a processing system may be configured to write to and / or read from memory image data format 500a, and another processing system may be configured to write to and / or read from memory image data format 500b. A processing system configured for image data format 500a may not be able to directly write to and / or read from image data format 500b, and a processing system configured for image data format 500b may not be able to directly write to and / or read from image data format 500a. In order to write and / or read image data in formats 500a and 500b that are not configured for use by the processing system, various processes can be implemented to translate / convert image data into image data formats 500a and 500b that are configured for use by the processing system.

[0093] Figure 6 This is an illustration of examples of compressed image data in different image data formats (e.g., image data formats 500a, 500b) in a memory 600 (e.g., memory 220, 258, electronic storage device 426) according to some embodiments. Reference Figures 1 to 6 The memory 600 may be a component of a computing device (e.g., 110a-110d, 120a-120e, 200, 320, 350, 402, 404), such as non-volatile and / or volatile memory, such as local memory, notepad memory, cache memory, main memory, random access memory (e.g., DRAM and / or SRAM). The memory may be coupled to various processing systems of the computing device (e.g., 210, 212, 214, 216, 218, 252, 260, 428, 432).

[0094] The processing system can write and / or read image data 602a, 602b at memory 600. Figure 6In the example, a processing system configured to interleave image data formats (e.g., image data format 500a) can write to and / or read image data 602a at memory 600. Image data 602a can be compressed and includes metadata 604a and image color data 606a with a header 608 for compressed data. This compressed data includes components of image color data 610, 612, 614, and 616 (e.g., components 502-508 of the image color data). The components of the image color data may include a red component 610, a green component 612, a blue component 614, and an alpha (or transparency) component 616. Compressing image color data 606a achieves memory space savings 618.

[0095] A processing system configured for a non-interleaved image data format (e.g., image data format 500b) may not be able to directly write to and / or read image data 602a in an interleaved image data format at memory 600. To write to and / or read from an interleaved image data format not configured for the processing system, various processes can be implemented to translate / convert image data 602a into a non-interleaved image data format configured for the processing system. The translation / conversion processes may consume additional power to the computing power supply (e.g., battery) and incur performance speed costs.

[0096] Image data 602a can be copied and converted into image data 602b, resulting in additional memory space usage for memory 600 and additional processes for copying and converting image data 602a. Image data 604a can also be compressed and includes metadata 604b and image color data 606b with a header 608 for compressed data, which includes components of image color data 610, 612, and 614 (e.g., components 502-506 of the image color data). The components of the image color data may include red component 610, green component 612, and blue component 614. The components of the image color data may exclude alpha (or transparency) component 616. Compressing image color data 606b achieves memory space savings 618.

[0097] Figure 7 This is a tabular diagram 700 showing the mapping 700 between location identifiers of encoded metadata according to some embodiments and values ​​configured to represent the locations of components (e.g., components of image color data 502-508, 610-616) of image color data in memory (e.g., memory 220, 258, 600, electronic storage device 426). Reference Figures 1 to 7 Location identifier ( Figure 7The ID column in the image data (e.g., image data format 500a) can be encoded as metadata (e.g., metadata 604a) in an interleaved image data format (e.g., image data format 500a). Location identifiers can be configured to describe the location of image color data (e.g., components of image color data 606a, 502-508, 610-616) in an interleaved format within a portion of memory.

[0098] Location identifiers can be used with values ​​( Figure 7 The values ​​in the mapping 700 correspond to the red (R), green (G), blue (B), and / or alpha (A) (or transparency) component columns, and are configured to represent the positions of multiple components of image color data in an interlaced format within a portion of memory. The value of each column of the mapping 700 corresponds to the position of the corresponding component of the image color data in memory.

[0099] exist Figure 7 In the illustrated example, up to six values ​​can exist to represent the position of each component of the image color data in memory. The value "0" can be configured to indicate that a component of the image color data is compressed into a portion of the previous block in memory. The value "1" can be configured to indicate that a component of the image color data begins a new block of a first size (e.g., 32 bytes) in memory. The value "2" can be configured to indicate that a component of the image color data begins a new block of a second size (e.g., 64 bytes) in memory. The value "3" can be configured to indicate that a component of the image color data includes a first constant value in memory (e.g., "0"). The value "4" can be configured to indicate that a component of the image color data includes a second constant value in memory (e.g., "1"). Additional constant option values ​​(e.g., ...) Figure 7 The "Constant Option 1", "Constant Option 2", "Constant Option 3", and "Constant Option 4" can be configured to indicate that the components of the image color data include combinations of constant values. For example, Constant Option 1 can indicate that all components of the image color data can be a constant value "0", and Constant Option 2 can indicate that all components of the image color data can be a constant value "1". Constant Option 3 can indicate that the red, green, and blue components of the image color data can be a constant value "1", and the alpha (or transparency) component can be a constant value "0". Constant Option 4 can indicate that the red, green, and blue components of the image color data can be a constant value "0", and the alpha (or transparency) component can be a constant value "1". Other combinations of image color data components can be constant values.

[0100] exist Figure 7In the illustrated example, the order of the image color data components in memory can start with the red component, and the value of the red (R) component column can be "1" or "2". The values ​​of the green (G) and blue (B) component columns can be "0", "1", or "2". The value of the alpha (A) (or transparency) component can be "0", "1", "2", "3", or "4". Constant header option values ​​apply to all component columns. The possible combinations of values ​​for the component columns correspond to 64 identifiers.

[0101] Figure 7 The number, values, and configurations of the identifier, value, and component columns in the example are not intended to be limiting. It will be understood that fewer and / or additional numbers, values, and configurations of identifier, value, and component columns can be similarly implemented for metadata encoding and for describing the location of image color data in an interleaved format within a portion of memory for a part of the image.

[0102] In some implementations, mapping 700 may be a data structure stored in memory accessible by the processing system (e.g., 210, 212, 214, 216, 218, 252, 260, 428, 432). In some implementations, mapping 700 may be calculated in real time by the hardware, software, and / or firmware configuring the processing system.

[0103] Figure 8 This is an illustration of an example of compressed image data 802, including image data format-independent metadata 830, in a memory (e.g., memory 220, 258, 600, electronic storage device 426) according to some embodiments. Reference Figures 1 to 8 The memory can be a component of a computing device (e.g., 110a-110d, 120a-120e, 200, 320, 350, 402, 404), such as non-volatile and / or volatile memory, such as local memory, notepad memory, cache memory, main memory, random access memory (e.g., DRAM and / or SRAM), etc. The memory can be coupled to various processors (e.g., 210, 212, 214, 216, 218, 252, 260, 428, 432) of a processing system in the computing device. One processing system can be configured for interleaving image data formats (e.g., image data format 500a), and another processor can be configured for non-interleaved image data formats (e.g., image data format 500b).

[0104] Compressed image data 802 can be stored in memory in an interleaved image data format. Compressed image data 802 may include compressed and / or uncompressed components of image color data 810, 812, 814, and 816 (e.g., components of image color data 502-508, 610-616). For example, components of image color data may include red component 810, green component 812, blue component 814, and / or alpha (or transparency) component 816. A compression header 818 may be stored in memory preceding the compressed components of image color data 810, 812, 814, and 816. This compression header may be configured to indicate whether the components of image color data 810, 812, 814, and 816 are compressed and to provide compression-related data. The components of image color data 810, 812, 814, and 816 may be written to memory in block 822. In a non-limiting example, block 822 can be 32 bytes, and block 822 can be 64 bytes (e.g., two 32-byte blocks 822). Each image color data 840 of a portion of an image having components of image color data 810, 812, 814, 816 can be contained within 256 bytes (e.g., eight 32-byte blocks 822). Compressing image color data 840 by compressing at least one of the components of image color data 810, 812, 814, 816 can achieve various sizes of memory space savings 820, depending on the compression of the components of image color data 810, 812, 814, 816. Compressing image data 802 can include one or more of image color data 840 having at least one compressed component of image color data 810, 812, 814.

[0105] A processing system configured for interleaving image data formats can be configured to write compressed image data 802 directly to and / or read the compressed image data directly from memory. In some embodiments, the processing system can generate and compress image data to generate compressed image data 800. The processing system can write compressed image data 800 to memory in the same configuration as when compressed image data 802 is stored in memory. The compressed image data 802 stored in memory can be compressed image data 800 written to memory by the processing device. Writing compressed image data 800 to memory may also include writing a location identifier 832 (e.g., for each set of compressed image color data 840, such as components of image color data 810, 812, 814, 816, and / or compressed header 818) for each compressed image color data 840 (e.g., for each set of compressed image color data 810, 812, 814, 816, and / or compressed header 818). Figure 7Image data format-independent metadata 830 (ID column value). The processing system can read compressed image data 800 from memory in the same configuration as compressed image data 802 stored in memory. Compressed image data 802 stored in memory can be compressed image data 800 read from memory by the processing device. In some embodiments, compressed image data 800 read from memory can be compressed image data 802 stored in memory by the processing system or another processing system configured to interleave image data formats. Whether written to or read from memory by the processing system, compressed image data 800 can be the same as image data 802 stored in memory.

[0106] A processing system configured for non-interleaved image data formats can be configured to write and / or read compressed image data 802 directly from memory using metadata (e.g., image data format-independent metadata 830) with a location identifier 832. The processing system can decode the metadata (e.g., image data format-independent metadata 830) and interpret the location identifier 832 to identify the positions of the components of image color data 810, 812, 814, 816 of the compressed image data 802 in memory. For example, compressed image color data 840 may have a location identifier value "16", which the processing system can decode to a value "2100", as in a location identifier and value mapping (e.g., mapping 700). The value "2100" may indicate to the processing system that the red component 810 is in a second-size block, the green component begins a new first-size block, and the blue and alpha components are compressed as part of the previous block in memory. The processing system can directly read compressed image data 804 from compressed image data 802 by using the positions of the image color data components 810, 812, 814, and 816 of compressed image data 802. This includes one or more components of the image color data 810, 812, 814, and 816. In other words, the processing system can read compressed image data 804 without additional processing to translate / convert compressed image data 802 into a non-interleaved image data format.

[0107] Figure 9 This is a process flowchart illustrating a method 900 for image compression, executable by a processing system (e.g., 210, 212, 214, 216, 218, 252, 260, 428, 432) of a computing device (e.g., 110a-110d, 120a-120e, 200, 320, 350, 402, 404) according to various embodiments. Reference Figures 1 to 9Method 900 may be implemented by a processing system of a computing device including memory (e.g., memory 220, 258, 600, electronic storage device 426), such as non-volatile and / or volatile memory, such as local memory, notepad memory, cache memory, main memory, random access memory (e.g., DRAM and / or SRAM), etc. In some embodiments, method 900 may be implemented by a processing system executing one or more modules (e.g., image data analysis module 408, metadata generation module 410). In some embodiments, the processing system implementing method 900 may be configured to interleave image data formats. Components for performing the operations in method 900 may include processing systems (e.g., 210, 212, 214, 216, 218, 252, 260, 428, 432) and / or modules (e.g., image data analysis module 408, metadata generation module 410).

[0108] In block 902, the processing system may analyze image color data (e.g., image color data 840) stored in a portion of memory in an interleaved image data format (e.g., image data format 500a). Analyzing the image color data may include identifying aspects of the image color data, such as the location of the image data (including the image color data) in memory, the image data format (e.g., interleaved and / or non-interleaved image data formats), whether the image data (including the image color data) is compressed, the type of compression, etc.

[0109] In block 904, the processing system can identify the location of components of image color data in memory (e.g., components of image color data 502-508, 610-616, 810-816). For example, the location can be identified based on which blocks of image color data the components of image color data begin with (e.g., block 822).

[0110] In box 906, the processing system may generate a location identifier based on the location of the components of the image color data in memory (e.g., Figure 7 (The value of the ID column in the memory). The location of the image color data component in memory may be specific to an absolute location within memory and / or a location relative to other components of the image color data in memory. In some embodiments, the location of the image color data component in memory may be a specific block location in memory containing at least a portion of the image color data component. In some embodiments, the location of the image color data component in memory may be a relative block location in memory relative to other block locations in memory containing at least a portion of the image color data component.

[0111] The processing system can be configured to position the components of the image color data in memory relative to their representative values ​​(e.g., Figure 7 The values ​​of the red (R), green (G), blue (B), and / or alpha (A) (or transparency) component columns in the image color data are correlated with and / or these locations are represented as representative values. Based on one or more representative values ​​of the locations of the image color data in memory, the processing system can be configured to generate location identifiers. In some embodiments, the processing system can be configured to generate location identifiers in a data structure (e.g., Figure 7 The system searches for one or more representative values ​​of the location of the image color data components in the mapping (700) and locates the corresponding location identifier. In some implementations, the processing system can use one or more representative values ​​of the location of the image color data components as input to a software and / or hardware algorithm to generate location identifiers algorithmically.

[0112] In block 908, the processing system may encode metadata for image color data stored in a portion of memory in an interleaved image data format using a location identifier (e.g., location identifier 832). In some embodiments, in block 908, the processing system may encode the metadata as image data format-independent metadata (e.g., 830). The processing system may write the location identifier for each image color data to the metadata for the corresponding image color data.

[0113] Figure 10 This is a process flowchart illustrating a method 1000 for image decompression, executable by a processing system (e.g., 210, 212, 214, 216, 218, 252, 260, 428, 432) of a computing device (e.g., 110a-110d, 120a-120e, 200, 320, 350, 402, 404) according to various embodiments. Reference Figures 1 to 10 Method 1000 may be implemented by a processing system of a computing device including memory (e.g., memory 220, 258, 600, electronic storage device 426), such as non-volatile and / or volatile memory, such as local memory, notepad memory, cache memory, main memory, random access memory (e.g., DRAM and / or SRAM), etc. In some embodiments, method 1000 may be implemented by a processing system executing one or more modules (e.g., metadata decoding module 436). In some embodiments, the processing system implementing method 1000 may be configured for non-interleaved image data formats and may be a different processing system that can implement method 900. Components for performing the operations in method 1000 may include processing systems (e.g., 210, 212, 214, 216, 218, 252, 260, 428, 432) and / or modules (e.g., metadata decoding module 436).

[0114] In box 1002, metadata (e.g., image data format-independent metadata 830) with a location identifier (e.g., location identifier 832) for image color data (e.g., image color data 840) stored in a portion of memory in an interleaved image data format (e.g., image data format 500a) is retrieved. As part of data access to the memory for the image color data, the processing system may retrieve and read the metadata with the location identifier associated with the image color data. The metadata with the location identifier may also be stored in the memory storing the image color data.

[0115] In box 1004, the processing system can use location identifiers of image color data stored in a portion of memory in an interleaved image data format to decode metadata. The processing system can be configured to correlate the locations of the components of the image color data in memory (e.g., components of image color data 502-508, 610-616, 810-816) with their representative values ​​(e.g., ...). Figure 7 The values ​​of the red (R), green (G), blue (B), and / or alpha (A) (or transparency) component columns in the image color data are correlated with and / or these locations are represented as representative values. Based on the location identifiers used for image color data, the processing system can be configured to generate and / or identify one or more representative values ​​among the representative values ​​of the locations of the components of the image color data in memory. In some embodiments, the processing system can be configured in a data structure (e.g., Figure 7 Find the location identifier in the mapping 700 (e.g., Figure 7 The system uses the ID column value to locate the position of the image color data components, and selects one or more representative values ​​from the representative values. In some implementations, the processing system may use the location identifier as input to a software and / or hardware algorithm to generate one or more representative values ​​from the representative values ​​of the position of the image color data components algorithmically.

[0116] In block 1006, the processing system may identify the location of image color data stored in a portion of memory in an interleaved image data format based on a location identifier. Using one or more representative values ​​of the locations of the image color data components in memory derived from the location identifier, the processing system may be configured to locate the components of the image color data in memory. The location of the components of the image color data in memory may be specific to an absolute location within memory and / or a location relative to other components of the image color data in memory. In some embodiments, the location of the components of the image color data in memory may be a specific block location in memory containing at least a portion of the image color data. In some embodiments, the location of the components of the image color data in memory may be a relative block location in memory relative to other block locations in memory containing at least a portion of the image color data. The processing system may use representative values ​​of the locations of the components of the image color data in memory to identify the block locations of the components of the image color data in memory.

[0117] In box 1008, the processing system can retrieve at least a portion of image color data from memory based on the location of image color data stored in a portion of memory in an interleaved image data format. The processing system can be configured, for example, by software and / or hardware, to retrieve one or more components of the image color data. Using the location of the components of the image color data, the processing system can directly retrieve one or more components of the image color data from them. Figure 11A This is a process flowchart illustrating a method 1100 for image compression, executable by one or more processors within a processing system of a computing device, according to various embodiments. Reference Figures 1 to 11A Method 1100 may be implemented by a processor (e.g., 210, 212, 214, 216, 218, 252, 260, 428, 432) within the processing system of a computing device. Components for performing the operations in method 1100 may include the processing system (e.g., 210, 212, 214, 216, 218, 252, 260, 428, 432) and / or modules (e.g., metadata decoding module 436).

[0118] In block 1102, the processing system may determine the type of data compression or packing used for image data chunks. In some embodiments, the processor may analyze the image data chunks to determine their compressibility and, based on their compressibility, determine the appropriate packing type for the image data chunks.

[0119] In block 1104, the processing system may generate metadata describing the packing to be applied to image data chunks. The metadata may include information indicating the location of one or more chunks and / or the location of chunk data within or across one or more chunks. In some embodiments, the metadata describing the packing type for the image data chunks enables the image data chunks to be read independently of a second image data chunk. In some embodiments, the metadata describing the packing type for the image data chunks enables the image data chunks to be tiled for writing and linearly read. In some embodiments, generating the metadata describing the packing type for the image data chunks may include generating metadata indicating whether the image data chunks are compressed or uncompressed.

[0120] In block 1106, the processing system may package image data chunks according to a determined packaging type. In some embodiments, packaging image data chunks may include packaging two or more image data chunks according to a determined packaging type.

[0121] In block 1108, the processing system can transmit packaged image data chunks and metadata to a second computing device. In some embodiments, the processor can transmit two or more packaged image data chunks and metadata to the second computing device.

[0122] In operation 1110, the processing system can repeat the operations of boxes 1102-1108 to process multiple image data blocks.

[0123] Figure 11B This is a conceptual block diagram illustrating image data compression mode 1120 according to various implementation schemes. (Reference) Figures 1 to 11B The image data compression mode 1120 can be implemented by the processor (e.g., 210, 212, 214, 216, 218, 252, 260, 428, 432) of a computing device (e.g., wireless devices 120a-120e, 200, 320, 402, 404).

[0124] Image data 1122 may include lines 1124, 1126, 1128, and 1130. Each of lines 1124-1130 may include 64 bytes of data. In some embodiments, the processing system may compress each of lines 1124, 1126, 1128, and 1130 individually, and each compressed line may be stored in a 32-byte block or a 64-byte block aligned to 32 bytes.

[0125] The processing system can compress image data according to one or more examples 1120 of image data compression. As illustrated in example 1140, the processing system can compress four lines 1124-1130 into a 32-byte block. As illustrated in example 1142, the processing system can compress three lines (e.g., lines 1124-1128 in example 1142) into a 32-byte block, and can compress one line (e.g., line 1130 in example 1142) into another 32-byte block. As illustrated in example 1144, the processing system can bridge a line (e.g., line 1126) across two 32-byte blocks. As illustrated in examples 1144 and 1146, the processor can compress two lines into a 32-byte block (e.g., lines 1128 and 1130 in examples 1144 and 1146). As illustrated in Example 1146, the processing system may bridge lines from one 32-byte block to another 32-byte block (i.e., two lines in 64 bytes, or "packet 64B"). In various embodiments, the processing system may include a header 1132 at the beginning of at least one block, as further described below. In some embodiments, the processing system may add padding bits 1134 to fill the 32-byte block.

[0126] The attached table illustrates the compression ratios (CRs) that can be achieved for each row 1124-1130. The table includes example data sizes for image data 1142 (256B) and for each of rows 1124-1130 (64B). The table also includes the total CR for image data 1142 using “baseline” compression or using “packet 64B” compression, and the compression ratios for each row 1124-1130 (first CR, second CR, third CR, fourth CR). For baseline compression with a compression ratio of 8:1 (8), rows 1124-1130 can be compressed into a 32-byte block, as in example 1140. The effective compression ratio for each row 1124-1130 can be 2:1 (2), since a 32-byte block can be retrieved from memory with 64-byte rows 1124-1130. For a baseline compression with a compression ratio of 4:1 (4), lines 1124-1130 can be compressed into two 32-byte blocks, as in Example 1142. The effective compression ratio for each line 1124-1130 can be 2:1 (2) because a 32-byte block can be retrieved from memory with 64-byte lines 1124-1130. For a baseline compression with a compression ratio of 2:1 (2), lines 1124-1130 can be compressed into four 32-byte blocks, as in Example 1144. The effective compression ratio for each line 1124, 1128, 1130 that is compressed into a 32-byte block can be 2:1 (2) because a 32-byte block can be retrieved from memory with 64-byte lines 1124, 1128, 1130. The effective compression ratio for each line 1126 used for bridging across two 32-byte blocks can be 1:1 (1) because a 64-byte block (or two 32-byte blocks) can be retrieved from memory with a 64-byte line 1126. For packet 64B compression with a compression ratio of 2.7:1 (2.7), lines 1124-1130 can be compressed into three 32-byte blocks, as in example 1146. The effective compression ratio for each line 1124, 1126 used for bridging across two 32-byte blocks can be 1:1 (1) because a 64-byte block (or two 32-byte blocks) can be retrieved from memory with a 64-byte line 1124, 1126. The effective compression ratio for each line 1128, 1130 compressed into 32-byte blocks can be 2:1 (2) because a 32-byte block can be retrieved from memory with a 64-byte line 1128, 1130.

[0127] Figure 11C This is a conceptual block diagram illustrating metadata encoding 1185 according to various implementation schemes. (Reference) Figures 1 to 11CThe metadata encoding 1185 can be implemented by the processing system (e.g., 210, 212, 214, 216, 218, 252, 260, 428, 432) of a computing device (e.g., wireless devices 120a-120e, 200, 320, 402, 404).

[0128] To enable random access to image data, the location and size of each 64-byte block can be described in the metadata. In some implementations, each 64-byte block can be read from a 32-byte block or two 32-byte blocks (sometimes referred to as 64-byte blocks) totaling 64 bytes. In some implementations, the processing system can preferentially compress blocks into 32-byte blocks, which can improve the efficiency and performance of compression and decompression operations. In some implementations, if more than one 64-byte block is compressed into the same block, a compression header must be provided for each block. In some implementations, a 64-byte block can be loaded into the previous block (which can be represented by "0"), the beginning of the 32-byte compressed block (which can be represented by "1"), or the beginning of the 64-byte compressed block (which can be represented by "2") when being compressed.

[0129] In some implementations, the metadata encoding scheme may include two states (encoded by 1 bit) for the initial chunk and three states (encoded by more than 1 bit and less than or equal to 2 bits) for the additional chunks. For example, for four chunks, the metadata may be encoded for 54 states (i.e., 2*3*3*3 states), which may be encoded with 6 bits (or 7 bits if kept separate, i.e., 1+2+2+2 bits). In various implementations, the metadata encoding scheme may be extended to more or fewer chunks.

[0130] In some implementations, the first 64-byte block may begin at the start of the block and cannot be compressed to correspond to the value "0". In some implementations, the two rows may share a 64-byte block if compression is insufficient to overcome the row overhead caused by separating two rows into two 32-byte blocks. In such implementations, the "0" metadata encoding may not follow the "2" metadata encoding, resulting in 34 possible states. In some implementations, bridging options may be indicated by "3" metadata encoding (i.e., a "3" value may indicate whether the block bridges from the previous block or continues). In some implementations, 7 bits may be used to fully describe the bridging options. In some implementations, the metadata encoding scheme may be generalized to encode higher-order states, such as overlapping more than two tiles.

[0131] Metadata encodings 1150-1160 illustrate non-limiting examples of this information encoded in metadata. Metadata encoding 1150 "1 1" indicates that two chunks each begin at the start of a 32-byte block. Metadata encoding 1152 "1 0 1" indicates the start of a 32-byte compressed block, followed by a 64-byte chunk loaded into the 32-byte block, followed by the start of another 32-byte compressed block. Metadata encoding 1154 "1 2" indicates the start of a 32-byte compressed block, in this example, followed by the start of a 64-byte block of uncompressed image data. Metadata encoding 1156 "2 0 1" indicates the start of a 64-byte compressed block, followed by a 64-byte chunk loaded into the second 32-byte block, followed by another 32-byte compressed block. Metadata encoding 1158 "1 0 0" indicates the start of a 32-byte compressed block, followed by a 64-byte chunk loaded into the same 32-byte block, followed by a second 64-byte chunk loaded into the same 32-byte block. Metadata encoding 1160 represents a special case where "2 2 0" indicates the start of a 64-byte uncompressed block, followed by the start of another 64-byte uncompressed block, and then a 64-byte chunk being loaded into a second 64-byte block. In metadata encoding 1160, the first "2" value is not subsequently an indication that it shares a block with another chunk, and in some implementations, this may indicate the presence of uncompressed image data.

[0132] In some implementations, the processing system may divide 64-byte blocks across two 32-byte blocks (i.e., "bridge" or "overlap" between or across two 32-byte blocks). For example, if a data line (e.g., lines 1124-1130) requires more than 32 bytes (e.g., 64 bytes) to be compressed, the processing system may compress the first portion of the line in a 32-byte block and the remainder in subsequent 32-byte blocks. Furthermore, in some implementations, the overlap or bridging of blocks across blocks may continue serially, such that the first line may be packed into a portion of a first 32-byte block and a second 32-byte block; the second line may be packed into the remainder of a second 32-byte block and a portion of a third 32-byte block, and so on. Various implementations are possible to prioritize 64-byte compression and / or 256-byte compression, which the processing system may perform dynamically or statically depending on the specific implementation. To save space, the processing system may omit the header, where the 32B compression can be decoded separately in other ways. In some implementations, the processing system may dynamically determine whether to compress chunks within 32 bytes, or bridge chunks on two 32-byte blocks to another compressed block that can fit into the remainder of each 32-byte block. In some implementations, the processing system may be configured to dynamically determine chunk compression in a general way for a particular implementation, for example, preferring fully compressed access over compression of individual access. In some implementations, the processing system may be configured to dynamically determine chunk compression based on buffer size (i.e., buffer capacity) or buffer utilization (i.e., the amount of data stored in the buffer) or for a specific use case. In some implementations, the processing system may be configured to dynamically determine chunk compression to meet compressibility targets. For example, the processing system may be configured to ensure a certain balance of compressibility, such as minimum compressibility of complete tiles. Figure 11C The examples illustrated are not exhaustive, and other forms of metadata encoding are possible in various implementations.

[0133] Figure 11D This is a conceptual block diagram illustrating metadata encoding 1190 according to some implementation schemes. (Reference) Figures 1 to 11D Metadata encoding 1190 can be implemented by the processing system.

[0134] Metadata may include information describing the packing type used to pack image data into three blocks N-1, N, and N+1. Block N-1 may correspond to the last block where the previous block was placed, and block N may correspond to the next unused block. In some embodiments, packing (e.g., block location) may be built progressively from the first block to the last block. In some embodiments, packing may be built progressively. In some embodiments, packing may be computed in parallel. In some embodiments, packing may be built progressively. In some embodiments, packing may be pre-computed and searched in parallel.

[0135] In some implementations, information may be encoded in metadata using a single bit, a combination of bits or bit values, or any other suitable encoding of the information. In some implementations, symbols are concatenated to form a complete encoding. In some implementations, for each symbol, block N may be the next unpadded block. For example, metadata encoding 1191 "0" may indicate that a 64-byte block is loaded into a block, such as into block N-1. Metadata encoding 1192 "1" (e.g., in header 1192a) may indicate the beginning of a new block in a 32-byte compressed block. Metadata encoding 1193 "2" followed by a "1" or "2" encoded block (e.g., "1 / 2") may indicate an uncompressed 64-byte block in a 64-byte block. In such implementations, the end of a block may be considered as "next symbol" as 1 or 2. As another example, metadata encoding 1194 "2" followed by a "0" or "3" encoded block (e.g., "0 / 3") (e.g., in new header 1194a) can indicate the start of a new compressed block of 64 bytes. In some implementations, the new header (e.g., 1192a, 1194a) can reflect the type of compression and can encode the necessary information for starting a new compressed block and information for managing the new block. For example, headers 1192a, 1194a can indicate a start header. Metadata encoding 1195 "3" followed by a "1" or "2" encoded block can indicate a bridging block packed into a previous block (such as block N-1) and / or a block extending (or overlapping) from the previous block. Metadata encoding 1196 "3" followed by a "0" or "3" encoded block can also indicate a bridging block packed into a previous block (such as block N-1).

[0136] Headers 1191a, 1195a, and 1196a may indicate that a new chunk is managed by the previous header (i.e., information about the chunk can be found in an earlier header). For example, the headers may encode information about the next chunk (in addition to previous chunks), or they may encode offsets indicating the location of more information for that chunk, or any combination thereof. In some embodiments, optional headers 1194b and 1196b may be inserted after a "0" chunk. In some embodiments, headers 1194b and 1196b may include headers inserted at the beginning of a chunk, but interrupting the compressed information of the encoded chunk that spans from the previous chunk to the chunk in which headers 1194b and 1196b are inserted. Headers 1194b and 1196b may be optional when there are no subsequent chunks. In some embodiments, these headers may also be omitted if any number of subsequent "0" chunks are not followed by "3" chunks. In this scenario, decoding of these "0" blocks only occurs when two blocks, rather than just one, are available. In some implementations, the presence of optional headers 1194b and 1196b indicates that each block can be read and decoded individually. Without optional headers 1194b and 1196b, subsequent "0" blocks may require reading two blocks for decoding. In some implementations, for "3" blocks, the optional headers 1194b and 1196b can be omitted if no subsequent blocks are available (e.g., the last block in the tile set).

[0137] Figure 12 This is a process flowchart illustrating operations 1200, which can be executed by a processing system of a computing device as part of a method 1100 for image compression, according to various implementation schemes. Reference Figures 1 to 12 Operation 1200 and method 1100 may be implemented by a processor (e.g., 210, 212, 214, 216, 218, 252, 260, 428, 432) of a processing system of a computing device (e.g., wireless devices 120a-120e, 200, 320, 402, 404). Components for performing the functions in block 1202 may include the processor (e.g., 210, 212, 214, 216, 218, 252, 260, 428, 432).

[0138] Image data can be compressed and stored in memory. A portion of the memory storing the compressed image data may be referred to as a partition. For example, a partition may be one or more blocks of memory capable of storing compressed image data (e.g., 32-byte, 64-byte, etc. portions of memory). The compressed image data of a partition may be stored in a single block, bridge two blocks, or within multiple blocks. After performing the operation at block 1102 of method 1100, the processing system may generate metadata indicating the partition offset of the partition in block 1202 in which the block is grouped. In some embodiments, the processing system may generate metadata indicating the partition size of the partition in which the block is grouped. In some embodiments, the processing system may generate metadata indicating the block offset of one or more blocks within a partition. In some embodiments, the processing system may generate metadata indicating the number of blocks in a partition. In some embodiments, the processing system may generate metadata indicating the location of headers within a partition. In some embodiments, the processing system may generate metadata indicating that the block header includes an offset field.

[0139] In box 1204, the processor can pack image data blocks according to the determined packing type by grouping the blocks into partitions.

[0140] The processor can then perform the operation of block 1108 of method 1100 as described.

[0141] Figure 13A This is a process flowchart illustrating a method 1300 for image decompression, executable by a processing system of a computing device according to various implementation schemes. (Reference) Figures 1 to 13A Method 1300 may be implemented by a processor (e.g., 210, 212, 214, 216, 218, 252, 260, 428, 432) of a processing system of a computing device (e.g., wireless devices 120a-120e, 200, 320, 402, 404). Components for performing the operations in method 1300 may include the processor (e.g., 210, 212, 214, 216, 218, 252, 260, 428, 432).

[0142] In box 1302, the processing system can decode the metadata describing the packing type used for image data chunking.

[0143] In block 1304, the processing system may determine the packing type for the image data chunks based on the decoded metadata. In some embodiments, the processing system may identify the blocks in which the image data chunks are packed. In some embodiments, the processing system may identify the partition containing the blocks in which the image data chunks are packed. In some embodiments, the processing system may identify the partition offset or partition size. In some embodiments, the processing system may identify the block offset of the blocks within the partition. In some embodiments, the processing system may identify the number of blocks in the partition. In some embodiments, the processing system may identify the location of the block header within the partition. In some embodiments, the processing system may identify that the block header includes an offset field. Components for performing the operations in block 1304 may include processors (e.g., 210, 212, 214, 216, 218, 252, 260, 428, 432).

[0144] In block 1306, the processing system can unpack the image data chunks according to the determined packing type used for the image data chunks. In some embodiments, the processing system can read the image data chunks independently of the second image data chunk. In some embodiments, the processor can read the image data chunks linearly, wherein the image data chunks are written in a tiled manner.

[0145] The processing system can repeat the operations of boxes 1302-1306 to process multiple image data blocks.

[0146] Figure 13B This is a conceptual block diagram illustrating examples of image decompression operations 1350 according to various implementation schemes. (Reference) Figures 1 to 13B Operation 1350 can be implemented by a processor (e.g., 210, 212, 214, 216, 218, 252, 260, 428, 432) of a processing system of a computing device (e.g., wireless devices 120a-120e, 200, 320, 402, 404).

[0147] In various implementations, the receiving computing device may receive compressed image data chunks and associated metadata (e.g., 1185).

[0148] In operation 1352, the processing system of the receiving computing device can decode metadata describing the packing type used for image data chunks. In some embodiments, the metadata may be included in the compressed tile. For example, the processing system may determine from the metadata a partition offset (e.g., field A: 0 bytes), a partition size (e.g., field B: 64 bytes), a block offset within the partition (e.g., field C: 3), the number of blocks in the partition header (e.g., field D: 3), whether a header is inserted at the 32-byte mark in the 64-byte partition (e.g., field E: yes (Y) or no (N)), and whether the header for that block includes an offset field (e.g., field F: yes (Y) or no (N)). In some embodiments, the block offset within the partition (e.g., field C) and the number of blocks in the partition header (e.g., field D) may be encoded or placed in the compressed tile. In some embodiments, the presence of an offset (e.g., field F: Y) may indicate that the first chunk in the block (i.e., a chunk that does not detach from or continue from the previous chunk) begins at the offset (to account for detachment or continuation). In this example, the third block is an overhanging block, and the previous block is not overhanging, so field F can indicate no for the third block, and field F can indicate yes for the fourth block.

[0149] In operation 1354, the processing system may load the indicated partition. For example, fields A and B may indicate the memory partition to be loaded (e.g., a 64B block) or the memory partition to be accessed (e.g., all blocks).

[0150] In operation 1356, the processing system can locate block information within a partition. In some embodiments, this block information may include block offsets within the partition (e.g., field C) and the number of blocks in the partition header (e.g., field D), and may be encoded or placed into compressed tiles. For example, fields C and D may indicate the location of data in the indicated block within the partition. In some embodiments, the total number allows header data to be packed at the beginning of the partition. In some embodiments, fields E and F may indicate bridging of one or more blocks. In some embodiments, the offset value may be determined based on values ​​in the header and / or intermediate headers.

[0151] In operation 1358, the processing system may transmit image data and related metadata to a decompressor block (or any suitable function of the computing device) for unpacking according to the determined packing type used for image data chunking.

[0152] Various implementations of methods and operations 900, 1000, 1100, 1120, 1185, 1200, 1300, and 1350 can be implemented in a variety of network computing devices, examples of which are shown in […]. Figure 14 Example in Figure 14This is a component block diagram of a network computing device 1400 suitable for use with various implementation schemes. Such a network computing device may include at least... Figure 14 The components shown. (See reference.) Figures 1 to 14 The network computing device 1400 may include a processing system 1401 coupled to volatile memory 1402 (e.g., 426) and mass non-volatile memory such as a disk drive 1403. The network computing device 1400 may also include peripheral memory access devices coupled to the processing system 1401, such as floppy disk drives, compact optical disc (CD) or digital video optical disc (DVD) drives 1406. The network computing device 1400 may also include a network access port 1404 (or interface) coupled to the processor 1401 for establishing data connections to networks such as the Internet and / or local area networks coupled to other system computers and servers. The network computing device 1400 may be connected to one or more antennas for transmitting and receiving electromagnetic radiation, which may be connected to a wireless communication link. The network computing device 1400 may include additional access ports for coupling to peripheral devices, external memory, or other devices, such as USB, FireWire, Thunderbolt, etc.

[0153] Various implementations of methods and operations 900, 1000, 1100, 1120, 1185, 1200, 1300, and 1350 can be performed in a variety of wireless devices (e.g., wireless devices 120a-120e, 200, 320, 402, 404), examples of which are described in... Figure 15 Example in Figure 15 This is a component block diagram of a wireless device 1500 suitable for use with various implementation schemes. (Reference) Figures 1 to 15 The wireless device 1500 may include a first SOC 202 (e.g., an SOC-CPU) coupled to a second SOC 204 (e.g., a 5G-enabled SOC). The first SOC 202 and the second SOC 204 may be coupled to internal memories 426, 430, 1516, a display 1512, and a speaker 1514. Additionally, the wireless device 1500 may include an antenna 1504 for transmitting and receiving electromagnetic radiation that can be connected to a wireless data link, and / or a cellular transceiver 266 coupled to one or more processors in the first SOC 202 and / or the second SOC 204. The wireless device 1500 may also include menu selection buttons or a joystick switch 1520 for receiving user input.

[0154] The wireless device 1500 may also include a voice codec (CODEC) circuit 1510 that digitizes sound received from a microphone into data packets suitable for wireless transmission and decodes the received voice data packets to generate an analog signal for use with a speaker to produce sound. Furthermore, one or more of the processor in the first SOC 202 and the second SOC 204, the wireless transceiver 266, and the CODEC 1510 may include digital signal processor (DSP) circuitry (not shown separately).

[0155] The processors of network computing device 1500 and wireless device 1500 can be any programmable microprocessor, microcomputer, or one or more multiprocessor chips that can be configured via software instructions (applications) to perform a variety of functions, including those described in the various embodiments below. In some wireless devices, multiple processors may be provided, such as one processor within SOC 204 dedicated to wireless communication functions and another within SOC 202 dedicated to running other applications. Software applications may be stored in memories 426, 430, and 1516, and then accessed and loaded into the processor. The processor may include internal memory sufficient to store application software instructions.

[0156] As used in this application, the terms "component," "module," "system," etc., are intended to include computer-related entities such as, but not limited to, hardware, firmware, combinations of hardware and software, software, or software being executed, configured to perform specific operations or functions. For example, a component can be, but is not limited to, a process running on a processor, a processor, an object, an executable file, an execution thread, a program, and / or a computer. By way of illustration, both an application running on a wireless device and the wireless device itself can be referred to as a component. One or more components may reside within a process and / or execution thread, and components may reside on a processor or core and / or be distributed across two or more processors or cores. Furthermore, these components may execute on various non-transitory computer-readable media on which various instructions and / or data structures are stored. Components may communicate via local and / or remote processes, function or procedure calls, electronic signals, data packets, memory read / write, and other known network, computer, processor, and / or process-related communication methods.

[0157] The various embodiments illustrated and described are provided merely as examples illustrating the various features of the claims. However, the features shown and described with respect to any given embodiment are not necessarily limited to the associated embodiment and may be used or combined with other embodiments shown and described. Furthermore, the claims are not intended to be limited to any one of the exemplary embodiments. For example, one or more operations of methods 900, 1000, 1100, 1120, 1185, 1200, 1300, and 1350 may substitute for or combine with one or more operations of methods 900, 1000, 1100, 1120, 1185, 1200, 1300, and 1350.

[0158] Specific implementation embodiments are described in the following paragraphs. While some of the specific implementation examples below are described based on exemplary methods, further exemplary implementations may include: the exemplary methods implemented by a computing device, as discussed in the following paragraphs, the computing device including a processing system configured with processing system executable instructions for performing the operations of the methods of the exemplary embodiments below; the exemplary methods implemented by a computing device, as discussed in the following paragraphs, the computing device including components for performing the functions of the methods of the exemplary embodiments below; and the exemplary methods discussed in the following paragraphs may be implemented as a non-transitory processing system readable storage medium storing processing system executable instructions configured to cause the processing system of the computing device to perform the operations of the methods of the exemplary embodiments below.

[0159] Example 1. A method for image compression executed by a processing system of a computing device, the method comprising: identifying the location of image color data in an interleaved format within a portion of memory for a portion of an image; and encoding metadata with a location identifier configured to describe the location of the image color data in the interleaved format within the portion of memory for the portion of the image.

[0160] Example 2. The method according to Example 1, wherein encoding the metadata with the location identifier includes encoding image data format-independent metadata.

[0161] Example 3. The method according to any one of Examples 1 or 2, the method further comprising generating the position identifier based on the position of the image color data in the interlaced format of the portion of the image within the portion of the memory.

[0162] Example 4. The method according to any one of Examples 1 to 3, wherein the location identifier is configured to indicate to the image decoder device that a component of the image color data is one of the following: compressed into a portion of a previous block, starting a block of a first size, starting a block of a second size, or being a first constant value or a second constant value.

[0163] Example 5. The method according to any one of Examples 1 to 4, wherein the location identifier is configured to indicate to the image decoder device that all components of the image color data are constant values.

[0164] Example 6. The method according to any one of Examples 1 to 5, wherein the location identifier is configured to indicate to the image decoder device that the starting component of the image color data is one of the following: starting a block of a first size, starting a block of a second size, being a first constant value, or being a second constant value.

[0165] Example 7. The method according to any one of Examples 1 to 6, wherein the image color data of the portion of the image in the portion of the memory in the interlaced format includes compressed image color data for at least one component of the image color data.

[0166] Example 8. The method according to any one of Examples 1 to 7, wherein the image color data of the portion of the image in the portion of the memory in the interlaced format includes a plurality of components of the image color data, such that each of the plurality of components represents either a color value or a transparency value.

[0167] Example 9. A method executed by a processing system of a computing device for image decompression, the method comprising: decoding metadata with a location identifier configured to describe the location of image color data of a portion of an image in an interleaved format within a portion of memory; and identifying, according to the location identifier, the location of the image color data of the portion of the image in the interleaved format within the portion of memory.

[0168] Example 10. The method according to Example 9, wherein the metadata is independent of the image data format.

[0169] Example 11. The method according to any one of Examples 9 or 10, wherein identifying the position of the image color data of the portion of the image in the interlaced format within the portion of the memory according to the position identifier comprises: identifying the position of the image color data of the portion of the image in the interlaced format within the portion of the memory according to a value associated with the position identifier, wherein each of the values ​​is configured to represent the position of one of a plurality of components of the image color data of the portion of the image in the interlaced format within the portion of the memory.

[0170] Example 12. The method according to any one of Examples 9 to 11, wherein decoding the metadata with a location identifier configured to describe the location of the image color data in the interleaved format within the portion of the memory of the portion of the image comprises: locating values ​​based on the location identifier to indicate the positions of a plurality of components of the image color data in the interleaved format within the portion of the memory of the portion of the image.

[0171] Example 13. The method according to any one of Examples 9 to 11, wherein decoding the metadata with a location identifier configured to describe the location of the image color data in the interleaved format within the portion of the memory of the portion of the image comprises: generating, based on the location identifier, values ​​of the locations of a plurality of components of the image color data in the interleaved format within the portion of the memory of the portion of the image.

[0172] Example 14. The method according to any one of Examples 9 to 13, wherein the location identifier is configured to indicate to the image decoder device that a component of the image color data is one of the following: compressed into a portion of a previous block, starting a block of a first size, starting a block of a second size, or being a first constant value or a second constant value.

[0173] Example 15. The method according to any one of Examples 9 to 14, wherein the location identifier is configured to indicate to the image decoder device that all components of the image color data are constant values.

[0174] Example 16. The method according to any one of Examples 9 to 15, wherein the location identifier is configured to indicate to the image decoder device that the starting component of the image color data is one of the following: starting a block of a first size, starting a block of a second size, being a first constant value, or being a second constant value.

[0175] Example 17. The method according to any one of Examples 9 to 16, wherein the image color data of the portion of the image in the portion of the memory in the interlaced format includes compressed image color data for at least one component of the image color data.

[0176] Example 18. According to the method of Examples 9 to 17, the image color data of the portion of the image in the portion of the memory in the interlaced format includes a plurality of components of the image color data, such that each of the plurality of components represents either a color value or a transparency value.

[0177] The foregoing method descriptions and process flowcharts are provided as illustrative examples only and are not intended to require or imply that the operations of the various embodiments must be performed in the given order. As those skilled in the art will recognize, the operations in the foregoing embodiments can be performed in any order. Words such as “afterward,” “then,” “next,” etc., are not intended to limit the order of operations; these words are used to guide the reader through the description of the method. Furthermore, any reference to singular claim elements (e.g., references using the articles “a,” “an,” or “described”) should not be construed as limiting that element to the singular.

[0178] The various exemplary logic blocks, modules, components, circuits, and algorithmic operations described in conjunction with the embodiments disclosed herein can be implemented as electronic hardware, computer software, or a combination of both. To clearly illustrate this interchangeability between hardware and software, various exemplary components, blocks, modules, circuits, and operations have been generally described above in terms of their functionality. Whether such functionality is implemented as hardware or software depends on the specific application and the design constraints imposed on the overall system. Those skilled in the art may implement the described functionality in different ways for each specific application, but such implementation decisions should not be construed as departing from the scope of the claims.

[0179] Hardware for implementing the various exemplary logic units, logic blocks, modules, and circuits described in conjunction with the embodiments disclosed herein may be implemented or executed using a general-purpose processor, digital signal processor (DSP), application-specific integrated circuit (ASIC), field-programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic unit, discrete hardware component, or any combination thereof designed to perform the functions described herein. While the general-purpose processor may be a microprocessor, in alternative embodiments, the processor may be any conventional processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of receiver intelligent objects, such as a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors combined with a DSP core, or any other such configuration. Alternatively, some operations or methods may be performed by circuitry specific to a given function.

[0180] In various implementations, the described functionality may be implemented in hardware, software, firmware, or any combination thereof. If implemented in software, the functionality may be stored as one or more instructions or code on a non-transitory computer-readable storage medium or a non-transitory processor-readable storage medium. The operation of the methods or algorithms disclosed herein may be implemented in a processor-executable software module or processor-executable instructions, which may reside on a non-transitory computer-readable or processor-readable storage medium. A non-transitory computer-readable or processor-readable storage medium may be any storage medium that can be accessed by a computer or processor. By way of example and without limitation, such non-transitory computer-readable or processor-readable storage media may include RAM, ROM, EEPROM, FLASH memory, CD-ROM or other optical disc storage devices, magnetic disk storage devices or other magnetic storage intelligent objects, or any other medium that can be used to store desired program code in the form of instructions or data structures and is accessible by a computer. As used herein, disks and optical discs include compact optical discs (CDs), laser discs, optical discs, digital versatile optical discs (DVDs), floppy disks, and Blu-ray discs, wherein disks typically magnetically reproduce data, while optical discs optically reproduce data using lasers. The above combinations are also included within the scope of non-transitory computer-readable and processor-readable media. Additionally, the operation of a method or algorithm may reside as one or any combination or set of code and / or instructions on a non-transitory processor-readable and / or computer-readable storage medium, which may be incorporated into a computer program product.

[0181] The above description of the disclosed embodiments is provided to enable any person skilled in the art to implement or use the claims. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein can be applied to other embodiments without departing from the scope of the claims. Therefore, this disclosure is not intended to be limited to the embodiments shown herein, but should be granted the broadest scope consistent with the following claims and the principles and novel features disclosed herein.

Claims

1. A method for image compression executed by a processing system of a computing device, the method comprising: The location of image color data in an interlaced format within a portion of memory that identifies a portion of the image; as well as The metadata is encoded with a location identifier, which is configured to describe the location of the image color data of the portion of the image within the portion of the memory in the interleaved format.

2. The method of claim 1, wherein encoding the metadata with the location identifier includes encoding image data format-independent metadata.

3. The method of claim 1, further comprising generating the location identifier based on the location of the image color data in the interlaced format of the portion of the image within the portion of the memory.

4. The method of claim 1, wherein the location identifier is configured to indicate to the image decoder device that a component of the image color data is one of: being compressed as part of a previous block, starting a block of a first size, starting a block of a second size, or being a first constant value or a second constant value.

5. The method of claim 1, wherein the location identifier is configured to indicate to the image decoder device that all components of the image color data are constant values.

6. The method of claim 1, wherein the location identifier is configured to indicate to the image decoder device that the starting component of the image color data is one of: starting a block of a first size, starting a block of a second size, being a first constant value, or being a second constant value.

7. The method of claim 1, wherein the image color data of the portion of the image in the portion of the memory in the interlaced format includes compressed image color data for at least one component of the image color data.

8. The method of claim 1, wherein the image color data of the portion of the image in the portion of the memory in the interlaced format comprises a plurality of components of the image color data, such that each of the plurality of components represents either a color value or a transparency value.

9. A computing device, the computing device comprising a processing system configured to: The location of image color data in an interlaced format within a portion of memory that identifies a portion of the image; and The metadata is encoded with a location identifier, which is configured to describe the location of the image color data of the portion of the image within the portion of the memory in the interleaved format.

10. The computing device of claim 9, wherein the processing system is configured to encode the metadata as image data format-independent metadata.

11. The computing device of claim 9, wherein the processing system is further configured to generate the location identifier based on the location of the image color data in the interleaved format within the portion of the memory of the portion of the image.

12. The computing device of claim 9, wherein the processing system is configured such that the location identifier is configured to indicate to the image decoder device that a component of the image color data is one of: being compressed as part of a previous block, starting a block of a first size, starting a block of a second size, being a first constant value or a second constant value, or the starting component of the image color data is one of: starting a block of the first size, starting a block of the second size, being the first constant value or the second constant value.

13. The computing device of claim 9, wherein the processing system is configured such that the location identifier is configured to indicate to the image decoder device that all components of the image color data are constant values.

14. The computing device of claim 9, wherein the processing system is configured such that the image color data of the portion of the image in the portion of the memory in the interleaved format includes compressed image color data for at least one component of the image color data.

15. The computing device of claim 9, wherein the processing system is configured such that the image color data of the portion of the image in the portion of the memory in the interleaved format includes a plurality of components of the image color data, such that each of the plurality of components represents either a color value or a transparency value.

16. A method performed by a processing system of a computing device for image decompression, the method comprising: The metadata is decoded using a location identifier, which is configured to describe the location of image color data in an interleaved format within a portion of memory for a portion of the image; as well as The location of the image color data of the portion of the image, in the interlaced format, within the portion of the memory, is identified by the location identifier.

17. The method of claim 16, wherein the metadata is image data format independent.

18. The method of claim 16, wherein identifying the location of the image color data of the portion of the image in the portion of the memory in the interlaced format according to the location identifier comprises: The location of the image color data of the portion of the image in the portion of the memory in the interlaced format is identified by a value associated with the location identifier, wherein each of the values ​​is configured to represent the location of one of a plurality of components of the image color data of the portion of the image in the interlaced format in the portion of the memory.

19. The method of claim 16, wherein decoding the metadata with the location identifier configured to describe the location of the image color data of the image in the interleaved format within the portion of the memory of the portion of the image comprises: The location identifier is used to locate the positions of multiple components of the image color data, configured to represent a portion of the image, within the portion of the memory in the interlaced format.

20. The method of claim 16, wherein decoding the metadata using a location identifier of the location of the image color data in the interleaved format within the portion of the memory, configured to describe the portion of the image, comprises: Based on the location identifier, values ​​are generated for the positions of multiple components of the image color data, configured to represent the portion of the image, within the portion of the memory in the interlaced format.

21. The method of claim 16, wherein the location identifier is configured to indicate to the image decoder device that a component of the image color data is one of: being compressed as part of a previous block, starting a block of a first size, starting a block of a second size, or being a first constant value or a second constant value.

22. The method of claim 16, wherein the location identifier is configured to indicate to the image decoder device that all components of the image color data are constant values.

23. The method of claim 16, wherein the location identifier is configured to indicate to the image decoder device that the starting component of the image color data is one of: starting a block of a first size, starting a block of a second size, being a first constant value, or being a second constant value.

24. The method of claim 16, wherein the image color data of the portion of the image in the portion of the memory in the interlaced format includes compressed image color data for at least one component of the image color data.

25. The method of claim 16, wherein the image color data of the portion of the image in the portion of the memory in the interlaced format comprises a plurality of components of the image color data, such that each of the plurality of components represents either a color value or a transparency value.

26. A computing device, the computing device comprising a processing system configured to: The metadata is decoded using location identifiers configured to describe the location of image color data in an interleaved format within a portion of memory for a portion of the image; and The location of the image color data of the portion of the image, in the interlaced format, within the portion of the memory, is identified by the location identifier.

27. The calculation of claim 26, wherein the processing system is further configured to identify the position of the image color data of the portion of the image in the interleaved format within the portion of the memory according to a value associated with the position identifier, wherein each of the values ​​is configured to represent the position of one of a plurality of components of the image color data of the portion of the image in the interleaved format within the portion of the memory.

28. The calculation of claim 26, wherein the processing system is further configured to locate, based on the location identifier, values ​​of multiple components of image color data configured to represent a portion of the image within the portion of the memory in the interleaved format.

29. The calculation of claim 26, wherein the processing system is further configured to generate, based on the location identifier, values ​​for the positions of multiple components of the image color data in the portion of the memory configured to represent the portion of the image in the interleaved format.

30. The calculation of claim 26, wherein the processing system is further configured to obtain one of a color value or a transparency value from a plurality of components of the image color data of the portion of the image in the portion of the memory in the interleaved format.

Images