Semiconductor chips and semiconductor articles

Abstract

With regard to a semiconductor chip for a core particle, a structure capable of appropriately forming an inductor is provided. An inductor (21) is formed in a wiring layer other than a wiring layer in which a plurality of bumps (13) are formed. The inductor (21) overlaps at least one of the plurality of bumps (13) in plan view. Thus, the inductor (21) can be appropriately formed without being restricted by the arrangement of the bumps.

Description

Technical Field

[0001] This disclosure relates to a semiconductor chip for use as a core. Background Technology

[0002] In recent years, a new technology known as "chip" has attracted much attention in the field of semiconductor technology. Chip refers to the technique of deliberately dividing large-scale circuits that were previously integrated into a single semiconductor chip into multiple smaller semiconductor chips, connecting these multiple semiconductor chips to a substrate called an "intermediate layer" via microbumps, and then mounting them onto a packaging substrate.

[0003] Furthermore, in most cases, semiconductor products include circuit configurations that incorporate inductors. Examples of circuit configurations that include inductors include LC-PLL (Phase Locked Loop) circuits used as clock sources.

[0004] Patent Document 1 discloses a structure for a semiconductor integrated circuit used in a receiving device that reduces the area occupied by the inductor in the equalizer performing equalization processing.

[0005] Existing technical documents

[0006] Patent documents

[0007] Patent Document 1: Japanese Patent Application Publication No. 2023-45027 Summary of the Invention

[0008] -The technical problem the invention aims to solve-

[0009] For example, in LC-PLL circuits, the inductor requires a high Q value due to the need for high speed and low jitter. Therefore, when forming an inductor on a semiconductor substrate, it is preferable to have fewer constraints on its size and arrangement. However, prior art documents, including Patent Document 1, have not disclosed any structures for forming inductors in the die.

[0010] This disclosure relates to semiconductor chips for use as chips, and provides a structure in which an inductor can be appropriately formed.

[0011] - Technical solutions used to solve technical problems -

[0012] The semiconductor chip for use in the first aspect of this disclosure includes a semiconductor substrate, a first wiring layer, and a second wiring layer. The first wiring layer is disposed on the semiconductor substrate and has a plurality of bumps formed thereon. The second wiring layer is disposed between the semiconductor substrate and the first wiring layer and has an inductor formed thereon. The inductor overlaps with at least one of the plurality of bumps when viewed from above.

[0013] According to this method, in a semiconductor chip for use as a die, the inductor is formed on a second wiring layer outside of a first wiring layer where multiple bumps are formed. The inductor overlaps with at least one of the multiple bumps when viewed from above. Therefore, the inductor can be appropriately formed without being constrained by the arrangement of the bumps. For example, for an inductor included in an LC-PLL circuit, it can be formed in a manner with a large area and a high Q value.

[0014] -The effects of the invention-

[0015] According to this disclosure, an inductor can be appropriately formed for a semiconductor chip used as a chip. Attached Figure Description

[0016] Figure 1 This is a cross-sectional view showing an example of the configuration of a semiconductor product according to an embodiment.

[0017] Figure 2 yes Figure 1 The circuit functions of semiconductor products.

[0018] Figure 3 This is an example of the circuit configuration of a PLL circuit.

[0019] Figure 4 yes Figure 3 Example of circuit configuration for the dashed section. Figure 4 In this context, (a) represents LCVCO. Figure 4 (b) in the figure represents an LCVCO with a transformer.

[0020] Figure 5 This is an example of a layer structure in a semiconductor chip involved in the implementation method.

[0021] Figure 6 This is a top view showing an example of the arrangement of microbumps, inductors, and capacitors in a semiconductor chip according to the embodiment.

[0022] Figure 7 (a) to (c) in the embodiments are the first examples of shielding structures involved in the implementation.

[0023] Figure 8 (a) to (c) are the second examples of the shielding structure involved in the implementation method.

[0024] Figure 9 (a) to (c) are the third examples of the shielding structure involved in the implementation method.

[0025] Figure 10 (a) to (d) are the fourth examples of shielding structures involved in the implementation method.

[0026] Figure 11(a) to (d) in the embodiments are the fifth examples of shielding structures involved in the implementation.

[0027] Figure 12 (a) to (e) are the sixth examples of shielding structures involved in the implementation method. Detailed Implementation

[0028] Hereinafter, embodiments will be described with reference to the accompanying drawings. In this specification, "top view" refers to viewing a semiconductor chip or the like from a direction perpendicular to the surface of the semiconductor chip.

[0029] Figure 1 This is a cross-sectional view showing an example of the configuration of a semiconductor product according to an embodiment. Figure 1 The semiconductor product shown is composed of a chip and an architecture. Figure 1 The semiconductor product shown includes a packaging substrate 1, an interposer layer 2 having a relay wiring structure, and semiconductor chips 11 and 12 as semiconductor chips for use as cores.

[0030] On the underside of the package substrate 1, a BGA (Ball Grid Array) 3, serving as an example of an external connection terminal, is formed. Furthermore, a capacitor 4 is formed on the same side of the package substrate 1. An interposer 2 is arranged on the upper side of the package substrate 1 via a plurality of microbumps 5.

[0031] Semiconductor chip 11 is connected to the upper surface of the dielectric layer 2 via a plurality of microbumps 13. Semiconductor chip 12 is connected to the upper surface of the dielectric layer 2 via a plurality of microbumps 14. Semiconductor chip 11 includes transceiver circuitry 15, and semiconductor chip 12 includes transceiver circuitry 16. Transceiver circuitry 15 and transceiver circuitry 16 transmit and receive data via the dielectric layer 2. Transceiver circuitry 15 and 16 can also be provided as IP macros.

[0032] Figure 2 This is a diagram illustrating an example of the circuit functions of transceiver circuits 15 and 16. Figure 2 The circuit shown constitutes a transceiver system based on the BoW (Bunch of Wires) standard. The BoW standard refers to a standard where only the master chip has a clock source, and the slave chip receives the clock from the master chip.

[0033] The transceiver circuit 15 includes a PLL (Phase Locked Loop) circuit 17 as a clock source. The transceiver circuit 15 uses the clock generated by the PLL circuit 17 to transmit data and also transmit the clock signal. The transceiver circuit 16 uses the clock signal sent from the transceiver circuit 15 to perform tasks such as restoring the transmitted data.

[0034] Figure 3 This is a typical circuit configuration example of a PLL circuit. Figure 3 The PLL circuit shown is a so-called LC-PLL, including a phase comparator (PFD) 21, a charge pump (CP) 22, a low-pass filter (LPF) 23, a voltage-controlled oscillator (VCO) 24, and a frequency divider (DIV) 25. The phase comparator 21 outputs a pulse signal as the phase difference between the input reference clock refclk and the clock obtained by dividing the output clock vcoclk. The charge pump 22 outputs a current corresponding to the detected phase difference. The low-pass filter 23 generates a control voltage Vtol based on the output current of the charge pump 22, and the voltage-controlled oscillator 24 oscillates at a frequency corresponding to the control voltage Vtol, generating the output clock vcoclk.

[0035] Figure 4 It is shown Figure 3 The diagram shows an example of the circuit configuration for section A (shown by the dashed line). Figure 4 (a) in the text is an example of an LCVCO. Figure 4 (b) is an example of an LCVCO with a transformer.

[0036] exist Figure 4 In example (a), the LCVCO comprises an LPF and a VCO. The LPF contains capacitors and resistors, generating a control voltage Vtol. The VCO consists of a pair of MOM capacitors connected in series, a pair of variable capacitors connected in series with capacitance varying according to the control voltage Vtol, an inductor, and a pair of cross-coupled inverters connected in parallel, generating a differential output clock (CK, CKX). The variable capacitors are formed, for example, by varactor diodes.

[0037] exist Figure 4 In example (b), the LCVCO comprises an LPF and a VCO, and has a transformer. The LPF has... Figure 4 The circuit structure is the same as (a) in the example. The VCO, besides... Figure 4 In addition to the circuit configuration in (a), it also has a secondary inductor that is connected in parallel with the capacitor and forms a transformer. The secondary inductor is configured to be able to switch between an ON state and a OFF state via a switching circuit, thereby switching the transformer on and off.

[0038] Here, because LC-PLLs require high speed and low jitter, the inductors used in LCVCOs need to have a high Q (Quality Factor) value and need to be formed with large-size, low-resistance wiring. Therefore, in general semiconductor chips, inductors are preferably formed on, for example, a low-resistance top layer (e.g., an aluminum wiring layer). However, in a chip architecture, multiple microbumps are formed on the top layer of the semiconductor chip. Therefore, in semiconductor chips used in chips, if an attempt is made to form inductors on the same top layer, the constraints caused by the arrangement of microbumps are significant, making it difficult to form suitable inductors.

[0039] In other words, because the microbumps are formed on the top layer of the semiconductor chip and arranged regularly with a narrow pitch, there is insufficient space on the top layer to freely form inductors. Furthermore, if inductors and microbumps are placed close together on the top layer, interference may cause changes in inductance or introduce noise. In this case, the characteristics of the PLL will deteriorate, so sufficient spacing must be ensured between the inductors and microbumps. Moreover, even if inductors can be formed in the free space on the top layer, the layout of the PLL circuit will be constrained by the placement of the inductors. This may lead to an increase in the area of ​​the PLL circuit or increased installation difficulty.

[0040] Therefore, in this embodiment, the inductor is not formed on the top layer of the semiconductor chip, but on an intermediate layer (e.g., a copper wiring layer). The wiring resistance is higher in the intermediate layer compared to the top layer. However, in the case of PLL circuits used in the BoW standard, for example, low long-term jitter is not required, and the requirement for low jitter is not so high; the inductor used in LCVCOs does not require such a high Q value. Therefore, in semiconductor chips used as chips, even if the inductor is formed on an intermediate layer, by appropriately selecting the intermediate layer and setting the inductor to an appropriate size, the desired characteristics regarding Q value and so on can be obtained.

[0041] Figure 5 This is an example of a layer structure in the semiconductor chip 11 involved in the implementation method. For example... Figure 5As shown, in this embodiment, the microbump layer with microbumps 13 is located on the topmost layer. Below the microbump layer, there is an inductor layer, on which an inductor comprising an LC-PLL is formed. Furthermore, below the inductor layer, there is a MOM (Metal-Oxide-Metal) capacitor layer forming a capacitor. In addition, in this embodiment, a shielding layer with shielding wiring is provided above and below the inductor layer. Between the shielding layer and the microbump layer, a power grid layer is provided, on which a power grid with grid-like power wiring is formed. The power grid is also formed on the same wiring layer as the inductor layer. Below the MOM capacitor layer, a transistor layer with transistor groups is provided. The transistor groups are formed, for example, on a semiconductor substrate. Furthermore, in addition to the above layers, a connection layer with interconnect wiring is also provided. The connection layer is also formed on the above layers as needed. It should be noted that each layer can be composed of a single wiring layer or multiple adjacent wiring layers.

[0042] Figure 6 This is a top view showing an example of the arrangement of microbumps, inductors, and capacitors in the semiconductor chip 11 according to the embodiment. Figure 6 In the arrangement example, in the microbump layer, 4×4 microbumps 13 are arranged regularly. That is, four microbumps 13 arranged at the vertices of a roughly rectangular shape are grouped together, and the groups of microbumps are arranged regularly in a grid pattern.

[0043] It should be noted that microbumps are, for example, bumps with a size of less than tens of μm, particularly bumps with a size of several μm to tens of μm. For example, when the bump shape is approximately spherical, the size of the bump is the diameter of the sphere; when the bump shape is approximately cylindrical, the size of the bump is the diameter of the cylinder; and when the bump shape is approximately cuboid, the size of the bump is the length of the long side, short side, or diagonal of the rectangle when viewed from above.

[0044] Furthermore, two inductors 21 are arranged in the inductor layer. A portion of the inductor 21 overlaps with the microbump 13 when viewed from above.

[0045] With this arrangement, the inductor 21 can be formed freely and appropriately in size and position without being constrained by the arrangement of the microbumps 13. Therefore, the desired characteristics, such as the Q value, can be obtained for the inductor 21. It should be noted that the size of the inductor is, for example, the outer diameter of the inductor; when the inductor is formed by spiral wiring, the size of the inductor is the outer diameter of the spiral.

[0046] Furthermore, assume that each of the microbumps 13 has a size Dim_B when viewed from above, and is arranged at intervals Int_B. Assume that the inductor 21 has a size Dim_I when viewed from above. In this case, the following relationship can also be satisfied:

[0047] Dim_I < 2×Dim_B + Int_B

[0048] This relationship. That is, as... Figure 6 As shown, the inductor 21 can be configured such that, when viewed from above, its size converges within the space occupied by a group of four microbumps 13 arranged at the apex of a generally rectangular shape.

[0049] Furthermore, four capacitors 22 are arranged in the MOM capacitor layer. A portion of the capacitors 22 overlaps with the microbumps 13 when viewed from above. In addition, a portion of the capacitors 22 overlaps with the inductor 21 when viewed from above.

[0050] With this arrangement, the capacitor 22 can be formed freely and appropriately in terms of size and position, without being constrained by the arrangement of the microbumps 13 and the inductor 21. It should be noted that the capacitor 22 may also not overlap with the microbumps 13 and the inductor 21 when viewed from above.

[0051] (Shielding structure)

[0052] For an inductor formed in an inductor layer, if there are structures forming current loops in the surrounding area of ​​its upper, lower, or same layers, it itself becomes an inductor, resulting in mutual induction with the actual inductor. Due to this mutual induction, the characteristics of the actual inductor will change. To avoid / suppress this change in characteristics, a shielding structure is formed in this embodiment. The shielding structure consists of shielding wiring formed in the shielding layers provided in the upper and lower layers of the inductor layer, and shielding wiring formed in the inductor layer itself.

[0053] It should be noted that in the following description, in the top view, the horizontal direction in the attached drawing is set as the X direction, and the vertical direction in the attached drawing is set as the Y direction.

[0054] (first example)

[0055] Figure 7 This illustrates a first example of the shielding structure involved in the implementation method. Figure 7 middle, Figure 7 (a) is a top view showing the inductor layer and the underlying shielding layer. Figure 7 (b) is a top view showing the inductor layer and the shielding layer above it. Figure 7 (c) in the middle is along Figure 7 The sectional view taken along line A-B in (a) and (b).

[0056] like Figure 7 As shown in (a), a pair of shielding wires 31 extending in the Y direction are formed on the lower layer of inductor 21. When viewed from above, the shielding wires 31 are connected to power supply wires 33 and 34 via vias 36 at two locations P1 and P2 sandwiching inductor 21, and their potentials are fixed. Figure 7 As shown in (b), a pair of shielding wires 32 extending in the Y direction are formed on the upper layer of the inductor 21. When viewed from above, the pair of shielding wires 32 are connected to the power supply wires 33 and 34 via vias 37 at two locations P3 and P4 that sandwich the inductor 21, and the potential is fixed.

[0057] A pair of shielded wirings 31 form a current loop by connecting at two locations P1 and P2. A pair of shielded wirings 32 form a current loop by connecting at two locations P3 and P4. Since these current loops affect the characteristics of the inductor 21, to suppress this effect, it is preferable that the connection locations P1 to P4 be located as far away from the inductor 21 as possible. For example, it is preferable that the distance between each connection location P1 to P4 and the inductor 21 is greater than the inductor's dimension Dim_I.

[0058] (Second example)

[0059] Figure 8 A second example of the shielding structure involved in the embodiment is shown. Figure 8 middle, Figure 8 (a) is a top view showing the inductor layer and the underlying shielding layer. Figure 8 (b) is a top view showing the inductor layer and the shielding layer above it. Figure 8 (c) in the middle is along Figure 8 The sectional view taken along line A-B in (a) and (b).

[0060] like Figure 8 As shown in (a), a pair of shielding wires 31 extending in the Y direction are formed on the lower layer of inductor 21. However, the pair of shielding wires 31 are connected to the power supply wire 35 via a via 38 at only one location, and their potential is fixed. Figure 8 As shown in (b), a pair of shielding wires 32 extending in the Y direction are formed on the upper layer of the inductor 21. However, the pair of shielding wires 32 are connected to the power supply wires 35 via vias 39 at only one location, and the potential is fixed.

[0061] In the second example, unlike the first, the shielding wiring does not form a current loop. Therefore, it has no effect on the characteristics of inductor 21.

[0062] (Third case)

[0063] Figure 9A third example of the shielding structure involved in the implementation is shown. Figure 9 middle, Figure 9 (a) is a top view showing the inductor layer and the underlying shielding layer. Figure 9 (b) is a top view showing the inductor layer and the shielding layer above it. Figure 9 (c) in the middle is along Figure 9 The sectional view taken along line A-B in (a) and (b).

[0064] like Figure 9 As shown in (a), a pair of shielding wires 31 extending in the Y direction are formed on the lower layer of inductor 21. However, the potential of the pair of shielding wires 31 is not fixed, but rather floating. Figure 9 As shown in (b), a pair of shielding wires 32 extending in the Y direction are formed on the upper layer of inductor 21. However, the potential of the pair of shielding wires 32 is not fixed, but is in a floating state.

[0065] In the third example, unlike the first, the shielding wiring does not form a current loop. Therefore, it has no effect on the characteristics of inductor 21.

[0066] It should be noted that in the first to third examples, shielding wiring is formed on both the lower and upper layers of inductor 21, but this is not a limitation. For example, shielding wiring may be formed only on the lower layer or only on the upper layer of inductor 21. Furthermore, in the first to third examples, a pair of shielding wiring is formed, but this is not a limitation. For example, a single shielding wiring may be formed, or three or more shielding wiring may be formed.

[0067] (Fourth case)

[0068] Figure 10 A fourth example of the shielding structure involved in the implementation is shown. Figure 10 middle, Figure 10 (a) is a top view showing the inductor layer and the underlying shielding layer. Figure 10 (b) is a top view showing the inductor layer and the shielding layer above it. Figure 10 (c) in the middle is along Figure 10 The sectional views taken along line A-B in (a) and (b) are shown. Figure 10 (d) in the middle is along Figure 10 The sectional view taken along line C-D in (a) and (b).

[0069] like Figure 10As shown in (a) and (b), two shielding wires 41 and 42 are formed in the same wiring layer as inductor 21, surrounding both sides of inductor 21 in the X direction and both sides in the Y direction. The two ends of shielding wires 41 and 42 are connected via vias 46 to shielding wire 43 formed in the lower shielding layer, and the two ends are connected via vias 47 to shielding wire 44 formed in the upper shielding layer. Here, shielding wires 41 and 42 are, for example, power lines of a power grid formed in the same inductor layer as inductor 21. Therefore, the potential of shielding wires 41, 42, 43, and 44 is fixed.

[0070] like Figure 10 As shown, a gap 61 is formed between shielded wiring 41 and shielded wiring 42. The gap 61 prevents the formation of current loops by the portions of shielded wiring 41 and 42 that extend in a manner that surrounds both sides of the inductor 21 in the X direction and both sides in the Y direction.

[0071] It should be noted that, in the fourth example, the gap 61 is formed in the portion of the shielding wiring 41 and the shielding wiring 42 that extends in a manner surrounding both sides of the inductor 21 in the X direction, but the location of the gap 61 is not limited to the manner of the fourth example. The location of the gap 61 can be any location that can prevent the formation of a current loop. For example, the gap 61 can also be formed in the portion of the shielding wiring 41 and the shielding wiring 42 that extends in a manner surrounding both sides of the inductor 21 in the Y direction.

[0072] On the other hand, the two ends of shielded wirings 41 and 42 are connected to shielded wirings 43 and 44, thereby forming a current loop. In order to suppress the influence of this current loop on the inductor characteristics, shielded wirings 43 and 44 are preferably located as far away from the inductor 21 as possible. For example, it is preferable that the distance between each of shielded wirings 43 and 44 and the inductor 21 when viewed from above is greater than the size Dim_I of the inductor 21.

[0073] (Fifth case)

[0074] Figure 11 This illustrates a fifth example of a shielding structure involved in the implementation method. Figure 11 middle, Figure 11 (a) is a top view showing the inductor layer and the underlying shielding layer. Figure 11 (b) is a top view showing the inductor layer and the shielding layer above it. Figure 11 (c) in the middle is along Figure 11 The sectional views taken along line A-B in (a) and (b) are shown. Figure 11 (d) in the middle is along Figure 11 The sectional view taken along line C-D in (a) and (b).

[0075] like Figure 11 As shown in (a) and (b), shielding wiring 45 is formed in the same wiring layer as inductor 21, surrounding both sides of inductor 21 in the X direction and both sides in the Y direction. Both ends of shielding wiring 45 are connected to shielding wiring 43 formed in the lower shielding layer via vias 48, and both ends are connected to shielding wiring 44 formed in the upper shielding layer via vias 49. Here, similar to the fourth example, shielding wiring 45 is, for example, composed of power wiring of a power grid formed in the same inductor layer as inductor 21. Therefore, the potential of shielding wirings 43, 44, and 45 is fixed.

[0076] like Figure 11 As shown, a gap 62 is formed in the shielding wiring 45. The gap 62 prevents the formation of a current loop from the portion of the shielding wiring 45 that extends to surround both sides of the inductor 21 in the X direction and both sides in the Y direction. It should be noted that, similar to the fourth example, the location of the gap 62 is not limited to the method in the fifth example; it can be any location that prevents the formation of a current loop.

[0077] Furthermore, in the fifth example, the two ends of shielded wiring 45 are connected to shielded wirings 43 and 44, but unlike the fourth example, the connection of the shielded wiring does not form a current loop. Therefore, it has no effect on the characteristics of inductor 21.

[0078] (Sixth case)

[0079] Figure 12 A sixth example of the shielding structure involved in the implementation is shown. Figure 12 middle, Figure 12 (a) is a top view showing the inductor layer and the underlying shielding layer. Figure 12 (b) is a top view showing the inductor layer and the shielding layer above it. Figure 12 (c) in the middle is along Figure 12 The sectional views taken along line A-B in (a) and (b) are shown. Figure 12 (d) in the middle is along Figure 12 The sectional view taken along line C-D in (a) and (b) of the diagram. Figure 12 (e) in the middle is along Figure 12 The sectional views taken along line E-F in (a) and (b).

[0080] In the sixth example, by actively utilizing the current loop formed by the shielded wiring to create a transformer between the transformer and inductor 21, the inductance value of inductor 21 is changed, thereby expanding the oscillation range of the LC-VCO. That is, a transformer is formed in the sixth example. The switching elements SW1 and SW2 are configured to switch between an on state (conducting) and a non-conducting state (disconnecting). Here, the switching elements SW1 and SW2 are composed of transistors located on the lower layer of inductor 21.

[0081] like Figure 12 As shown in (a), a pair of shielding wires 51 extending in the Y direction are formed on the lower layer of inductor 21. The pair of shielding wires 51 are connected to the power supply wire 53 via a via 54 at only one location, and their potential is fixed. Furthermore, the pair of shielding wires 51 are interconnected via a switching element SW1 and a connecting wire 56. The location where the power supply wire 53 is connected and the location where the switching element SW1 is connected are situated at the position where the inductor 21 is clamped when viewed from above.

[0082] Similarly, as Figure 12 As shown in (b), a pair of shielding wires 52 extending in the Y direction are formed on the upper layer of inductor 21. The pair of shielding wires 52 are connected to the power supply wire 53 via a via 55 at only one location, and their potential is fixed. Furthermore, the pair of shielding wires 52 are interconnected via a switching element SW2 and a connecting wire 57. The location where the power supply wire 53 is connected and the location where the switching element SW2 is connected are situated at the position where the inductor 21 is clamped when viewed from above.

[0083] When switching element SW1 is turned on, a pair of shielded wires 51 conduct to each other, forming a current loop 58 (the dashed line in the figure). This creates a transformer between inductor 21 and the parasitic inductance generated by current loop 58, thus changing the inductance value of inductor 21. Furthermore, when switching element SW2 is turned on, a pair of shielded wires 52 conduct to each other, forming a current loop 59 (the dashed line in the figure). This also creates a transformer between inductor 21 and the parasitic inductance generated by current loop 59, thus changing the inductance value of inductor 21.

[0084] It should be noted that the dimensions of the current loop 58 formed by the shielded wiring 51 and the current loop 59 formed by the shielded wiring 52 are different. Correspondingly, the inductance value of the parasitic inductor generated by the current loop is also different between the current loop 58 and the current loop 59. Therefore, by changing the combination of the on / off states of the switching elements SW1 and SW2, the inductance value of the inductor 21 can be changed in various modes.

[0085] It should be noted that the shielding structure in the sixth example can also be applied to devices other than semiconductor chips used in the core. This shielding structure enables an inductor structure where the inductance value can be changed by switching elements on and off. For example, it can be used to implement an LCVCO with a transformer.

[0086] -Industry Applicability-

[0087] In this disclosure, a structure is provided for semiconductor chips for use as chips, which can be appropriately formed into inductors, and is therefore useful, for example, for the miniaturization of semiconductor articles.

[0088] - Symbol Explanation -

[0089] 1 Packaging substrate

[0090] 2. Intermediary layer

[0091] 11, 12 Semiconductor chips

[0092] 13, 14 Microbumps

[0093] 17 PLL Circuit

[0094] 21 Inductors

[0095] 22 Capacitors

[0096] Shielded cabling 31, 32

[0097] Shielded cabling 41, 42, 43, 44, 45

[0098] Shielded cabling 51, 52

[0099] SW1 and SW2 are switching elements.

Claims

1. A semiconductor chip for use as a chip, characterized in that: The semiconductor chip includes a semiconductor substrate, a first wiring layer, and a second wiring layer. The first wiring layer is disposed on the semiconductor substrate and has multiple bumps formed thereon. The second wiring layer is disposed between the semiconductor substrate and the first wiring layer, and an inductor is formed therein. The inductor overlaps with at least one of the plurality of bumps when viewed from above.

2. The semiconductor chip according to claim 1, characterized in that: The plurality of bumps are micro-bumps.

3. The semiconductor chip according to claim 1, characterized in that: The plurality of bumps, when viewed from above, each have a size of Dim_B and are arranged at intervals of Int_B. The inductor has a size of Dim_I when viewed from above. The following relationship must be satisfied: Dim_I < 2 × Dim_B + Int_B.

4. The semiconductor chip according to claim 1, characterized in that: The semiconductor chip includes a third wiring layer, which is disposed between the semiconductor substrate and the second wiring layer, or between the first wiring layer and the second wiring layer, and forms a capacitor thereon. The capacitor overlaps with the inductor when viewed from above.

5. The semiconductor chip according to claim 4, characterized in that: The capacitor has a MOM structure.

6. The semiconductor chip according to claim 1, characterized in that: The semiconductor chip includes a first shielding wiring, which is disposed on a fourth wiring layer located above or below the second wiring layer, and is arranged to have a portion overlapping the inductor when viewed from above.

7. The semiconductor chip according to claim 6, characterized in that: The first shielding wiring is a pair of shielding wirings extending in a first direction.

8. The semiconductor chip according to claim 7, characterized in that: The pair of shielded wires are connected to each other at a first position and a second position in the first direction and have a fixed potential. The first and second positions are located where the inductor is clamped when viewed from above.

9. The semiconductor chip according to claim 8, characterized in that: The inductor has a size of Dim_I when viewed from above. The distance between the first position and the second position and the inductor is greater than Dim_I.

10. The semiconductor chip according to claim 7, characterized in that: The pair of shielded wires are connected to each other at only one location in the first direction and have a fixed potential.

11. The semiconductor chip according to claim 7, characterized in that: The pair of shielded wires are not connected to each other and are in a floating state.

12. The semiconductor chip according to claim 7, characterized in that: The pair of shielded wirings are interconnected at a first position in the first direction and have a fixed potential, and are interconnected at a second position in the first direction via a switching element, the switching element being configured to switch between an on state and a non-conducting state. The first and second positions are located where the inductor is clamped when viewed from above.

13. The semiconductor chip according to claim 12, characterized in that: The switching element is composed of a transistor formed on the lower layer of the second wiring layer.

14. The semiconductor chip according to claim 1, characterized in that: The semiconductor chip includes a second shielding wiring formed in the second wiring layer to surround the inductor when viewed from above.

15. The semiconductor chip according to claim 14, characterized in that: The semiconductor chip includes a pair of shielded wirings disposed on a fourth wiring layer located above or below the second wiring layer, which, when viewed from above, clamps the inductor extension. The second shielding wire is connected to the pair of shielding wires, and the potential of the second shielding wire is fixed.

16. The semiconductor chip according to claim 15, characterized in that: The inductor has a size of Dim_I when viewed from above. The spacing between each pair of shielded wirings and the inductor when viewed from above is greater than Dim_I.

17. The semiconductor chip according to claim 1, characterized in that: The semiconductor chip includes a phase-locked loop circuit, which contains an LC voltage-controlled oscillator. The inductor is used in the LC voltage-controlled oscillator.

18. A semiconductor article composed of a chip and an architecture, characterized in that: The semiconductor product includes a packaging substrate, an interposer, and a first semiconductor chip. The interposer layer has a relay wiring structure and is connected to the surface of the packaging substrate. The first semiconductor chip is the semiconductor chip described in any one of claims 1 to 17. The first semiconductor chip is connected to the side of the interposer layer opposite to the packaging substrate via the plurality of bumps.

19. The semiconductor article according to claim 18, characterized in that: The semiconductor product includes a second semiconductor chip, which is connected to the side of the interposer layer opposite to the packaging substrate via a plurality of bumps. The first semiconductor chip includes a phase-locked loop circuit, which contains an LC voltage-controlled oscillator and generates a clock signal. The inductor is used in the LC voltage-controlled oscillator. The second semiconductor chip receives the clock signal output from the first semiconductor chip.

20. A semiconductor chip, characterized in that: The semiconductor chip includes a semiconductor substrate, a first wiring layer, and a pair of shielding wirings. The first wiring layer is disposed on the semiconductor substrate and an inductor is formed thereon. The pair of shielded wirings are arranged on a second wiring layer located above or below the first wiring layer, extending in a first direction, and arranged to have a portion overlapping the inductor when viewed from above. The pair of shielded wirings are interconnected at a first position in the first direction and have a fixed potential, and are interconnected at a second position in the first direction via a switching element, the switching element being configured to switch between an on state and a non-conducting state. The first and second positions are located where the inductor is clamped when viewed from above.

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