Overhanging patterns for advanced oled patterning

Abstract

The embodiments described herein relate to subpixel circuits and methods for forming subpixel circuits. The subpixel circuit includes adjacent overhang structures, an anode, an organic light-emitting diode (OLED) material disposed on the anode, and a cathode disposed on the OLED material. The OLED material extends below the adjacent overhang structure. The cathode extends below the adjacent overhang structure. The overhang structure is defined by a second structure extending laterally beyond the overhang extension of the first structure. The first structure is disposed on a substrate. The first structure includes a lower segment having a first lateral etch rate and an upper segment deposited on the lower segment having a second lateral etch rate. The second lateral etch rate is different from the first lateral etch rate.

Description

Technical Field

[0001] The embodiments described herein generally relate to displays. More specifically, the embodiments described herein relate to subpixel circuits that can be used in displays, such as organic light-emitting diode (OLED) displays, and methods for forming subpixel circuits. Background Technology

[0002] Input devices, including display devices, can be used in a wide variety of electronic systems. An organic light-emitting diode (OLED) is a light-emitting diode (LED) in which the emitting electroluminescent layer is a film of organic compounds that emits light in response to an electric current. OLED devices are classified as bottom-emitting devices if the emitted light passes through a transparent or translucent bottom electrode and a substrate on which the panel is fabricated. Top-emitting devices are classified based on whether the light emitted by the OLED device exits through a cover added after the device is manufactured. OLEDs are used in many electronic devices today to create display devices. Today's electronics manufacturers are pushing for smaller sizes of these displays while providing higher resolutions than just a few years ago.

[0003] OLED pixel patterning is currently based on processes that limit panel size, pixel resolution, and substrate size. Pixel patterning can be achieved using photolithography instead of fine metal masks. Currently, OLED pixel patterning requires the removal of organic material after the patterning process. During removal, the organic material leaves behind particles that degrade OLED performance. Therefore, this technology requires sub-pixel circuits and methods for forming these circuits to increase the number of pixels per inch and provide improved OLED performance. Summary of the Invention

[0004] In one embodiment, a sub-pixel circuit is disclosed. The sub-pixel circuit includes adjacent overhang structures, an anode, an organic light-emitting diode (OLED) material disposed on the anode, and a cathode disposed on the OLED material. The OLED material extends below the adjacent overhang structure. The cathode extends below the adjacent overhang structure. The overhang structure is defined by a second structure extending laterally beyond the overhang extension of the first structure. The first structure is disposed on a substrate. The first structure includes a lower segment having a first lateral etch rate and an upper segment deposited on the lower segment having a second lateral etch rate. The second lateral etch rate is different from the first lateral etch rate.

[0005] In another embodiment, an apparatus is disclosed. The apparatus includes a substrate, a plurality of adjacent pixel-isolation structures (PIS) disposed on the substrate, and a plurality of sub-pixels. Each sub-pixel includes an adjacent overhang structure, an anode, an organic light-emitting diode (OLED) material disposed on the anode, and a cathode disposed on the OLED material. The overhang structure is defined by an overhang extension of a second structure extending laterally beyond the first structure. The first structure is disposed on the substrate. The first structure includes a first endpoint of a bottom surface of the first structure, a second endpoint of a bottom surface of the first structure, a lower segment having a first lateral etch rate, and an upper segment deposited on the lower segment having a second lateral etch rate. The first endpoint extends to or beyond a first edge of the PIS, and the second endpoint extends to or beyond a second edge of the PIS. The second lateral etch rate is different from the first lateral etch rate. The OLED material extends below the adjacent overhang structure. The cathode extends below the adjacent overhang structure.

[0006] In another embodiment, a method for forming a sub-pixel circuit is disclosed. The method includes disposing a lower segment layer having a first lateral etch rate on a substrate. An anode is deposited on the substrate. An upper segment layer having a second lateral etch rate is disposed on the lower segment layer. The first lateral etch rate is different from the second lateral etch rate. The lower segment layer and the upper segment layer form a first structural layer. A second structural layer is disposed on the first structural layer. Resist-exposed portions of the first and second structural layers are removed to form adjacent overhang structures, which are defined by overhang extensions of a second structure formed by the second structural layer, the overhang extensions laterally extending beyond the first structure formed by the first structural layer. The first structure is disposed on the substrate. The first structure includes an upper segment formed by the upper segment layer and a lower segment formed by the lower segment layer. Attached Figure Description

[0007] To gain a more detailed understanding of the features and methods employed in this disclosure, a more specific description of the disclosure, which has been briefly outlined above, can be obtained with reference to embodiments, some of which are illustrated in the accompanying drawings. However, it should be noted that the drawings illustrate only exemplary embodiments and should not be construed as limiting the scope, as this disclosure allows for other equally effective embodiments.

[0008] Figure 1A This is a schematic cross-sectional view of the sub-pixel circuit according to an embodiment.

[0009] Figure 1B This is a schematic cross-sectional view of the overhang structure of the sub-pixel circuit according to an embodiment.

[0010] Figure 2 This is a flowchart of a method for forming a sub-pixel circuit according to an embodiment.

[0011] Figures 3A to 3J According to the implementation method Figure 2 A schematic cross-sectional view of the substrate during the method for forming sub-pixel circuits.

[0012] For ease of understanding, the same reference numerals have been used to denote common elements in the figures where possible. It is contemplated that elements disclosed in one embodiment may be advantageously used in other embodiments without further detail. Detailed Implementation

[0013] The embodiments described herein generally relate to displays. More specifically, the embodiments described herein relate to subpixel circuits that can be used in displays, such as organic light-emitting diode (OLED) displays, and methods for forming subpixel circuits.

[0014] Figure 1A This is a schematic cross-sectional view of the sub-pixel circuit 100. Figure 1B This is a schematic cross-sectional view of the overhang structure 110 of the sub-pixel circuit 100. The sub-pixel circuit 100 includes a substrate 102. A base layer (not shown) may be patterned on the substrate 102. The base layer includes, but is not limited to, a CMOS layer. A metal layer (e.g., anode 104) may be patterned on the substrate 102 (or, if a base layer is present, the anode 104 may be patterned on the base layer) and defined by adjacent pixel isolation structures (PIS) 126 disposed on the substrate 102. In one embodiment, the anode 104 is pre-patterned on the substrate 102 (or the base layer). For example, the substrate 102 is pre-patterned to have an anode 104 that is indium tin oxide (ITO). The anode 104 is configured to operate as the anode of a corresponding sub-pixel. In one embodiment, the anode 104 is a layer stack of a first transparent conductive oxide (TCO) layer, a second metal layer disposed on the first TCO layer, and a third TCO layer disposed on the second metal layer. Anode 104 includes, but is not limited to, chromium, titanium, gold, silver, copper, aluminum, ITO, combinations thereof, or other suitable conductive materials.

[0015] PIS 126 is disposed on substrate 102. PIS 126 may be disposed on substrate 102 (or a base layer). PIS 126 includes one of organic materials, organic materials on which an inorganic coating is disposed, or inorganic materials. Organic materials of PIS 126 include, but are not limited to, polyimide. Inorganic materials of PIS 126 include, but are not limited to, silicon oxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (Si2N2O), magnesium fluoride (MgF2), or combinations thereof. Adjacent PIS 126 define corresponding sub-pixels and expose the anode 104 of the corresponding sub-pixel circuit 100.

[0016] The subpixel circuit 100 has a plurality of subpixel lines (e.g., a first subpixel line 106A and a second subpixel line 106B). The subpixel lines are adjacent to each other along the pixel plane. Each subpixel line includes at least two subpixels. For example, the first subpixel line 106A includes a first subpixel 108A and a second subpixel (not shown), and the second subpixel line 106B includes a third subpixel 108C and a fourth subpixel (not shown). Although Figure 1A The first subpixel line 106A and the second subpixel line 106B are depicted, but the subpixel circuit 100 of the embodiments described herein may include two or more subpixel lines, such as a third subpixel line and a fourth subpixel line. Each subpixel line has an OLED material configured to emit white, red, green, blue, or other colors of light when powered on. For example, the OLED material of the first subpixel line 106A emits red light when powered on, the OLED material of the second subpixel line 106B emits green light when powered on, the OLED material of the third subpixel line emits blue light when powered on, and the OLED material of the fourth subpixel emits light of a different color when powered on. The OLED materials within a pixel line may be configured to emit the same color of light when powered on. For example, the OLED materials of the first subpixel 108A and the second subpixel of the first subpixel line 106A emit red light when powered on, and the OLED materials of the third subpixel 108C and the fourth subpixel of the second subpixel line 106B emit green light when powered on.

[0017] Each subpixel line includes an adjacent overhang structure 110, wherein adjacent subpixel lines share the adjacent overhang structure 110. The overhang structure 110 is permanent to the subpixel line 100. The overhang structure 110 further defines each subpixel line of the subpixel circuit 100. Each overhang structure 110 includes an adjacent overhang portion 109. The adjacent overhang portion 109 is defined by an overhang extension 109A of the second structure 110B extending laterally beyond the upper surface 105 of the first structure 110A. The first structure 110A is disposed above the upper surface 103 of the PIS 126. The first endpoint 120A of the bottom surface 118 of the first structure 110A may extend to or beyond the first edge 117A of the PIS 126. The second endpoint 120B of the bottom surface of the first structure 110A may extend to or beyond the second edge 117B of the PIS 126. The first structure 110A includes an upper segment 119A and a lower segment 119B. The upper segment 119A is disposed above the lower segment 119B. The thickness ratio of the upper segment 119A to the lower segment 119B is approximately 1:1 to approximately 1:2. The first structure 110A has a total thickness of approximately 150 nm to approximately 250 nm. The upper segment 119A has a larger width adjacent to the second structure 110B and a smaller width adjacent to the lower segment 119B. The lower segment 119B has a larger width adjacent to PIS 126 and a smaller width adjacent to the upper segment 119A. The upper segment 119A has an upper sidewall 111A, and the lower segment 119B has a lower sidewall 111B. The upper sidewall 111A of the upper segment 119A and the lower sidewall 111B of the lower segment 119B may be inclined or curved.

[0018] The second structure 110B is disposed on the upper segment 119A of the first structure 110A. The second structure 110B may be disposed on the upper surface 105 of the first structure 110A. The bottom surface 107 and the upper surface 115 of the second structure 110B may be inclined or curved. The second structure has a width W1 of about 0.5 µm to about 2 µm (such as about 1 µm). The bottom surface 118 of the lower segment 119B of the first structure 110A has a width W2 of about 0.5 µm to about 2 µm (such as about 1 µm). The width W2 of the bottom surface 118 is approximately equal to the width W1 of the second structure 110B.

[0019] The width W2 of the bottom surface 118 (which is approximately equal to the width W1 of the second structure 110B and extends to or beyond the first edge 117A and the second edge 117B of PIS 126) reduces the likelihood of an abrupt step at the interface between the anode 104 and the first structure 110A, and thus reduces the likelihood of failure.

[0020] The second structure 110B can also be disposed on the intermediate structure. The intermediate structure can be disposed on the upper surface 105 of the first structure 110A. The intermediate structure can be a seed layer or an adhesive layer. The seed layer acts as a current path for the sub-pixel circuit 100. The seed layer may include titanium (Ti) material. The adhesive enhancement layer improves the adhesion between the first structure 110A and the second structure 110B. The adhesive layer may include chromium (Cr) material.

[0021] In one embodiment, which can be combined with other embodiments, the overhang structure 110 includes a second structure 110B having a conductive inorganic material and a first structure 110A having a non-conductive inorganic material. The conductive material of the second structure 110B includes copper (Cu), chromium (Cr), aluminum (Al), aluminum neodymium (AlNd), molybdenum (Mo), molybdenum-tungsten (MoW), or combinations thereof. The non-conductive material of the first structure 110A includes amorphous silicon (a-Si), silicon nitride (Si3N4), silicon oxide (SiO2), silicon oxynitride (Si2N2O), or combinations thereof. The overhang structure 110 is able to remain in place, that is, it is permanent.

[0022] In another embodiment, the second structure includes an inorganic material. The inorganic material of the second structure includes titanium (Ti), silicon nitride (Si3N4), silicon oxide (SiO2), silicon oxynitride (Si2N2O), or combinations thereof. The first structure includes a conductive material. The conductive material of the first structure 110A includes aluminum (Al), aluminum neodymium (AlNd), molybdenum (Mo), molybdenum tungsten (MoW), copper (Cu), or combinations thereof.

[0023] The lower segment 119B is deposited at a first temperature, and the upper segment 119A is deposited at a second temperature. In some embodiments, the first temperature and the second temperature are different. The first temperature can be from about 250°C to about 350°C, such as 295°C to 305°C. The second temperature can be from about 100°C to about 200°C, such as about 145°C to about 155°C. Deposition at the first temperature results in the lower segment 119B having a first lateral etch rate, while deposition at the second temperature results in the upper segment 119A having a second lateral etch rate. In one embodiment, the lower segment 119B is amorphous silicon, silicon nitride, or silicon oxide, and the upper segment 119A is amorphous silicon. The higher deposition temperature of the material of the lower segment 119B results in the lower segment 119B of the first structure 110A having a higher density than the upper segment 119A of the first structure 110A. The higher density results in a slower etch rate for the lower segment 119B, leading to reduced lateral etch. For example, the etching rate of the upper segment 119A is approximately 2 to 3 times that of the lower segment 119B. In some instances, the etching rate of the upper segment 119A is approximately 3 nm / sec, while the etching rate of the lower segment 119B is approximately 1 nm / sec. The reduction in lateral etching decreases the likelihood of the lower segment 119B being over-etched in the lateral direction, resulting in a lower probability of PIS exposure and thus a lower probability of subpixel circuit failure.

[0024] Adjacent overhangs 109 are defined by overhang extensions 109A. At least the bottom surface 107 of the second structure 110B is wider than the upper surface 105 of the first structure 110A to form the overhang extension 109A. The overhang extension 109A of the second structure 110B forms the overhang 109 and allows the second structure 110B to shield the first structure 110A. The shielding of the overhang 109 provides for the vapor deposition of the OLED material 112 and the cathode 114. The OLED material 112 may include one or more of HIL, HTL, EML, and ETL. The OLED material 112 is disposed above and in contact with the anode 104. In some embodiments, the OLED material 112 is disposed below the adjacent overhang 109 and may contact the lower sidewall 111B of the lower segment 119B. In other embodiments, the OLED material 112 is disposed below the adjacent overhang 109 and can contact the lower sidewall 111B of the lower segment 119B and the upper sidewall 111A of the upper segment 119A. For example, the OLED material 112 is different from the materials of the first structure 110A, the second structure 110B and the intermediate structure.

[0025] A cathode 114 is disposed on the OLED material 112 and extends below the adjacent overhang 109. The cathode 114 extends beyond the endpoint of the OLED material 112. For example, the cathode 114 may contact the lower sidewall 111B of the lower segment 119B. In other embodiments, the cathode 114 may contact the lower sidewall 111B of the lower segment 119B and the upper sidewall 111A of the upper segment 119A. The overhang structure 110 and the evaporation angle set by the evaporation source define the deposition angle; that is, the overhangs 109 provide a shielding effect during evaporation deposition at the evaporation angle set by the evaporation source.

[0026] The cathode 114 comprises a conductive material, such as a metal. For example, the cathode 114 includes, but is not limited to, silver, magnesium, chromium, titanium, aluminum, ITO, or combinations thereof. In one embodiment, the material of the cathode 114 differs from the materials of the first structure 110A, the second structure 110B, and the intermediate structure. In some embodiments, the OLED material 112 and the cathode 114 are disposed on the sidewall 113 of the second structure 110B of the pendant structure 110. In other embodiments, the OLED material 112 and the cathode 114 are disposed on the upper surface 115 of the second structure 110B of the pendant structure 110. In yet another embodiment, the OLED material 112 and the cathode 114 terminate on either the lower sidewall 111B or the upper sidewall 111A, i.e., not disposed on the sidewall 113 or the upper surface 115 of the second structure 110B.

[0027] Each sub-pixel includes a wrapping layer 116. The wrapping layer 116 may be or may correspond to a local passivation layer. The wrapping layer 116 of the respective sub-pixel is disposed above the cathode 114 (and OLED material 112), and the wrapping layer 116 extends below at least a portion of each of the overhangs 109, and extends along the upper sidewall 111A and lower sidewall 111B of the first structure 110A and the sidewall 113 of the second structure 110B. In some embodiments, the wrapping layer 116 extends to contact the lower sidewall 111B of the first structure 110A. In some embodiments, the wrapping layer 116 extends to contact the upper sidewall 111A and lower sidewall 111B of the first structure 110A. In some embodiments, the wrapping layer 116 extends to contact the second structure 110B at the lower surface of the overhang extension 109A. In some embodiments, the packaging layer 116 terminates at either the upper sidewall 111A or the lower sidewall 111B, that is, it is not disposed on the sidewall 113 of the second structure 110B, the upper surface 115 of the second structure 110B, or the lower surface of the overhang extension 109A of the overhang structure 110. The packaging layer 116 comprises a non-conductive inorganic material, such as a silicon-containing material. The silicon-containing material may include a material containing Si3N4.

[0028] In embodiments including one or more capping layers, the capping layers are disposed between the cathode 114 and the packaging layer 116. For example, a first capping layer and a second capping layer are disposed between the cathode 114 and the packaging layer 116. Each of the embodiments described herein may include one or more capping layers disposed between the cathode 114 and the packaging layer 116. The first capping layer may include an organic material. The second capping layer may include an inorganic material, such as lithium fluoride. The first and second capping layers may be deposited by vapor deposition. In another embodiment, the sub-pixel circuit 100 further includes at least one global passivation layer disposed over the overhang structure 110 and the packaging layer 116. In yet another embodiment, the sub-pixel includes an intermediate passivation layer disposed over the overhang structure 110 of each of the sub-pixels 106 and between the packaging layer 116 and the global passivation layer.

[0029] Figure 2 A flowchart of a method 200 for forming a sub-pixel circuit 100. Figures 3A to 3J This is a schematic cross-sectional view of the substrate 102 during the method 200 for forming the sub-pixel circuit 100.

[0030] At operation 202, such as Figure 3A As shown, a metal layer (e.g., anode 104) and multiple pixel isolation structures (PIS) 126 are disposed on a substrate 102. The anode 104 may be deposited on the substrate 102. The anode 104 may be deposited using metal-organic decomposition (MOD). The multiple PIS 126 separate the anode 104 from adjacent anodes 104. The multiple PIS 126 are disposed on the substrate 102. The thickness of the anode 104 is approximately 200 nm to approximately 300 nm, such as approximately 250 nm.

[0031] At operation 204, such as Figure 3B As shown, a lower segment layer 319B of the first structural layer 310A is deposited on the substrate 102. The lower segment layer 319B is deposited using chemical vapor deposition (CVD). The lower segment layer 319B has a thickness of about 100 nm to about 250 nm (e.g., about 150 nm to about 200 nm). The lower segment layer 319B is deposited at a first temperature of about 250 °C to about 350 °C (e.g., 300 °C). The lower segment layer 319B comprises amorphous silicon (a-Si), silicon nitride (Si3N4), silicon oxide (SiO2), silicon oxynitride (Si2N2O), or a combination thereof.

[0032] At operation 206, such as Figure 3CAs shown, an upper segment layer 319A of the first structural layer 310A is deposited on top of a lower segment layer 319B. The upper segment layer 319A is deposited using chemical vapor deposition (CVD). The upper segment layer 319A has a thickness of about 100 nm to about 250 nm (e.g., about 150 nm to about 200 nm). The upper segment layer 319A is deposited at a second temperature of about 100°C to about 200°C (e.g., 150°C). The upper segment layer 319A comprises amorphous silicon (a-Si), silicon nitride (Si3N4), silicon oxide (SiO2), silicon oxynitride (Si2N2O), or a combination thereof.

[0033] At operation 208, such as Figure 3D As shown, a second structural layer 310B is deposited on top of a first structural layer 310A. The second structural layer 310B can be deposited using sputtering. The second structural layer 310B has a thickness of approximately 400 nm to approximately 600 nm. The second structural layer 310B comprises a conductive or non-conductive material. Conductive materials include copper (Cu), aluminum (Al), neodymium aluminum (AlNd), molybdenum (Mo), molybdenum-tungsten (MoW), or combinations thereof. Non-conductive materials include amorphous silicon (a-Si), silicon nitride (Si3N4), silicon oxide (SiO2), silicon oxynitride (Si2N2O), germanium (Ge), germanium arsenide (GeAs Group III or IV), or combinations thereof.

[0034] In some embodiments, an intermediate structure may be deposited between the second structural layer 310B and the first structural layer 310A. The intermediate structure material has a thickness of about 10 nm to about 20 nm. The intermediate structure material includes chromium (Cr), titanium (Ti), or tantalum nitride (TaN).

[0035] At operation 210, such as Figure 3E As shown, a resist 330 is disposed and patterned on the second structural layer 310B. The resist 330 is either a positive or negative resist. A positive resist includes resist portions that, when exposed to electromagnetic radiation, are soluble in the resist developer coated onto the resist after the pattern is written into the resist using electromagnetic radiation. A negative resist includes resist portions that, when exposed to radiation, are insoluble in the resist developer coated onto the resist after the pattern is written into the resist using electromagnetic radiation. The chemical composition of the resist 330 determines whether the resist is a positive or negative resist. A portion of the second structural layer is patterned to form the pixel opening of the first sub-pixel 108A. The patterning is performed using one of photolithography, digital photolithography, or laser ablation.

[0036] At operation 212, such as Figure 3FAs shown, the portions of the upper segment 319A and lower segment 319B of the first structural layer 310A and the second structural layer 310B exposed by the resist 330 are removed to form the first structure 110A and the second structure 110B. Removing portions of the first structural layer 310A and the second structural layer 310B forms multiple sub-pixels (e.g., first sub-pixel 108A and third sub-pixel 108C). In some embodiments, a wet etching process can be used to remove the first structural layer 310A and the second structural layer 310B exposed by the resist 330. In some embodiments, low-power isotropic etching can be used to remove the first structural layer 310A and the second structural layer 310B exposed by the resist 330. In some embodiments, silicon fluoride (SF6), trifluoromethane (CHF3), or oxygen (O2) can be used to remove the first structural layer 310A and the second structural layer 310B exposed by the resist 330. The etching selectivity between the material of the first structural layer 310A corresponding to the first structure 110A and the material of the second structural layer 310B corresponding to the second structure 110B, and the etching process for removing the exposed portions of the second structural layer 310B and the first structural layer 310A, provides a bottom surface 107 of the second structure 110B that is wider than the upper surface 105 of the first structure 110A, to form the overhang extension 109A of the overhang 109.

[0037] Furthermore, the etch selectivity between the material of the upper layer 319A corresponding to the upper segment 119A and the material of the lower layer 319B corresponding to the lower segment 119B provides a slower etch rate for the lower segment 119B. The higher deposition temperature results in a higher density for the lower layer 319B, leading to reduced lateral etching of the lower layer 319B. The etch rate of the upper layer 319A is approximately two to three times that of the lower layer 319B. The resist 330 is then removed from the second structure 110B.

[0038] At operation 214, such as Figure 3G As shown, an OLED material layer 312, a cathode layer 314, and a packaging layer material 316 are deposited on the first sub-pixel 108A. The shielding of adjacent overhangs 109 provides vapor deposition for each of the OLED material layer 312 and the cathode layer 314. The total thickness of the OLED material layer 312 and the cathode layer 314 is from about 100 nm to 150 nm. The packaging layer material 316 is deposited on the cathode layer 314. The thickness of the packaging layer material 316 is from about 10 nm to about 50 nm. The shielding of adjacent overhangs 109 provides vapor deposition for the packaging layer material 316.

[0039] At operation 216, such as Figure 3HAs shown, resist 340 is placed in the first sub-pixel 108A. Resist 340 can be either a positive or negative resist. The chemical composition of resist 340 determines whether it is a positive or negative resist. Resist 340 is patterned to protect the first sub-pixel 108A from subsequent etching processes. Patterning can be achieved using photolithography, digital lithography, or laser ablation.

[0040] At operation 218, such as Figure 3I As shown, the portions of the OLED material layer 312, cathode layer 314, and packaging layer material 316 exposed to the resist 340 are removed to form the OLED material 112, cathode 114, and packaging layer 116 of the first sub-pixel 108A. These portions of the OLED material layer 312, cathode layer 314, and packaging layer material 316 can be removed using ashing (e.g., O2 ashing). The surface of the anode 104 can be cleaned using UV ozone (O3) cleaning.

[0041] At operation 220, such as Figure 3J As shown, remove resist 340.

[0042] In summary, a subpixel circuit and a method for forming the subpixel circuit are disclosed. The subpixel circuit includes adjacent overhangs having a first structure and a second structure. The bottom surface of the second structure extends beyond the edge of the upper surface of the first structure to form the overhang extension of the second structure. The first structure includes a lower segment and an upper segment disposed above the lower segment. The lower segment is deposited at a higher temperature than the upper segment to reduce the lateral etching amount of the lower segment of the first structure. The reduction in lateral etching reduces the likelihood of abrupt steps at the interface between the anode 104 and the first structure 110A, reduces the likelihood of exposed PIS, and thus reduces the likelihood of failure.

[0043] Although the foregoing describes an embodiment of this disclosure, other and additional embodiments of this disclosure may be designed without departing from its basic scope, the scope of which is defined by the following claims.

Claims

1. A sub-pixel circuit, the sub-pixel circuit comprising: Adjacent overhang structures, the overhang structures being defined by a second structure extending laterally beyond the overhang extension of the first structure, the first structure being mounted on a substrate; wherein the first structure comprises: The lower segment has a first lateral etching rate; The upper segment, which is deposited on top of the lower segment, has a second lateral etch rate, wherein the second lateral etch rate is different from the first lateral etch rate; anode; Organic light-emitting diode (OLED) material, the organic light-emitting diode (OLED) material disposed on the anode, wherein the OLED material extends below the adjacent overhang structure; as well as A cathode is disposed on the OLED material and extends below the adjacent overhang structure.

2. The sub-pixel as described in claim 1, wherein: The lower section is deposited at a first temperature of about 250°C to about 350°C; and The upper section was deposited at a second temperature of about 100°C to about 200°C.

3. The sub-pixel as described in claim 1, wherein: The upper surface of the second structure has a first width; and The bottom surface of the first structure has a second width, wherein the first width of the upper surface is equal to the second width of the bottom surface.

4. The sub-pixel of claim 1, wherein the material of the upper segment and the lower segment comprises amorphous silicon (a-Si), silicon nitride (Si3N4), silicon oxide (SiO2), silicon oxynitride (Si2N2O), or a combination thereof.

5. The sub-pixel of claim 1, wherein the material of the upper segment is the same as the material of the lower segment.

6. The sub-pixel of claim 1, wherein the second structure comprises copper (Cu), aluminum (Al), neodymium aluminum (AlNd), molybdenum (Mo), molybdenum tungsten (MoW), or a combination thereof.

7. The sub-pixel of claim 1, wherein the second structure comprises amorphous silicon (a-Si), silicon nitride (Si3N4), silicon oxide (SiO2), silicon oxynitride (Si2N2O), germanium (Ge), germanium arsenide (GeAs group III or IV), or a combination thereof.

8. An apparatus comprising: substrate; Multiple adjacent pixel isolation structures (PIS) are disposed on the substrate; Multiple sub-pixels, each sub-pixel containing: Adjacent overhang structures, the overhang structures being defined by a second structure extending laterally beyond the overhang extension of the first structure, the first structure being mounted on a substrate; wherein the first structure comprises: The first endpoint of the bottom surface of the first structure may extend to or beyond the first edge of the PIS; and The second endpoint of the bottom surface of the first structure may extend to or beyond the second edge of the PIS; The lower segment has a first lateral etching rate; The upper segment, which is deposited on top of the lower segment, has a second lateral etch rate, wherein the second lateral etch rate is different from the first lateral etch rate; anode; Organic light-emitting diode (OLED) material, the organic light-emitting diode (OLED) material disposed on the anode, wherein the OLED material extends below the adjacent overhang structure; as well as A cathode is disposed on the OLED material and extends below the adjacent overhang structure.

9. The apparatus of claim 8, wherein: The lower section was deposited at a first temperature of approximately 250°C to approximately 350°C; and The upper section was deposited at a second temperature of about 100°C to about 200°C.

10. The apparatus of claim 8, wherein the second structure comprises copper (Cu), aluminum (Al), neodymium aluminum (AlNd), molybdenum (Mo), molybdenum tungsten (MoW), or a combination thereof.

11. The apparatus of claim 8, wherein the second structure comprises amorphous silicon (a-Si), silicon nitride (Si3N4), silicon oxide (SiO2), silicon oxynitride (Si2N2O), germanium (Ge), germanium arsenide (GeAs group III or IV), or a combination thereof.

12. The apparatus of claim 8, wherein: The upper surface of the second structure has a first width; and The bottom surface of the first structure has a second width, wherein the first width of the upper surface is equal to the second width of the bottom surface.

13. The apparatus of claim 12, wherein the first width and the second width are about 0.5 µm to about 2 µm.

14. The apparatus of claim 8, wherein the materials of the upper and lower sections comprise amorphous silicon (a-Si), silicon nitride (Si3N4), silicon oxide (SiO2), silicon oxynitride (Si2N2O), or combinations thereof.

15. The apparatus of claim 8, wherein the material of the upper section is the same as the material of the lower section.

16. A method for forming a sub-pixel circuit, the method comprising: A lower segment layer having a first lateral etching rate is disposed on a substrate, wherein an anode is deposited on the substrate; An upper segment layer having a second lateral etching rate is disposed on the lower segment layer, wherein the first lateral etching rate is different from the second lateral etching rate, and wherein the lower segment layer and the upper segment layer form a first structural layer. The second structural layer is deposited on top of the first structural layer; as well as The resist-exposed portions of the first and second structural layers are removed to form adjacent overhang structures, the overhang structures being defined by overhang extensions of a second structure formed by the second structural layer, the overhang extensions laterally extending beyond the first structure formed by the first structural layer, the first structure being disposed on the substrate, wherein the first structure comprises: The upper segment is formed by the aforementioned upper layer; as well as The lower segment formed by the lower segment layer.

17. The method of claim 16, wherein: The lower section was deposited at a first temperature of approximately 250°C to approximately 350°C; and The upper section was deposited at a second temperature of about 100°C to about 200°C.

18. The method of claim 16, wherein: The upper surface of the second structure has a first width; and The bottom surface of the first structure has a second width, wherein the first width of the upper surface is equal to the second width of the bottom surface.

19. The method of claim 16, further comprising: Depositing organic light-emitting diode (OLED) material layers, cathode layers, and packaging layer materials; and Remove portions of the OLED material, the cathode layer, and the packaging layer material to form the OLED material, cathode, and packaging layer.

20. The method of claim 16, wherein the materials of the upper segment and the lower segment comprise amorphous silicon (a-Si), silicon nitride (Si3N4), silicon oxide (SiO2), silicon oxynitride (Si2N2O), or combinations thereof, and wherein the material of the upper segment is the same as the material of the lower segment.

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