Packaging substrates with embedded capacitor packages having redistribution layers (RDL) for aligning capacitor terminal connections to a semiconductor die in an integrated circuit (IC) package, and related methods of manufacture

Abstract

An integrated circuit (IC) package substrate with an embedded capacitor package having a redistribution layer (RDL) for aligning capacitor terminals to die interconnects of a semiconductor die (“die”), and related IC packages and manufacturing methods. The capacitor package can be embedded in the package substrate of the IC package, for example, to provide decoupling capacitance or filtering for the die of the IC package. The RDL is constructed on the capacitor substrate of the capacitor package such that the RDL interconnects of the RDL are coupled to the capacitor terminals of the capacitor. The RDL redistributes the connections to the capacitor terminals of the capacitor to a desired pattern and / or spacing to align the capacitor terminals with the die interconnects of the die coupled to the package substrate of the IC package. This minimizes the signal path length between the capacitor and the die to minimize inductance in the capacitor loop.

Description

[0001] Priority application

[0002] This application claims priority to U.S. Patent Application Serial No. 18 / 418,505, filed January 22, 2024, entitled “PACKAGE SUBSTRATE WITHEMBEDDED CAPACITOR PACKAGE HAVING REDISTRIBUTION LAYER(S) (RDL(s)) FORALIGNING CAPACITOR TERMINALS CONNECTIONS TO SEMICONDUCTOR DIE IN ANINTEGRATED CIRCUIT (IC) PACKAGE, AND RELATED FABRICATION METHODS”, the entire contents of which are incorporated herein by reference. background

[0003] I. Technical Field

[0004] This disclosure relates to integrated circuit (IC) packages including substrates having embedded capacitors (e.g., silicon capacitors), and more specifically to bumps in embedded capacitors of metal interconnects coupled to the substrate to provide signal routing paths to a semiconductor die (“die”) coupled to the substrate.

[0005] II. Background Technology

[0006] Integrated circuits (ICs) are the cornerstone of electronic devices. ICs are packaged in IC packages, also known as “semiconductor packages” or “chip packages.” An IC package includes one or more semiconductor dies that serve as the IC, mounted on and electrically coupled to a substrate such as a wiring substrate (e.g., a package substrate) to provide physical support and electrical interfaces for the dies. The dies are electrically connected to exposed metal interconnects (e.g., metal traces) in an upper layer of the substrate as part of a signal routing path. The substrate also includes one or more metallization layers comprising metal interconnects (e.g., metal traces, metal lines), wherein vertical interconnect channels (vias) couple the metal interconnects between adjacent metallization layers together to provide electrical interfaces between dies. If the substrate is a package substrate, the substrate also includes a lower outer metallization layer comprising metal interconnects coupled to external metal interconnects (e.g., ball grid array (BGA) interconnects) to provide external interfaces between dies in the IC package. External metal interconnects can also be coupled (e.g., soldered) to traces in a printed circuit board (PCB) to attach the package to the PCB and make its die interface with the circuitry of the PCB.

[0007] Passive electrical devices (such as capacitors) can be embedded in the embedded package substrate (EPS) of an IC package and electrically coupled to a die coupled to the package substrate to provide the desired circuitry functionality to the coupled die. For example, the electrical device can be embedded in the core layer of a cored package substrate. Embedding the electrical device in the package substrate allows for positioning the electrical device closer to the coupled die to minimize the signal path length between the electrical device and the die. Embedded capacitors are electrically coupled to the die interconnects of the die in the IC package via interconnect metal traces coupled to one or more metallization layers in the package substrate, which in turn couple to conductive bumps (e.g., solder bumps) coupled to the die interconnects of the die. For example, passive electrical devices (such as capacitors in the form of silicon capacitors (e.g., deep trench capacitors (DTCs))) can be embedded in the package substrate and coupled to the die to provide decoupling capacitance as part of the power distribution network (PDN) in the IC package. Capacitors can also be used to provide bypass capacitance to provide a low-impedance shunt path for high-frequency noise signals. In either case, it is desirable to minimize the signal path length between the capacitor and the die to minimize the inductance in the connection path so as not to reduce the capacitor’s ability to store energy that will be discharged during transient power events for use in decoupling capacitors or in response to high-frequency signals. Summary of the Invention

[0008] The aspects disclosed herein include a package substrate with an embedded capacitor package in an integrated circuit (IC) package, the embedded capacitor package having a redistribution layer (RDL) for aligning the capacitor terminal connections of the capacitor to a semiconductor die (“die”). Related integrated circuit (IC) packages and manufacturing methods are also disclosed. The capacitor package may be embedded in the package substrate of the IC package to provide decoupling capacitance or filtering to the die, wherein the package substrate acts as a wiring substrate providing a signal routing path between the capacitor in the capacitor package and the die. In this regard, in an exemplary aspect, the embedded capacitor package includes an RDL formed on the substrate of the capacitor such that RDL interconnects (e.g., metal traces) of the RDL are coupled to the capacitor terminals of the capacitor. The RDL is a metal layer that may be added and patterned during substrate manufacturing to allow the formation of finer-pitched metal interconnects that match the pitch of the coupled components. In this regard, the RDL redistributes the connections to the capacitor terminals of the capacitor to a desired pattern and / or pitch. In this way, the capacitor package can be embedded in the package substrate of the IC package, such that the RDL interconnects of the RDL align the connections to the capacitor terminals of the capacitor with the die interconnects of the die coupled to the package substrate of the IC package to minimize the signal path length between the capacitor and the die. Minimizing the connection path between the capacitor and the die minimizes the inductance in the capacitor loop. Minimizing the inductance in the capacitor loop may be important so as not to reduce the effective capacitance of the capacitor for its intended application (e.g., decoupling capacitor, bypass capacitor). Furthermore, minimizing the reduction in capacitance in the capacitor loop avoids the need to provide additional capacitors in the IC package to obtain the required or desired capacitance.

[0009] As an example, a capacitor package embedded in a packaging substrate may include a silicon capacitor package comprising a silicon capacitor formed in a silicon substrate, wherein one or more RDLs are formed on the substrate. For example, the silicon capacitor may be a deep trench capacitor (DTC), comprising a vertical capacitor formed by etched deep trenches in the silicon substrate. The trenches of the silicon capacitor include adjacent electrodes separated by dielectric layers to form the capacitor. The capacitor includes metal layers, each metal layer connected to the electrodes of the capacitor and having exposed metal pads that can be raised by external bumps (e.g., by solder bumps) to provide external terminals for the capacitor. RDLs may be formed on the silicon substrate of the capacitor, wherein RDL interconnects of the RDLs are coupled to the external bumps of the capacitor package. Additional RDLs may be formed on the substrate of the capacitor as part of the silicon capacitor package to redistribute the connections to the external bumps of the capacitor to a desired pattern and / or spacing. In this way, the silicon capacitor package can be embedded in the package substrate of the IC package, such that the RDL interconnect with the built-in RDL aligns the connection of the external bumps of the capacitor package with the die interconnect of the die coupled to the package substrate of the IC package to minimize the signal path length between the capacitor and the die.

[0010] In this regard, in one exemplary aspect, a packaging substrate is provided. The packaging substrate includes a first metallization layer comprising a plurality of first metal interconnects having a first spacing in a first direction. The packaging substrate also includes a capacitor package comprising a capacitor. The capacitor includes: a capacitor substrate including a first surface; and a plurality of capacitor terminals having a second spacing different from the first spacing in the first direction. The capacitor package also includes an RDL substrate adjacent to the capacitor substrate. The RDL substrate includes a first RDL comprising a plurality of first RDL interconnects each coupled to a capacitor terminal in the plurality of capacitor terminals and each coupled to a first metal interconnect in the plurality of first metal interconnects.

[0011] In another exemplary aspect, a method of manufacturing a package substrate is provided. The method includes providing a first metallization layer including a plurality of first metal interconnects having a first spacing in a first direction. The method also includes providing a capacitor package, including providing a capacitor, comprising: forming a capacitor substrate including a first surface; and forming a plurality of capacitor terminals having a second spacing different from the first spacing in the first direction. Providing the capacitor package further includes forming an RDL substrate adjacent to the capacitor substrate, comprising: forming a first RDL including a plurality of first RDL interconnects adjacent to the capacitor substrate; and coupling each of the plurality of first RDL interconnects to a capacitor terminal among the plurality of capacitor terminals and a first metal interconnect among the plurality of first metal interconnects.

[0012] In another exemplary aspect, an IC package is provided. The IC package includes a package substrate comprising: a first metallization layer including a plurality of first metal interconnects having a first spacing in a first direction; and a capacitor package. The capacitor package includes a capacitor comprising: a capacitor substrate including a first surface; and a plurality of capacitor terminals having a second spacing different from the first spacing in the first direction. The capacitor package further includes an RDL substrate adjacent to the capacitor substrate. The RDL substrate includes a first RDL including a plurality of first RDL interconnects each coupled to a capacitor terminal in the plurality of capacitor terminals and each coupled to a first metal interconnect in the plurality of first metal interconnects. The IC package further includes a die including a plurality of die interconnects having the first spacing in the first direction and each coupled to a first metal interconnect in the plurality of first metal interconnects. Attached Figure Description

[0013] Figure 1A This is a side view of an exemplary integrated circuit (IC) package, which includes a package substrate having a capacitor in the form of a silicon capacitor embedded in a die layer, wherein the silicon capacitor is coupled to a die coupled to the package substrate via a connection wound in the package substrate. Figures 1B to 1D yes Figure 1A A top view of the corresponding patterns of the capacitor terminals of the silicon capacitor in the IC package, the metal interconnects of the package substrate coupled to the capacitor terminals, and the die interconnects of the die. Figure 2A and Figure 2BThe images shown are a side view and a close-up side view of an exemplary IC package, which includes a die-packed substrate with a capacitor package embedded in a die layer. The capacitor package includes an RDL formed on the substrate of the capacitor, the RDL having RDL interconnects coupled to the capacitor terminals of the capacitor to redistribute the connection to the capacitor terminals to align with the die interconnects of the die coupled to the package substrate of the IC package in order to minimize the signal path length between the capacitor and the die. Figures 2C to 2E It can be provided for use Figure 2A and Figure 2B A top view of the corresponding exemplary interconnect patterns of the capacitor terminals of the capacitor, the RDL interconnects of the RDL of the capacitor package, and the die interconnects of the die in the IC package. Figures 2F to 2H It can be provided for use Figure 2A and Figure 2B A top view of the capacitor terminals of the capacitor, the RDL interconnects of the RDL of the capacitor package, and the die interconnects of the die in the IC package; Figure 3 This is a side view of another exemplary IC package including a die-package substrate, wherein a capacitor package is embedded in the metallization layer of the die-package substrate, wherein the capacitor package includes an RDL formed on the substrate of the capacitor, the RDL having RDL interconnects coupled to the capacitor terminals of the capacitor to redistribute the connection to the capacitor terminals to align with the die interconnects of the die coupled to the package substrate of the IC package in order to minimize the signal path length between the capacitor and the die; Figure 4 This is a side view of another exemplary IC package including a dieless package substrate with an embedded capacitor package, wherein the capacitor package includes an RDL formed on the substrate of the capacitor, the RDL having RDL interconnects coupled to the capacitor terminals of the capacitor to redistribute the connection to the capacitor terminals to align with the die interconnects of the die coupled to the package substrate of the IC package in order to minimize the signal path length between the capacitor and the die. Figure 5 This is a flowchart illustrating an exemplary process for manufacturing a package substrate including an embedded capacitor package, the embedded capacitor package including an RDL formed on the substrate of the capacitor, wherein RDL interconnects of the RDL are coupled to capacitor terminals of the capacitor to redistribute the connections to the capacitor terminals to align with die interconnects of a die coupled to the package substrate in the IC package, in order to minimize the signal path length between the capacitor and the die, including but not limited to... Figures 2A to 4 Capacitors and IC packages in the middle; Figure 6A and Figure 6B This is a flowchart illustrating the manufacturing process of a capacitor package. Each capacitor package includes an RDL formed on a capacitor substrate, wherein RDL interconnects are coupled to capacitor terminals to redistribute connections to the capacitor terminals, allowing the capacitor package to be disposed within an IC package. The connections of the capacitor terminals are aligned with die interconnects of a die coupled to the package substrate of the IC package to minimize the signal path length between the capacitor and the die, including but not limited to... Figures 2A to 4 The capacitor in; Figures 7A to 7H It is based on 6A and Figure 6B An exemplary manufacturing stage during the manufacture of a capacitor, as shown in the exemplary manufacturing process. Figures 8A to 8E This is a flowchart illustrating a manufacturing process for a package substrate including an embedded capacitor package. The embedded capacitor package includes an RDL formed on the capacitor substrate, wherein RDL interconnects are coupled to capacitor terminals to redistribute connections to the capacitor terminals for alignment with die interconnects of a die coupled to the package substrate within the IC package, minimizing the signal path length between the capacitor and the die, including but not limited to... Figures 2A to 4 Capacitors and IC packages in the middle; Figures 9A to 9I It is based on 8A to Figure 8E An exemplary manufacturing stage during the manufacturing of the packaging substrate in an exemplary manufacturing process; Figure 10 This is a block diagram of an exemplary wireless communication device including one or more IC packages, the one or more IC packages including a package substrate having embedded capacitor packages, including but not limited to... Figures 2A to 4 , Figure 7H and Figure 9I The capacitor package includes an RDL formed on a capacitor substrate, wherein RDL interconnects of the RDL are coupled to capacitor terminals of the capacitor to redistribute the connections to the capacitor terminals for alignment with die interconnects of a die coupled to the package substrate in the IC package, thereby minimizing the signal path length between the capacitor and the die, including but not limited to... Figures 2A to 4 and Figure 9I The IC package in question, and the IC package may be manufactured according to a manufacturing process, including but not limited to... Figure 5 , Figures 6A to 6B and Figures 8A to 8E The exemplary manufacturing process in; and Figure 11This is a block diagram of an exemplary electronic device in the form of a processor-based system, the electronic device including one or more IC packages, the one or more IC packages including a package substrate having embedded capacitor packages, including but not limited to Figures 2A to 4 , Figure 7H and Figure 9I The capacitor package includes an RDL formed on a capacitor substrate, wherein RDL interconnects of the RDL are coupled to capacitor terminals of the capacitor to redistribute the connections to the capacitor terminals for alignment with die interconnects of a die coupled to the package substrate in the IC package, thereby minimizing the signal path length between the capacitor and the die, including but not limited to... Figures 2A to 4 and Figure 9I The IC package in question, and the IC package may be manufactured according to a manufacturing process, including but not limited to... Figure 5 , Figures 6A to 6B and Figures 8A to 8E An exemplary manufacturing process is shown in the figure. Detailed Implementation

[0014] Several exemplary aspects of this disclosure will now be described with reference to the accompanying drawings. The word “exemplary” is used herein to mean “serving as an example, instance, or illustration.” Any aspect described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other aspects.

[0015] The aspects disclosed herein include a package substrate with an embedded capacitor package in an integrated circuit (IC) package, the embedded capacitor package having a redistribution layer (RDL) for aligning the capacitor terminal connections of the capacitor to a semiconductor die (“die”). Related integrated circuit (IC) packages and manufacturing methods are also disclosed. The capacitor package may be embedded in the package substrate of the IC package to provide decoupling capacitance or filtering to the die, wherein the package substrate acts as a wiring substrate providing a signal routing path between the capacitor in the capacitor package and the die. In this regard, in an exemplary aspect, the embedded capacitor package includes an RDL formed on the substrate of the capacitor such that RDL interconnects (e.g., metal traces) of the RDL are coupled to the capacitor terminals of the capacitor. The RDL is a metal layer that may be added and patterned during substrate manufacturing to allow the formation of finer-pitched metal interconnects that match the pitch of the coupled components. In this regard, the RDL redistributes the connections to the capacitor terminals of the capacitor to a desired pattern and / or pitch. In this way, the capacitor package can be embedded in the package substrate of the IC package, such that the RDL interconnects of the RDL align the connections to the capacitor terminals of the capacitor with the die interconnects of the die coupled to the package substrate of the IC package to minimize the signal path length between the capacitor and the die. Minimizing the connection path between the capacitor and the die minimizes the inductance in the capacitor loop. Minimizing the inductance in the capacitor loop may be important so as not to reduce the effective capacitance of the capacitor for its intended application (e.g., decoupling capacitor, bypass capacitor). Furthermore, minimizing the reduction in capacitance in the capacitor loop avoids the need to provide additional capacitors in the IC package to obtain the required or desired capacitance.

[0016] Before discussing examples of package substrates that can be disposed in IC packages, wherein the package substrate includes an embedded capacitor package, the embedded capacitor package including an RDL formed on the substrate of the capacitor to align connections to capacitor terminals of the capacitor with die interconnects coupled to the die of the package substrate in the IC package (from... Figure 2A (Starting), first about Figures 1A to 1D The description does not include an exemplary IC package 100 with such capacitor packages.

[0017] In this respect, Figure 1AThis is a side view of an exemplary IC package 100, which includes a package substrate 102 having an embedded silicon capacitor 104. For example, the silicon capacitor 104 may be a deep trench capacitor (DTC). In this example, the silicon capacitor 104 is embedded in a core layer 106 of the package substrate 102, which serves as a core-package substrate. The silicon capacitor 104 may be included in the IC package 100 to provide decoupling or filtering capacitance for circuitry in a die 108 within the package substrate 102. In this regard, the silicon capacitor 104 includes capacitor terminals 110 in the form of interconnect bumps 112, which are exposed from a first surface 114 of a capacitor substrate 116 in which the capacitor of the silicon capacitor 104 is formed. To electrically couple the silicon capacitor 104 to the die 108, the capacitor terminals 110 are coupled to first metal interconnects 118(1) in a first metallization layer 120(1) of the package substrate 102. Capacitor terminals 110 are coupled to second metal interconnects 118(2) in a second metallization layer 120(2) in the package substrate 102, wherein the second metallization layer 120(2) is disposed on and / or adjacent to a first surface 114 of the capacitor substrate 116. Connections are made and wired from the second metal interconnects 118(2) in the second metallization layer 120(2) to the first metal interconnects 118(1) in the first metallization layer 120(1) of the package substrate 102. Die interconnects 122 of die 108 exposed from the bottom surface 124 of die 108 are coupled to the first metal interconnects 118(1) exposed from the first outer surface 126 of the first metallization layer 120(1) to provide electrical coupling between die 108 and silicon capacitor 104.

[0018] However, as Figure 1A As shown, the wiring connections between the second metal interconnect 118(2) and the first metal interconnect 118(1) in the package substrate 102, from the capacitor terminal 110 of the silicon capacitor 104 to the die interconnect 122, are “wrapped” signal routing paths. This means that these connections must be wired not only vertically in the second vertical direction (Z-axis direction) but also horizontally in the first horizontal direction (X-axis and / or Y-axis direction) to wire the connections to couple the capacitor terminal 110 of the silicon capacitor 104 to the die interconnect 122 of the die 108. This also… Figures 1B to 1D As shown in the figures, these illustrations depict capacitor terminals 110 exposed from the first surface 114 of the capacitor substrate 116. Figure 1B ), and the second metal interconnect 118(2) coupled to the second metallization layer 120(2) of the capacitor terminal 110 ( Figure 1C ), and die interconnect 122 of die 108 ( Figure 1D A top view of ( ). For example Figure 1B and Figure 1CAs shown, the alignment of the capacitor terminal 110 and the second metal interconnect 118(2) is aligned in two first horizontal directions (X-axis and Y-axis directions) and has the same spacing P1, P2 in the respective first horizontal directions (X-axis and Y-axis directions). However, as Figure 1D As shown, the die interconnects 122 of die 108 are not aligned with the capacitor terminals 110 of silicon capacitor 104 in the two first horizontal directions (X-axis and Y-axis directions). For example, some die interconnects 122 have smaller spacings P3 and P4 in the two first horizontal directions (X-axis and Y-axis directions) compared to the spacing P1 and P2 of the closest aligned capacitor terminals 110 in the second vertical direction (Z-axis direction).

[0019] The entangled signal routing path between silicon capacitor 104 and die 108 increases the signal path length between them. This increases the inductance in the signal routing path between silicon capacitor 104 and die 108. It is generally desirable to minimize the signal path length between silicon capacitor 104 and die 108 to minimize the inductance in the connection path so as not to degrade the energy stored by silicon capacitor 104, which will be discharged during transient power events for decoupling or in response to high-frequency signals.

[0020] To reduce the number of signal routing paths caused by the entanglement between capacitors and dies in IC packages, a method is provided. Figure 2A and Figure 2B The IC package 200 is described in more detail below. Figure 2A This is a side view of an IC package 200 including a capacitor package 228, which includes an RDL substrate 230 formed on or adjacent to a first surface 214 of a capacitor substrate 216 (in this example, a silicon capacitor 204) of a capacitor 232. For example, the capacitor substrate 216 may be a silicon substrate in which capacitive elements are formed. As an example, the silicon capacitor 204 may be a deep trench capacitor (DTC). The RDL substrate 230 is a substrate comprising one or more RDLs. Figure 2A As shown in and Figure 2BAs shown in more detail, the RDL substrate 230 includes one or more RDLs 234, which in this example are two (2) RDLs 234(1), 234(2), to redistribute the connections from the capacitor terminals 210 of the silicon capacitor 204 to the die interconnects 222 of the die 208 exposed from the bottom surface 224 of the die 208. The RDLs 234(1), 234(2) redistribute the connections from the capacitor terminals 210 of the silicon capacitor 204 to the die interconnects 222 of the die 208 to align the connections to the capacitor terminals 210 and the die interconnects 222 to minimize the signal path length between the die 208 and the silicon capacitor 204, thereby minimizing the resistance and / or inductance in the capacitive loop provided by the silicon capacitor 204. For example, if the silicon capacitor 204 is coupled to the power and ground connections of the die 208, the silicon capacitor 204 provides decoupling capacitance for the power distribution network (PDN) of the IC package 200 and the die 208. If silicon capacitor 204 is coupled to a filter circuit in die 208, then silicon capacitor 204 provides capacitance for such filter circuitry. In either case, minimizing the signal path length between die 208 and silicon capacitor 204 is desirable.

[0021] like Figure 2B As further shown, in this example, the capacitor package 228 is fully embedded in the package substrate 202. This is not necessary. For example, the capacitor package 228 may be only partially embedded in the package substrate 202 in a first horizontal direction (X-axis and Y-axis directions) and / or a second vertical direction (Z-axis direction). As an example, the package substrate 202 may be a modified semi-additive process (mSAP) substrate formed by forming a metallization layer in an additive process. The package substrate 202 may also be an embedded trace substrate (ETS). As another example, the package substrate 202 may be an intermediary substrate that provides signal routing paths between multiple package layers, such as in a three-dimensional IC (3DIC) package.

[0022] In this example, capacitor package 228 is embedded in core layer 206 of package substrate 202. Core layer 206 is adjacent to second metallization layer 220(2) in the second vertical direction (Z-axis direction), which is adjacent to RDL substrate 230 in the second vertical direction (Z-axis direction). Second metallization layer 220(2) includes second metal interconnect 218(2) coupled to first RDL interconnect 236(1) (e.g., metal trace) in first RDL 234(1) which is part of RDL substrate 230. RDL 234 including first RDL 234(1) is a metal layer that can be added and patterned during the fabrication of substrate (such as capacitor substrate 216) to allow the formation of finer pitch metal interconnects / traces that can match the spacing of coupled components. A second metal interconnect 218(2) in the second metallization layer 220(2) is coupled to a first metal interconnect 218(1) in the first metallization layer 220(1), which is exposed from a first outer surface 226 of the package substrate 202. A die interconnect 222 is coupled to the first metal interconnect 218(1). In this way, the die interconnect 222 is coupled to the first RDL interconnect 236(1) of the first RDL 234(1) of the RDL substrate 230 (e.g., a metal trace) through the connection between the first metal interconnect 218(1) and the second metal interconnect 218(2). As discussed in more detail below, the first RDL interconnect 236(1) of the first RDL 234(1) may be formed and patterned to align with the die interconnect 222 of the die 208 to provide an alignment connection between the die 208 and the RDL substrate 230.

[0023] Continue to refer to Figure 2BIn this example, the RDL substrate 230 also includes a second RDL 234(2), which includes a second RDL interconnect 236(2). Similar to the first RDL 234(1), the second RDL 234(2) is a metal layer that can be added and patterned during the fabrication of a substrate (such as capacitor substrate 216) to allow the formation of finer-pitched metal interconnects / traces that match the spacing of the coupled components. The second RDL interconnect 236(2) is coupled to a corresponding capacitor terminal 210 of a silicon capacitor 204 exposed from a first surface 214 of the capacitor substrate 216. In this example, the capacitor terminal 210 is a first interconnect bump 238 formed on the first surface 214 of the capacitor substrate 216 and coupled to an electrode inside the silicon capacitor 204. For example, the first interconnect bump 238 may be a solder bump that forms a solder joint between the capacitor terminal 210 and the second RDL interconnect 236(2). As another example, the first interconnect bump 238 can also be a ball grid array (BGA) interconnect. The coupling of capacitor terminal 210 to the second RDL interconnect 236(2) of the second RDL 234(2) provides electrical coupling between capacitor terminal 210 and die interconnect 222 via coupling of the second RDL interconnect 236(2) to the first RDL interconnect 236(1) coupled to die interconnect 222. In this way, silicon capacitor 204 is coupled to die 208 to provide capacitance in the circuitry to die 208, such as decoupling capacitors or capacitors used for filtering circuits.

[0024] In this example, the RDL substrate 230 includes a second interconnect bump 240 formed on the first RDL interconnect 236(1) and coupled to a second metal interconnect 218(2) to couple the first RDL interconnect 236(1) to the second metal interconnect 218(2). For example, the second interconnect bump 240 may be a solder bump that forms a solder joint between the first RDL interconnect 236(1) and the second metal interconnect 218(2). As another example, the second interconnect bump 240 may also be a ball grid array (BGA) interconnect. The second interconnect bump 240 may be disposed in an opening 244 formed in a solder mask layer 246 adjacent to the first RDL 234(1) along a second vertical direction (Z-axis direction). In the same example, the first metallization layer 220(1) includes a third interconnect bump 242 formed on the die interconnect 222 or the first metal interconnect 218(1) to couple the die interconnect 222 to the first metal interconnect 218(1). For example, the third interconnect bump 242 may be a solder bump that forms a solder joint between the die interconnect 222 and the first metal interconnect 218(1). As another example, the third interconnect bump 242 may also be a ball grid array (BGA) interconnect.

[0025] As discussed in more detail below, by providing the RDL substrate 230, the connection between the capacitor terminal 210 of the silicon capacitor 204 and the die interconnect 222 of the die 208 can be aligned. In this regard, a second RDL interconnect 236(2) can be formed in the second RDL 234(2) of the RDL substrate 230 to align with the capacitor terminal 210 and the second metal interconnect 218(2) of the second metallization layer 220(2). In this example, the second RDL interconnect 236(2) in the second RDL 234(2) of the RDL substrate 230 has a second longitudinal axis LA2 intersecting the corresponding capacitor terminal 210 along a second vertical direction (Z-axis direction). A first RDL interconnect 236(1) can be formed in the first RDL 234(1) of the RDL substrate 230 to align with the first metal interconnect 218(1) and the die interconnect 222 in the first metallization layer 220(1). In this example, the first RDL interconnect 236(1) in the first RDL 234(1) of the RDL substrate 230 has a first longitudinal axis LA1 along the second vertical direction (Z-axis direction) that intersects with the corresponding first metal interconnect 218(1) and die interconnect 222. In this way, the RDL substrate 230 facilitates the redistribution of the connection from the capacitor terminal 210 of the silicon capacitor 204 to the die interconnect 222 of the die 208 in the first horizontal direction (X-axis and / or Y-axis direction) to reduce the signal path length between the silicon capacitor 204 and the die 208.

[0026] For example Figure 2A and Figure 2B An example of how the RDL substrate 230 aligns with the connection between the die interconnect 222 in the IC package 200 and the capacitor terminal 210 of the capacitor 232 is provided. Figures 2C to 2E . Figures 2C to 2E yes Figure 2A and 2B An exemplary capacitor terminal 210 of capacitor 232 in IC package 200 ( Figure 2C ), the first RDL 234(1) of the RDL substrate 230 of the capacitor package 228, and the first RDL interconnect 236(1) Figure 2D ), and die interconnect 222 of die 208 ( Figure 2E The corresponding top view of ( ). For example Figure 2C As shown, the capacitor terminals 210 of the silicon capacitor 204 have a first alignment and a minimum second spacing P5, P6 in the corresponding first horizontal directions (X-axis and Y-axis directions). However, as Figure 2EAs shown, the die interconnects 222 of die 208 are not aligned with the capacitor terminals 210 of silicon capacitor 204 in the two first horizontal directions (X-axis and Y-axis directions). Therefore, if the die interconnects 222 are directly coupled to the interconnects aligned with the capacitor terminals 210, the die interconnects 222 will not be aligned with the capacitor terminals 210, thus requiring winding signal routing in the package substrate 202. For example, when the die interconnects 222 have a smaller pitch than the capacitor terminals 210, some die interconnects 222 have smaller first pitches P7 and P8 in the two first horizontal directions (X-axis and Y-axis directions) compared to the minimum second pitch P5 and P6 of the closest aligned capacitor terminals 210 in the second vertical direction (Z-axis direction).

[0027] However, in this example, such as Figure 2D As shown, the first RDL 234(1) of the RDL substrate 230 has a first RDL interconnect 236(1) aligned with the die interconnect 222 in the first horizontal directions (X-axis and Y-axis directions). The first RDL interconnect 236(1) has the same spacing P7, P8 as the die interconnect 222 in both first horizontal directions (X-axis and Y-axis directions). This provides an alignment connection between the RDL substrate 230 and the die interconnect 222 through the first metallization layer 220(1). The first metallization layer 220(1) can be like Figure 2D The first RDL interconnect 236(1) is patterned as in the first RDL interconnect. However, the second RDL 234(2) in the RDL substrate 230 may have a second RDL interconnect 236(2), which is like... Figure 2C The capacitor terminals 210 are patterned as shown to align with the capacitor terminals 210. In this respect, the RDL substrate 230 redistributes the connection between the capacitor terminals 210 and the first metal interconnect 218(1) to provide greater alignment between the connections of the capacitor terminals 210 and the die interconnect 222, thereby reducing the signal routing path between the die 208 and the silicon capacitor 204. For example, the first pitch P7, P8 may be 130 micrometers (μm) and smaller than the second pitch P5, P6, which may be 150 micrometers (μm).

[0028] However, the RDL substrate 230 can also be designed to align the capacitor terminals 210 of capacitors 232 with a smaller pitch than that of die interconnects 222. This is in Figures 2F to 2H The example is shown below. Figure 2F As shown, the capacitor terminals 210 of the silicon capacitor 204 may have a first alignment and a second spacing P7, P8 in corresponding first horizontal directions (X-axis and Y-axis directions). However, as Figure 2HAs shown, the die interconnects 222 of die 208 are not aligned with the capacitor terminals 210 of silicon capacitor 204 in the two first horizontal directions (X-axis and Y-axis directions) and have a larger first minimum spacing P5, P6. For example, when the die interconnects 222 have a larger spacing than the capacitor terminals 210, some die interconnects 222 have a larger minimum first spacing P5, P6 in the two first horizontal directions (X-axis and Y-axis directions) compared to the second spacing P7, P8 that is closest to the aligned capacitor terminals 210 in the second vertical direction (Z-axis direction).

[0029] In this example, such as Figure 2G As shown, the second RDL 234(2) of the RDL substrate 230 has a second RDL interconnect 236(2) aligned with the capacitor terminal 210 in the first horizontal directions (X-axis and Y-axis directions). The second RDL interconnect 236(2) has the same spacing P7, P8 as the capacitor terminal 210 in both first horizontal directions (X-axis and Y-axis directions). This provides an alignment connection between the RDL substrate 230 and the capacitor terminal 210 through the second metallization layer 220(2). However, the first RDL 234(1) in the RDL substrate 230 may have a first RDL interconnect 236(1), which is like... Figure 2H The die interconnect 222 shown is patterned to align with the die interconnect 222. In this respect, the RDL substrate 230 redistributes the connection between the capacitor terminal 210 and the first metal interconnect 218(1) to provide greater alignment between the connection of the capacitor terminal 210 and the die interconnect 222, thereby reducing the signal routing path between the die 208 and the silicon capacitor 204.

[0030] It should be noted that, Figure 2A and Figure 2B In the IC package 200, the RDL substrate 230 may be formed to include only one RDL 234 (1), which has an RDL interconnect 236 (1) coupled to a second metal interconnect 218 (2) of a capacitor terminal 210 and a second metallization layer 220 (2). Similarly, in Figure 2A and Figure 2B In the IC package 200, the package substrate 202 may include only one metallization layer 220 (1), which couples the RDL substrate 230 to the die interconnect 222 of the die 208 to couple the capacitor terminal 210 to the die interconnect 222 of the die 208.

[0031] Figure 3 This is a side view of another exemplary IC package 300, which also includes a package 228 having a core layer 306 and an embedded capacitor (such as...). Figure 2A and Figure 2B The core-packaged substrate 302 in the IC package 200. However, in Figure 3 In the IC package 300, the capacitor package 228 is embedded in the metallization layer 320 of the package substrate 302 instead of the core layer 306. Figure 3 IC package 300 and Figure 2A and Figure 2B Common components among the IC packages 200 are shown with the same component number.

[0032] Figure 4 This is a side view of another exemplary IC package 400, which includes a package 228 with an embedded capacitor (such as...). Figure 2A and Figure 2B The coreless packaging substrate 402 in the IC package 200. However, in Figure 4 In the IC package 400, the capacitor package 228 is embedded in the metallization layer 420, excluding the core layer. Figure 4 IC package 400 and Figure 2A and Figure 2B Common components among the IC packages 200 are shown with the same component number.

[0033] A package substrate with an embedded capacitor package can be manufactured according to a manufacturing process. The embedded capacitor package includes an RDL formed on the capacitor substrate, wherein RDL interconnects of the RDL are coupled to capacitor terminals of the capacitor to redistribute the connection to the capacitor terminals to align with die interconnects of a die coupled to the package substrate within the IC package, thereby minimizing the connection path length between the capacitor and the die. In this respect, Figure 5 This is a flowchart illustrating an exemplary manufacturing process 500 for manufacturing a package substrate, which includes, but is not limited to, the package substrate. Figures 2A to 4 The packaging substrates 202, 302, and 402 in the package have embedded capacitor packages, including but not limited to... Figures 2A to 4 The capacitor package 228 includes an RDL formed on a capacitor substrate, wherein RDL interconnects of the RDL are coupled to capacitor terminals of the capacitor to redistribute the connection to the capacitor terminals for alignment with die interconnects of a die coupled to the package substrate in the IC package, thereby minimizing the connection path length between the capacitor and the die. Reference Figures 2A to 2B Discussion of the packaging substrate 202 and embedded capacitor package 228 in IC package 200 Figure 5 The manufacturing process 500 is included, but the manufacturing process 500 is not limited to this.

[0034] In this respect, such as Figure 5As shown, the manufacturing process 500 of manufacturing the packaging substrate 202 may include providing a first metallization layer 220 (1), which includes a plurality of first metal interconnects 218 (1) having a first spacing P7, P8 or P5, P6 in a first direction (X-axis and / or Y-axis direction). Figure 5 (See box 502 in the middle). Manufacturing process 500 may also include providing capacitor package 228 ( Figure 5 Box 504 in the middle), which includes providing capacitor 232 ( Figure 5 (Frame 506), including a capacitor substrate 216 forming a first surface 214 ( Figure 5 (in the frame 508), and a plurality of capacitor terminals 210 formed in the first direction (X-axis and / or Y-axis direction) having a second spacing P5, P6 or P7, P8 different from the first spacing P7, P8 or P5, P6. Figure 5 (Frame 510 in the middle). Manufacturing process 500 may also include forming an RDL substrate 230 adjacent to the capacitor substrate 216. Figure 5 (in box 512), which includes forming a first RDL 234(1), the first RDL including a plurality of first RDL interconnects 236(1) adjacent to the capacitor substrate 216. Figure 5 (in box 514), and coupling each of the plurality of first RDL interconnects 236(1) to the capacitor terminals 210 of the plurality of capacitor terminals 210 and the first metal interconnects 218(1) of the plurality of first metal interconnects 218(1) (in box 514), and coupling each of the plurality of first RDL interconnects 236(1) to the capacitor terminals 210 of the plurality of capacitor terminals 210 and the first metal interconnects 218(1) of the plurality of first metal interconnects 218(1). Figure 5 (Box 516 in the middle).

[0035] The packaging substrate can be manufactured in other manufacturing processes, including but not limited to... Figures 2A to 4 The packaging substrates 202, 302, and 402 in the package have embedded capacitor packages, including but not limited to... Figures 2A to 4 The capacitor package 228 includes an RDL formed on the substrate of the capacitor, wherein the RDL interconnects of the RDL are coupled to the capacitor terminals of the capacitor to redistribute the connection to the capacitor terminals to align with the die interconnects of the die coupled to the package substrate in the IC package to minimize the connection path length between the capacitor and the die.

[0036] For example, Figure 6A and Figure 6BThis is a flowchart illustrating a manufacturing process 600 for manufacturing a capacitor package. Each capacitor package includes an RDL formed on a capacitor substrate, wherein RDL interconnects of the RDL are coupled to capacitor terminals of the capacitor to redistribute connections to the capacitor terminals, allowing the capacitor package to be disposed within an IC package. The capacitor terminals of the capacitor are aligned with die interconnects of a die coupled to the package substrate of the IC package to minimize the connection path length between the capacitor and the die, including but not limited to... Figures 2A to 4 The capacitor package 228 in the middle. Figures 7A to 7H It is based on 6A and Figure 6B Exemplary manufacturing stages 700A-700H during the manufacturing of the capacitor package in the exemplary manufacturing process 600 are described below. Figure 2A and Figure 2B Let's discuss the exemplary capacitor package 228 in the IC package 200. Figure 6A and Figure 6B In manufacturing process 600, the capacitor package is manufactured into multiple capacitor packages according to the reconstructed wafer manufacturing process, but this is not limiting.

[0037] In this respect, such as Figure 7A As shown in the exemplary manufacturing stage 700A, the first step in the manufacturing process 600 may be placing the silicon capacitor 204 on the reconstructed wafer 702. Figure 6A (See frame 602 in the image). Silicon capacitors 204 can be manufactured using a different silicon capacitor manufacturing process. Each silicon capacitor 204 includes a capacitor substrate 216 in which capacitors are formed. Multiple silicon capacitors 204 can be placed on a reconstruction wafer 702 such that an RDL substrate 230 can be formed thereon to contact its capacitor terminals 210 to form multiple capacitor packages 228, which can then be diced to provide multiple individual capacitor packages 228. Then, as part of a package substrate manufacturing process, those capacitor packages 228 can be embedded in the package substrate 202, as will be described below. Figures 8A to 8E The examples discussed in the text.

[0038] Subsequently, as Figure 7B As shown in the exemplary manufacturing stage 700B, the next step in the manufacturing process 600 may be to encapsulate the silicon capacitor 204 placed on the reconstructed wafer 702 with molding material 704. Figure 6A (See box 604 in the image). This is to protect the silicon capacitor 204 and its capacitor terminals 210 and to insulate the capacitor terminals 210 from each other in preparation for further processing. Then, as... Figure 7CAs shown in the exemplary manufacturing stage 700C, the next step in the manufacturing process 600 may be to grind the back side of the molding material 704 onto the first surface 214 of the capacitor substrate 216 and expose the capacitor terminals 210. Figure 6A (Box 606 in the middle). Then, as... Figure 7D As shown in the exemplary manufacturing stage 700D, the next step in manufacturing process 600 may be to form an RDL substrate 230 on a first surface 214 of molding material 704, which will become part of capacitor package 228. Figure 6A (in frame 608). RDL substrate 230 can be formed by constructing one or more RDLs 234(1), 234(2), each RDL having as previously stated. Figure 2A and Figure 2B The RDL interconnects 236(1) and 236(2) are described. The process of forming RDL 234(1) and 234(4) may be to provide a coating to expose and pattern openings for the design redistribution of signal routing paths and to form RDL interconnects 236(1) and 236(2) using an under-bump metallization (UBM) process.

[0039] Then, as Figure 7E As shown in the exemplary manufacturing stage 700E, the next step in the manufacturing process 600 may be to pattern openings 705 in the RDL 234(1) of the RDL substrate 230 to prepare for metal plating in order to form metal interconnects 706 (e.g., copper pillars), which will be used to couple the RDL substrate 230 to the second metallization layer 220(2). Figure 6B (Frame 610 in the middle). The combined RDL substrate 230 and silicon capacitor 204 will be diced to form capacitor package 228. Then, as Figure 7F As shown in the exemplary manufacturing stage 700F, the next step in manufacturing process 600 may be to remove the reconstructed wafer 702 to prepare for dicing to fabricate individual capacitor substrates 216. Figure 6B (Box 612 in the middle). Then, as... Figure 7G As shown in the exemplary manufacturing stage 700G, the next step in manufacturing process 600 is to cut or divide the capacitor substrate 216 to provide individual capacitor packages 228. Figure 6B (See box 614 in the image). This provides a separate capacitor substrate 228 that can be embedded in the package substrate 202, such as... Figure 7H The manufacturing stage 700H is shown in the figure. Figure 6B (Box 616 in the middle).

[0040] Figures 8A to 8EThis is a flowchart illustrating another manufacturing process 800 for manufacturing a package substrate including an embedded capacitor package, the embedded capacitor package including an RDL formed on a capacitor substrate, wherein RDL interconnects of the RDL are coupled to capacitor terminals of the capacitor to redistribute the connections to the capacitor terminals for alignment with die interconnects of a die coupled to the package substrate in the IC package, to minimize the connection path length between the capacitor and the die, including but not limited to... Figures 2A to 4 The packaging substrates 202, 302, and 402 are used in this process. Figures 9A to 9I It is based on 8A to Figure 8E Exemplary manufacturing stages 900A-900I during the manufacturing of the package substrate in exemplary manufacturing process 800. As an example, Figures 8A to 8E The manufacturing process 800 can be used Figure 6A and 6B The manufacturing process in step 600 is performed to produce the capacitor package. See below for reference. Figure 2A and Figure 2B Discussion of exemplary package substrate 202 in IC package 200 Figures 8A to 8E The manufacturing process is 800, but this is not limiting.

[0041] In this respect, such as Figure 9A As shown in the exemplary manufacturing stage 900A, the first step in the manufacturing process 800 may be the formation of the core layer 206, since this example involves manufacturing a packaging substrate 202 including the core layer 206. Figure 8A (See box 802 in the image). For example, core layer 206 can be composed of elements between forty (40) and two hundred (200). The core layer 206 is made of a relatively hard material between m. An opening 902 is formed in the core layer 206 to allow via formation in order to provide connection coupling through the core layer 206. Then, as Figure 9B As shown in exemplary manufacturing stage 900B, the next step in manufacturing process 800 may be forming a via 904 in opening 902 and forming metal interconnects 218(2), 218(3) to provide interconnects for electrical coupling to the via 904. Figure 8B (Box 804 in the text). Then, as... Figure 9C As shown in exemplary manufacturing stage 900C, the next step in manufacturing process 800 may be forming a cavity 906 in core layer 206 to prepare for embedding capacitor package 228 in core layer 206. Figure 8C (Box 806 in the middle). Then, as... Figure 9D As shown in the exemplary manufacturing stage 900D, the next step in the manufacturing process 800 may be to form a strip layer 908 and then embed the capacitor package 228 into the cavity 906. Figure 8D(See box 808 in the image). The capacitor package 228 is coupled to the strip layer 908 to temporarily hold the capacitor package 228 in the cavity 906.

[0042] Then, as Figure 9E As shown in exemplary manufacturing stage 900E, the next step in manufacturing process 800 may be to form an insulating layer 910 on the core layer 206 on the opposite side of the metallization layer 220 (3) to insulate the metal interconnect 218 (3). Figure 8C (Box 810 in the middle). Then, as... Figure 9F As shown in exemplary manufacturing stage 900F, the next step in manufacturing process 800 may be forming an insulating layer 912 on core layer 206, which insulates the second metal interconnect 218(2) and will be part of the second metallization layer 220(2) of package substrate 202. Figure 8C (Box 812 in the middle). Then, as... Figure 9G As shown in the exemplary manufacturing stage 900G, the next step in the manufacturing process 800 may be the formation of a via 914, which is in the form of a second metal interconnect 218(2) in the second metallization layer 220(2) and coupled to the capacitor terminal 210 of the capacitor package 228. Figure 8D (Box 814 in the middle).

[0043] Then, as Figure 9H As shown in exemplary manufacturing stage 900H, the next step in manufacturing process 800 may be the formation of metal interconnects 218(1), 218(4), which will be part of an outer metallization layer to provide metal interconnects for coupling to capacitor package 228. Figure 8D (Box 816 in the middle). Then, as... Figure 9I As shown in the exemplary manufacturing stage 900I, the next step in the manufacturing process 800 may be to form an outer metallization layer 220(1), 220(4) with an opening 916 that exposes a first metal interconnect 218(1) to allow die interconnect 222 of die 208 to couple to the first metal interconnect 218(1) in order to provide electrical coupling to capacitor package 228. Figure 8E (Box 818 in the middle).

[0044] It should be understood that the terms “first,” “second,” “third,” etc., used herein are relative terms and do not imply limitation or a strict orientation. It should also be understood that the terms “top,” “above,” “over,” and “bottom,” “below,” “below,” “below,” “top,” “bottom,” “below,” “bottom,” “below,” “top,” “above,” “top,” “bottom,” “below,” “bottom,” “below,” “top,” “above,” “top,” “bottom,” “below,” “bottom,” “below,” “top,” “top,” “top,” “bottom,” “below,” “bottom,” “bottom,” “bottom,” “bottom,” “top,” “top,” “top,” “bottom,” “bottom,” “bottom,” “bottom,” “bottom,” “bottom,” “top,” “top,” “above,” “top,” “bottom,” “bottom,” “bottom,” “bottom,” “bottom,” “bottom,” “bottom,” “bottom,” “top,” “above,” “top,” “above,” “bottom,” “bottom,” “bottom,” “bottom,” “bottom,” “bottom,” “bottom,” “bottom,” “bottom,” “bottom,” “bottom,” “top,” “above,” “top,” “above,” “top,” “above,” “bottom,” “bottom,” “bottom,” “bottom,” “bottom,” “bottom,” “bottom,” “bottom,” “bottom,” “bottom,” “bottom,” “bottom,” “bottom,” “bottom,” “bottom,” “top,” “above,” “top,” “above,” “top,” “above,” “top,” “bottom ...

[0045] Additionally, as discussed in this paper, object "proximity" refers to an object being next to or adjacent to another stated object. Adjacent objects may not be directly physically coupled to each other. An object may be directly adjacent to another object, meaning that such an object is directly next to or adjacent to another object, without any other object or layer situated between the directly adjacent objects. An object may be indirectly or indirectly adjacent to another object, meaning that such objects are not directly next to or directly close to each other, but rather that an intermediate object or layer is situated between the non-directly adjacent objects.

[0046] The following can be configured in or integrated into any processor-based device: a capacitor package comprising an RDL formed on a capacitor substrate, wherein RDL interconnects of the RDL are coupled to capacitor terminals of the capacitor to redistribute the connections to the capacitor terminals for alignment with die interconnects of a die coupled to the substrate of the IC package in order to minimize the signal path length between the capacitor and the die (including but not limited to...). Figures 2A to 4 and Figure 7H Capacitor package 228), and IC packages including such capacitor packages (including but not limited to capacitor packages 228). Figures 2A to 2B , Figure 3 , Figure 4 and Figure 9I IC packages 200, 300, and 400 are included in the design, and the IC package can be manufactured according to the manufacturing process (including but not limited to...). Figure 5 , Figures 6A to 6B and Figures 8A to 8EThe exemplary manufacturing processes 500, 600, and 800 described herein are used to manufacture, and are manufactured according to any aspect disclosed herein. Examples not intended to be limiting include: set-top boxes, entertainment units, navigation devices, communication devices, fixed location data units, mobile location data units, Global Positioning System (GPS) devices, mobile phones, cellular phones, smartphones, Session Initiation Protocol (SIP) phones, tablet devices, tablet phones, servers, computers, portable computers, mobile computing devices, wearable computing devices (e.g., smartwatches, health or fitness trackers, glasses, etc.), desktop computers, personal digital assistants (PDAs), monitors, computer monitors, televisions, tuners, radios, satellite radios, music players, digital music players, portable music players, digital video players, video players, digital video disc (DVD) players, portable digital video players, automobiles, vehicle components, avionics systems, drones, and multirotor aircraft.

[0047] In this respect, Figure 10 An exemplary wireless communication device 1000 is illustrated, which includes one or more IC packages 1002, 1002(1), 1002(2) (including but not limited to...) Figures 2A to 4 and Figure 9I IC packages 200, 300, and 400 are included in the IC package. Each IC package includes packages 1003, 1003(1), and 1003(2) with embedded capacitors (including but not limited to...). Figures 2A to 4 , Figure 7H and Figure 9I The capacitor package 228 includes a package substrate comprising an RDL formed on the capacitor substrate, wherein RDL interconnects of the RDL are coupled to capacitor terminals of the capacitor to redistribute the connections to the capacitor terminals for alignment with die interconnects of the die coupled to the package substrate in the IC package to minimize the signal path length between the capacitor and the die, and the IC package may be manufactured according to the manufacturing process (including but not limited to...) Figure 5 , Figures 6A to 6B and Figures 8A to 8E The exemplary manufacturing processes 500, 600, 800 in this document are used to manufacture the product, and the product is manufactured according to any aspect disclosed herein.

[0048] As an example, the wireless communication device 1000 may include any of the devices mentioned above or be installed in any of the devices mentioned above. Figure 10As shown, the wireless communication device 1000 includes a transceiver 1004 and a data processor 1006. The data processor 1006 may include memory for storing data and program code. The transceiver 1004 includes a transmitter 1008 and a receiver 1010 supporting bidirectional communication. Generally, the wireless communication device 1000 may include any number of transmitters 1008 and / or receivers 1010 for any number of communication systems and frequency bands. All or part of the transceiver 1004 may be implemented on one or more analog ICs, RF ICs (RFICs), mixed-signal ICs, etc.

[0049] The transmitter 1008 or receiver 1010 can be implemented using either a superheterodyne architecture or a direct conversion architecture. In a superheterodyne architecture, the signal undergoes multi-stage frequency conversion between RF and baseband. For example, for receiver 1010, the signal is converted from RF to intermediate frequency (IF) in one stage, and then from IF to baseband in another stage. In a direct conversion architecture, the signal is converted between RF and baseband in a single stage. Superheterodyne and direct conversion architectures can use different circuit blocks and / or have different requirements. Figure 10 In the wireless communication device 1000, the transmitter 1008 and the receiver 1010 are implemented using a direct frequency conversion architecture.

[0050] In the transmission path, data processor 1006 processes the data to be transmitted and provides I and Q analog output signals to transmitter 1008. In the exemplary wireless communication device 1000, data processor 1006 includes digital-to-analog converters (DACs) 1012(1) and 1012(2) to convert the digital signals generated by data processor 1006 into I and Q analog output signals (e.g., I and Q output currents) for further processing.

[0051] Within transmitter 1008, low-pass filters 1014(1) and 1014(2) filter the I and Q analog output signals, respectively, to remove unwanted signals caused by the previous digital-to-analog conversion. Amplifiers (AMPs) 1016(1) and 1016(2) amplify the signals from low-pass filters 1014(1) and 1014(2), respectively, and provide I and Q baseband signals. Upconverter 1018 uses mixers 1020(1) and 1020(2) to upconvert the I and Q baseband signals from transmit (TX) local oscillator (LO) signal generator 1022 to provide upconverted signal 1024. Filter 1026 filters the upconverted signal 1024 to remove unwanted signals caused by upconversion and noise in the receive band. Power amplifier (PA) 1028 amplifies the upconverted signal 1024 from filter 1026 to obtain the desired output power level and provides the transmit RF signal. The RF signal is routed through the duplexer or switch 1030 and transmitted via the antenna 1032.

[0052] In the receiving path, antenna 1032 receives signals transmitted by the base station and provides the received RF signal, which is routed through duplexer or switch 1030 and provided to low-noise amplifier (LNA) 1034. Duplexer or switch 1030 is designed to operate using a specific receive (RX) to TX duplexer frequency separation, such that the RX signal is isolated from the TX signal. The received RF signal is amplified by LNA 1034 and filtered by filter 1036 to obtain the desired RF input signal. Downconversion mixers 1038(1) and 1038(2) mix the output of filter 1036 with the I and Q RXLO signals (i.e., LO_I and LO_Q) from RX LO signal generator 1040 to generate I and Q baseband signals. The I and Q baseband signals are amplified by AMPs 1042(1) and 1042(2) and further filtered by low-pass filters 1044(1) and 1044(2) to obtain I and Q analog input signals, which are provided to data processor 1006. In this example, data processor 1006 includes analog-to-digital converters (ADCs) 1046(1) and 1046(2) to convert the analog input signals into digital signals to be further processed by data processor 1006.

[0053] exist Figure 10In the wireless communication device 1000, a TX LO signal generator 1022 generates I and Q TXLO signals for up-conversion, while an RX LO signal generator 1040 generates I and Q RX LO signals for down-conversion. Each LO signal is a periodic signal with a specific base frequency. A TX phase-locked loop (PLL) circuit 1048 receives timing information from a data processor 1006 and generates control signals for adjusting the frequency and / or phase of the TX LO signals from the TX LO signal generator 1022. Similarly, an RX PLL circuit 1050 receives timing information from a data processor 1006 and generates control signals for adjusting the frequency and / or phase of the RX LO signals from the RX LO signal generator 1040.

[0054] Figure 11 An example of a processor-based system 1100 is illustrated, which includes one or more IC packages 1102, 1102(1)-1102(8) (including but not limited to...) Figures 2A to 4 and Figure 9I IC packages 200, 300, and 400 are included in the IC package. Each IC package includes packages 1104, 1104(1)-1104(8) with embedded capacitors (including but not limited to...). Figures 2A to 4 , Figure 7H and Figure 9I The capacitor package 228 includes a package substrate comprising an RDL formed on the capacitor substrate, wherein RDL interconnects of the RDL are coupled to capacitor terminals of the capacitor to redistribute the connections to the capacitor terminals for alignment with die interconnects of the die coupled to the package substrate in the IC package to minimize the signal path length between the capacitor and the die, and the IC package may be manufactured according to the manufacturing process (including but not limited to...) Figure 5 , Figures 6A to 6B and Figures 8A to 8E The exemplary manufacturing processes 500, 600, 800 in this document are used to manufacture the product, and the product is manufactured according to any aspect disclosed herein.

[0055] In this example, the processor-based system 1100 may include a capacitor package 1104, which is included in an IC package 1102, such as a system-on-a-chip (SoC) 1106. The processor-based system 1100 includes a CPU 1108, which includes one or more processors 1110, which may also be referred to as a CPU core or processor core. The CPU 1108 may be disposed in an IC package 1102 (1), which includes a package substrate having an embedded capacitor package 1104 (1). The CPU 1108 may have a cache memory 1112 coupled to the CPU 1108 for fast access to temporarily stored data. The CPU 1108 is coupled to a system bus 1114 and may be coupled to master and slave devices included in the processor-based system 1100. As is well known, the CPU 1108 communicates with these other devices by exchanging address, control, and data information via the system bus 1114. For example, CPU 1108 can communicate bus transaction requests to memory controller 1116, which is an example of a slave device. Although in Figure 11 Not illustrated, but multiple system buses 1114 may be provided, each of which constitutes a different structure.

[0056] Other master and slave devices can be connected to system bus 1114. For example... Figure 11As illustrated, by way of example, these devices may include a memory system 1120, one or more input devices 1122, one or more output devices 1124, one or more network interface devices 1126, and one or more display controllers 1128, the memory system including a memory controller 1116 and a memory array 1118. The memory system 1120 may be disposed in an IC package 1102(2) including a package substrate having an embedded capacitor package 1104(2). The network interface device 1126 may be disposed in an IC package 1102(3) including a package substrate having an embedded capacitor package 1104(3). Each of the memory system 1120, one or more input devices 1122, one or more output devices 1124, one or more network interface devices 1126, and one or more display controllers 1128 may be disposed in the same or different circuit packages. Input device 1122 and / or output device 1124 may be disposed in corresponding IC packages 1102(4), 1102(5), which include a package substrate having corresponding embedded capacitor packages 1104(4), 1104(5). Input device 1122 may include any type of input device, including but not limited to input keys, switches, voice processors, etc. Output device 1124 may include any type of output device, including but not limited to audio, video, other visual indicators, etc. Network interface device 1126 may be any device configured to allow the exchange of data to and from network 1130. Network 1130 may be any type of network, including but not limited to wired or wireless networks, private or public networks, local area networks (LANs), wireless local area networks (WLANs), wide area networks (WANs), Bluetooth. ™ Networks and the Internet. The network interface device 1126 can be configured to support any type of communication protocol desired.

[0057] CPU 1108 can also be configured to access display controller 1128 via system bus 1114 to control information transmitted to one or more displays 1132. Display 1132 may be disposed in IC package 1102 (6), which includes a package substrate having embedded capacitor package 1104 (6). Display controller 1128 transmits information to be displayed to display 1132 via one or more video processors 1134, which process the information to be displayed into a format suitable for display 1132. As an example, display controller 1128 and video processor 1134 may be disposed in corresponding IC packages 1102 (7), 1102 (8), which include package substrates having corresponding embedded capacitor packages 1104 (7), 1104 (8), or may be disposed in the same IC package 1102, or may be disposed in the same IC package 1102 (1) containing CPU 1108. The display 1132 may include any type of display, including but not limited to cathode ray tube (CRT), liquid crystal display (LCD), plasma display, light-emitting diode (LED) display, etc.

[0058] Those skilled in the art will further understand that the various exemplary logic blocks, modules, circuits, and algorithms described in connection with the aspects disclosed herein can be implemented as electronic hardware, stored in memory or another computer-readable medium and executed by a processor or other processing device, or a combination of both. The memory disclosed herein can be of any type and size and can be configured to store any type of information desired. To clearly illustrate this interchangeability, the functionality of the various exemplary components, blocks, modules, circuits, and steps has been generally described above. How such functionality is implemented depends on the specific application, design choices, and / or design constraints imposed on the overall system. Those skilled in the art may implement the described functionality in different ways for each specific application, but such specific implementation decisions should not be construed as departing from the scope of this disclosure.

[0059] The various exemplary logic blocks, modules, and circuits described in conjunction with the aspects disclosed herein may be implemented or executed using a processor, digital signal processor (DSP), application-specific integrated circuit (ASIC), field-programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic unit, discrete hardware component, or any combination thereof, designed to perform the functions described herein. The processor may be a microprocessor, but in alternative embodiments, the processor may be any conventional processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors cooperating with a DSP core, or any other such configuration).

[0060] The aspects disclosed herein may be embodied in hardware and instructions stored in the hardware, and may reside in, for example, random access memory (RAM), flash memory, read-only memory (ROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), registers, hard disks, removable disks, CD-ROMs, or any other form of computer-readable medium known in the art. An exemplary storage medium is coupled to a processor, enabling the processor to read information from and write information to the storage medium. Alternatively, the storage medium may be integral with the processor. The processor and storage medium may reside in an ASIC. The ASIC may reside in a remote station. Alternatively, the processor and storage medium may reside as discrete components in a remote station, base station, or server.

[0061] It should also be noted that the operational steps described in any of the exemplary aspects of this document are described for the purpose of providing examples and discussion. The described operations may be performed in many different orders other than the order illustrated. Furthermore, the operations described in a single operational step may actually be performed in multiple different steps. In addition, one or more operational steps discussed in the exemplary aspects may be combined. It should be understood that, as will be apparent to those skilled in the art, many different modifications may be made to the operational steps illustrated in the flowcharts. Those skilled in the art will also understand that any of a variety of different techniques and arts can be used to represent information and signals. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be mentioned throughout the above description may be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, light fields or optical particles, or any combination thereof.

[0062] The prior description of this disclosure is provided to enable any person skilled in the art to make or use this disclosure. Various modifications to this disclosure will be apparent to those skilled in the art, and the general principles defined herein can be applied to other variations. Therefore, this disclosure is not intended to be limited to the examples and designs described herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

[0063] Specific implementation examples are described in the following numbered clauses: 1. A packaging substrate, the packaging substrate comprising: A first metallization layer, the first metallization layer including a plurality of first metal interconnects having a first spacing in a first direction; A capacitor package, the capacitor package comprising: A capacitor, the capacitor comprising: A capacitor substrate, the capacitor substrate including a first surface; and Multiple capacitor terminals, wherein the multiple capacitor terminals have a second spacing different from the first spacing in the first direction; and A redistribution layer (RDL) substrate, the redistribution layer (RDL) substrate being adjacent to the capacitor substrate, the RDL substrate comprising: The first RDL includes a plurality of first RDL interconnects, each of which is coupled to a capacitor terminal in the plurality of capacitor terminals and to a first metal interconnect in the plurality of first metal interconnects.

[0064] 2. The packaging substrate according to Clause 1, wherein the first pitch is smaller than the second pitch.

[0065] 3. The packaging substrate according to Clause 2, wherein the first pitch is 130 micrometers (µm) and the second pitch is 150 µm.

[0066] 4. The packaging substrate according to Clause 1, wherein the first pitch is greater than the second pitch.

[0067] 5. The packaging substrate according to Clause 4, wherein each of the plurality of first RDL interconnects has a first axis intersecting the first metal interconnect along a second direction orthogonal to the first direction.

[0068] 6. The packaging substrate according to any one of claims 1 to 5, wherein the RDL substrate further comprises a second RDL, the second RDL comprising a plurality of second RDL interconnects each coupled to a capacitor interconnect in a plurality of capacitor interconnects and coupled to a first RDL interconnect in a plurality of first RDL interconnects.

[0069] 7. The packaging substrate according to Clause 6, wherein each of the plurality of second RDL interconnects has a second axis intersecting the capacitor terminals of the plurality of capacitor terminals along a second direction orthogonal to the first direction.

[0070] 8. The packaging substrate according to any one of clauses 1 to 7, wherein the plurality of capacitor terminals include a plurality of first interconnecting bumps.

[0071] 9. The packaging substrate according to Clause 8, wherein the RDL substrate further includes a plurality of second interconnect bumps, each coupled to a first interconnect bump in the plurality of first interconnect bumps and each coupled to a first metal interconnect in the plurality of first metal interconnects.

[0072] 10. The packaging substrate according to Clause 9, wherein: The RDL substrate further includes a solder resist layer adjacent to the first RDL in a second direction orthogonal to the first direction, the solder resist layer including a plurality of openings; and Each of the plurality of second interconnect bumps is at least partially disposed in an opening of the plurality of openings and coupled to a first RDL interconnect of the plurality of first RDL interconnects.

[0073] 11. The packaging substrate according to claim 9 or 10, wherein the packaging substrate further comprises a plurality of third interconnect bumps adjacent to the first metallization layer, each of the plurality of third interconnect bumps being coupled to a second interconnect bump of the plurality of second interconnect bumps.

[0074] 12. The packaging substrate according to any one of clauses 1 to 11, wherein: The packaging substrate includes a core-packaged substrate, the core-packaged substrate including a core layer adjacent to the first metallization layer in a second direction orthogonal to the first direction; and The capacitor package is at least partially embedded in the core layer.

[0075] 13. The packaging substrate according to any one of clauses 1 to 11, wherein the packaging substrate includes a coreless packaging substrate.

[0076] 14. The packaging substrate according to any one of clauses 1 to 11 and 13, wherein the packaging substrate is at least partially embedded in the first metallization layer.

[0077] 15. The packaging substrate according to any one of clauses 1 to 14, wherein the capacitor comprises a silicon capacitor.

[0078] 16. The packaging substrate according to any one of Clauses 1 to 15, wherein the packaging substrate is integrated into a device selected from the group consisting of: set-top boxes; entertainment units; navigation devices; communication devices; fixed location data units; mobile location data units; global positioning system (GPS) devices; mobile phones; cellular phones; smartphones; session initiation protocol (SIP) phones; tablet computers; tablet phones; servers; computers; portable computers; mobile computing devices; wearable computing devices; desktop computers; personal digital assistants (PDAs); computer monitors; televisions; tuners; radios; satellite radios; music players; digital music players; portable music players; digital video players; video players; digital video disc (DVD) players; portable digital video players; automobiles; vehicle components; avionics systems; unmanned aerial vehicles; and multirotor aircraft.

[0079] 17. A method for manufacturing a packaging substrate, the method comprising: A first metallization layer is provided, the first metallization layer including a plurality of first metal interconnects having a first spacing in a first direction; and Provide capacitor packages, including: Provide capacitors, including: A capacitor substrate is formed, the capacitor substrate including a first surface; and Forming a plurality of capacitor terminals, the plurality of capacitor terminals having a second spacing different from the first spacing in the first direction; and A redistribution layer (RDL) substrate is formed adjacent to the capacitor substrate, comprising: Forming a first RDL, the first RDL including a plurality of first RDL interconnects adjacent to the capacitor substrate; and Each of the plurality of first RDL interconnects is coupled to a capacitor terminal of the plurality of capacitor terminals and a first metal interconnect of the plurality of first metal interconnects.

[0080] 18. The method according to Clause 17, wherein the first spacing is smaller than the second spacing.

[0081] 19. The method according to Clause 17, wherein the first spacing is greater than the second spacing.

[0082] 20. The packaging substrate according to any one of clauses 17 to 19, wherein forming the RDL substrate further comprises: Forming a second RDL, the second RDL including a plurality of second RDL interconnects adjacent to the first RDL in a second direction orthogonal to the first direction; and Each of the plurality of second RDL interconnects is coupled to a capacitor interconnect in a plurality of capacitor interconnects and a first RDL interconnect in a plurality of first RDL interconnects.

[0083] 21. The method according to any one of clauses 17 to 20, wherein the method further comprises: A core layer formed adjacent to the first metallization layer in a second direction orthogonal to the first direction; and The capacitor package is at least partially embedded in the core layer.

[0084] 22. The method according to any one of clauses 17 to 21, wherein: The capacitor package also includes: The capacitor is mounted on the wafer; Forming the RDL substrate includes forming the RDL substrate adjacent to the capacitor substrate on the wafer; and The wafer is cut to provide the capacitor substrate.

[0085] 23. The method according to any one of clauses 17 to 22, wherein the method further comprises: A cavity is formed in the first metallization layer; and The capacitor package is at least partially embedded in the cavity.

[0086] 24. The method according to any one of clauses 17 to 22, wherein the method further comprises: A core layer is formed adjacent to the first metallization layer in a second direction orthogonal to the first direction; A cavity is formed in the core layer; and The capacitor package is at least partially embedded in the cavity.

[0087] 25. An integrated circuit (IC) package, the integrated circuit (IC) package comprising: Packaging substrate, the packaging substrate comprising: A first metallization layer, the first metallization layer including a plurality of first metal interconnects having a first spacing in a first direction; and A capacitor package, the capacitor package comprising: A capacitor, the capacitor comprising: A capacitor substrate, the capacitor substrate including a first surface; and Multiple capacitor terminals, wherein the multiple capacitor terminals have a second spacing different from the first spacing in the first direction; and A redistribution layer (RDL) substrate, the redistribution layer (RDL) substrate being adjacent to the capacitor substrate, the RDL substrate comprising: A first RDL, the first RDL comprising a plurality of first RDL interconnects, each coupled to a capacitor terminal in the plurality of capacitor terminals and each coupled to a first metal interconnect in the plurality of first metal interconnects; and The die includes a plurality of die interconnects, the plurality of die interconnects having the first spacing in the first direction and each being coupled to a first metal interconnect among the plurality of first metal interconnects.

[0088] 26. The IC package according to Clause 25, wherein the first pitch is smaller than the second pitch.

[0089] 27. The IC package according to Clause 25, wherein the first pitch is greater than the second pitch.

[0090] 28. An IC package according to any one of clauses 25 to 27, wherein each of the plurality of first RDL interconnects has a first axis intersecting the first metal interconnect along a second direction orthogonal to the first direction.

[0091] 29. An IC package according to any one of clauses 25 to 28, wherein: The packaging substrate includes a core-packaged substrate, the core-packaged substrate including a core layer adjacent to the first metallization layer in a second direction orthogonal to the first direction; and The capacitor package is at least partially embedded in the core layer.

[0092] 30. An IC package according to any one of clauses 25 to 28, wherein: The packaging substrate includes a coreless packaging substrate; and The packaging substrate is at least partially embedded in the first metallization layer.

Claims

1. A packaging substrate, the packaging substrate comprising: A first metallization layer, the first metallization layer including a plurality of first metal interconnects having a first spacing in a first direction; A capacitor package, the capacitor package comprising: A capacitor, the capacitor comprising: A capacitor substrate, the capacitor substrate including a first surface; and Multiple capacitor terminals, wherein the multiple capacitor terminals have a second spacing different from the first spacing in the first direction; and A redistribution layer (RDL) substrate, the redistribution layer (RDL) substrate being adjacent to the capacitor substrate, the RDL substrate comprising: The first RDL includes a plurality of first RDL interconnects, each of which is coupled to a capacitor terminal in the plurality of capacitor terminals and to a first metal interconnect in the plurality of first metal interconnects.

2. The packaging substrate according to claim 1, wherein the first spacing is smaller than the second spacing.

3. The packaging substrate according to claim 2, wherein the first pitch is 130 micrometers (µm) and the second pitch is 150 µm.

4. The packaging substrate according to claim 1, wherein the first spacing is greater than the second spacing.

5. The packaging substrate of claim 1, wherein each of the plurality of first RDL interconnects has a first axis intersecting the first metal interconnect along a second direction orthogonal to the first direction.

6. The packaging substrate of claim 1, wherein the RDL substrate further comprises a second RDL, the second RDL comprising a plurality of second RDL interconnects each coupled to a capacitor interconnect in a plurality of capacitor interconnects and coupled to a first RDL interconnect in a plurality of first RDL interconnects.

7. The packaging substrate of claim 6, wherein each of the plurality of second RDL interconnects has a second axis intersecting a capacitor terminal among the plurality of capacitor terminals along a second direction orthogonal to the first direction.

8. The packaging substrate of claim 1, wherein the plurality of capacitor terminals include a plurality of first interconnect bumps.

9. The packaging substrate of claim 8, wherein the RDL substrate further comprises a plurality of second interconnect bumps, each coupled to a first interconnect bump in the plurality of first interconnect bumps and each coupled to a first metal interconnect in the plurality of first metal interconnects.

10. The packaging substrate according to claim 9, wherein: The RDL substrate further includes a solder resist layer adjacent to the first RDL in a second direction orthogonal to the first direction, the solder resist layer including a plurality of openings; and Each of the plurality of second interconnect bumps is at least partially disposed in an opening of the plurality of openings and coupled to a first RDL interconnect of the plurality of first RDL interconnects.

11. The packaging substrate of claim 9, wherein the packaging substrate further comprises a plurality of third interconnect bumps adjacent to the first metallization layer, each of the plurality of third interconnect bumps being coupled to a second interconnect bump of the plurality of second interconnect bumps.

12. The packaging substrate according to claim 1, wherein: The packaging substrate includes a core-packaged substrate, the core-packaged substrate including a core layer adjacent to the first metallization layer in a second direction orthogonal to the first direction; and The capacitor package is at least partially embedded in the core layer.

13. The packaging substrate according to claim 1, wherein the packaging substrate includes a coreless packaging substrate.

14. The packaging substrate of claim 1, wherein the packaging substrate is at least partially embedded in the first metallization layer.

15. The packaging substrate of claim 1, wherein the capacitor comprises a silicon capacitor.

16. The packaging substrate of claim 1, wherein the packaging substrate is integrated into a device selected from the group consisting of: set-top boxes; entertainment units; navigation devices; communication devices; fixed location data units; mobile location data units; global positioning system (GPS) devices; mobile phones; cellular phones; smartphones; session initiation protocol (SIP) phones; tablet computers; tablet phones; servers; computers; portable computers; mobile computing devices; wearable computing devices; desktop computers; personal digital assistants (PDAs); computer monitors; televisions; tuners; radios; satellite radios; music players; digital music players; portable music players; digital video players; video players; digital video disc (DVD) players; portable digital video players; automobiles; vehicle components; avionics systems; unmanned aerial vehicles; and multirotor aircraft.

17. A method for manufacturing a packaging substrate, the method comprising: A first metallization layer is provided, the first metallization layer including a plurality of first metal interconnects having a first spacing in a first direction; as well as Provide capacitor packages, including: Provide capacitors, including: A capacitor substrate is formed, the capacitor substrate including a first surface; and Forming a plurality of capacitor terminals, the plurality of capacitor terminals having a second spacing different from the first spacing in the first direction; and A redistribution layer (RDL) substrate is formed adjacent to the capacitor substrate, comprising: Forming a first RDL, the first RDL including a plurality of first RDL interconnects adjacent to the capacitor substrate; and Each of the plurality of first RDL interconnects is coupled to a capacitor terminal of the plurality of capacitor terminals and a first metal interconnect of the plurality of first metal interconnects.

18. The method of claim 17, wherein the first spacing is smaller than the second spacing.

19. The method of claim 17, wherein the first spacing is greater than the second spacing.

20. The packaging substrate of claim 17, wherein forming the RDL substrate further comprises: A second RDL is formed, the second RDL including a plurality of second RDL interconnects adjacent to the first RDL in a second direction orthogonal to the first direction; as well as Each of the plurality of second RDL interconnects is coupled to a capacitor interconnect in a plurality of capacitor interconnects and a first RDL interconnect in a plurality of first RDL interconnects.

21. The method according to claim 17, further comprising: A core layer is formed adjacent to the first metallization layer in a second direction orthogonal to the first direction; as well as The capacitor package is at least partially embedded in the core layer.

22. The method of claim 17, wherein: The capacitor package also includes: The capacitor is mounted on the wafer; Forming the RDL substrate includes forming the RDL substrate adjacent to the capacitor substrate on the wafer; and The wafer is cut to provide the capacitor substrate.

23. The method according to claim 17, further comprising: A cavity is formed in the first metallization layer; as well as The capacitor package is at least partially embedded in the cavity.

24. The method according to claim 17, further comprising: A core layer is formed adjacent to the first metallization layer in a second direction orthogonal to the first direction; A cavity is formed in the core layer; as well as The capacitor package is at least partially embedded in the cavity.

25. An integrated circuit (IC) package, the integrated circuit (IC) package comprising: Packaging substrate, the packaging substrate comprising: A first metallization layer, the first metallization layer including a plurality of first metal interconnects having a first spacing in a first direction; and A capacitor package, the capacitor package comprising: A capacitor, the capacitor comprising: A capacitor substrate, the capacitor substrate including a first surface; and Multiple capacitor terminals, wherein the multiple capacitor terminals have a second spacing different from the first spacing in the first direction; and A redistribution layer (RDL) substrate, the redistribution layer (RDL) substrate being adjacent to the capacitor substrate, the RDL substrate comprising: A first RDL, the first RDL comprising a plurality of first RDL interconnects, each coupled to a capacitor terminal in the plurality of capacitor terminals and each coupled to a first metal interconnect in the plurality of first metal interconnects; and The die includes a plurality of die interconnects, the plurality of die interconnects having the first spacing in the first direction and each being coupled to a first metal interconnect among the plurality of first metal interconnects.

26. The IC package of claim 25, wherein the first pitch is smaller than the second pitch.

27. The IC package of claim 25, wherein the first pitch is greater than the second pitch.

28. The IC package of claim 25, wherein each of the plurality of first RDL interconnects has a first axis intersecting the first metal interconnect along a second direction orthogonal to the first direction.

29. The IC package according to claim 25, wherein: The packaging substrate includes a core-packaged substrate, the core-packaged substrate including a core layer adjacent to the first metallization layer in a second direction orthogonal to the first direction; and The capacitor package is at least partially embedded in the core layer.

30. The IC package according to claim 25, wherein: The packaging substrate includes a coreless packaging substrate; and The packaging substrate is at least partially embedded in the first metallization layer.

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