MEMS device back cavity offset test structure and test method, semiconductor devices

Abstract

This application discloses a back cavity offset testing structure and method for MEMS devices, as well as a semiconductor device. The back cavity offset testing structure includes: a substrate, which includes a first surface and a second surface opposite to the first surface; a back cavity extending through the second surface of the substrate; at least four capacitance testing structures, each including a test diaphragm, a first pad, and a second pad. The first pad is connected to one end of the test diaphragm, and the second pad is connected to the substrate corresponding to the test diaphragm. The test diaphragm is partially located outside the back cavity, and the projection of the test diaphragm onto the substrate overlaps with the projection of the back cavity onto the substrate. The at least four capacitance testing structures are arranged circumferentially around the back cavity, and each capacitance testing structure is independent of the others. This application can monitor the offset of the back cavity during photolithography, improve the reliability of the device, and save production time and manpower.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and more specifically to a back cavity offset test structure and test method for MEMS devices, and semiconductor devices. Background Technology

[0002] With the continuous development of semiconductor technology, in the sensor product market, smartphones, integrated CMOS and microelectromechanical systems (MEMS) devices are increasingly becoming the most mainstream and advanced technologies, and with the updates of technology, they are developing towards smaller size, higher performance and lower power consumption.

[0003] Among them, MEMS microphones, fabricated using microelectromechanical systems (MEMS) technology, are widely used due to their advantages over traditional microphones, such as small size, low cost, and stable performance. MEMS microphones typically consist of a substrate, diaphragm, backplate, cavity, and other components, and convert sound signals into electrical signals through the diaphragm.

[0004] Below the diaphragm is a sacrificial layer that forms the vibration space of the diaphragm. Above the diaphragm is a cavity formed to create the space between the diaphragm and the backplate. Sound enters through the acoustic aperture, causing the diaphragm to vibrate. The specific process includes the growth of the first sacrificial layer and photolithography, the growth of the diaphragm and photolithography, the growth of the second sacrificial layer and photolithography, the growth of the third sacrificial layer and photolithography, the growth of the backplate and photolithography, back-side thinning, back-side cavity opening, and sacrificial layer release process, etc.

[0005] When creating a back cavity on the back, issues such as ion implantation angle deviation, uneven plasma sheath, and dry etching process problems can cause the back cavity structure to shift relative to the front structure, thus affecting the microphone's acoustic load and consequently its performance.

[0006] The method of monitoring the offset of the back cavity structure by designing a test structure is not only time-consuming and labor-intensive, but may also have large errors, resulting in inaccurate monitoring results. In related technologies, the offset value is obtained by visual inspection. Summary of the Invention

[0007] The summary section introduces a series of simplified concepts, which will be further explained in detail in the detailed description section. This summary section is not intended to limit the key and essential technical features of the claimed technical solution, nor is it intended to determine the scope of protection of the claimed technical solution.

[0008] To address the existing problems, this application provides a back cavity offset test structure for MEMS devices, the test structure including: A substrate, the substrate comprising a first surface and a second surface opposite to the first surface; A back cavity extends through the second surface of the substrate; At least four capacitance test structures are provided, each of which includes a test diaphragm, a first pad, and a second pad. The first pad is connected to one end of the test diaphragm, and the second pad is connected to the substrate corresponding to the test diaphragm. The test diaphragm is located outside the back cavity, and the projection of the test diaphragm on the substrate overlaps with the projection of the back cavity on the substrate. The at least four capacitance test structures are arranged at circumferential intervals along the back cavity, and each capacitance test structure is independent of the others.

[0009] In some examples, when the back cavity is not offset, the distance from the point where each test diaphragm intersects the edge of the back cavity to the outer edge of the test diaphragm is equal to its distance to the inner edge of the test diaphragm.

[0010] In some examples, the capacitance test structure includes a first capacitance test structure, a second capacitance test structure, a third capacitance test structure, and a fourth capacitance test structure. The test diaphragms of the first capacitance test structure and the third capacitance test structure are spaced apart in a first direction, and the test diaphragms of the second capacitance test structure and the fourth capacitance test structure are arranged opposite to each other in a second direction. The first direction is the direction in which the center point of the test diaphragm of the first capacitance test structure extends towards the center point of the cavity of the back cavity, and the second direction is the direction in which the center point of the test diaphragm of the second capacitance test structure extends towards the center point of the cavity of the back cavity, and the second direction is perpendicular to the first direction.

[0011] In some examples, the shape of the projection of the test diaphragm onto the substrate includes a rectangle or a square.

[0012] In some examples, the substrate includes multiple photolithographic exposure areas, and at least one of the back cavity offset test structures is disposed in each photolithographic exposure area.

[0013] In some examples, the test diaphragm includes a first dielectric layer, a conductive layer, and a second dielectric layer stacked from bottom to top, wherein one end of the conductive layer is connected to the first pad.

[0014] In some examples, a MEMS device diaphragm is also formed on the substrate. The MEMS device diaphragm is independent of the test diaphragm and has the same composition structure as the test diaphragm. The MEMS device diaphragm and the test diaphragm are fixed by the first dielectric layer and the second dielectric layer.

[0015] A second aspect of this application provides a method for testing the back cavity offset of a MEMS device, the method comprising: A substrate is provided, the substrate including a device region and a cavity offset test region, the device region having a MEMS device formed thereon, and the cavity offset test region having the cavity offset test structure described above. The capacitance value between the test diaphragm and the substrate is measured using the first and second pads on the capacitance test structure. The actual distance between the outer edge of the test diaphragm and the edge of the back cavity it is close to is obtained by using the capacitance value; The offset of the back cavity is determined based on the actual distance and the target distance. If the offset exceeds a predetermined range, the MEMS device is marked as abnormal.

[0016] In some examples, the capacitance between the test diaphragm and the substrate is measured using the first and second pads, including: Configure the probes of the capacitance tester, the probes including a first tip and a second tip; Connect the first pin tip to the first pad, and connect the second pin tip to the second pad; The capacitance value is obtained by the capacitance testing instrument in the capacitance testing machine.

[0017] A third aspect of this application provides a semiconductor device, the semiconductor device including a MEMS device and the aforementioned back cavity offset test structure, wherein the MEMS device and the back cavity offset test structure are formed on the same substrate.

[0018] The back cavity offset test structure and test method of the MEMS device and the semiconductor device of this application embodiment are provided by setting at least four capacitance test structures circumferentially spaced in the back cavity. Each capacitance test structure includes a test diaphragm, a first pad and a second pad. The first pad is connected to one end of the test diaphragm and the second pad is connected to the substrate corresponding to the test diaphragm. The offset of the back cavity is monitored by testing the capacitance between the diaphragm and the substrate. This can avoid the human error of visual measurement in related technologies, improve the reliability of the product, and save time and manpower, thereby improving production efficiency. Attached Figure Description

[0019] The following drawings, which are incorporated herein by reference and are used to understand this application, illustrate embodiments of the invention and their descriptions to explain the principles of the invention.

[0020] In the attached image: Figure 1A A top view of the back cavity offset test structure of a MEMS device according to a specific embodiment of this application is shown.

[0021] Figure 1B It shows Figure 1A Enlarged schematic diagram of a portion of the first embodiment; Figure 1C It shows Figure 1A Enlarged schematic diagram of a portion of the second embodiment; Figure 2 A cross-sectional view of the back cavity offset test structure of a MEMS device according to a specific embodiment of this application is shown.

[0022] Figure 3 A cross-sectional view of a MEMS device according to a specific embodiment of this application is shown; Figure 4 A flowchart illustrating a method for testing the back cavity offset of a MEMS device according to a specific embodiment of this application is shown. Detailed Implementation

[0023] The present application will now be described more fully with reference to the accompanying drawings, in which embodiments of the present application are illustrated. However, the present application can be implemented in various forms and should not be construed as limited to the embodiments set forth herein. Rather, providing these embodiments will make the disclosure thorough and complete, and will fully convey the scope of the present application to those skilled in the art. In the drawings, for clarity, the dimensions and relative dimensions of layers and regions may be exaggerated. The same reference numerals denote the same elements throughout.

[0024] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this application, the first element, component, area, layer, or portion discussed below may be referred to as the second element, component, area, layer, or portion.

[0025] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below” or “under” the other element or feature will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both upper and lower orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0026] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the scope of this application. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0027] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art. It will also be understood that terms as defined in commonly used dictionaries shall be interpreted as having a meaning consistent with their meaning in the relevant field and / or the context of this specification, and not as in an ideal or overly formal sense, unless expressly defined herein.

[0028] To fully understand this application, detailed steps and structures will be presented in the following description to illustrate the technical solutions proposed in this application. Preferred embodiments of this application are described in detail below; however, in addition to these detailed descriptions, this application may have other implementation methods.

[0029] With the continuous development of semiconductor technology, in the sensor product market, smartphones, integrated CMOS and microelectromechanical systems (MEMS) devices are increasingly becoming the most mainstream and advanced technologies, and with the updates of technology, they are developing towards smaller size, higher performance and lower power consumption.

[0030] Among them, MEMS microphones, fabricated using microelectromechanical systems (MEMS) technology, are widely used due to their advantages over traditional microphones, such as small size, low cost, and stable performance. MEMS microphones typically consist of a substrate, diaphragm, backplate, cavity, and other components, and convert sound signals into electrical signals through the diaphragm.

[0031] Below the diaphragm is a sacrificial layer that forms the vibration space of the diaphragm. Above the diaphragm is a cavity formed to create the space between the diaphragm and the backplate. Sound enters through the acoustic aperture, causing the diaphragm to vibrate. The specific process includes the growth of the first sacrificial layer and photolithography, the growth of the diaphragm and photolithography, the growth of the second sacrificial layer and photolithography, the growth of the third sacrificial layer and photolithography, the growth of the backplate and photolithography, back-side thinning, back-side cavity opening, and sacrificial layer release process, etc.

[0032] When creating a back cavity on the back, issues such as ion implantation angle deviation, uneven plasma sheath, and dry etching process problems can cause the back cavity structure to shift relative to the front structure, thus affecting the microphone's acoustic load and consequently its performance.

[0033] The method of monitoring the offset of the back cavity structure by designing a test structure is not only time-consuming and labor-intensive, but may also have large errors, resulting in inaccurate monitoring results. In related technologies, the offset value is obtained by visual inspection.

[0034] Therefore, in view of the aforementioned technical problems, this application proposes a back cavity offset test structure and test method for MEMS devices, and a semiconductor device. The back cavity offset test structure for MEMS devices includes: A substrate, the substrate comprising a first surface and a second surface opposite to the first surface; A back cavity extends through the second surface of the substrate; At least four capacitance test structures are provided, each of which includes a test diaphragm, a first pad, and a second pad. The first pad is connected to one end of the test diaphragm, and the second pad is connected to the substrate corresponding to the test diaphragm. The test diaphragm is located outside the back cavity, and the projection of the test diaphragm on the substrate overlaps with the projection of the back cavity on the substrate. The at least four capacitance test structures are arranged at circumferential intervals along the back cavity, and each capacitance test structure is independent of the others.

[0035] The back cavity offset test structure and test method of the MEMS device and the semiconductor device of this application embodiment are provided by arranging four capacitance test structures at circumferential intervals along the back cavity. Each capacitance test structure includes a test diaphragm, a first pad and a second pad. The first pad is connected to one end of the test diaphragm and the second pad is connected to the substrate corresponding to the test diaphragm. The offset of the back cavity is monitored by testing the capacitance between the test diaphragm and the substrate. This can avoid the human error of visual measurement in related technologies, improve the reliability of the product, and save production time and manpower, thereby improving production efficiency.

[0036] Example 1 Below, for reference Figures 1A to 1C , Figure 2 and Figure 3 The back cavity offset test structure of the MEMS device in this application is described in detail.

[0037] For example, the back cavity offset test structure of the MEMS device of this application includes: a substrate, a back cavity, and at least four capacitance test structures.

[0038] For example, such as Figure 1A and Figure 2 As shown, the substrate 100 includes a first surface 101 and a second surface 102 opposite to it.

[0039] The substrate 100 is a bulk silicon substrate, which may be at least one of the following materials: Si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP, InGaAs or other III / V compound semiconductors, including multilayer structures composed of these semiconductors, or silicon on insulator (SOI), silicon on insulator (SSOI), silicon on insulator (S-SiGeOI), silicon on insulator (SiGeOI), and germanium on insulator (GeOI), etc.

[0040] The back cavity 110 extends through the second surface 102 of the substrate 100.

[0041] Exemplary, the back cavity offset test structure of this application embodiment is formed synchronously with the MEMS device, such as... Figure 2 and Figure 3As shown, the cavity offset test structure and the MEMS device are formed on the same substrate 100. The substrate 100 includes a device region and a cavity offset test region. The MEMS device is formed in the device region, and the cavity offset test structure is formed in the cavity offset test region. The MEMS device can be any suitable device known to those skilled in the art. In this embodiment, the technical solution of this application is explained and illustrated mainly by taking the case of the MEMS device as a MEMS microphone as an example. Since the cavity offset test structure and the MEMS device are formed synchronously, for example, the diaphragm of the MEMS device, i.e., the MEMS device diaphragm 131, is formed synchronously during the formation of the test diaphragm 121 of the cavity offset test structure, the back cavity 110 of the MEMS device is formed synchronously during the formation of the back cavity 110 of the cavity offset test structure, and the back plate layer 150 of the MEMS device is formed synchronously during the formation of the back plate layer 150 of the cavity offset test structure, etc., the cavity offset of the cavity offset test is basically equivalent to the cavity offset of the MEMS device. The cavity offset of the MEMS device can be obtained by monitoring the cavity offset of the cavity offset test structure.

[0042] For example, such as Figure 1A As shown, at least four capacitance test structures 120 are arranged circumferentially around the back cavity 110. Specifically, at least two capacitance test structures 120, such as a first capacitance test structure and a third capacitance test structure, are located in a first direction, which is the direction in which the center point of the test diaphragm of the first capacitance test structure extends towards the center point of the cavity of the back cavity. At least two capacitance test structures 120, such as a second capacitance test structure and a fourth capacitance test structure, are located in a second direction, which is the direction in which the center point of the test diaphragm of the second capacitance test structure extends towards the center point of the cavity of the back cavity. The second direction is perpendicular to the first direction, so that the back cavity offset in the first and second directions can be monitored simultaneously. For example, if the first direction is vertical and the second direction is horizontal, the capacitance test structures can monitor the offset of the back cavity in both the horizontal and vertical directions.

[0043] Furthermore, such as Figure 1A As shown, four capacitance test structures 120 are provided, specifically including a first capacitance test structure, a second capacitance test structure, a third capacitance test structure, and a fourth capacitance test structure. The test diaphragms of the first and third capacitance test structures are spaced apart in a first direction, while the test diaphragms of the second and fourth capacitance test structures are spaced apart in a second direction. This allows for back cavity offset monitoring in four directions (up, down, left, and right) of the back cavity, improving monitoring accuracy.

[0044] like Figure 2As shown, the capacitance test structure 120 includes a test diaphragm 121, a first pad 122, and a second pad 123. The first pad 122 is connected to one end of the test diaphragm 121, and the second pad 123 is connected to the substrate 100 corresponding to the test diaphragm 121. Figure 1A As shown, the test diaphragm 121 is partially located outside the back cavity 110, and the projection of the test diaphragm 121 on the substrate 100 overlaps with the projection of the back cavity 110 on the substrate 100. That is, a part of the test diaphragm 121 is on the side of the back cavity 110 away from the first surface 101. This part of the test diaphragm 121 is called the first part, and the other part of the test diaphragm 121 is on the side of the back cavity close to the first surface 101. This part of the test diaphragm is called the second part. Thus, the capacitance between the substrate and the test diaphragm can be determined by the actual distance between the first part and the edge of the back cavity it is close to, as well as the capacitance of the test diaphragm connected to the first pad. Conversely, by obtaining the capacitance between the test diaphragm and the substrate through the first pad and the second pad, the actual distance can be obtained through the capacitance. By comparing this actual distance with the target distance, the offset of the back cavity can be obtained. How to determine the offset of the back cavity through the capacitance between the test diaphragm and the substrate will be described in detail in the subsequent back cavity offset test method.

[0045] For example, the process for forming the back cavity offset test structure and MEMS device includes: growth of a first sacrificial layer and photolithography etching; growth of a diaphragm (test diaphragm and MEMS device diaphragm) and photolithography etching; growth of a second sacrificial layer and photolithography etching; growth of a third sacrificial layer and photolithography etching; growth of a backplate layer and photolithography etching; thinning of the back side of the substrate (i.e., the second surface); etching of the back side of the substrate to form a back cavity penetrating the substrate from the back side of the substrate; and sacrificial layer release process, etc., thereby forming a back cavity such as... Figure 2 and Figure 3 The back cavity offset test structure and MEMS device are shown.

[0046] like Figure 2 As shown, a first isolation layer 103 is formed on the substrate 100. The material of the first isolation layer includes, but is not limited to, silicon nitride. A test diaphragm 121 is formed on the first isolation layer. Exemplarily, the test diaphragm 121 includes a first dielectric layer 140, a conductive layer 141, and a second dielectric layer 142 stacked from bottom to top. The material of the first dielectric layer includes, but is not limited to, silicon nitride, the material of the conductive layer includes, but is not limited to, polysilicon, and the material of the second dielectric layer is the same as that of the first dielectric layer, thereby forming a sandwich structure test diaphragm. The conductive layer 141 includes a plurality of sub-conductive layers spaced apart. The sub-conductive layers are isolated from each other by a second isolation layer 143. The material of the isolation layer includes, but is not limited to, silicon dioxide.

[0047] A backplate layer 150 is formed above the test diaphragm 121. The backplate layer 150 is suspended above the test diaphragm 121. A cavity 151 is formed between the backplate layer 150 and the test diaphragm 121. Multiple acoustic holes 152 are formed in the backplate layer. The acoustic holes 152 can also be used as release holes for the release of the relevant sacrificial layer during the manufacturing process of the back cavity offset test structure.

[0048] In some examples, the shape of the projection of the test diaphragm onto the substrate includes a rectangle or a square.

[0049] In some examples, when the back cavity is not offset, the distance from the point where each test diaphragm intersects the edge of the back cavity to the outer edge of the test diaphragm is equal to its distance to the inner edge of the test diaphragm. Here, the inner edge of the test diaphragm refers to the edge of the test diaphragm located on one side of the back cavity edge and close to the center of the back cavity in the direction extending from the center of the test diaphragm to the center of the back cavity; the outer edge of the test diaphragm refers to the edge of the test diaphragm located on the other side of the back cavity edge and away from the center of the back cavity in the direction extending from the center of the test diaphragm to the center of the back cavity.

[0050] Specifically, such as Figure 1A As shown, the edge of the cavity is located at the exact center of the rectangle or square. Therefore, the predetermined value (i.e., standard value) of the capacitance between the diaphragm and the substrate can be determined by the width of the rectangle or square and half its length. During cavity offset monitoring, the distance between the diaphragm and the substrate is determined by testing the capacitance. Comparing this distance to half the length of the rectangle or square yields the cavity offset. In some examples, the width of the rectangle or square is greater than 20µm, for example, 20µm, 40µm, or 60µm, and the length is greater than 20µm, for example, 20µm, 40µm, or 60µm.

[0051] In the exemplary back cavity offset test structure, the test diaphragm 121 and the MEMS device diaphragm 131 are independent of each other, i.e., not connected, for example, isolated by a second isolation layer 143. Since the test diaphragm and the MEMS device diaphragm are formed synchronously during fabrication, their film compositions are identical; that is, the MEMS device diaphragm 131 is also a sandwich structure. The MEMS device diaphragm 131 includes a first dielectric layer 140, a conductive layer 141, and a second dielectric layer 142, and the MEMS device diaphragm and the test diaphragm are fixed by the first dielectric layer 140 and the second dielectric layer 142. It is worth noting that although the test diaphragm and the MEMS device diaphragm are formed synchronously, different mask layers are used during patterning, resulting in a structure as shown in the diagram. Figure 2 and Figure 3The graphs shown are of different test diaphragms and MEMS device diaphragms 131.

[0052] For example, the substrate includes multiple lithographic exposure areas (shots), which are the exposure areas covered in one exposure of the lithography machine. They are usually rectangular. At least one back cavity offset test structure is set on each lithographic exposure area (shot) so that the back cavity offset is monitored during one lithography operation.

[0053] This concludes the description of the key structures of the back cavity offset test structure for the MEMS device of this application. Other structures may also be included in the complete back cavity offset test structure for the MEMS device, which will not be elaborated here.

[0054] The back cavity offset test structure and test method of the MEMS device and the semiconductor device of this application embodiment are provided by setting at least four capacitance test structures in the circumferential direction of the back cavity. Each capacitance test structure includes a test diaphragm, a first pad and a second pad. The first pad is connected to one end of the test diaphragm and the second pad is connected to the substrate corresponding to the test diaphragm. The offset of the back cavity is monitored by testing the capacitance between the diaphragm and the substrate. This can avoid the human error of visual measurement in related technologies, improve the reliability of the product, and save time and manpower, thereby improving production efficiency.

[0055] Example 2 This application also provides a method for testing the back cavity offset of a MEMS device. This method can be based on the back cavity offset test structure of the MEMS device in the aforementioned embodiment one, such as... Figure 4 As shown, the back cavity offset testing method for MEMS devices according to an embodiment of the present invention includes the following steps: Step S41, providing a substrate, the substrate including a device region and a back cavity offset test region, the device region having a MEMS device formed thereon, and the back cavity offset test region having a back cavity offset test structure as described in Embodiment 1; Step S42: Measure the capacitance value between the test diaphragm and the substrate using the first and second pads on the capacitance test structure. Step S43: The actual distance between the outer edge of the test diaphragm and the edge of the back cavity it is close to, based on the capacitance value; Step S44: Determine the offset of the back cavity based on the actual distance and the target distance. If the offset exceeds a predetermined range, mark the MEMS device as abnormal.

[0056] For example, measuring the capacitance value between the test diaphragm and the substrate using the first and second pads on the capacitance test structure includes: Configure the probes of the capacitance tester, the probes including a first tip and a second tip; The first tip is connected to the first pad on the capacitor test structure, and the second tip is connected to the second pad on the capacitor test structure; The capacitance value is obtained by the capacitance testing instrument in the capacitance testing machine.

[0057] The back cavity offset testing method for MEMS devices in this application embodiment obtains the capacitance value through the first pad and the second pad. For example, the capacitance value of a capacitance test structure in the first direction is obtained according to the formula C=ε.S / d, where ε represents the dielectric constant; S represents the area of ​​the substrate and the test diaphragm facing each other; and d represents the vertical distance between the substrate and the test diaphragm. The capacitance value is related to the area S of the substrate and the test diaphragm facing each other, and the area S of the substrate and the test diaphragm facing each other is equal to the product of the width of the test diaphragm and the distance between the outer edge of the test diaphragm and the edge of the back cavity it is close to.

[0058] like Figure 1B and Figure 1CAs shown, C1 = ε.S / d = ε.wd1 / d, where w represents the width of the test diaphragm, d1 represents the distance between the outer edge of the test diaphragm and the edge of the back cavity when the back cavity has not shifted (i.e., d1 is the target distance), and d represents the vertical distance between the substrate and the test diaphragm (i.e., the thickness of the dielectric material beneath the test diaphragm). The width direction of the test diaphragm is perpendicular to the extension direction of d1. Each test structure also includes an inherent capacitor, which includes an upper electrode and a lower electrode, and a dielectric layer located between the upper and lower electrodes. The upper electrode is electrically connected to its adjacent test diaphragm, and a first pad is disposed on the upper electrode. The lower electrode is the substrate portion opposite to the upper electrode. The dielectric layer of the inherent capacitor and the dielectric layer beneath the diaphragm can use the same material or different materials, such as two stacked silicon nitride layers or a stack of silicon nitride, silicon oxide, and silicon nitride layers. The inherent capacitor is located on the outside of the test diaphragm. The inherent capacitance is defined as C0, then C0 = ε.S / d = ε.w0d0 / d, where w0 is the width of the upper plate of the inherent capacitor. The upper plate has one end away from the test diaphragm and the other end connected to the test diaphragm. The distance between the two ends is d0, and the extension direction of d0 is perpendicular to the width direction of the upper plate of the inherent capacitor. C3 = ε.S / d = ε.wd2 / d, where d2 represents the actual distance between the outer edge of the test diaphragm and the edge of the back cavity it is close to when the back cavity is offset. Thus, the measured actual capacitance value C3 = C2 + C0, then d2 = (C3 - C0) / (ε.w) × d. By comparing d2 with the target distance d1, the offset of the back cavity can be determined, that is, the offset is the difference between d2 and d1. If the difference between d2 and d1 exceeds the predetermined range, it means that the offset of the back cavity exceeds the specification requirements, and the MEMS device is marked as abnormal.

[0059] MEMS devices that fail the test are recorded to form ink dot patterns that conform to the deep silicon etching process. Then, MEMS chips are screened based on the ink dot patterns, and defective MEMS devices are removed to ensure product reliability.

[0060] It is worth mentioning that when the sacrificial layer between the substrate and the test diaphragm is not released, the sacrificial layer becomes the dielectric layer between the test diaphragm and the substrate. Furthermore, if the dielectric layer of this capacitor structure is a stacked structure, such as a silicon nitride layer, a silicon oxide layer (which can be the sacrificial layer), and a silicon nitride layer, and a first isolation layer, such as a silicon nitride layer, is formed above the substrate, this first isolation layer also serves as the dielectric layer between the test diaphragm and the substrate, then the capacitor is a series capacitor. The relationship between the total capacitance and the individual layers of the capacitor structure is: 1 / C Total =1 / C LSN +1 / C Oxide +1 / C LSN C LSN、 C Oxide、C LSN The calculation can be based on the relative permittivity and thickness of each of the three dielectric layers, as well as the face-to-face area between the test diaphragm and the substrate.

[0061] The back cavity offset testing method for MEMS devices according to embodiments of this application tests the back cavity offset using a back cavity offset testing structure formed on the same substrate as the MEMS device. The back cavity offset testing structure consists of at least four capacitance testing structures spaced circumferentially in the back cavity. Each capacitance testing structure includes a test diaphragm, a first pad, and a second pad. The first pad is connected to one end of the test diaphragm, and the second pad is connected to the substrate corresponding to the test diaphragm. The capacitance value between the test diaphragm and the substrate of the corresponding capacitance testing structure is obtained through the first and second pads. Then, based on the correlation between capacitance and area, the actual distance between the outer edge of the test diaphragm and the edge of the back cavity it is close to is obtained. The actual distance is compared with the target distance to determine the offset of the back cavity, thereby monitoring whether the offset of the back cavity meets the requirements. This method can improve product reliability while saving production time and manpower.

[0062] Example 3 This application also provides a semiconductor device, which includes a MEMS device and a back cavity offset test structure as described above. The MEMS device and the back cavity offset test structure are formed on the same substrate. Based on the back cavity offset test structure, the offset of the back cavity during the manufacturing process of the MEMS device can be monitored, thereby improving the reliability of the MEMS device and saving production time and manpower.

[0063] Although several embodiments have been described herein, it should be understood that many other modifications and embodiments will arise in the mind of those skilled in the art, all of which will fall within the spirit and scope of the concept disclosed herein. More specifically, various modifications and changes may be made in terms of the arrangement and / or components of the subject matter within the scope of this disclosure, the drawings, and the appended claims. In addition to modifications and changes in the components and / or arrangement, the use of alternative methods will also be obvious to those skilled in the art.

Claims

1. A back cavity offset testing structure for a MEMS device, characterized in that, The test structure includes: A substrate, the substrate comprising a first surface and a second surface opposite to the first surface; A back cavity extends through the second surface of the substrate; At least four capacitance test structures are provided, each of which includes a test diaphragm, a first pad, and a second pad. The first pad is connected to one end of the test diaphragm, and the second pad is connected to the substrate corresponding to the test diaphragm. The test diaphragm is located outside the back cavity, and the projection of the test diaphragm on the substrate overlaps with the projection of the back cavity on the substrate. The at least four capacitance test structures are arranged at circumferential intervals along the back cavity, and each capacitance test structure is independent of the others.

2. The back cavity offset test structure as described in claim 1, characterized in that, When the back cavity is not offset, the distance from the point where each test diaphragm intersects with the edge of the back cavity to the outer edge of the test diaphragm is equal to its distance to the inner edge of the test diaphragm.

3. The back cavity offset test structure as described in claim 1, characterized in that, The capacitance test structure includes a first capacitance test structure, a second capacitance test structure, a third capacitance test structure, and a fourth capacitance test structure. The test diaphragms of the first capacitance test structure and the third capacitance test structure are spaced apart in a first direction, and the test diaphragms of the second capacitance test structure and the fourth capacitance test structure are spaced apart in a second direction. The first direction is the direction in which the center point of the test diaphragm of the first capacitance test structure extends towards the center point of the cavity of the back cavity, and the second direction is the direction in which the center point of the test diaphragm of the second capacitance test structure extends towards the center point of the cavity of the back cavity, and the second direction is perpendicular to the first direction.

4. The back cavity offset test structure as described in claim 1, characterized in that, The shape of the projection of the test diaphragm onto the substrate can be rectangular or square.

5. The back cavity offset test structure as described in claim 1, characterized in that, The substrate includes multiple photolithographic exposure areas, and at least one of the back cavity offset test structures is provided in each of the photolithographic exposure areas.

6. The back cavity offset test structure as described in claim 1, characterized in that, The test diaphragm includes a first dielectric layer, a conductive layer, and a second dielectric layer stacked from bottom to top, wherein one end of the conductive layer is connected to the first pad.

7. The back cavity offset test structure as described in claim 6, characterized in that, A MEMS device diaphragm is also formed on the substrate. The MEMS device diaphragm is independent of the test diaphragm and has the same composition structure as the test diaphragm. The MEMS device diaphragm and the test diaphragm are fixed by the first dielectric layer and the second dielectric layer.

8. A method for testing the back cavity offset of a MEMS device, characterized in that, The method includes: A substrate is provided, the substrate including a device region and a back cavity offset test region, the device region having a MEMS device formed thereon, and the back cavity offset test region having a back cavity offset test structure as described in any one of claims 1-7; The capacitance value between the test diaphragm and the substrate is measured using the first and second pads on the capacitance test structure. The actual distance between the outer edge of the test diaphragm and the edge of the back cavity it is close to is obtained by using the capacitance value; The offset of the back cavity is determined based on the actual distance and the target distance. If the offset exceeds a predetermined range, the MEMS device is marked as abnormal.

9. The back cavity offset testing method as described in claim 8, characterized in that, The capacitance value between the test diaphragm and the substrate is measured through the first pad and the second pad, including: Configure the probes of the capacitance tester, the probes including a first tip and a second tip; Connect the first pin tip to the first pad, and connect the second pin tip to the second pad; The capacitance value is obtained by the capacitance testing instrument in the capacitance testing machine.

10. A semiconductor device, characterized in that, The semiconductor device includes a MEMS device and the back cavity offset test structure according to any one of claims 1-7, wherein the MEMS device and the back cavity offset test structure are formed on the same substrate.

Images