Face-to-face bonding wafer packaging method and packaging structure

Abstract

This invention provides a method and structure for packaging face-to-face bonded wafers. A first alignment mark with a special pattern is pre-set on the first metal layer of the first wafer. This first alignment mark is aligned using a non-visual direct identification method, simultaneously forming a through-silicon via (TSV) and a first via serving as a second alignment mark. The second alignment mark is directly identified on the process operation surface of the first wafer in subsequent processes. This ensures that each etching step in the subsequent process involves configuring at least one independent alignment mark on the mask for alignment, overcoming the limitation of non-visual direct identification alignment being unusable when the metal layer is blocked. Through the coordinated alignment, mutual complementarity, and end-to-end adaptation of the two marks, the entire subsequent process stage after bonding is covered, solving the industry problem of lacking dedicated photolithography patterns for face-to-face bonded wafers. This improves photolithography misalignment defects, effectively enhances process stability and chip electrical interconnect reliability, and meets the industrial production needs of high-precision MEMS chip 3D integration.

Description

Technical Field

[0001] This invention relates to the field of semiconductor packaging, and more particularly to a face-to-face bonding wafer packaging method and packaging structure. Background Technology

[0002] In microelectromechanical systems (MEMS) wafer-to-wafer face-to-face bonding, the active surfaces of two wafers are bonded together to achieve heterogeneous chip integration or three-dimensional stacking, thereby improving chip integration density and performance. The incoming material alignment point, as the core reference for initial wafer positioning, is typically preset in a non-active region at the wafer edge or at a specific location on the surface for precise alignment of the two wafers before bonding, ensuring the alignment accuracy of circuits and microstructures after bonding. However, with face-to-face bonding, the active surfaces of the two wafers are tightly bonded, and the active surface of one wafer is covered by the other. This makes it impossible for the original incoming material alignment point to be observed at the packaging end of the incoming wafer, preventing subsequent positioning and calibration using the original alignment point. Figure 1 This is a schematic diagram of face-to-face bonding of incoming materials without alignment marks. For example... Figure 1 As shown, the upper wafer is the first wafer 101, and the lower wafer is the second wafer 102. The bonding composite structure 103 formed by bonding the active surfaces of the two wafers lacks alignment marks. This makes it impossible to determine the precise position of the first wafer 101, and also prevents the completion of post-bonding positioning calibration, process connection, and other subsequent processes. Consequently, the entire production process stalls, making it impossible to continue operations. This not only affects production efficiency but may also cause wafer loss and increase production costs. Subsequent processes cannot be performed.

[0003] At this point, the alignment marks left in the subsequent processing of the incoming wafers become crucial. Figure 2 This is a schematic diagram of wafer-to-wafer bonding with alignment marks etched on the back side of the second wafer, using existing technology. (Example:) Figure 2 As shown, the upper wafer is the first wafer 201, the lower wafer is the second wafer 202, and the active surfaces of the two wafers are bonded to form a bonding composite structure 203. The back side of the lower second wafer 202 is etched with special markings 204, which can be used for double-sided alignment after face-to-face bonding of the wafers. Figure 3 This is a schematic diagram showing the location of the observation camera on the back side of the first wafer in the prior art. (Example) Figure 3As shown, three observation cameras 205 are disposed on the back side of the first wafer 201. The three observation cameras 205 are evenly distributed along the circumference of the first wafer 201, and are respectively observation camera A, observation camera B, and observation camera C. However, the above-mentioned method of etching alignment marks on the back side of the wafer has limitations because the detection camera 205 on the back side of the first wafer 201 cannot directly penetrate the face-to-face bonded composite structure 203 to identify the special marks 204 on the back side of the second wafer 202. Alignment needs to be indirectly associated through multiple systems. The positions of the alignment marks are fixed and few, and the exposure accuracy deviation is generally >5μm, which poses a risk of alignment misalignment and cannot meet the requirements of accurate positioning in many cases.

[0004] Therefore, providing a face-to-face bonding wafer packaging method and structure that enables precise positioning during the face-to-face bonding process is of great significance for improving production efficiency and reducing production costs. Summary of the Invention

[0005] The technical problem to be solved by the present invention is to enable precise positioning in the wafer face-to-face bonding process, and to provide a method and structure for packaging face-to-face bonded incoming wafers.

[0006] To address the aforementioned problems, this invention provides a face-to-face bonding wafer packaging method, comprising: providing an initial bonding structure, the initial bonding structure including a first wafer and a second wafer, the active surfaces of the first wafer and the second wafer being face-to-face bonded, and a first alignment mark being present in a first metal layer of the first wafer, the first metal layer being the metal layer closest to the back side of the first wafer; achieving alignment by penetrating the back side of the first wafer to identify the first alignment mark through a non-visual direct identification method; simultaneously forming through-silicon vias and a first via corresponding to the first alignment mark on the back side of the first wafer, the first via serving as a second alignment mark; and achieving alignment by directly identifying the second alignment mark during subsequent processes on the back side of the first wafer.

[0007] In some embodiments, before the first wafer and the second wafer are bonded, the first alignment mark is formed simultaneously in the front-end process when forming the first metal layer of the first wafer.

[0008] In some embodiments, the first alignment mark is an identifiable specific pattern formed on the first metal layer.

[0009] In some embodiments, the first alignment marker is a positive or negative graphic.

[0010] In some embodiments, the shape of the first alignment mark is a positive graphic.

[0011] In some embodiments, there are multiple first alignment marks, which are arranged in an array on the wafer.

[0012] In some embodiments, the size of the first alignment mark ranges from 100 to 300 μm.

[0013] In some embodiments, the minimum width of the metal region of the first alignment mark is greater than 30 μm.

[0014] In some embodiments, the bottom of the second alignment mark is connected to the first alignment mark.

[0015] In some embodiments, the size of the second alignment mark ranges from 60 to 150 μm.

[0016] In some embodiments, the minimum width of the cutout area of ​​the second alignment mark is greater than 18 μm.

[0017] In some embodiments, the cross-sectional shape of the second alignment mark is the same as the graphic shape of the first alignment mark.

[0018] In some embodiments, the axis of the second alignment mark passes through the center point of the first alignment mark.

[0019] In some embodiments, the second alignment mark corresponds one-to-one with the first alignment mark.

[0020] In some embodiments, the step of performing subsequent processes on the back side of the first wafer includes: depositing a dielectric layer on the back side of the first wafer and aligning it by directly identifying the second alignment mark; forming a patterned photoresist mask layer on the dielectric layer; forming a patterned dielectric layer based on the photoresist mask layer; and exposing the underlying metal structure by opening a window at the bottom of the through-silicon via.

[0021] In some embodiments, during the step of depositing a dielectric layer on the back side of the first wafer, the dielectric layer is also deposited on the inner wall of the second alignment mark.

[0022] In some embodiments, the step of forming a patterned photoresist mask layer on the dielectric layer, wherein the second alignment mark is masked by the photoresist mask layer; and the step of forming a patterned dielectric layer based on the photoresist mask layer and exposing the underlying metal structure by opening a window at the bottom of the through-silicon via further includes removing the residual photoresist mask layer to re-expose the second alignment mark.

[0023] In some embodiments, performing subsequent process steps on the back side of the first wafer includes: aligning by directly identifying the second alignment mark, forming a redistribution layer on the surface of the patterned dielectric layer and re-exposing the second alignment mark, the redistribution layer being connected to the underlying metal structure.

[0024] In some embodiments, the step of achieving alignment by directly identifying the second alignment mark, forming a redistribution layer on the surface of the patterned dielectric layer, and re-exposing the second alignment mark specifically includes: forming a metal seed layer on the surface of the patterned dielectric layer; achieving alignment by directly identifying the second alignment mark, forming a patterned wiring photoresist layer on the surface of the metal seed layer; filling the area of ​​the wiring photoresist layer not covered by photoresist with metal to form a redistribution layer, wherein the conductive lines of the redistribution layer are connected to the underlying metal structure.

[0025] In some embodiments, the step of performing subsequent processes on the back side of the first wafer includes: achieving alignment by directly identifying the second alignment mark, and forming a composite structure of a patterned protective layer and solder balls on the surface of the redistribution layer.

[0026] In some embodiments, the step of forming a composite structure of a patterned protective layer and solder balls on the surface of the redistribution layer by directly identifying the second alignment mark to achieve alignment further includes: forming a protective layer on the surface of the redistribution layer; achieving alignment by directly identifying the second alignment mark to form a patterned protective layer, the patterned protective layer including pad openings; and placing solder balls in the pad opening area to form a composite structure of the patterned protective layer and solder balls.

[0027] To address the aforementioned issues, this invention also provides a face-to-face bonded in-process wafer packaging structure, comprising an in-process wafer and a second wafer, wherein the first wafer and the second wafer are bonded face-to-face with their active surfaces facing each other. The first wafer includes: a first alignment mark located on a first metal layer of the first wafer, the first metal layer being the native metal layer closest to the back surface of the first wafer; a through-silicon via (TSV) extending from the back surface of the first wafer to a lower metal structure therein and electrically connected to the lower metal structure; and a second alignment mark formed synchronously with the via of the TSV, the second alignment mark extending from the back surface of the first wafer to above the first alignment mark.

[0028] In some embodiments, the second alignment mark extends from the back side of the first wafer to connect with the upper surface of the first alignment mark.

[0029] In some embodiments, the inner wall of the second alignment mark is covered with a patterned dielectric layer.

[0030] In some embodiments, a redistribution layer is formed on the patterned dielectric layer, and the redistribution layer is electrically connected to the through-silicon via.

[0031] In some embodiments, the surfaces of the redistribution layer and the patterned dielectric layer are covered with a patterned protective layer, the protective layer having an opening in the pad area of ​​the redistribution layer, a solder ball being disposed within the opening, and the solder ball being electrically connected to the redistribution layer.

[0032] In some embodiments, the first alignment mark is an identifiable specific pattern formed on the first metal layer.

[0033] In some embodiments, the cross-sectional shape of the first alignment mark is a positive or negative shape.

[0034] In some embodiments, there are multiple first alignment marks, which are arranged in an array on the first wafer.

[0035] In some embodiments, the second alignment mark is a through hole with a specific cross-sectional shape.

[0036] In some embodiments, the cross-sectional shape of the second alignment mark is the same as the graphic shape of the first alignment mark.

[0037] In some embodiments, the second alignment mark corresponds one-to-one with the first alignment mark.

[0038] The above technical solution involves pre-setting a first alignment mark with a special pattern on the first metal layer of the first wafer. A through-silicon via (TSV) and a second TSV serving as the second alignment mark are simultaneously formed by aligning the first alignment mark using a non-visual direct identification method. The second alignment mark is then directly identified on the process operation surface of the first wafer during subsequent processes. This ensures that each etching step in the later stages of the process is equipped with at least one independent alignment mark for alignment, overcoming the limitation of non-visual direct identification alignment being unusable when the metal layer is obscured. Through the coordinated alignment, mutual complementarity, and end-to-end adaptation of these two types of marks, the entire post-bonding process is covered, solving the industry problem of face-to-face incoming wafers lacking dedicated photolithography patterns. This improves photolithography misalignment defects, effectively enhances process stability and chip electrical interconnect reliability, and meets the industrial production needs of high-precision MEMS chip 3D integration.

[0039] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit the invention. Techniques, methods, and apparatus known to those skilled in the art may not be discussed in detail, but where appropriate, such techniques, methods, and apparatus should be considered part of the specification. Attached Figure Description

[0040] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0041] Figure 1 This is a schematic diagram of face-to-face bonding of wafers without alignment marks; Figure 2 This is a schematic diagram of wafer-to-wafer bonding with alignment marks etched on the back side of the second wafer in the prior art; Figure 3 This is a schematic diagram of the location of the observation camera on the back side of the first wafer in the prior art; Figure 4 This is a flowchart of the face-to-face bonding wafer packaging method provided in the first embodiment of the present invention; Figure 5 This is a flowchart of the subsequent processes of the first wafer after bonding, provided in the first embodiment of the present invention; Figure 6 This is a schematic diagram of the device structure formed by the step of forming a first alignment mark in the first metal layer of the first wafer according to the first embodiment of the present invention; Figure 7 This is a cross-sectional schematic diagram of the first alignment mark provided in the first embodiment of the present invention; Figure 8 This is a schematic diagram of the device structure formed by the steps of forming a silicon through-hole and a second alignment mark on the back side of the first wafer according to the first embodiment of the present invention. Figure 9 This is a top view schematic diagram of the second alignment mark provided in the first embodiment of the present invention; Figure 10 This is a schematic diagram of the device structure formed by the step of forming a patterned photoresist mask layer on a dielectric layer according to the first embodiment of the present invention; Figure 11 This is a schematic diagram of the device structure formed by the steps of forming a patterned dielectric layer and exposing the underlying metal structure by opening a window at the bottom of the through-silicon via according to the first embodiment of the present invention. Figure 12 This is a schematic diagram of the device structure formed by the step of forming a redistribution layer on the surface of a patterned dielectric layer and exposing a second alignment mark, as provided in the first embodiment of the present invention. Figure 13 This is a schematic diagram of the device structure formed by the steps of forming a patterned protective layer and solder ball composite structure on the surface of the redistribution layer according to the first embodiment of the present invention. Figure 14This is a schematic diagram of the distribution of the first alignment mark on the back side of the first wafer provided in the first embodiment of the present invention; Figure 15 This is a top view schematic diagram of the first alignment mark provided in the second embodiment of the present invention; Figure 16 This is a top view schematic diagram of the first alignment mark provided in the third embodiment of the present invention; Figures 17A-17F This is a top view of the first alignment mark and the second alignment mark provided in the fourth embodiment of the present invention.

[0042] Explanation of reference numerals in the attached figures: 101, 201 – First wafer; 102, 202 – Second wafer; 103, 203 — bonded composite structure; 204 - Special marking; 205 — Camera inspection; 10 – Second wafer; 11—First wafer; 12—Bonded composite structure; 130—First metal layer; 13, 23, 33 — First alignment markers; 13' — First alignment mark projection; 14—Lower metal structure; 15—Second alignment marker; 16—Through Silicon Via; 161—Through Silicon Via; 17—Dielectric layer; 171—Graphical media layer; 18 — Rewiring layer; 180 — Photoresist mask layer; 19—A composite structure of a patterned protective layer and solder balls; 191—Graphical protective layer; 192—Welding ball. Detailed Implementation

[0043] The technical solutions in the embodiments of the present invention will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of them. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0044] Figure 4This is a flowchart of the face-to-face bonding wafer packaging method provided in the first embodiment of the present invention. Figure 4 As shown, the face-to-face bonding wafer packaging method includes: Step S1, providing an initial bonding structure, the initial bonding structure including a first wafer and a second wafer, the active surfaces of the first wafer and the second wafer being face-to-face bonded, and a first alignment mark being present on a first metal layer of the first wafer, the first metal layer being the metal layer closest to the back side of the first wafer; Step S2, achieving alignment by penetrating the back side of the first wafer to identify the first alignment mark through a non-visual direct identification method; Step S3, simultaneously forming silicon vias and a first via corresponding to the first alignment mark on the back side of the first wafer, the first via serving as a second alignment mark; Step S4, achieving alignment by directly identifying the second alignment mark when performing subsequent processes on the back side of the first wafer. This face-to-face bonding wafer packaging method ensures photolithographic accuracy and improves photolithographic misalignment by providing photolithographic marks in every process requiring photolithographic alignment.

[0045] The following is combined Figure 6 , Figure 8 , Figure 10 , Figure 11 , Figure 12 , Figure 13 The steps are explained in detail, including: Figure 6 This is a schematic diagram of the device structure formed by the step of forming a first alignment mark in the first metal layer of the first wafer according to the first embodiment of the present invention; Figure 8 This is a schematic diagram of the device structure formed by the steps of forming a silicon through-hole and a second alignment mark on the back side of the first wafer according to the first embodiment of the present invention. Figure 10 This is a schematic diagram of the device structure formed by the step of forming a patterned photoresist mask layer on a dielectric layer according to the first embodiment of the present invention; Figure 11 This is a schematic diagram of the device structure formed by the steps of forming a patterned dielectric layer and exposing the underlying metal structure by opening a window at the bottom of the through-silicon via according to the first embodiment of the present invention. Figure 12 This is a schematic diagram of the device structure formed by the step of forming a redistribution layer on the surface of a patterned dielectric layer and exposing a second alignment mark, as provided in the first embodiment of the present invention. Figure 13 This is a schematic diagram of a device structure in the first embodiment of the present invention, which has a composite structure of a patterned protective layer and solder balls formed on the surface of the redistribution layer.

[0046] refer to Figure 6In step S1, an initial bonding structure is provided, the initial bonding structure including a first wafer 11 and a second wafer 10, the active surfaces of the first wafer 11 and the second wafer 10 are bonded face to face, and a first alignment mark 13 is provided on the first metal layer 130 of the first wafer 11, the first metal layer 130 being the native metal layer closest to the back side of the first wafer 11.

[0047] The first metal layer 130 is formed in the front-end process before the first wafer 11 and the second wafer 10 are bonded, and the first alignment mark 13 is formed at the same time.

[0048] Figure 6 The diagram shows the structure after the first wafer 11 and the second wafer 10 are bonded face-to-face. Figure 6 As shown, the upper wafer is the first wafer 11, and the lower wafer is the second wafer 10. The active surfaces of the first wafer 11 and the second wafer 10 are bonded together to form a bonding composite structure 12. The bonding composite structure 12 includes a bonding surface and two adjacent active surface layers of the wafers, forming an integrated, dense interconnect structure after face-to-face bonding of the two wafers. The surface of the first wafer 11 furthest from the bonding composite structure 12 is the back surface of the first wafer 11. Figure 6 In this process, the back side of the first wafer 11 is the upper surface of the first wafer 11, and this back side is the process operation surface for all subsequent processes of the first wafer 11. Figure 6 The back side of the first wafer 11 is a silicon substrate, and subsequent processes are performed on the silicon substrate during packaging.

[0049] The native metal layer is a metal interconnect structure formed in the front-end process before bonding of the first wafer 11. The native metal layer is located near the device region of the active surface of the first wafer 11. The first metal layer 130 is the first native metal layer formed on the silicon substrate of the first wafer 11 in the front-end process. The first alignment mark 13 is a specific identifiable pattern formed on the first metal layer 130. In a specific process, the first alignment mark 13 is formed simultaneously when the first metal layer 130 is patterned.

[0050] The first alignment mark 13 has a specific graphic shape that can be clearly distinguished from the actual process graphic. In a specific embodiment, the graphic outline of the first alignment mark 13 includes clear straight edges, avoiding excessively sharp corner structures, ensuring that the edges are flat after the process is formed, which facilitates feature extraction by the equipment; at the same time, it has feature redundancy, so that local process deviations or media coverage do not affect the overall recognition, thus improving process robustness.

[0051] The first alignment mark 13 can be either a positive or a negative graphic. A positive graphic refers to a graphic pattern in which the metal is retained, while a negative graphic refers to a graphic pattern in which the metal is removed. Generally, using a positive graphic can achieve a higher recognition rate and facilitate alignment.

[0052] Figure 7 This is a top view schematic diagram of the first alignment mark provided in the first embodiment of the present invention. (See diagram below.) Figure 7 As shown, the pattern of the first alignment mark 13 is an octagonal star, including a central square area and four protruding areas. Each protruding area has an inwardly recessed isosceles triangular notch at its outer end. The octagonal star has eight points and rotational symmetry, providing multi-dimensional edge features and multi-dimensional alignment references in the horizontal, vertical, and 45° oblique directions, exhibiting high recognition robustness and strong resistance to process interference.

[0053] The shape of the first alignment mark 13 is a positive graphic. Specifically, the metal of the pattern of the first alignment mark 13 is retained, and the metal around the pattern is removed.

[0054] The steps for forming the first alignment mark 13 in the front-end process include: after depositing a metal layer on the first wafer 11, when coating photoresist and forming the patterned first metal layer 130 through exposure and development processes, the patterned area of ​​the first alignment mark 13 is defined simultaneously. Specifically, the photoresist in the patterned area is retained as a protective mask for subsequent etching, while the photoresist around the pattern is completely removed to expose the underlying metal layer; a dry etching process is used to directionally etch the surrounding metal layer without photoresist protection to completely remove it; finally, the remaining photoresist is stripped off to obtain an alignment mark pattern composed only of metal, with a regular structure surrounded by an insulating dielectric layer.

[0055] Figure 14 This is a schematic diagram showing the distribution of the first alignment mark on the back side of the first wafer according to the first embodiment of the present invention. Figure 14As shown, a plurality of first alignment marks 13 are formed on the first wafer 11, and the first alignment marks 13 are arranged in an array on the first wafer 11. Specifically, in the effective process area of ​​the first wafer 11, the first alignment marks 13 are evenly distributed in three rows and five columns. Each chip unit is provided with an octagonal star-shaped first alignment mark 13. The first alignment marks 13 correspond one-to-one with the chip units, and the overall layout is equally spaced and symmetrical, completely covering the core processing area of ​​the first wafer 11. Furthermore, the first alignment marks 13 are formed in the non-functional area of ​​each chip unit, such as the edge of the chip unit or next to the dicing slot. Each chip unit is equipped with a dedicated alignment reference, which can achieve wafer-level full-area accurate alignment and avoid alignment differences between the chip units at the edge and the chip units at the center. When a first alignment mark 13 fails to identify due to process deviation, it can be switched to an adjacent first alignment mark 13 to complete the alignment, avoiding the scrapping of the entire wafer due to local marking defects, and significantly improving process yield and stability.

[0056] In some embodiments, the first alignment mark 13 may be set according to alignment requirements.

[0057] Compared to the single calibration mode of single-point marking, multiple alignment marks can effectively offset local position deviations caused by factors such as wafer warpage, process thermal stress, and mechanical deformation. By calibrating lithography parameters in multiple regions simultaneously, the uniformity of lithography across the entire wafer is greatly improved, and the problem of local lithography offset on the wafer is reduced.

[0058] Figure 15 This is a top view schematic diagram of the first alignment mark provided in the second embodiment of the present invention. (See diagram below.) Figure 15 As shown, in the second embodiment, the first alignment mark 23 is a positive shape. Furthermore, the first alignment mark 23 is cross-shaped, formed by the integral intersection of two mutually perpendicular rectangular arms of equal width, possessing fourfold rotational symmetry. It can simultaneously provide clear linear edge features in two vertical directions (e.g., X-axis and Y-axis), and its central intersection point can serve as the absolute origin, enabling synchronous calibration of translation and rotation angles, providing bidirectional alignment assurance for subsequent processes.

[0059] The size of the first alignment mark 23 ranges from 100 to 300 μm. This size defines the width and height of the first alignment mark 23, ensuring clear contrast even after infrared light penetrates the silicon substrate, and preventing blurry infrared images or failure of the device to capture images due to excessively thin linewidths. Simultaneously, the minimum width of the metal region of the first alignment mark 23 is greater than 30 μm, ensuring that the metal linewidth guarantees smooth, undeformed mark edges after metal deposition and etching.

[0060] Figure 15In this diagram, the first alignment mark 23 has a mark width of L2, a mark height of H2, and a minimum pattern width of D2. Both the mark width L2 and the mark height H2 do not exceed the mark size of the first alignment mark 23. The minimum pattern width D2 is the minimum width of the metal region of the first alignment mark 23. Specifically, L2 ∈ [100μm, 300μm], H2 ∈ [100μm, 300μm], and D2 > 30μm.

[0061] Figure 16 This is a top view schematic diagram of the first alignment mark provided in the third embodiment of the present invention. (See diagram below.) Figure 16 As shown, in the third embodiment, the pattern shape of the first alignment mark 33 is also cross-shaped. However, unlike the second embodiment, the first alignment mark 33 is a negative shape, that is, the metal of the pattern of the first alignment mark 33 is removed, while the surrounding metal is retained. Specifically, the first alignment mark 33 includes a cross-shaped hollow area (the metal is completely removed) and four equally sized square metal areas (the metal is completely retained). The four metal squares are centrally symmetrically distributed, and the whole has fourfold rotational symmetry and mirror symmetry. The negative shape ensures that process deviations in the local hollow area will not destroy the overall metal surrounding structure, providing strong fault tolerance. Even if some edges are blurred, the mark center can still be fitted.

[0062] Figure 16 In this embodiment, the side length of a single metal cube of the first alignment mark 33 is D3, the overall horizontal span of the mark is L3, and the vertical span is H3. Correspondingly, the mark width of the first alignment mark 33 is L3, and the mark height is H3. The minimum width of the metal retention area of ​​the first alignment mark 33 is D3, meaning that the minimum width D3 is the minimum width of the metal area surrounding the hollowed-out area of ​​the first alignment mark 33, which differs from the second embodiment. Similar to the second embodiment, the mark size range of the first alignment mark 33 is the same, satisfying: L3∈[100μm, 300μm], H3∈[100μm, 300μm], D3>30μm.

[0063] Figures 17A-17F This is a top view of the first alignment mark and the second alignment mark provided in the fourth embodiment of the present invention. Figures 17A-17F Six patterns are listed, all of which can serve as the graphic shape for the first alignment mark. Among them, Figure 17A It is H-shaped; Figure 17B It is a hollow H-shaped structure, consisting of two vertical rectangular areas and a horizontal rectangular area connected in the middle, forming a hollow structure similar to the letter H. Figure 17CIt is also based on the H-shaped outline, with two additional horizontal hollowings added to the middle horizontal connecting part. The whole is composed of two vertical rectangular areas and three horizontal rectangular connecting areas, forming a more layered hollow structure; Figure 17D It is in the shape of an I; Figure 17E The I-shaped hollow structure is based on a contour similar to the I shape, with an additional vertical hollowing added to the middle vertical area. The whole is composed of two upper and lower horizontal rectangular areas and the middle vertical hollowing area, which is Figure 17B the vertically rotated figure of; Figure 17F It is a multi-vertical-bar hollowed I shape, also based on the I-shaped contour, with two additional vertical hollowings added to the middle vertical area. The whole is composed of two upper and lower horizontal rectangular areas and the middle vertical hollowing area, which is Figure 17C the vertically rotated figure of. The graphic contour of each pattern contains clear straight edges and closed regions, without overly sharp corner structures, ensuring that the edges are flat after the process is formed, facilitating the extraction of device features; at the same time, each pattern has symmetry, providing multi-dimensional edge features in the horizontal and vertical directions, facilitating the synchronous calibration of the translation and rotation angles by the lithography machine. Local process deviations or medium coverage do not affect the overall recognition, improving the robustness of the manufacturing process.

[0064] Referring to step S2, alignment is achieved by directly identifying through the back of the first wafer 11 in a non-visual direct recognition manner to identify the first alignment mark 13.

[0065] Among them, the non-visual direct recognition manner refers to a manner of directly obtaining information through other technical means without relying on direct observation by the human eye. That is to say, the non-visual direct recognition manner does not require the human eye or the vision system (including the lens) to directly observe the target object, but converts non-visual signals into data or images that can be understood by people. In a specific embodiment, the non-visual direct recognition manner is an infrared detection method.

[0066] As mentioned above, the back of the first wafer 11 is a silicon substrate, the first metal layer is the native metal layer closest to the back of the first wafer 11, the first alignment mark 13 is located on the first metal layer 130, and the infrared (IR) detection method can clearly capture the first metal layer and the first alignment mark 13 inside the silicon substrate by using the penetration characteristics of infrared rays for materials such as silicon wafers, borosilicate glass, and quartz. In the Through-Silicon Via (TSV) process, the first alignment mark 13 is identified by the infrared detection method to complete alignment, and the silicon via via hole 16 is etched. In some embodiments, the non-visual direct recognition manner is X-ray recognition, which uses the attenuation difference after X-rays penetrate an object for recognition.

[0067] Metals (e.g., aluminum, copper, gold), photoresist, micromechanical structures, etc., are opaque or highly reflective to infrared light. When metal is formed on the first alignment mark 13 in the subsequent process of the first wafer 11, infrared light cannot penetrate the metal and identify the first alignment mark 13. Therefore, forming the second alignment mark 15 is of great significance.

[0068] refer to Figure 8 In step S3, a silicon via 16 and a first via corresponding to the first alignment mark 15 are simultaneously formed on the back side of the first wafer 11, with the first via serving as the second alignment mark 15.

[0069] In the first embodiment, the second alignment mark 15 is a through hole with a specific cross-sectional shape. And, as... Figure 8 As shown, the bottom of the second alignment mark 15 is connected to the first alignment mark 13. That is, the bottom of the second alignment mark 15 extends directly to the first alignment mark 13. When forming the second alignment mark 15, the first alignment mark 13 can be used as an etching stop layer. Specifically, the metal region of the first alignment mark 13 is used as the etching stop layer; that is, when the first alignment mark 13 is a positive pattern, the patterned region of the first alignment mark 13 is used as the etching stop layer; when the first alignment mark 13 is a negative pattern, the non-patterned region of the first alignment mark 13 is used as the etching stop layer. Figure 8 In this process, the second alignment mark 15 and the through-silicon via 16 have different depths. Accordingly, in the same through-silicon via process, they can be etched in two batches. In embodiments where the precision requirement is not high, the second alignment mark 15 and the through-silicon via 16 can also be etched in the same batch.

[0070] Figure 9 This is a top view of the second alignment mark provided in the first embodiment of the present invention. The figure enclosed by the dashed lines is the projection 13' of the first alignment mark 13 at the position of the second alignment mark 15. Figure 9 As shown, the cross-sectional shape of the second alignment mark 15 is the same as the graphic shape of the first alignment mark 13, which is also an octagonal star shape, including a central square area and four protruding areas, with an inwardly concave isosceles triangular notch formed at the outer end of each protruding area.

[0071] Furthermore, the axis of the second alignment mark 15 passes through the center point of the first alignment mark 13, and the cross-section of the second alignment mark 15 is concentrically set with the projection 13' of the first alignment mark, with their geometric centers coinciding. This coinciding of their geometric centers not only unifies the alignment reference, avoiding translational and rotational angle deviations caused by differences in the center positions of different marks, thus ensuring the overlay accuracy of processes such as through-silicon via etching and redistribution, and providing a foundation for the electrical reliability of vertical interconnect structures; it also simplifies the alignment process, eliminating the need to reposition new center coordinates, allowing direct reuse of the same reference for calibration, reducing additional operational steps and equipment errors caused by switching between multiple marks, shortening alignment time, and improving overall process efficiency.

[0072] In the embodiment where the first alignment mark 13 is used as the etching stop layer for forming the second alignment mark 15, when the first alignment mark 13 is a positive pattern, the geometric center of the second alignment mark 15 and the projection 13' of the first alignment mark can be made to coincide.

[0073] In the second embodiment, the cross-sectional shape of the second alignment mark is similar to... Figure 15 The first alignment mark 23 in the second alignment mark is the same as the first alignment mark 23. Both are cross-shaped and have fourfold rotational symmetry, which can simultaneously provide clear linear edge features in two vertical directions. Furthermore, the axis of the second alignment mark passes through the center point of the first alignment mark 23.

[0074] In the fourth embodiment, the cross-sectional shape of the second alignment mark is as follows: Figures 17A-17F Any one of them, and the same shape as the first alignment mark.

[0075] The size range of the second alignment mark 15 differs from that of the first alignment mark 13. In the first embodiment, the size range of the second alignment mark 15 is 60~150μm, that is, the length and width of the cross-section of the second alignment mark 15 are both 60~150μm. Furthermore, the minimum width of the cutout area of ​​the second alignment mark 15 is greater than 18μm, enabling the second alignment mark 15 to meet the minimum resolution threshold of the lithography machine's vision system, while also adapting to the minimum linewidth of the dry etching process, thus avoiding rough or broken marks at the edges after etching. Compared to the first alignment mark 13, the second alignment mark 15 is smaller in size, which, while meeting recognition accuracy, reduces the occupation of the process area on the back side of the first wafer 11, adapting to the layout requirements of subsequent processes.

[0076] In another embodiment, the cross-sectional shape of the second alignment mark 15 is different from that of the first alignment mark 13, but both can be clearly distinguished from the actual process pattern. The shape must be compatible with standard photolithography and dry etching processes, without complex hollowing or ultra-fine structures, to ensure compatibility with subsequent manufacturing processes and facilitate industrial manufacturing.

[0077] In some embodiments, the second alignment mark 15 is the first via. The via structure has a physical morphological difference with a recessed interior and a raised surrounding area, forming significant optical contrast and height difference features. In the lithography machine's visual recognition mode, the trench contour can be accurately captured by scanning the light and dark boundaries or morphology. Even if the infrared alignment fails due to the coverage of the metal seed layer or redistribution layer, it can still stably provide a clear alignment reference.

[0078] The second alignment mark 15 corresponds one-to-one with the first alignment mark 13. That is, a second alignment mark 15 is formed above each first alignment mark 13, and the cross section of the second alignment mark 15 and the geometric center of the projection of the first alignment mark 13 on the same plane completely coincide, which can completely eliminate the origin offset between different marks. Figure 14 In this configuration, the first alignment mark 13 is arranged in an array on the first wafer 11, and correspondingly, the second alignment mark 15 is arranged in an array on the first wafer 11, with the same arrangement position as the first alignment mark 13. Compared to the single calibration mode of single-point marking, multiple point markings can effectively offset local position deviations caused by factors such as wafer warpage, process thermal stress, and mechanical deformation. By calibrating photolithography parameters synchronously in multiple regions, the uniformity of photolithography across the entire wafer is significantly improved, reducing local photolithography offset problems on the wafer. This fully ensures the alignment accuracy of core processes such as through-silicon via (TSV) technology, redistribution line (RDL) technology, and pad windowing, guaranteeing the accuracy requirements of MEMS chips for vertical interconnect structures.

[0079] In some embodiments, all the second alignment marks 15 have the same shape, all the first alignment marks 13 have the same shape, and the graphic shape of the first alignment marks 13 is also the same as the cross-sectional shape of the second alignment marks 15. In other embodiments, the cross-sectional shape of the second alignment marks 15 is not exactly the same as the graphic shape of the first alignment marks 13.

[0080] Figures 17A-17F The six patterns listed can also serve as the shapes for the second alignment mark.

[0081] The second alignment mark 15 is formed synchronously with the through-silicon via 16, meaning that the second alignment mark 15 and the through-silicon via 16 are formed in the same through-silicon via etching process, and can be formed in different batches of etching in the same through-silicon via etching process.

[0082] Step S3 can complete the synchronous etching of the second alignment mark 15 and the silicon via 16 without adding any additional process steps, which greatly shortens the process cycle, reduces equipment occupation and process cost, effectively improves wafer packaging capacity and production efficiency, reduces the risk of wafer damage, particle contamination and pattern distortion caused by multiple process operations, and avoids overlay errors and process defects that may be caused by additional photolithography steps.

[0083] The second alignment mark 15 and the through-silicon via 16 formed in the same through-silicon via etching process have at least one of the following characteristics: (a) neither the second alignment mark 15 nor the through-silicon via 16 has any traces of subsequent processing such as secondary etching, re-etching, or hole enlargement; (b) the second alignment mark 15 and the through-silicon via 16 have the same defect type, including plasma damage, stress distribution damage, etc.; (c) the second alignment mark 15 and the through-silicon via 16 have the same connection process.

[0084] In steps S1 to S3 of this technical solution, during the manufacturing stage of the first wafer, a special alignment pattern conforming to photolithography recognition standards is designed on the first metal layer to form the first alignment mark. The size of the first alignment mark is precisely matched to the infrared equipment's recognition threshold and the process accuracy requirements. Utilizing the optical properties of infrared light penetrating the silicon substrate, accurate alignment in the first photolithography process is successfully completed, establishing a unified alignment reference throughout the entire process from the source. This solves the technical problem of initial photolithography alignment being impossible for unmarked incoming wafers. Furthermore, a second alignment mark is simultaneously formed in the existing etching process for alignment in subsequent processes.

[0085] Referring to step S4, when performing subsequent processes on the back side of the first wafer 11, alignment is achieved by directly identifying the second alignment mark 15.

[0086] Figure 5 This is a flowchart of the subsequent processes for the bonded first wafer provided in the first embodiment of the present invention. For example... Figure 5 As shown, step S4 includes: step S41, depositing a dielectric on the back side of the first wafer and aligning it by directly identifying the second alignment mark, forming a patterned photoresist mask layer on the dielectric layer; step S42, forming a patterned dielectric layer based on the photoresist mask layer and exposing the underlying metal structure by opening a window at the bottom of the through-silicon via.

[0087] refer to Figure 10 Following step S41, a dielectric layer 17 is deposited on the back side of the first wafer 11, and alignment is achieved by directly identifying the second alignment mark 15; a patterned photoresist mask layer 180 is formed on the dielectric layer 17. The dielectric layer 17 covers the back surface of the first wafer 11, including the inner wall of the through-silicon via 16, that is, the dielectric layer 17 covers the sidewalls and bottom wall of the through-silicon via 16. Furthermore, the dielectric layer 17 is also deposited on the inner wall of the second alignment mark 15. The dielectric layer 17 is a silicon dioxide layer.

[0088] In one embodiment, the specific process is as follows: 1. Conformal deposition is performed on the process operation surface of the first wafer 11 using plasma-enhanced chemical vapor deposition (PECVD) to uniformly and continuously cover the surface of the process operation surface of the first wafer 11, as well as the sidewalls and bottom walls of the silicon via 16, thereby forming a dense dielectric layer 17, achieving preliminary dielectric insulation of the silicon via 16 and passivation protection of the surface of the first wafer 11; 2. An anti-reflective coating (ARC) and a spin-coated photoresist layer are sequentially coated on the surface of the dielectric layer 17 to form a photolithographic stack; a photoresist mask layer 180 matching the design pattern is formed on the surface of the photolithographic stack to complete the patterning definition of the lower dielectric layer 17, providing a mask reference for the selective etching of the dielectric layer 17 in the subsequent dry etching process.

[0089] from Figure 8 As can be seen, after step S3, the second alignment mark 15 formed on the back side of the first wafer 11 is a via of a specific shape, which can directly identify the second alignment mark 15. That is, the second alignment mark 15 can be directly observed and identified on the process operation surface of the first wafer 11 through the lithography machine vision system. Accordingly, during the execution of step S41, alignment can be achieved by directly identifying the second alignment mark 15.

[0090] refer to Figure 11 In step S42, a patterned dielectric layer 171 is formed based on the photoresist mask layer 180, and a window is opened at the bottom of the through-silicon via 16 to expose the underlying metal structure 14. In step S42, using the photoresist mask layer 180 as an etching barrier mask, a dry etching process with a high selectivity is employed to perform patterned etching on the dielectric layer 171 covering the inner wall of the through-silicon via 16 and the wafer surface. This completes the directional windowing process at the bottom of the through-silicon via 16, removing the dielectric layer material in the area corresponding to the bottom of the through-silicon via 16 and the photoresist mask layer 180.

[0091] The lower metal structure 14 is a bottom landing pad, which provides a stable and reliable electrical contact interface for subsequent metal filling of through-silicon vias and redistribution layer interconnection, ensuring the conductivity and structural stability of the vertical interconnect structure and meeting the electrical interconnection requirements of high-precision packaging of MEMS face-to-face bonding wafers.

[0092] like Figure 10 As shown, after step S41 is completed, the second alignment mark 15 is blocked by the photoresist mask layer 180. Correspondingly, as... Figure 11 As shown, step S42 further includes removing the photoresist mask layer 180 remaining on the process operation surface of the first wafer 11, thereby re-exposing the through-silicon via 16 and the second alignment mark 15. Removing the photoresist residue covering the second alignment mark 15 restores the outline clarity and device recognizability of the second alignment mark 15, preventing photolithographic alignment failure due to the absence of the second alignment mark 15. This provides a stable and unified visual alignment reference for subsequent key processes such as redistribution layer fabrication, polyimide patterning, and pad windowing, enabling the photolithography equipment to accurately capture the alignment mark and complete the alignment, thus eliminating overlay misalignment problems caused by the loss of the alignment reference in the process.

[0093] Forming a dielectric layer 17 on the back side of the first wafer 11 and then photolithographically forming a patterned dielectric layer 171 is a core process step after dry etching of the through-silicon via (TSV) 16. This patterned dielectric layer 171 serves to insulate, passivate, and protect the sidewalls of the TSV 16 from the back side of the wafer, preventing leakage and short circuits in subsequent metal filling and redistribution processes. It also acts as a support and barrier layer for subsequent photolithography, etching, and metal interconnect processes. The patterned dielectric layer 171 precisely enables bottom-hole opening and area isolation, laying a crucial structural foundation for exposing the bottom landing pads and completing vertical electrical interconnects. It is a vital intermediate step connecting the TSV etching and metallization processes.

[0094] refer to Figure 5 as well as Figure 12 Step S4 further includes: step S43, achieving alignment by directly identifying the second alignment mark 15, forming a redistribution layer 18 on the surface of the patterned medium layer 171 and re-exposing the second alignment mark, the redistribution layer 18 being connected to the lower metal structure 14.

[0095] Step S43 further includes: (1) forming a metal seed layer on the surface of the patterned dielectric layer 171; (2) achieving alignment by directly identifying the second alignment mark 15, and forming a patterned wiring photoresist layer on the surface of the metal seed layer; (3) filling the area of ​​the wiring photoresist layer not covered by photoresist with metal to form a redistribution layer 18, wherein the conductive lines of the redistribution layer 18 are connected to the underlying metal structure 14. After the redistribution layer 18 is formed, the through-silicon via (TSV) forms a TSV 161, wherein the TSV 161 includes the TSV 16 and the metal structure formed by its inner wall that is connected to the underlying metal structure 14 and the redistribution layer 18. One end of the redistribution layer 18 is precisely electrically connected to the underlying metal structure 14 through the TSV 161, and the other end extends to form the outside, constructing a signal transmission path from the inside of the chip to the outside, ensuring stable and low-loss transmission of current and high-frequency signals, and providing a reliable electrical connection for the packaging structure. The redistribution layer 18 can flexibly adjust the signal path through the wiring design, compensate for the positional deviation caused by processes such as silicon via etching and bonding, and improve overlay accuracy and process yield.

[0096] The redistribution layer 18 also has a preset pad area. The pad area is used for electrical communication with the solder ball 192.

[0097] During the formation of the redistribution layer 18, metal can be sputtered onto the surface of the first wafer 11. If infrared detection is used to align the wafer using the first alignment mark 13, the sputtered metal layer will block the infrared light from penetrating the metal, causing the first alignment mark 13 to fail and resulting in alignment failure. However, using the second alignment mark 15 for alignment can avoid the influence of the metal layer.

[0098] like Figure 12 As shown, after performing (1) to (3), step S43 further includes removing the remaining wiring photoresist layer and the metal seed layer, re-exposing the second alignment mark 15, restoring the outline clarity and device recognizability of the second alignment mark 15, and avoiding photolithography alignment failure caused by the absence of the second alignment mark 15. This provides a stable and unified visual alignment reference for key processes such as polyimide patterning and pad windowing, enabling the photolithography equipment to accurately capture the alignment mark and complete the alignment, thus eliminating overlay misalignment caused by the loss of the alignment reference in the process.

[0099] refer to Figure 5 and Figure 13Step S4 further includes: Step S44, achieving alignment by directly identifying the second alignment mark 15, and forming a patterned protective layer and solder ball composite structure 19 on the surface of the redistribution layer 18. The patterned protective layer and solder ball composite structure 19 includes a patterned protective layer 191 and solder balls 192.

[0100] Step S44 further includes: 1) forming a protective layer on the surface of the redistribution layer 18; 2) achieving alignment by directly identifying the second alignment mark 15 to form a patterned protective layer 191, the patterned protective layer 191 including pad openings; 3) setting solder balls 191 in the pad opening area to form a composite structure 19 of patterned protective layer and solder balls.

[0101] The protective layer in step 1) is a polyimide layer. The protective layer can provide comprehensive electrical insulation and physical protection for the redistribution layer 18, preventing the redistribution layer 18 from being subjected to mechanical scratches, chemical corrosion or environmental moisture erosion in subsequent processes. At the same time, it provides a flat process substrate for subsequent photolithography patterning. The thickness of the protective layer must be strictly controlled within a preset range to balance the insulation performance and the process controllability of subsequent window etching.

[0102] Step 2) To effectively avoid the risk of overlay misalignment caused by the alignment failure of the infrared detection method, the patterned protective layer 191 opens a pad window in the preset pad area of ​​the redistribution layer 18. The size and position of the window must be completely matched with the RDL pad, and the tolerance is controlled at the sub-micron level to ensure that the pad surface of the redistribution layer 18 is fully exposed, providing a reliable electrical contact interface for subsequent solder ball interconnection. In some embodiments, the second alignment mark 15 is formed in the non-functional area of ​​each chip cell, such as the edge of the chip cell or next to the scribe line. The protective layer in step 1) will not cover the second alignment mark 15.

[0103] Step 3) The solder ball 191 forms a strong metallurgical bond and electrical connection with the exposed pad, constructing a vertical interconnect composite structure from the lower metal structure 14, the silicon via 16, the redistribution layer 18 to the solder ball 191. This structure enables efficient transmission of signals between the chip and the external packaging substrate, while ensuring mechanical connection strength and long-term reliability.

[0104] In the back-end redistribution (RDL) and pad fabrication processes, the surface of the first wafer 11 is completely covered by a continuously deposited metal seed layer. The metal material completely blocks infrared light penetration, causing the original infrared detection alignment method to malfunction and leading to subsequent issues such as photolithography alignment misalignment and structural alignment deviations. To address the problem of infrared alignment failure caused by the metal seed layer blocking, this solution further forms a second alignment mark 15 with a special alignment pattern on the back side of the first wafer 11 using dry etching, based on the first alignment mark 13. The second alignment mark 15 formed by dry etching is directly formed on the process operation surface of the first wafer 11, without relying on infrared penetration for identification. Even with full metal layer coverage, the second alignment mark 15 can still be identified by a front-side visual inspection device. Furthermore, the second alignment mark 15 is formed in the non-functional area of ​​each chip cell, such as the chip cell edge or next to the scribe line, and is not covered by the protective layer of the functional area. This enables stable and precise alignment of subsequent key processes such as polyimide lithography and pad windowing, overcoming the alignment bottleneck caused by metal layer shielding and ensuring the continuity and precision of the later packaging process.

[0105] As can be seen from step S4, by setting the first alignment mark 13 and the second alignment mark 15 to form a dual alignment guarantee, each etching of the subsequent process of this solution can be configured with at least one independent alignment mark to achieve alignment, making up for the defect that infrared alignment cannot be used after the metal layer is blocked; and by setting multiple alignment marks on the first wafer 11 to form multi-point calibration alignment, the global photolithography overlay accuracy is further improved, ensuring the electrical interconnection reliability of the through silicon via and the redistribution layer, and meeting the full-process alignment requirements of high-precision packaging of face-to-face bonding MEMS wafers.

[0106] This technical solution addresses the common industry problem of inaccurate alignment after active surface bonding of MEMS wafers in face-to-face bonding mode. It constructs a multi-level, end-to-end alignment marking system. A first alignment mark 13 with a specially patterned design is pre-set on the first metal layer of the first wafer 11 as the alignment mark for the first photomask (the step of forming through-silicon vias). A second alignment mark 15 is simultaneously formed during the dry etching step on the back of the first wafer 11 to form through-silicon vias, and this second alignment mark is used as the alignment mark for subsequent processes. Through the coordinated alignment, mutual supplementation, and end-to-end adaptation of these two marks, the entire downstream process after bonding is covered. This solves the industry problem of lacking dedicated photolithography patterns for face-to-face wafers, improves photolithography misalignment defects, effectively enhances process stability and chip electrical interconnect reliability, and meets the industrial production needs of high-precision MEMS chip 3D integration.

[0107] Based on the same inventive concept, this application also provides a face-to-face bonding wafer packaging structure.

[0108] refer to Figure 13 The face-to-face bonded wafer packaging structure includes a first wafer 11 and a second wafer 10, which are bonded face-to-face with their active surfaces facing each other. The first wafer 11 includes a first alignment mark 13, a second alignment mark 15, and a through-silicon via (TSV) 161. The first alignment mark 13 is located on a first metal layer 130 of the first wafer 11, which is the native metal layer closest to the back surface of the first wafer. The TSV 161 extends from the back surface of the first wafer 11 to a lower metal structure 14 inside it and is electrically connected to the lower metal structure 11. The second alignment mark 15 is formed synchronously with the TSV via 16 of the TSV 161, and extends from the back surface of the first wafer 11 above the first alignment mark 13. The TSV 161 includes the TSV via 16 and a metal structure formed by its inner wall that communicates with the lower metal structure 14 and the redistribution layer 18.

[0109] The native metal layer is formed in the front-end process of the first wafer 11 and is located in the device region near the active surface of the first wafer 11. This first metal layer is the native metal layer first formed on the silicon substrate of the first wafer 11 in the front-end process. The first alignment mark 13 is a identifiable specific pattern formed on the first metal layer 130. In a specific process, the first alignment mark 13 is formed simultaneously with the patterning of the first metal layer 130.

[0110] The first alignment mark 13 can be either a positive or a negative pattern. A positive pattern refers to a pattern in which the metal is retained, while a negative pattern refers to a pattern in which the metal is removed.

[0111] like Figure 7 As shown, the cross-sectional shape of the first alignment mark 13 is a positive shape. Specifically, the metal of the pattern of the first alignment mark 13 is retained, while the surrounding metal is removed. The shape of the first alignment mark 13 is an octagonal star, including a central square area and four protruding areas, each of which has an inwardly recessed isosceles triangular notch at its outer end.

[0112] A plurality of first alignment marks 13 are formed on the first wafer 11, and the first alignment marks 13 are arranged in an array on the first metal layer. For example... Figure 14As shown, in the effective process area of ​​the first wafer 11, each chip unit is provided with an octagonal star-shaped first alignment mark 13. The first alignment mark 13 corresponds one-to-one with the chip unit, and the overall arrangement is equally spaced and symmetrical, completely covering the core processing area of ​​the first wafer 11. Each chip unit is equipped with a dedicated alignment reference, which can achieve precise alignment across the entire wafer, avoiding alignment differences between chip units at the edge and those at the center. When a first alignment mark 13 fails to identify due to process deviation, it can be switched to an adjacent first alignment mark 13 to complete the alignment, avoiding the scrapping of the entire wafer due to local marking defects.

[0113] Compared to the single calibration mode of single-point marking, multiple point marking can effectively offset local position deviations caused by factors such as wafer warpage, process thermal stress, and mechanical deformation. By calibrating lithography parameters in multiple regions simultaneously, the uniformity of lithography across the entire wafer is greatly improved, and the problem of local lithography offset on the wafer is reduced.

[0114] like Figure 15 As shown, in the second embodiment, the cross-sectional shape of the first alignment mark 23 is a positive shape, and the cross-sectional shape of the first alignment mark 23 is a cross shape, which is formed by the integral intersection of two mutually perpendicular rectangular arms of equal width. It has fourfold rotational symmetry and can simultaneously provide clear linear edge features in two vertical directions. Its central intersection point can be used as the absolute origin.

[0115] The size of the first alignment mark 23 ranges from 100 to 300 μm, and the minimum width of the metallic region is greater than 30 μm. The mark size is used to define the width and height of the first alignment mark 23. (Continue to refer to...) Figure 15 The first alignment mark 23 has a mark width of L2, a mark height of H2, and a minimum pattern width of D2. Therefore, the mark width L2 and the mark height H2 cannot exceed the mark size of the first alignment mark 23, satisfying: L2∈[100μm, 300μm], H2∈[100μm, 300μm], D2>30μm.

[0116] like Figure 16As shown, in the third embodiment, the pattern shape of the first alignment mark 33 is also cross-shaped. However, unlike the second embodiment, the first alignment mark 33 is a negative graphic; the metal of the pattern of the first alignment mark 33 is removed, while the surrounding metal is retained. The side length of a single metal block of the first alignment mark 33 is D3, and the overall horizontal span of the mark is L3, and the vertical span is H3. The minimum width of the pattern D3 is the minimum width of the metal-retained area of ​​the first alignment mark 33, which differs from the second embodiment. Similar to the second embodiment, the mark size range of the first alignment mark 33 is the same, satisfying: L3∈[100μm, 300μm], H3∈[100μm, 300μm], D3>30μm.

[0117] Figures 17A-17F Six patterns are listed, all of which can serve as the graphic shape for the first alignment mark.

[0118] The second alignment mark 15 is a via of a specific shape. Furthermore, in the first embodiment, as... Figure 13 As shown, the second alignment mark 15 extends from the back side of the first wafer 11 to connect with the upper surface of the first alignment mark 13. That is, the bottom of the second alignment mark 15 reaches the first alignment mark 13. In some embodiments, there is a certain distance between the bottom of the second alignment mark 15 and the mark of the first alignment mark 13, and the second alignment mark 15 is a shallow hole located above the first alignment mark 13.

[0119] Figure 9 The shape enclosed by the dashed line is the projection 13' of the first alignment mark 13 onto the cross-section of the second alignment mark 15. It can be seen that the cross-sectional shape of the second alignment mark 15 is the same as the graphic shape of the first alignment mark 13, but the dimensions are different. In the first embodiment, the mark width and mark height of the cross-section of the second alignment mark 15 are both in the range of 60~150μm, and the minimum width of the cutout area of ​​the second alignment mark 15 is greater than 18μm. The mark size of the second alignment mark 15 is smaller than that of the first alignment mark 13, which, while meeting the recognition accuracy requirements, can reduce the occupation of the process area on the back side of the first wafer 11, adapting to the layout requirements of the back-end process. The cross-sectional shape of the second alignment mark 15 can also be referenced... Figure 15 Figure 17.

[0120] In another embodiment, the cross-sectional shape of the second alignment mark 15 is different from that of the first alignment mark 13. However, the shape of the second alignment mark 15 is adaptable to standard photolithography and dry etching processes, without complex cutouts or ultra-fine structures, ensuring compatibility with subsequent manufacturing processes and facilitating industrial manufacturing. Furthermore, the cross-section of the second alignment mark 15 coincides with the geometric center of the projection 13' of the first alignment mark.

[0121] The second alignment mark 15 corresponds one-to-one with the first alignment mark 13. Accordingly, the second alignment marks 15 are arranged in an array on the first wafer 11. Compared with the single calibration mode of single-point marking, multiple point markings can effectively offset local position deviations caused by factors such as wafer warpage, process thermal stress, and mechanical deformation. By calibrating photolithography parameters in multiple regions simultaneously, the uniformity of photolithography across the entire wafer is greatly improved, the problem of local photolithography offset on the wafer is reduced, and the alignment accuracy of core structures such as through-silicon via (TSV) processes, redistribution processes, and pad openings is fully guaranteed, thus fully guaranteeing the accuracy requirements of MEMS chips for vertical interconnect structures.

[0122] Continue to refer to Figure 13 The inner wall of the second alignment mark 15 is covered with a patterned dielectric layer 171. The patterned dielectric layer 171 can be deposited on the surface of the process operation surface of the first wafer 11 by plasma chemical vapor deposition and patterned by dry etching. The patterned dielectric layer 171 can be used for insulation and protection of the surface of the first wafer 11, avoiding problems such as leakage and short circuits in the subsequently filled metal, and can also serve as a support layer and barrier layer for the metal interconnect structure.

[0123] A redistribution layer 18 is formed on the patterned dielectric layer 171, and the redistribution layer 18 is located away from the bonding layer of the first wafer 11. The redistribution layer 18 is electrically connected to the lower metal structure 14 through the inner wall of the through-silicon via 161. The redistribution layer 18 also has a predetermined pad area.

[0124] The redistribution layer 18 and the patterned dielectric layer 171 are covered with a patterned protective layer 191. The protective layer 191 has openings formed in the pad areas of the redistribution layer 18, and solder balls 192 are disposed within these openings. The solder balls 192 are electrically connected to the redistribution layer 18. The patterned protective layer 191 and the solder balls 192 form a composite structure 19 of the patterned protective layer and solder balls. The patterned protective layer 191 is a polyimide layer.

[0125] The redistribution layer 18 is located above the patterned dielectric layer 171 on the back surface of the first wafer 11, and is the core interconnect layer between the patterned dielectric layer 171 and the patterned protective layer 191. It can redistribute the vertical electrical signals emanating from the through-silicon via 161 to preset pad areas via horizontal wiring, achieving efficient signal fan-out and pin mapping, while avoiding occupation of the chip's active area and improving wafer layout density. Furthermore, one end of the redistribution layer 18 is precisely electrically connected to the underlying metal structure 14 through the through-silicon via 161, and the other end extends to form the exterior, constructing a signal transmission path from the inside of the chip to the outside, ensuring stable and low-loss transmission of current and high-frequency signals, and providing reliable electrical connections for the packaging structure.

[0126] The second alignment mark 15 is formed synchronously with the through-silicon via 16, meaning that the second alignment mark 15 and the through-silicon via 16 are formed in the same through-silicon via etching process, and can be formed in different batches of etching in the same through-silicon via etching process.

[0127] The second alignment mark 15 and the through-silicon via 16 formed in the same through-silicon via etching process have at least one of the following characteristics: (a) neither the second alignment mark 15 nor the through-silicon via 16 has any traces of subsequent processing such as secondary etching, re-etching, or hole enlargement; (b) the second alignment mark 15 and the through-silicon via 16 have the same type of defect, including plasma damage, stress distribution damage, etc.; (c) the dielectric layer covering the inner wall and bottom wall of the second alignment mark 15 and the dielectric layer inside the through-silicon via 16 are deposited by the same plasma chemical vapor deposition process, and have consistent film thickness, uniformity, and density. These characteristics can be used to determine whether the second alignment mark 15 and the through-silicon via 16 in the packaging structure are formed synchronously.

[0128] The above technical solution involves a first alignment mark formed on the first metal layer of the first wafer, which can be aligned non-visually to form through-silicon vias (TSVs) and simultaneously form a second alignment mark. The second alignment mark extends from the back of the first wafer to above the first alignment mark. This second alignment mark can be directly identified on the process operation surface of the first wafer and used to form the various packaging layers on the back of the first wafer. Through the coordinated alignment, mutual complementarity, and end-to-end adaptation of these two marks, the entire process from photolithography to packaging can be covered. This solves the industry problem of face-to-face wafer arrivals lacking dedicated photolithography patterns, improves photolithography misalignment defects, effectively enhances process stability and chip electrical interconnect reliability, and meets the industrial production needs of high-precision MEMS chip 3D integration.

[0129] It should be noted that references to "an embodiment," "an embodiment," "an exemplary embodiment," "some embodiments," etc., in the specification indicate that the described embodiments may include specific features, structures, or characteristics, but each embodiment may not necessarily include that specific feature, structure, or characteristic. Furthermore, such phrases do not necessarily refer to the same embodiment. In addition, when a specific feature, structure, or characteristic is described in connection with an embodiment, whether explicitly described or not, implementing such a feature, structure, or characteristic in conjunction with other embodiments is within the knowledge of those skilled in the art.

[0130] It should be noted that the terms "comprising" and "having," and their variations, used in this invention document are intended to cover non-exclusive inclusion. The terms "first," "second," etc., are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence, unless explicitly indicated by the context. It should be understood that such data used interchangeably where appropriate. Furthermore, embodiments and features within embodiments of this invention can be combined with each other unless otherwise specified. In addition, descriptions of well-known components and technologies have been omitted in the above description to avoid unnecessarily obscuring the concepts of this invention. In the various embodiments described above, each embodiment focuses on its differences from other embodiments; similar or identical parts between embodiments can be referred to interchangeably.

[0131] The above description is only a preferred embodiment of the present invention. It should be noted that those skilled in the art can make several improvements and modifications without departing from the principle of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. A method for face-to-face bonding of incoming wafers for packaging, characterized in that, include: An initial bonding structure is provided, the initial bonding structure including a first wafer and a second wafer, the active surfaces of the first wafer and the second wafer being bonded face to face, and a first alignment mark being provided on a first metal layer of the first wafer, the first metal layer being the metal layer closest to the back side of the first wafer; Alignment is achieved by penetrating the back of the first wafer to identify the first alignment mark through a non-visual direct identification method; Silicon vias and a first via corresponding to the first alignment mark are simultaneously formed on the back side of the first wafer, with the first via serving as the second alignment mark; When performing subsequent processes on the back side of the first wafer, alignment is achieved by directly identifying the second alignment mark.

2. The method according to claim 1, characterized in that, Before the first wafer is bonded to the second wafer, the first alignment mark is formed simultaneously during the formation of the first metal layer of the first wafer in the front-end process.

3. The method according to claim 1, characterized in that, The first alignment mark is a recognizable specific pattern formed on the first metal layer.

4. The method according to claim 1, characterized in that, The first alignment marker is either a positive or negative graphic.

5. The method according to claim 1, characterized in that, There are multiple first alignment marks, which are arranged in an array on the first wafer.

6. The method according to claim 1, characterized in that, The size of the first alignment mark ranges from 100 to 300 μm.

7. The method according to claim 1, characterized in that, The minimum width of the metal region of the first alignment mark is greater than 30 μm.

8. The method according to claim 1, characterized in that, The bottom of the second alignment mark is connected to the first alignment mark.

9. The method according to claim 1, characterized in that, The size of the second alignment mark ranges from 60 to 150 μm.

10. The method according to claim 1, characterized in that, The minimum width of the cutout area of ​​the second alignment mark is greater than 18 μm.

11. The method according to claim 1, characterized in that, The cross-sectional shape of the second alignment mark is the same as the graphic shape of the first alignment mark.

12. The method according to claim 1, characterized in that, The second alignment mark corresponds one-to-one with the first alignment mark.

13. The method according to claim 1, characterized in that, The steps for performing subsequent processes on the back side of the first wafer include: A dielectric layer is deposited on the back side of the first wafer, and alignment is achieved by directly identifying the second alignment mark, forming a patterned photoresist mask layer on the dielectric layer; A patterned dielectric layer is formed based on the photoresist mask layer, and a window is opened at the bottom of the through-silicon via to expose the underlying metal structure.

14. The method according to claim 13, characterized in that, In the step of depositing a dielectric layer on the back side of the first wafer, the dielectric layer is also deposited on the inner wall of the second alignment mark.

15. The method according to claim 13, characterized in that, include: In the step of forming a patterned photoresist mask layer on the dielectric layer, the second alignment mark is blocked by the photoresist mask layer; The steps of forming a patterned dielectric layer based on the photoresist mask layer and exposing the underlying metal structure by opening a window at the bottom of the through-silicon via further include removing the residual photoresist mask layer to re-expose the second alignment mark.

16. The method according to claim 13, characterized in that, The steps for performing subsequent processes on the back side of the first wafer include: Alignment is achieved by directly identifying the second alignment mark, forming a redistribution layer on the surface of the patterned medium layer and re-exposing the second alignment mark, the redistribution layer connecting to the underlying metal structure.

17. The method according to claim 16, characterized in that, The steps for performing subsequent processes on the back side of the first wafer include: Alignment is achieved by directly identifying the second alignment mark, forming a composite structure of a patterned protective layer and solder balls on the surface of the redistribution layer.

18. The method according to claim 17, characterized in that, The step of achieving alignment by directly identifying the second alignment mark and forming a composite structure of a patterned protective layer and solder balls on the surface of the redistribution layer further includes: A protective layer is formed on the surface of the redistribution layer; Alignment is achieved by directly identifying the second alignment mark, forming a graphical protective layer, which includes pad openings; Solder balls are placed in the windowed area of ​​the solder pad to form a composite structure of a patterned protective layer and solder balls.

19. A face-to-face bonded wafer packaging structure, comprising a first wafer and a second wafer, wherein the first wafer and the second wafer are bonded face-to-face with their active surfaces facing each other, characterized in that, The first wafer includes: The first alignment mark is located in the first metal layer of the first wafer, and the first metal layer is the native metal layer closest to the back side of the first wafer; Through-silicon vias (TSVs) extend from the back side of the first wafer into an internal lower metal structure and are electrically connected to the lower metal structure. The second alignment mark is a first via formed synchronously with the through-silicon via (TSV) via of the first wafer, and the second alignment mark extends from the back side of the first wafer to above the first alignment mark.

20. The packaging structure according to claim 19, characterized in that, The second alignment mark extends from the back side of the first wafer to the upper surface of the first alignment mark.

21. The packaging structure according to claim 19, characterized in that, The inner wall of the second alignment mark is covered with a patterned dielectric layer.

22. The packaging structure according to claim 21, characterized in that, A redistribution layer is formed on the patterned dielectric layer, and the redistribution layer is electrically connected to the through-silicon via.

23. The packaging structure according to claim 22, characterized in that, The surfaces of the redistribution layer and the patterned dielectric layer are covered with a patterned protective layer. The protective layer forms a window in the pad area of ​​the redistribution layer, and a solder ball is disposed in the window. The solder ball is electrically connected to the redistribution layer.

24. The packaging structure according to claim 19, characterized in that, The first alignment mark is a recognizable specific pattern formed on the first metal layer.

25. The packaging structure according to claim 19, characterized in that, The first alignment marker is either a positive or negative graphic.

26. The packaging structure according to claim 19, characterized in that, There are multiple first alignment marks, which are arranged in an array on the first wafer.

27. The packaging structure according to claim 19, characterized in that, The cross-sectional shape of the second alignment mark is the same as the graphic shape of the first alignment mark.

28. The packaging structure according to claim 19, characterized in that, The second alignment mark corresponds one-to-one with the first alignment mark.

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