A wafer-level corrosion-resistant coating and its preparation method

Abstract

This invention discloses a wafer-level corrosion-resistant coating and its preparation method. The corrosion-resistant coating is attached to the inactive surface of a wafer substrate or the surface of a semiconductor cavity consumable. From the substrate outwards, it includes: a thermal stress gradient buffer layer, which is a silicon-rich and nitrogen-rich amorphous compound layer with a composition gradient along the thickness direction. The composition gradient is characterized by a higher molar percentage of silicon atoms near the substrate than near the outer side; and a stress dissipation nanolayer, deposited on the thermal stress gradient buffer layer, consisting of at least 20 cycles of alternating deposition of a first dielectric sublayer and a second dielectric sublayer. The combination of the composition gradient design of the thermal stress gradient buffer layer and the stepped annealing process of this invention significantly improves the bonding strength between the coating and the silicon substrate, achieving zero detachment in harsh thermal shock cyclic aging tests, effectively solving the industry problem of interfacial thermal mismatch.

Description

Technical Field

[0001] This invention relates to the field of semiconductor advanced process consumables and wafer protection technology, specifically to a wafer-level corrosion-resistant coating and its preparation method. Background Technology

[0002] As the feature size of semiconductor integrated circuits gradually enters the 5-nanometer and below node, the process conditions for core processes such as plasma etching and chemical vapor deposition in wafer manufacturing are becoming increasingly demanding. To achieve precise etching of high aspect ratio microstructures, high-concentration halogen gases are typically introduced into the process chamber to form high-density, high-energy plasmas under the excitation of radio frequency or microwave power supplies. These high-energy fluorine or chlorine radicals are not only used for etching photoresist and silicon substrates, but also exert intense physical bombardment and chemical corrosion on all exposed hardware within the chamber and the unprocessed surfaces of the wafer.

[0003] Traditional protective solutions often use anodic aluminum oxide or quartz as the protective layer. However, in modern high-density fluorine-based plasma environments, aluminum oxide reacts rapidly with fluorine free radicals to generate volatile aluminum fluoride or a porous layer. This porous product is prone to peeling off under thermal stress or plasma bombardment, forming micron- or nano-sized, potentially lethal particles. If these particles fall into the active areas of the wafer, they can directly cause short circuits or open circuits in the photolithography pattern, resulting in wafer scrap and severely impacting production yield.

[0004] In recent years, the industry has gradually adopted pure yttrium oxide coatings, which offer superior resistance to fluorine corrosion, as a protective material. Yttrium fluoride, formed by the reaction of yttrium oxide and fluorine, has an extremely high boiling point and is not easily volatilized, forming a dense passivation protective film on the surface. However, in long-term engineering applications, pure yttrium oxide coatings suffer from severe thermodynamic and mechanical defects, limiting their effectiveness.

[0005] First, the thermal stress mismatch problem is prominent. The coefficient of linear expansion of yttrium oxide differs significantly from that of the underlying silicon wafer or silicon carbide substrate. During the cyclic and drastic temperature rise and fall of the chamber in the etching process, huge thermal shear stress is generated at the interface between the coating and the substrate, making the coating extremely prone to large-area peeling and detachment.

[0006] Secondly, columnar crystal penetration defects lead to infiltration corrosion. Yttrium oxide coatings prepared by traditional physical vapor deposition or atmospheric plasma spraying inevitably exhibit coarse columnar crystals growing along the thickness direction in their microstructure. Fluorine free radicals in the plasma can easily penetrate along the grain boundary channels of the columnar crystals, directly corroding the underlying substrate and causing the coating to fail through penetration.

[0007] Third, its high brittleness easily leads to the propagation of microcracks. Pure ceramic coatings have extremely low fracture toughness. Under continuous high-frequency physical bombardment by plasma, the nanoscale microcracks generated on the surface will rapidly extend inward, eventually causing macroscopic cracking of the coating.

[0008] Therefore, how to overcome the single-dimensional protection limitations of pure yttrium oxide coatings, and solve the thermal stress mismatch between the coating and the wafer substrate, block the penetration channels of corrosive media, and endow the coating with stress dissipation capabilities through cross-scale design of material structures without sacrificing halogen corrosion resistance, has become a key technical challenge that urgently needs to be solved in the field of advanced semiconductor process consumables.

[0009] To address this, a wafer-level corrosion-resistant coating and its preparation method are proposed. Summary of the Invention

[0010] The purpose of this invention is to provide a wafer-level corrosion-resistant coating and its preparation method, thereby addressing one of the problems existing in the prior art.

[0011] Firstly, to solve the aforementioned technical problems, one technical solution adopted in this application is: a wafer-level corrosion-resistant coating, wherein the corrosion-resistant coating is attached to the inactive surface of a wafer substrate or the surface of a semiconductor cavity consumable, and comprises, from the substrate outwards, the following: A thermal stress gradient buffer layer, wherein the thermal stress gradient buffer layer is a silicon-rich and nitrogen-rich amorphous compound layer, and there is a composition gradient along the thickness direction inside it. The composition gradient is characterized by the molar proportion of silicon atoms on the side closer to the substrate being greater than the molar proportion of silicon atoms on the side closer to the outside. The stress dissipation nanolayer is deposited on the thermal stress gradient buffer layer and consists of at least 20 cycles of alternating deposition of a first dielectric sublayer and a second dielectric sublayer. The first dielectric sublayer is amorphous aluminum nitride or aluminum oxynitride, and the second dielectric sublayer is zirconium oxide or yttrium oxide modified with stabilizer doping. Incoherent grain boundaries are formed between adjacent sublayers. A high-density halogen-resistant barrier layer is deposited on the surface of the stress-dissipating nanolayer. The layer is made of a rare-earth-doped yttrium oxide composite phase material that has been treated with in-situ plasma fluorination. A cross-linked YOF bond network is formed in the composite phase material.

[0012] In one possible implementation, the thickness of the thermal stress gradient buffer layer is 50 nm to 150 nm; within this thickness range, the Young's modulus near the substrate region is controlled between 130 GPa and 160 GPa, and the Young's modulus near the stress dissipation nanolayer region smoothly transitions to between 180 GPa and 220 GPa.

[0013] In one possible implementation, in the stress-dissipating nanolayer, the thickness of a single first dielectric sublayer is 2 to 5 nanometers, and the thickness of a single second dielectric sublayer is 3 to 8 nanometers; the doping stabilizer is scandium oxide or erbium oxide, and its mass doping concentration in the second dielectric sublayer is 1.5% to 4.5%.

[0014] In one possible implementation, the thickness of the highly dense halogen-resistant barrier layer is 500 nm to 2000 nm; in the composite phase material, the doping amount of rare earth element M accounts for 2.5% to 12.5% ​​of the total rare earth and yttrium elements, and the doping amount of fluorine element accounts for 1.5% to 25% of the total mass of the composite phase material, wherein M is at least one rare earth element selected from gadolinium, erbium, or neodymium.

[0015] In one possible implementation, the microstructure of the high-density halogen-resistant barrier layer is a dense columnar crystal structure, and the grain boundaries of the columnar crystals are enriched with the doped rare earth elements to suppress the penetration of fluorinated plasma along the grain boundaries; the surface roughness Ra of the halogen-resistant barrier layer is less than 0.5 nanometers.

[0016] Secondly, to solve the above-mentioned technical problems, another technical solution adopted in this application is: a method for preparing the wafer-level corrosion-resistant coating, comprising the following continuous vacuum integrated process steps: Step S1, substrate surface activation: The wafer substrate to be processed is placed in the reaction chamber, and a mixture of argon and hydrogen gas is introduced to excite inductively coupled plasma to etch and clean the substrate surface and expose the dangling bonds. Step S2: Dynamic plasma-enhanced atomic layer deposition to construct a thermal stress gradient buffer layer: Using silicon and nitrogen precursors as reactants, during the deposition process, the pulse time of the silicon precursor is nonlinearly decreased while the pulse time of the nitrogen precursor is synchronously increased, so that a silicon-rich and nitrogen-rich buffer layer with gradient changes in composition and modulus is grown in situ on the substrate surface. Step S3: Magnetron sputtering to construct stress-dissipating nanolayers: Without disrupting the vacuum, the substrate is transferred to a multi-target sputtering chamber. Using dual-target co-sputtering or alternating sputtering modes, the first and second dielectric sublayers are deposited alternately at a constant substrate temperature. The sputtering power and substrate bias are controlled to induce the formation of high-density incoherent grain boundaries between the sublayers. Step S4: In-situ fluorination coupled with physical vapor deposition to construct a high-density halogen-resistant barrier layer: During the simultaneous deposition of rare earth-doped yttrium oxide by physical vapor deposition, fluorine-containing reactive gas is pulsedly introduced into the chamber. The in-situ excited fluorine radicals react with the deposited atoms in the gas phase or on the surface phase, and finally solidify to form a dense barrier layer with a YOF bonding network. Step S5, Step annealing to eliminate internal stress: Vacuum step heating annealing is performed on the deposited wafer to promote atomic-level interdiffusion at the interface of each layer to enhance the interlayer bonding force.

[0017] In one possible implementation, in step S2, the silicon precursor is bissilane or hexachlorosilane, and the nitrogen precursor is ammonia plasma; the substrate temperature is maintained at 250 degrees Celsius to 350 degrees Celsius.

[0018] In one possible implementation, in step S3, the substrate bias voltage during the deposition of the first dielectric sublayer is set to -30V to -50V, and the substrate bias voltage during the deposition of the second dielectric sublayer is switched to -80V to -120V. The continuous growth of columnar crystals is interrupted by the periodic jump of the bias voltage, thereby inducing lattice mismatch at the nanoscale.

[0019] In one possible implementation, in step S4, the fluorine-containing reactive gas is selected from high-purity gases such as nitrogen trifluoride, carbon tetrafluoride, or sulfur hexafluoride; an inductively coupled plasma source is used to dissociate the fluorine-containing gas separately, with a dissociation power of 800 watts to 1500 watts, to ensure that fluorine atoms form substituted solid solutions rather than agglomerated fluoride inclusions in the coating matrix.

[0020] In one possible implementation, step S5, the stepped annealing process includes: heating to 400 degrees Celsius at a rate of 2 degrees Celsius per minute and holding at that temperature for 2 hours; then heating to 650 to 800 degrees Celsius at a rate of 1 degree Celsius per minute and holding at that temperature for 4 hours; and finally, naturally cooling to room temperature with the furnace.

[0021] The wafer-level corrosion-resistant coating of this invention is attached to the inactive surface of a wafer substrate or the surface of a semiconductor cavity consumable. From the substrate outwards, it consists of a thermal stress gradient buffer layer, a stress dissipation nanolayer, and a high-density halogen-resistant barrier layer. Each layer achieves synergistic effects through atomic-level interface design, rather than simple mechanical stacking. The specific structure is as follows: The thermal stress gradient buffer layer is a silicon- and nitrogen-rich amorphous compound layer with a compositional gradient along its thickness. The molar percentage of silicon atoms closer to the substrate is greater than that closer to the outer layer. This layer acts as a thermodynamic buffer structure between the silicon or silicon carbide substrate and the upper heavy metal oxide layer. Through a continuous and gradual change in composition, the lattice constant and coefficient of thermal expansion smoothly transition from the substrate to the upper layer, eliminating thermal stress concentration caused by abrupt interface changes and improving the bonding stability between the coating and the substrate.

[0022] Stress-dissipating nanolayers are deposited and grown on a thermal stress gradient buffer layer, consisting of at least 20 alternating periods of first and second dielectric sublayers. The first dielectric sublayer is amorphous aluminum nitride or aluminum oxynitride, while the second dielectric sublayer is stabilized zirconium oxide or yttrium oxide. Incoherent grain boundaries are formed between adjacent sublayers. By leveraging the differences in crystal structure and elastic modulus between the two materials, dense incoherent grain boundaries are constructed at the sub-nanometer scale, forming a three-dimensional structure that intercepts cracks, dissipates plasma bombardment energy, and inhibits microcrack initiation and propagation.

[0023] A highly dense halogen-resistant barrier layer is deposited on the surface of a stress-dissipating nanolayer. The material is a rare-earth-doped yttrium oxide composite phase material that has undergone in-situ plasma fluorination treatment, forming a cross-linked YOF bond network inside. Through in-situ gas-phase fluorination technology, fluorine atoms are actively embedded into the crystal lattice to form stable chemical bonds. At the same time, the segregation effect of doped rare-earth elements at the grain boundaries is utilized to block the grain boundary penetration channels, achieving dual protection against halogen plasma through chemical passivation and physical barrier.

[0024] The preparation method of this invention employs a continuous vacuum integrated process to avoid the impact of atmospheric exposure on coating performance. The specific steps are as follows: Step S1, substrate surface activation: The wafer substrate to be processed is placed in the reaction chamber, and a mixture of argon and hydrogen gas is introduced to excite inductively coupled plasma to etch and clean the substrate surface, remove the natural oxide layer on the surface and expose dangling bonds, providing stable binding sites for subsequent buffer layer growth.

[0025] Step S2: Dynamic plasma-enhanced atomic layer deposition to construct a thermal stress gradient buffer layer: Using silicon and nitrogen precursors as reactants, a silicon-rich and nitrogen-rich buffer layer with gradient changes in composition and modulus is grown in situ on the substrate surface by nonlinearly decreasing the pulse time of the silicon precursor and synchronously increasing the pulse time of the nitrogen precursor, so as to achieve a smooth transition of modulus from the substrate side to the upper layer.

[0026] Step S3: Magnetron sputtering to construct stress-dissipating nanolayers: Without disrupting the vacuum, the substrate is transferred to a multi-target sputtering chamber. Using dual-target co-sputtering or alternating sputtering modes, the first and second dielectric sublayers are deposited alternately at a constant substrate temperature. By controlling the periodic jumps in sputtering power and substrate bias, high-density incoherent grain boundaries are induced between the sublayers.

[0027] Step S4: In-situ fluorination coupled with physical vapor deposition to construct a high-density halogen-resistant barrier layer: While depositing rare earth-doped yttrium oxide by physical vapor deposition, a fluorine-containing reactive gas is pulsed into the chamber. The in-situ excited fluorine radicals react with the deposited atoms in the gas phase or on the surface phase, solidifying to form a dense barrier layer with a YOF bonding network, simultaneously achieving chemical passivation and grain boundary sealing.

[0028] Step S5, Step annealing to eliminate internal stress: Vacuum step heating annealing is performed on the wafer after deposition. Through slow heating, segmented holding and natural cooling, atomic-level interdiffusion occurs at the interface of each layer, which enhances the interlayer bonding force, releases the residual internal stress accumulated during the deposition process, and improves the overall mechanical stability of the coating.

[0029] The present invention has the following beneficial effects: (1) The combination of the component gradient design of the thermal stress gradient buffer layer of the present invention with the stepped annealing process significantly improves the bonding strength between the coating and the silicon substrate, and can achieve zero peeling in the harsh thermal shock cycle aging test, effectively solving the industry problem of interface thermal mismatch.

[0030] (2) The non-coherent grain boundary structure of the stress dissipation nanolayer of the present invention can effectively suppress the initiation and convergence of microcracks. Under long-term plasma bombardment, only uniform atomic-level loss occurs on the coating surface, and no blocky peeling is generated, which greatly improves the wafer processing yield.

[0031] (3) The YOF bonding network and rare earth grain boundary sealing technology of the high-density halogen barrier layer of the present invention significantly reduce the physical and chemical etching rate of the coating in the halogen plasma environment, significantly extend the service life of the coating, and reduce the equipment consumable maintenance cost and downtime frequency of semiconductor wafer fabs.

[0032] (4) The preparation process of the present invention adopts a continuous vacuum integrated process, which does not require atmospheric exposure, avoids contamination of the coating interface, and is perfectly compatible with existing semiconductor wafer manufacturing processes, making it easy to industrialize and mass-produce. Attached Figure Description

[0033] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0034] Figure 1 This is a schematic flowchart of the wafer-level corrosion-resistant coating preparation method of the present invention; Figure 2 This is a block diagram of the wafer-level corrosion-resistant coating of the present invention; Figure 3 This is a schematic diagram of the structure of the electronic device of the present invention. Detailed Implementation

[0035] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0036] Figure 1 This is a schematic flowchart of a wafer-level corrosion-resistant coating preparation method according to an embodiment of the present invention.

[0037] like Figure 2 The diagram shown illustrates a module diagram of the wafer-level corrosion-resistant coating of this invention. It should be noted that if substantially the same result is achieved, the method described in this application is not necessarily the same. Figure 1 The sequence of processes shown is limited. Example

[0038] This embodiment is used for back-side protection of 12-inch single-crystal silicon wafers and for the surface of key load-bearing components of etching equipment. It can withstand long-term bombardment by high-density nitrogen trifluoride and sulfur hexafluoride mixed plasma, achieving zero particle shedding. The specific preparation steps are as follows: Step S1, Substrate Surface Activation: A cleaned 12-inch silicon wafer is transferred into the pretreatment chamber of an ultra-high vacuum composite deposition system. An argon-hydrogen mixture is introduced at a ratio of 80:20. The chamber pressure is controlled at 0.5 Pa, and inductively coupled plasma is excited. The radio frequency power is set to 1000 W to bombard the wafer surface. Hydrogen radicals can selectively remove the native oxide layer on the silicon surface and simultaneously form a large number of active dangling bonds on the silicon lattice surface, providing stable chemical bonding sites for the subsequent in-situ growth of the buffer layer.

[0039] Step S2, Plasma-Enhanced Atomic Layer Deposition Growth of the Thermal Stress Gradient Buffer Layer: The wafer is transferred to the plasma-enhanced atomic layer deposition chamber under in-situ high vacuum conditions, and the substrate temperature is controlled to be constant at 300 degrees Celsius. Bis(diethylamino)silane is used as the silicon precursor, and ammonia plasma is used as the nitrogen precursor, and a nonlinear cyclic deposition strategy is executed.

[0040] During the initial 50 deposition cycles, the pulse time for bis(diethylamino)silane was set to 0.8 seconds, and the pulse time for ammonia plasma was set to 0.2 seconds. At this stage, a silicon-rich amorphous network was formed with a Young's modulus of approximately 140 GPa, which highly matched the modulus of the silicon substrate. In the subsequent 300 deposition cycles, the pulse time for bis(diethylamino)silane was gradually shortened to 0.2 seconds, while the bombardment time for ammonia plasma was gradually extended to 0.8 seconds, achieving a continuous gradient in composition. Ultimately, a silicon-rich and nitrogen-rich buffer layer with a thickness of approximately 80 nanometers was grown on the wafer surface, with its Young's modulus smoothly transitioning from 140 GPa on the substrate side to 200 GPa on the top layer, effectively mitigating thermal stress concentration.

[0041] Step S3, bias-jump magnetron sputtering preparation of stress dissipation nanolayers: After the buffer layer is deposited, the wafer is seamlessly transferred into the multi-target co-sputtering physical vapor deposition chamber, the aluminum nitride target and the zirconium oxide target doped with 3% erbium oxide are turned on, and a mixed reaction atmosphere of argon, oxygen and nitrogen is introduced to perform the alternating deposition process.

[0042] During the deposition of the first dielectric sublayer (amorphous aluminum oxynitride), the target power was controlled at a medium level, and the RF bias applied to the wafer substrate was set to -40 volts. The low bias reduced the mobility of adsorbed atoms, forming a loose amorphous network, with the thickness of a single sublayer precisely controlled at 3 nanometers. Subsequently, the deposition of the second dielectric sublayer (erbium oxide-doped zirconium oxide) was switched, and the substrate bias was jumped to -100 volts. The high bias imparted higher kinetic energy to the deposited atoms, causing them to form a dense columnar crystal structure, with the thickness of a single sublayer controlled at 5 nanometers. This alternating deposition process was repeated for 40 cycles, forming a nanolayer stack with a total thickness of approximately 320 nanometers. 79 clear incoherent grain boundaries were formed between the sublayers, constructing a three-dimensional structure to intercept microcracks.

[0043] Step S4: In-situ fluorination deposition of a high-density halogen-resistant barrier layer: The wafer is transferred to the in-situ fluorination deposition chamber. A composite yttrium target doped with 10% by mass of gadolinium oxide and erbium oxide is activated, and a mixture of argon and oxygen is introduced, while high-purity carbon tetrafluoride gas is pulsed in. An independent remote inductively coupled plasma source is turned on, and the dissociation power is set to 1200 watts to completely dissociate the carbon tetrafluoride into highly reactive fluorine radicals.

[0044] During the gas-phase process of target atoms flying towards the wafer surface and the surface solidification and crystallization process, fluorine radicals react with the deposited atoms to form a cross-linked YOF ternary non-stoichiometric bonding network in situ. Simultaneously, due to the difference in ionic radius between the doped gadolinium and erbium ions and yttrium ions, under the surface thermal migration effect brought about by plasma bombardment, spontaneously segregate and enrich towards the columnar grain boundaries, forming an amorphous sealing layer that completely blocks the grain boundary penetration channels. Ultimately, a highly dense halogen-resistant barrier layer with a thickness of 1.5 micrometers and a surface roughness Ra of less than 0.3 nanometers is formed.

[0045] Step S5, Stepped Annealing: The deposited wafer is placed in a vacuum annealing furnace and heated to 400 degrees Celsius at a rate of 2 degrees Celsius per minute, and held for 2 hours to allow misaligned atoms inside the coating to rearrange short-range. Then, the temperature is increased to 750 degrees Celsius at a rate of 1 degree Celsius per minute and held for 4 hours to promote atomic-level thermal interdiffusion at the interfaces of each layer and form a chemical metallurgical bond. Finally, the wafer is allowed to cool naturally to room temperature in the furnace to release the residual internal stress accumulated during the deposition process and allow the coating to reach a mechanically stable state.

[0046] Comparative experiments and effect verification: To verify the technical advantages of this invention, a control group experiment was set up: a pure yttrium oxide single-layer coating was prepared using a traditional atmospheric plasma spraying process. The coating thickness was consistent with that of the embodiments of this invention, without a thermal stress gradient buffer layer and stress dissipation nanolayers. Other preparation conditions were kept as consistent as possible with those of this invention. Two sets of wafers were placed on a commercial etching machine and subjected to a 200-hour accelerated bombardment lifetime test under the same extreme conditions (power 2500 watts, gas flow ratio of carbon tetrafluoride:oxygen:argon = 100:10:50 standard cubic centimeters per minute, chamber pressure 20 millitor). The test results are as follows: (1) In the rapid thermal cycling shock test from 20 degrees Celsius to 450 degrees Celsius, the pure yttrium oxide coating of the control group showed fish-scale-like peeling at the edge during the 120th cycle and large-area collapse during the 180th cycle; after 500 extreme thermal shocks, the coating of the embodiment of the present invention was detected by ultrasonic scanning microscope and the interface between the coating and the silicon substrate was still tightly bonded without delamination or hollowing, proving that the thermal stress gradient buffer layer can effectively relieve thermal shear stress.

[0047] (2) The coating thickness loss was accurately measured using an ellipsometry and a profilometer. The average etching loss rate of the control group was 45.2 nanometers per hour; the average etching loss rate of the coating in the embodiment of the present invention was only 3.8 nanometers per hour, and the protection life was extended by nearly 12 times. X-ray photoelectron spectroscopy depth analysis revealed that a large number of fluoride ions had invaded and destroyed the crystal lattice at 800 nanometers inside the coating of the control group; in the coating of the embodiment of the present invention, the penetration depth of fluoride was controlled within tens of nanometers of the surface layer, confirming the synergistic protective effect of YOF bonding network and rare earth grain boundary sealing.

[0048] (3) Surface defects on the wafer were statistically analyzed using a surface particle scanner. The control group's surface was covered with detached debris particles larger than 0.1 micrometers. The coating surface of the embodiment of the present invention was unusually smooth, and the increase in particles was close to zero. Cross-sectional observation under an electron microscope showed that the coating of the control group had a large number of penetrating microcracks. The occasional nanocracks on the surface of the coating of the embodiment of the present invention were all passivated and deflected when they extended to the stress dissipation nanolayer, effectively preventing the coating from pulverizing and falling off.

[0049] It should be noted that the various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For system-type embodiments, since they are basically similar to method embodiments, the description is relatively simple; relevant parts can be referred to the descriptions in the method embodiments.

[0050] like Figure 3 This is a schematic diagram of the structure of an electronic device provided in an embodiment of the present disclosure. It illustrates a structural schematic diagram suitable for implementing the electronic device in the embodiment of the present disclosure. Figure 3The electronic device shown is merely an example and should not be construed as limiting the functionality and scope of the embodiments disclosed herein.

[0051] like Figure 3 As shown, the electronic device includes a processor, a memory, and a communication interface. The memory stores a computer program, and when the processor executes the computer program, it implements the wafer-level corrosion-resistant coating preparation method of the aforementioned embodiments of this disclosure. The electronic device can exchange data with other devices or systems through the communication interface, enabling real-time updates and sharing of data information.

[0052] The processor in the aforementioned electronic device serves as its core, responsible for executing the computer program stored in the memory to implement various functions of a wafer-level corrosion-resistant coating preparation method. The processor can employ a high-performance multi-core CPU or a dedicated chip to meet the demands of complex calculations and real-time processing. The memory stores the operating system, applications, data, and computer programs. In this embodiment, the memory stores the computer program implementing the wafer-level corrosion-resistant coating preparation method. The memory can be RAM, ROM, Flash memory, or other types of non-volatile memory. The communication interface connects the electronic device to other devices or networks, enabling data transmission and exchange. In this embodiment, the communication interface supports multiple communication protocols and interface standards, such as Wi-Fi, Bluetooth, USB, and Ethernet, to meet communication needs in different scenarios.

[0053] For a detailed description of this embodiment, please refer to the corresponding descriptions in the foregoing embodiments, which will not be repeated here.

[0054] According to embodiments of the present disclosure, a computer-readable storage medium stores a computer program, which, when executed by a processor, performs the functions of the aforementioned wafer-level corrosion-resistant coating preparation method according to various embodiments of the present disclosure.

[0055] The aforementioned computer-readable storage media include, but are not limited to: optical storage media (e.g., CD-ROM and DVD), magneto-optical storage media (e.g., MO), magnetic storage media (e.g., magnetic tape or portable hard drive), media with built-in rewritable non-volatile memory (e.g., memory card), and media with built-in ROM (e.g., ROM cartridge).

[0056] For a detailed description of this embodiment, please refer to the corresponding descriptions in the foregoing embodiments, which will not be repeated here.

[0057] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A wafer-level corrosion-resistant coating, characterized in that, The corrosion-resistant coating is adhered to the inactive surface of the wafer substrate or the surface of the semiconductor cavity consumable, and comprises, from the substrate outwards, the following: A thermal stress gradient buffer layer, wherein the thermal stress gradient buffer layer is a silicon-rich and nitrogen-rich amorphous compound layer, and there is a composition gradient along the thickness direction inside it. The composition gradient is characterized by the molar proportion of silicon atoms on the side closer to the substrate being greater than the molar proportion of silicon atoms on the side closer to the outside. The stress dissipation nanolayer is deposited on the thermal stress gradient buffer layer and consists of at least 20 cycles of alternating deposition of a first dielectric sublayer and a second dielectric sublayer. The first dielectric sublayer is amorphous aluminum nitride or aluminum oxynitride, and the second dielectric sublayer is zirconium oxide or yttrium oxide modified with stabilizer doping. Incoherent grain boundaries are formed between adjacent sublayers. A high-density halogen-resistant barrier layer is deposited on the surface of the stress-dissipating nanolayer. The layer is made of a rare-earth-doped yttrium oxide composite phase material that has been treated with in-situ plasma fluorination. A cross-linked YOF bond network is formed in the composite phase material.

2. The wafer-level corrosion-resistant coating according to claim 1, characterized in that, The thickness of the thermal stress gradient buffer layer is 50 nanometers to 150 nanometers; within this thickness range, the Young's modulus near the substrate region is controlled between 130 GPa and 160 GPa, and the Young's modulus near the stress dissipation nanolayer region smoothly transitions to between 180 GPa and 220 GPa.

3. The wafer-level corrosion-resistant coating according to claim 1, characterized in that, In the stress-dissipating nanolayer, the thickness of a single first dielectric sublayer is 2 to 5 nanometers, and the thickness of a single second dielectric sublayer is 3 to 8 nanometers; the doping stabilizer is scandium oxide or erbium oxide, and its mass doping concentration in the second dielectric sublayer is 1.5% to 4.5%.

4. The wafer-level corrosion-resistant coating according to claim 1, characterized in that, The thickness of the high-density halogen-resistant barrier layer is 500 nanometers to 2000 nanometers; in the composite phase material, the doping amount of rare earth element M accounts for 2.5% to 12.5% ​​of the total rare earth and yttrium elements, and the doping amount of fluorine element accounts for 1.5% to 25% of the total mass of the composite phase material, wherein M is at least one rare earth element selected from gadolinium, erbium or neodymium.

5. The wafer-level corrosion-resistant coating according to claim 1, characterized in that, The microstructure of the high-density halogen-resistant barrier layer is a dense columnar crystal structure, and the grain boundaries of the columnar crystals are enriched with the doped rare earth elements; the surface roughness Ra of the halogen-resistant barrier layer is less than 0.5 nanometers.

6. A method for preparing a wafer-level corrosion-resistant coating as described in any one of claims 1-5, characterized in that, The process includes the following continuous vacuum integration steps: Step S1: Place the wafer substrate to be processed in the reaction chamber, introduce a mixture of argon and hydrogen gas, and excite inductively coupled plasma to etch and clean the substrate surface and expose the dangling bonds. Step S2: Using silicon and nitrogen precursors as reactants, during the deposition process, the pulse time of the silicon precursor is nonlinearly decreased while the pulse time of the nitrogen precursor is synchronously increased, so that a silicon-rich and nitrogen-rich buffer layer with gradient changes in composition and modulus is grown in situ on the substrate surface. Step S3: Without disrupting the vacuum, transfer the substrate to the multi-target sputtering chamber and use dual-target co-sputtering or alternating sputtering mode to alternately deposit the first and second dielectric sublayers at a constant substrate temperature. Control the sputtering power and substrate bias to induce the formation of high-density incoherent grain boundaries between the sublayers. Step S4: During the simultaneous deposition of rare earth-doped yttrium oxide using physical vapor deposition, a fluorine-containing reactive gas is pulsedly introduced into the chamber. The in-situ excited fluorine radicals react with the deposited atoms in the gas phase or on the surface, and finally solidify to form a dense barrier layer with a YOF bonding network. Step S5: Perform vacuum step heating annealing on the deposited wafer to promote atomic-level interdiffusion at the interfaces of each layer to enhance the interlayer bonding force.

7. The preparation method according to claim 6, characterized in that, In step S2, the silicon precursor is bissilane or hexachlorosilane, and the nitrogen precursor is ammonia plasma; the substrate temperature is maintained at 250 degrees Celsius to 350 degrees Celsius.

8. The preparation method according to claim 6, characterized in that, In step S3, the substrate bias voltage during the deposition of the first dielectric sublayer is set to -30V to -50V, and the substrate bias voltage during the deposition of the second dielectric sublayer is switched to -80V to -120V.

9. The preparation method according to claim 6, characterized in that, In step S4, the fluorine-containing reactive gas is selected from high-purity gases such as nitrogen trifluoride, carbon tetrafluoride, or sulfur hexafluoride; an inductively coupled plasma source is used to dissociate the fluorine-containing gas separately, with a dissociation power of 800 watts to 1500 watts.

10. The preparation method according to claim 6, characterized in that, In step S5, the stepped annealing process includes: heating to 400 degrees Celsius at a rate of 2 degrees Celsius per minute and holding at that temperature for 2 hours; then heating to 650 to 800 degrees Celsius at a rate of 1 degree Celsius per minute and holding at that temperature for 4 hours; and finally cooling naturally to room temperature with the furnace.

Images