A thermal shock resistant thermopile infrared temperature measurement method, device and electronic equipment

Abstract

This invention provides a thermopile infrared temperature measurement method, apparatus, and electronic device resistant to thermal shock, relating to the field of infrared detection technology. The method includes: acquiring a first voltage signal and a second voltage signal from a thermopile-type infrared detector chip; wherein the thermopile-type infrared detector chip includes a first thermopile pixel and a second thermopile pixel integrated on the same substrate and sharing a cold-junction isothermal structure; the first voltage signal is output from the first thermopile pixel, and the second voltage signal is output from the second thermopile pixel; performing a differential operation on the first voltage signal and the second voltage signal to obtain a differential signal; and calculating the temperature value of the target being measured based on the differential signal. This invention has the advantages of lower noise, smaller chip area, higher yield, and simpler calibration, significantly improving the temperature measurement stability of thermopile infrared detectors in applications such as ear thermometers and wearable devices.

Description

Technical Field

[0001] This invention relates to the field of infrared detection technology, and in particular to a thermopile infrared temperature measurement method, apparatus, and electronic equipment resistant to thermal shock. Background Technology

[0002] Thermopile infrared detectors utilize the Seebeck effect to achieve non-contact temperature measurement, and their output voltage can be expressed as V(t) = N*S(T)*[T] h (t)-T c (t)]. Where T is... h (t) represents the temperature of the hot end (absorption film), T c (t) represents the cold junction (silicon-based / frame) temperature. This device is widely used in devices such as ear thermometers and wearable watches.

[0003] However, in practical use, detectors frequently encounter sudden changes in ambient temperature (i.e., thermal shock), such as when inserted into the ear canal, placed close to the skin, or when there are changes in ambient airflow. Thermal shock is coupled to the chip through three paths: conduction (the pins, lead frame, die attach adhesive layer, etc., rapidly inject the temperature change of the package substrate into the chip); convection (external airflow or insertion action alters the convective heat transfer of the gas on the outer surface of the cap and inside the cavity); and radiation (the inner wall of the package, windows, and cap become additional sources of infrared radiation due to the instantaneous temperature change). Because the equivalent thermal capacity and equivalent thermal resistance of the hot and cold ends are different, their dynamic response speeds to external thermal disturbances differ, leading to T... h The presence of transient temperature difference components unrelated to target radiation in -Tc, known as thermal shock spurious signals, manifests as zero-point drift, transient overshoot / undershoot, and sensitivity drift, severely compromising temperature measurement stability.

[0004] To suppress thermal shock, existing technologies such as Melexis' MLX90632 employ a four-pixel differential architecture, utilizing multiple "blind pixels" to offset parasitic heat flux. However, this architecture has significant shortcomings: (1) the large number of pixels leads to a decrease in MEMS yield and high calibration costs; (2) differential operations amplify the noise amplitude to twice that of a single pixel; (3) it is highly sensitive to matching errors such as Seebeck coefficient, thermal conductivity, and absorptivity between pixels, requiring complex compensation algorithms; (4) the effective light-receiving area is reduced; and (5) residual errors still exist under temperature gradients.

[0005] Therefore, a thermopile infrared temperature measurement method, device, and electronic equipment resistant to thermal shock are proposed. Summary of the Invention

[0006] This specification provides a thermopile infrared temperature measurement method, device, and electronic equipment that are resistant to thermal shock. It has the advantages of lower noise, smaller chip area, higher yield, and simpler calibration, which significantly improves the temperature measurement stability of thermopile infrared detectors in applications such as ear thermometers and wearable devices.

[0007] This specification provides a thermal shock resistant thermopile infrared temperature measurement method, including: Acquire a first voltage signal and a second voltage signal from a thermopile-type infrared detector chip; wherein, the thermopile-type infrared detector chip includes a first thermopile pixel and a second thermopile pixel integrated on the same substrate and sharing a cold junction isothermal structure, the first voltage signal is output from the first thermopile pixel, and the second voltage signal is output from the second thermopile pixel. Perform a differential operation on the first voltage signal and the second voltage signal to obtain a differential signal; The temperature value of the target being measured is calculated based on the differential signal.

[0008] Optionally, the thermopile infrared detector chip includes a packaging base and an optimized thermal resistance structure; The optimized thermal resistance structure is disposed between the substrate and the packaging base, and is enlarged by the back-side release process, so that the substrate and the packaging base are in partial contact or suspended support state; The substrate is further provided with a thermal capacity enhancement structure, which is used to increase the thermal capacity of the substrate, including a silicon wall structure formed on the substrate and retained or thickened.

[0009] Optionally, the cold-end isothermal structure includes a metal isothermal layer; The metal isothermal layer achieves high in-plane thermal conductivity through one or a combination of the following methods: thickening the top metal layer to act as a heat diffuser, or using a combination of multiple metal layers and a dense array of vias, wherein the dense array of vias forms a vertical heat conduction channel in the cold end anchor region; the metal isothermal layer is also used to reflect impact heat radiation from the inner wall of the package.

[0010] Optionally, the common-mode component canceled by the differential operation includes the temperature drift component caused by external thermal shock, which simultaneously acts on the cold ends of the first thermopile pixel and the second thermopile pixel; wherein, the thermal shock pseudo-signal generated by the isothermal changes between the hot and cold ends caused by the thermal shock satisfies: The pseudo-signal is canceled out as a common-mode component in the differential operation; where, For the number of thermocouple pairs, The equivalent Seebeck coefficient, This refers to the hot end temperature. This is the cold end temperature.

[0011] Optionally, the shared cold-end isothermal structure ensures that the cold-end temperatures of the two pixels satisfy the following conditions under thermal shock: Therefore, the differential signal is approximately V. diff =V1 V2≈ S (T h1 T h2 The chip contains two thermopile pixels, ensuring that the first noise amplitude of the output after differential operation satisfies σ. out1 ≈ σ, and the output second noise amplitude of the four-pixel differential architecture satisfies σ. out2 ≈2σ; where, This refers to the cold end temperature of the first thermopile pixel. σ represents the cold end temperature of the second thermopile pixel, and σ represents the noise amplitude of a single pixel.

[0012] Optionally, the chip is packaged using vacuum packaging or inert gas filling to reduce the impact of heat convection on temperature measurement.

[0013] Optionally, the inner wall of the chip's packaging cap is provided with a gold-plated layer to reduce the radiative thermal shock of the inner wall of the packaging.

[0014] This specification provides a thermopile infrared temperature measurement device resistant to thermal shock, comprising: An acquisition module is used to acquire a first voltage signal and a second voltage signal from a thermopile-type infrared detector chip; wherein, the thermopile-type infrared detector chip includes a first thermopile pixel and a second thermopile pixel integrated on the same substrate and sharing a cold junction isothermal structure, the first voltage signal is output by the first thermopile pixel, and the second voltage signal is output by the second thermopile pixel. The transport module is used to perform a differential operation on the first voltage signal and the second voltage signal to obtain a differential signal; The calculation module is used to calculate the temperature value of the target being measured based on the differential signal.

[0015] Optionally, the thermopile infrared detector chip includes a packaging base and an optimized thermal resistance structure; The optimized thermal resistance structure is disposed between the substrate and the packaging base, and is enlarged by the back-side release process, so that the substrate and the packaging base are in partial contact or suspended support state; The substrate is further provided with a thermal capacity enhancement structure, which is used to increase the thermal capacity of the substrate, including a silicon wall structure formed on the substrate and retained or thickened.

[0016] Optionally, the cold-end isothermal structure includes a metal isothermal layer; The metal isothermal layer achieves high in-plane thermal conductivity through one or a combination of the following methods: thickening the top metal layer to act as a heat diffuser, or using a combination of multiple metal layers and a dense array of vias, wherein the dense array of vias forms a vertical heat conduction channel in the cold end anchor region; the metal isothermal layer is also used to reflect impact heat radiation from the inner wall of the package.

[0017] Optionally, the common-mode component canceled by the differential operation includes the temperature drift component caused by external thermal shock, which simultaneously acts on the cold ends of the first thermopile pixel and the second thermopile pixel; wherein, the thermal shock pseudo-signal generated by the isothermal changes between the hot and cold ends caused by the thermal shock satisfies: The pseudo-signal is canceled out as a common-mode component in the differential operation; where, For the number of thermocouple pairs, The equivalent Seebeck coefficient, This refers to the hot end temperature. This is the cold end temperature.

[0018] Optionally, the shared cold-end isothermal structure ensures that the cold-end temperatures of the two pixels satisfy the following conditions under thermal shock: Therefore, the differential signal is approximately V. diff =V1 V2≈ S (T h1 T h2 The chip contains two thermopile pixels, ensuring that the first noise amplitude of the output after differential operation satisfies σ. out1 ≈ σ, and the output second noise amplitude of the four-pixel differential architecture satisfies σ. out2 ≈2σ; where, This refers to the cold end temperature of the first thermopile pixel. σ represents the cold end temperature of the second thermopile pixel, and σ represents the noise amplitude of a single pixel.

[0019] Optionally, the chip is packaged using vacuum packaging or inert gas filling to reduce the impact of heat convection on temperature measurement.

[0020] Optionally, the inner wall of the chip's packaging cap is provided with a gold-plated layer to reduce the radiative thermal shock of the inner wall of the packaging.

[0021] This specification also provides an electronic device, wherein the electronic device includes: A processor; and a memory storing computer-executable instructions, which, when executed, cause the processor to perform any of the methods described above.

[0022] This specification also provides a computer-readable storage medium that stores one or more programs that, when executed by a processor, implement any of the methods described above.

[0023] In this invention, dual-pixel equal-weighted difference is used, and the output noise amplitude is approximately [amount missing] of the single-pixel noise. The noise amplitude of the four-pixel differential output is approximately twice that of the single-pixel noise. Compared to existing technologies, the differential channel of this invention naturally provides an improvement of approximately 3dB in signal-to-noise ratio, which is beneficial for improving temperature measurement resolution. The number of pixels is halved, and the number of MEMS release structures and thermocouple interconnects is significantly reduced, resulting in a more compact layout, smaller chip area, and higher manufacturing yield. Simultaneously, the calibration dimension is reduced, eliminating the need for complex multi-pixel matching calibration and significantly lowering testing and data structure costs. High tolerance for matching errors: This invention uses a "shared isothermal cold end" design to ensure that the cold end temperatures of the two pixels are approximately equal under thermal shock, directly canceling cold end common-mode disturbances after differential processing. This simplifies the requirement for matching accuracy from "strict symmetry of multiple parameters" to "only requiring two pixels to share the same isothermal region," significantly reducing zero-point residuals and temperature gradient residual sensitivity issues caused by process mismatches. This invention suppresses thermal shock through multiple pathways at the physical structure level: increasing the conductive thermal resistance between the substrate and the package base via a back-side release process reduces conductive thermal shock injection; increasing the substrate's thermal capacity by thickening the silicon wall slows down the substrate's own temperature change rate; and achieving rapid isothermalization of the cold end through the high in-plane thermal conductivity of the metal isothermal layer (thickened top Al or multi-layer metal + dense via array), while the metal layer reflects the shock thermal radiation from the inner wall of the package. These three factors work synergistically to effectively suppress thermal shock spurious signals introduced by conduction, convection, and radiation. This invention can be further combined with packaging technologies such as vacuum packaging, inert gas filling, and gold plating on the inner wall of the cap to reduce interference from thermal convection and radiation at the packaging level, achieving dual thermal shock resistance at both the chip and package levels. Attached Figure Description

[0024] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0025] Figure 1 A schematic diagram illustrating the principle of a thermopile infrared temperature measurement method for thermal shock resistance provided in the embodiments of this specification; Figure 2 A schematic diagram of the differential architecture design of a dual-pixel + isothermal cold end thermopile provided in the embodiments of this specification; Figure 3This is a schematic diagram showing the arrangement of the silicon substrate and metal layers in the embodiments provided in this specification; Figure 4 A schematic diagram of a thermal shock resistant thermopile infrared temperature measuring device provided in the embodiments of this specification; Figure 5 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this specification; Figure 6 This is a schematic diagram of a computer-readable medium provided for embodiments of this specification.

[0026] The attached diagram shows: 1. Silicon substrate; 2. Metal layer; 3. Release region; 4. Hot end thin film region; 5. Blind pixel infrared reflective layer. Detailed Implementation

[0027] The following description is intended to disclose the present invention and enable those skilled in the art to implement it. The preferred embodiments described below are merely examples, and other obvious variations will occur to those skilled in the art. The basic principles of the invention defined in the following description can be applied to other embodiments, modifications, improvements, equivalents, and other technical solutions that do not depart from the spirit and scope of the invention.

[0028] The following is in conjunction with the appendix Figure 1-6 Exemplary embodiments of the invention will be described more fully here. However, exemplary embodiments can be implemented in many forms and should not be construed as limiting the invention to the embodiments set forth herein. Rather, these exemplary embodiments are provided to make the invention more comprehensive and complete, and to facilitate a full communication of the inventive concept to those skilled in the art. The same reference numerals in the figures denote the same or similar elements, components, or parts, and therefore repeated descriptions of them are omitted.

[0029] Subject to the technical concept of this invention, the features, structures, characteristics or other details described in a particular embodiment may be combined in one or more other embodiments in a suitable manner.

[0030] In the description of specific embodiments, the features, structures, characteristics, or other details described in this invention are intended to enable those skilled in the art to fully understand the embodiments. However, it is not excluded that those skilled in the art can practice the technical solutions of this invention without one or more of the specific features, structures, characteristics, or other details.

[0031] The flowcharts shown in the accompanying drawings are merely illustrative and do not necessarily include all content and operations / steps, nor do they necessarily need to be performed in the described order. For example, some operations / steps can be broken down, while others can be combined or partially combined; therefore, the actual execution order may change depending on the specific circumstances.

[0032] The block diagrams shown in the accompanying drawings are merely functional entities and do not necessarily correspond to physically independent entities. That is, these functional entities can be implemented in software, in one or more hardware modules or integrated circuits, or in different network and / or processor devices and / or microcontroller devices.

[0033] The terms “and / or” or “and / or” include all combinations of any one or more of the listed items.

[0034] Figure 1 This is a schematic diagram illustrating the principle of a thermopile infrared temperature measurement method for thermal shock resistance provided in an embodiment of this specification. The method may include: S110: Acquire a first voltage signal and a second voltage signal from the thermopile infrared detector chip; wherein, the thermopile infrared detector chip includes a first thermopile pixel and a second thermopile pixel integrated on the same substrate and sharing a cold junction isothermal structure, the first voltage signal is output from the first thermopile pixel, and the second voltage signal is output from the second thermopile pixel. S120: Perform a differential operation on the first voltage signal and the second voltage signal to obtain a differential signal; S130: Calculate the temperature value of the target object based on the differential signal.

[0035] In the specific embodiments described in this specification, the hot-end temperature is determined by "absorbed radiant power + heat exchanged from the surroundings": The cold junction temperature is driven by heat exchange between the package and the external environment: In the formula: This is the equivalent heat capacity of the hot end; This is the equivalent heat capacity of the cold end; This represents the rate of change of the hot-end temperature with respect to time. This represents the rate of change of the cold junction temperature with respect to time. The net radiant power radiated by the target and absorbed by the hot end is a function of time t. The effective emissivity of the hot end surface; The effective emissivity of the cold end surface; The effective area of ​​the hot end participating in heat exchange; The effective area for heat exchange at the cold end; This is the absolute temperature of the inner surface of the encapsulated cavity; The equivalent thermal resistance between the hot and cold ends; The equivalent convective heat transfer coefficient between the gas inside the encapsulation cavity and the hot / cold end; The absolute temperature of the gas inside the encapsulated cavity; The absolute temperature of the package base or package support structure; This represents the equivalent thermal resistance between the cold end and the package base.

[0036] When the sensor is subjected to external thermal shock, the gas temperature inside the encapsulation cavity... Inner surface temperature and the temperature of the packaging substrate This can change rapidly, causing the sensor system to enter a transient non-isothermal state. At this time, heat is coupled to the hot end through radiation, convection, and conduction. and cold end Because the equivalent heat capacity and equivalent thermal resistance of the hot and cold ends are different, their dynamic response speeds to external thermal disturbances are different, thus... - A transient temperature difference component, unrelated to the target radiation, appears. This transient temperature difference component will be further reflected in the thermopile output voltage, forming a thermal shock pseudo-signal.

[0037] Optionally, the thermopile infrared detector chip includes a packaging base and an optimized thermal resistance structure; The optimized thermal resistance structure is disposed between the substrate and the packaging base, and is enlarged by the back-side release process, so that the substrate and the packaging base are in partial contact or suspended support state; The substrate is further provided with a thermal capacity enhancement structure, which is used to increase the thermal capacity of the substrate, including a silicon wall structure formed on the substrate and retained or thickened.

[0038] Optionally, the cold-end isothermal structure includes a metal isothermal layer; The metal isothermal layer achieves high in-plane thermal conductivity through one or a combination of the following methods: thickening the top metal layer to act as a heat diffuser, or using a combination of multiple metal layers and a dense array of vias, wherein the dense array of vias forms a vertical heat conduction channel in the cold end anchor region; the metal isothermal layer is also used to reflect impact heat radiation from the inner wall of the package.

[0039] In the specific implementation of this specification, for ordinary analog front-ends (such as TO-packaged sensors), thermal conduction is the main source of thermal shock, which directly affects the temperature of the cold end. Thermal radiation and thermal convection thermal shocks can be significantly reduced through packaging techniques such as vacuum packaging, filling with inert gas, and gold plating on the inner wall of the cap.

[0040] To address the aforementioned issues and effectively manage thermal shock, a differential thermopile architecture design of "dual-pixel + isothermal cold end" is proposed, as illustrated in the diagram below. Figure 2 .

[0041] 1) Improve the thermal resistance between the silicon substrate and the packaging base—reduce the amount of thermal shock entering the thermopile through conduction. Technical solution: Minimize contact between the silicon substrate and the packaging base, preferably using a back-release process; 2) Increase the heat capacity of the silicon substrate – thermal shock enters the substrate, but the substrate temperature change is small. Technical solution: Make the silicon wall of the silicon substrate as thick as possible; 3) Use a metal layer around the cold end to create an isothermal cold end – achieve high in-plane thermal conductivity through metal.

[0042] like Figure 3 As shown, technical solution 1: thicken the top layer Al (heat diffusion sheet, as thick and continuous as possible), the metal can simultaneously reflect the impact heat radiation from the cold end; Technical Solution 2: Multi-layer metal + dense through-hole array, that is, to make "vertical heat conduction channels" in the cold end anchor area to reduce thermal resistance and achieve high in-plane thermal conductivity for rapid isothermalization.

[0043] Optionally, the common-mode component canceled by the differential operation includes the temperature drift component caused by external thermal shock, which simultaneously acts on the cold ends of the first thermopile pixel and the second thermopile pixel; wherein, the thermal shock pseudo-signal generated by the isothermal changes between the hot and cold ends caused by the thermal shock satisfies: The pseudo-signal is canceled out as a common-mode component in the differential operation; where, For the number of thermocouple pairs, The equivalent Seebeck coefficient, This refers to the hot end temperature. This is the cold end temperature.

[0044] In the specific implementation of this specification: 1. Conduction perspective: Thermal shock is injected into the body through a "thermal resistance network". and .

[0045] (1) Key transmission path (the encapsulation / TO cap system is typical): Pins / lead frames / bonding wires: Metals with high thermal conductivity are one of the channels through which external temperature changes are "injected" into the chip most quickly; Die attach / adhesive layer / base: transmits the temperature changes of the package base to the silicon substrate (cold ends are mostly attached to the silicon substrate / frame).

[0046] (2) Mechanisms of influence on temperature measurement (the two most common types of "errors" when conduction is dominant): The cold end is pulled quickly → the output exhibits baseline drift / overshoot; If the external temperature change first Pull it up (or pull it down), and the membrane area Because of its small heat capacity but through Being "dragged along" again will produce a transient state: This radiation, which does not originate from the target, will be treated by the algorithm as a "target temperature change".

[0047] Structural temperature difference causes change in "equivalent thermal short circuit" →Response rate changes over time; Conductive thermal resistance Not a constant: thermal conductivity of the material Stress / contact thermal resistance and gas thermal conductivity (if gas is present) all change with temperature. Therefore, for the same radiant power... You will get different This manifests as sensitivity / response rate drift: .

[0048] 2. Convection perspective: When the external airflow / insertion into the ear canal / close to the skin, the "convective thermal shock" has a significant impact.

[0049] Convection heat transfer: It is extremely sensitive to airflow speed, direction, and cavity geometry (even a slight breeze, hand shaking, or insertion motion will change it). ); Convection primarily acts on the outer surface of the cap, the window, and the packaging base, and then couples to the chip through conduction / radiation.

[0050] Typical phenomena caused by convection: The outer casing temperature is rapidly increased by convection → which in turn increases the temperature of the cold junction through conduction. ; It manifests as zero-point drift and slow return of output, with the time scale often determined by the thermal capacity of the package (from tens of milliseconds to several seconds, depending on the package quality and heat transfer intensity).

[0051] If there is gas inside the cavity: convection / natural convection will form a "thermal bridge" between the window and the chip; This significantly reduces the equivalent thermal resistance (coupling thermal nodes that should be separated), making thermal shocks easier to conduct. and Synchronous pulling results in complex overshoot / undershoot patterns. (This is why many high-stability applications prefer vacuum or low pressure and use structural design to suppress flow within the cavity.) 3. Radiation angle: Thermal shock causes the package / window itself to become an infrared interference source.

[0052] Thermal radiation exchange (using Stefan-Boltzmann): ; At a certain work location Neighborhood linearization: ; Therefore, radiation under small temperature differences can also be regarded as an "equivalent radiation thermal resistance": ; Target temperature measurement relies on: ; However, when the inner wall of the window / cap / support experiences a rapid temperature change under thermal shock, they also radiate to the absorbing membrane: ; Therefore, the hot end receives a superposition of radiation from the "target + package", and the output becomes: 4. Differences in "time constant" among the three channels: Why thermal shock exhibits multiple changes.

[0053] Treating the system as a hot RC network, each channel corresponds to a time constant: ; Radiation to the membrane: Chang Xiao Small → Fast (ms-level to tens of milliseconds); Conducted to silicon-based / framework: Large and complex paths → slow (hundreds of milliseconds to seconds or even longer); Convection to the outer shell: varies with h. Instability leads to poor repeatability; Therefore, "thermal shock" is not a single process, but a multi-stage coupling: external temperature change → first affecting the window and membrane through radiation / convection → then dragging the cold end away through conduction.

[0054] 5. Summary of the specific impacts on infrared thermometry results ("errors" from the physical to the algorithmic level).

[0055] Offset drift: and asynchronous changes lead to A bias term that is irrelevant to the target appears.

[0056] Transient overshoot / undershoot: Transient changes in the radiative background of the window / cap raise or lower the power at the hot end, causing short-term reading jumps.

[0057] Sensitivity drift (gain drift): thermal resistance Seebeck coefficient Even the optical / thermal properties of the absorption layer change with temperature, causing the same target to correspond to different outputs.

[0058] Differential errors caused by directional / non-uniform thermal fields: When temperature changes come from one side (insertion, wind direction, finger contact), the chip / package generates a lateral temperature gradient, and single-point or multi-pixel differential structures will exhibit residuals of varying degrees.

[0059] Optionally, the shared cold-end isothermal structure ensures that the cold-end temperatures of the two pixels satisfy the following conditions under thermal shock: Therefore, the differential signal is approximately V. diff =V1 V2≈ S (T h1 T h2 The chip contains two thermopile pixels, ensuring that the first noise amplitude of the output after differential operation satisfies σ. out1 ≈ σ, and the output second noise amplitude of the four-pixel differential architecture satisfies σ. out2 ≈2σ; where, This refers to the cold end temperature of the first thermopile pixel. σ represents the cold end temperature of the second thermopile pixel, and σ represents the noise amplitude of a single pixel.

[0060] In the specific implementation of this specification, to suppress thermal shock, the commonly used thermal shock-resistant architecture in industry is differential. The essence of this architecture is to use "blind pixels" to measure and cancel parasitic heat flux, i.e., thermal shock. A typical product is Melexis's mlx90632 surface-mount sensor system, which employs a four-pixel differential architecture combined with an integrated digital and analog circuitry architecture, achieving excellent differential performance. However, this type of architecture has the following shortcomings: 1) Mass Production and Cost: More Pixels and Computing Circuits: More MEMS structures mean greater pressure on yield; More calibration / coefficients → Devices are factory calibrated, coefficients are stored in EEPROM, and To / Ta is calculated externally (which also means testing / calibration and data structure costs).

[0061] 2) The noise will increase: Differentiation is the sum of variances. After differentiating, the noise amplitude is larger. If the noise of the four pixels is independent and the variances are similar, this will increase the noise amplitude. ,but That is, the output noise amplitude is about twice as much.

[0062] 3) Differential methods are very sensitive to "matching errors": residuals will be revealed if the absorptivity, stress, or heat capacity are asymmetrical. Differential cancellation is contingent upon: a high degree of matching in Seebeck coefficient, thermocouple resistance, thermal conductivity, absorptivity, and front-end gain; and strictly symmetrical geometric / thermal boundary conditions. If mismatches occur (e.g., MEMS film thickness, support beam dimensions, gap between the package cover and the film, differences in reflective / shielding layer processes, stress warping, etc.), the following will occur after differential cancellation: Zero-point residual (offset); Residual sensitivity to temperature gradients (items that were supposed to be eliminated were not completely eliminated). This will force you to perform more intensive calibration / compensation (Melexis also emphasizes that it maintains stability under thermal perturbations through its compensation algorithm).

[0063] 4) The effective light-receiving area is reduced: If the total chip area is fixed, then more pixels mean a decrease in effective absorption area, and the target signal amplitude will be smaller under the same optical conditions.

[0064] 5) The temperature gradient still exists over a certain measurement time: The Mlx90632 datasheet also warns that IR sensors experience increased errors under non-isothermal / gradient conditions, and device accuracy is guaranteed under "stable isothermal conditions." Temperature gradient compensation algorithms can only improve the accuracy to a certain extent, not completely eliminate the error.

[0065] If the two pixels are made to share the same true isothermal cold end (large heat diffusion layer + good thermal contact), then Doing the wrong thing: In other words, the cold junction common-mode disturbance is structurally canceled out. In thermocouple measurements, this corresponds to the idea of ​​"isothermal block / cold junction isothermization": as long as the junction is isotherm, the stray heat potentials can cancel each other out; otherwise, the temperature gradient will directly become a source of error.

[0066] Using the simplest "equal weight difference": 2-pixel difference: noise synthesis approximately ; 4-pixel (±1 weighted) difference: noise synthesis approximately ; Equal single-pixel noise Below, 2 pixels naturally have about 3dB less noise degradation in the differential channel (provided that too much responsivity is sacrificed due to the structure).

[0067] Fewer pixels, fewer MEMS film structures, and fewer interconnects typically mean: a more compact layout, smaller die area (more controllable cost); fewer mismatch points introduced by film release / stress / warpage (better yield); lower calibration dimensionality (easier to stabilize the model); and better handling of pixel mismatches.

[0068] Melexis' own thermal / mechanical design recommendations explicitly state that a larger thermal mass can reduce "thermal noise" caused by airflow, and suggest using an additional thermally conductive metal cover / structure to "smooth" thermal fluctuations and uniformly distribute the package temperature. This aligns with the design philosophy of "isothermal cold end": using thermal diffusion to smooth out high-frequency, localized disturbances.

[0069] Optionally, the chip is packaged using vacuum packaging or inert gas filling to reduce the impact of heat convection on temperature measurement.

[0070] Optionally, the inner wall of the chip's packaging cap is provided with a gold-plated layer to reduce the radiative thermal shock of the inner wall of the packaging.

[0071] In this invention, dual-pixel equal-weighted difference is used, and the output noise amplitude is approximately [amount missing] of the single-pixel noise. The noise amplitude of the four-pixel differential output is approximately twice that of the single-pixel noise. Compared to existing technologies, the differential channel of this invention naturally provides an improvement of approximately 3dB in signal-to-noise ratio, which is beneficial for improving temperature measurement resolution. The number of pixels is halved, and the number of MEMS release structures and thermocouple interconnects is significantly reduced, resulting in a more compact layout, smaller chip area, and higher manufacturing yield. Simultaneously, the calibration dimension is reduced, eliminating the need for complex multi-pixel matching calibration and significantly lowering testing and data structure costs. High tolerance for matching errors: This invention uses a "shared isothermal cold end" design to ensure that the cold end temperatures of the two pixels are approximately equal under thermal shock, directly canceling cold end common-mode disturbances after differential processing. This simplifies the requirement for matching accuracy from "strict symmetry of multiple parameters" to "only requiring two pixels to share the same isothermal region," significantly reducing zero-point residuals and temperature gradient residual sensitivity issues caused by process mismatches. This invention suppresses thermal shock through multiple pathways at the physical structure level: increasing the conductive thermal resistance between the substrate and the package base via a back-side release process reduces conductive thermal shock injection; increasing the substrate's thermal capacity by thickening the silicon wall slows down the substrate's own temperature change rate; and achieving rapid isothermalization of the cold end through the high in-plane thermal conductivity of the metal isothermal layer (thickened top Al or multi-layer metal + dense via array), while the metal layer reflects the shock thermal radiation from the inner wall of the package. These three factors work synergistically to effectively suppress thermal shock spurious signals introduced by conduction, convection, and radiation. This invention can be further combined with packaging technologies such as vacuum packaging, inert gas filling, and gold plating on the inner wall of the cap to reduce interference from thermal convection and radiation at the packaging level, achieving dual thermal shock resistance at both the chip and package levels.

[0072] Figure 4 This is a schematic diagram of a thermopile infrared temperature measurement device resistant to thermal shock, provided as an embodiment of this specification. The device may include: The acquisition module 10 is used to acquire a first voltage signal and a second voltage signal of the thermopile infrared detector chip; wherein, the thermopile infrared detector chip includes a first thermopile pixel and a second thermopile pixel integrated on the same substrate and sharing a cold junction isothermal structure, the first voltage signal is output by the first thermopile pixel, and the second voltage signal is output by the second thermopile pixel. The transport module 20 is used to perform a differential operation on the first voltage signal and the second voltage signal to obtain a differential signal; The calculation module 30 is used to calculate the temperature value of the target being measured based on the differential signal.

[0073] Optionally, the thermopile infrared detector chip includes a packaging base and an optimized thermal resistance structure; The optimized thermal resistance structure is disposed between the substrate and the packaging base, and is enlarged by the back-side release process, so that the substrate and the packaging base are in partial contact or suspended support state; The substrate is further provided with a thermal capacity enhancement structure, which is used to increase the thermal capacity of the substrate, including a silicon wall structure formed on the substrate and retained or thickened.

[0074] Optionally, the cold-end isothermal structure includes a metal isothermal layer; The metal isothermal layer achieves high in-plane thermal conductivity through one or a combination of the following methods: thickening the top metal layer to act as a heat diffuser, or using a combination of multiple metal layers and a dense array of vias, wherein the dense array of vias forms a vertical heat conduction channel in the cold end anchor region; the metal isothermal layer is also used to reflect impact heat radiation from the inner wall of the package.

[0075] Optionally, the common-mode component canceled by the differential operation includes the temperature drift component caused by external thermal shock, which simultaneously acts on the cold ends of the first thermopile pixel and the second thermopile pixel; wherein, the thermal shock pseudo-signal generated by the isothermal changes between the hot and cold ends caused by the thermal shock satisfies: The pseudo-signal is canceled out as a common-mode component in the differential operation; where, For the number of thermocouple pairs, The equivalent Seebeck coefficient, This refers to the hot end temperature. This is the cold end temperature.

[0076] Optionally, the shared cold-end isothermal structure ensures that the cold-end temperatures of the two pixels satisfy the following conditions under thermal shock: Therefore, the differential signal is approximately V. diff =V1 V2≈ S (Th1 T h2 The chip contains two thermopile pixels, ensuring that the first noise amplitude of the output after differential operation satisfies σ. out1 ≈ σ, and the output second noise amplitude of the four-pixel differential architecture satisfies σ. out2 ≈2σ; where, This refers to the cold end temperature of the first thermopile pixel. σ represents the cold end temperature of the second thermopile pixel, and σ represents the noise amplitude of a single pixel.

[0077] Optionally, the chip is packaged using vacuum packaging or inert gas filling to reduce the impact of heat convection on temperature measurement.

[0078] Optionally, the inner wall of the chip's packaging cap is provided with a gold-plated layer to reduce the radiative thermal shock of the inner wall of the packaging.

[0079] The functions of the apparatus in this embodiment have been described in the above method embodiments. Therefore, for any parts not detailed in this embodiment, please refer to the relevant descriptions in the foregoing embodiments, which will not be repeated here.

[0080] Based on the same inventive concept, embodiments of this specification also provide an electronic device.

[0081] The following describes embodiments of the electronic device of the present invention, which can be considered as specific implementations of the methods and apparatus embodiments of the present invention described above. Details described in the embodiments of the electronic device of the present invention should be considered as supplements to the methods or apparatus embodiments described above; details not disclosed in the embodiments of the electronic device of the present invention can be implemented with reference to the methods or apparatus embodiments described above.

[0082] Figure 5 This is a schematic diagram of an electronic device provided as an embodiment of this specification. Refer to the following... Figure 5 The electronic device 300 according to this embodiment of the present invention will be described. Figure 5 The electronic device 300 shown is merely an example and should not impose any limitations on the functionality and scope of use of the embodiments of the present invention.

[0083] like Figure 5 As shown, the electronic device 300 is presented in the form of a general-purpose computing device. The components of the electronic device 300 may include, but are not limited to: at least one processing unit 310, at least one storage unit 320, a bus 330 connecting different system components (including storage unit 320 and processing unit 310), a display unit 340, etc.

[0084] The storage unit stores program code that can be executed by the processing unit 310, causing the processing unit 310 to perform the steps described in the processing method section of this specification according to various exemplary embodiments of the present invention. For example, the processing unit 310 can perform, for example... Figure 1 The steps are shown.

[0085] The storage unit 320 may include a readable medium in the form of a volatile storage unit, such as a random access memory unit (RAM) 3201 and / or a cache storage unit 3202, and may further include a read-only memory unit (ROM) 3203.

[0086] The storage unit 320 may also include a program / utility 3204 having a set (at least one) program module 3205, such program module 3205 including but not limited to: an operating system, one or more application programs, other program modules and program data, each or some combination of these examples may include an implementation of a network environment.

[0087] Bus 330 can represent one or more of several types of bus structures, including a memory cell bus or memory cell controller, a peripheral bus, a graphics acceleration port, a processing unit, or a local bus using any of the various bus structures.

[0088] Electronic device 300 can also communicate with one or more external devices 400 (e.g., keyboard, pointing device, Bluetooth device, etc.), and with one or more devices that enable viewers to interact with electronic device 300, and / or with any device that enables electronic device 300 to communicate with one or more other computing devices (e.g., router, modem, etc.). This communication can be performed via input / output (I / O) interface 350. Furthermore, electronic device 300 can also communicate with one or more networks (e.g., local area network (LAN), wide area network (WAN), and / or public networks, such as the Internet) via network adapter 360. Network adapter 360 can communicate with other modules of electronic device 300 via bus 330. It should be understood that, although... Figure 5 As not shown, other hardware and / or software modules may be used in conjunction with electronic device 300, including but not limited to: microcode, device drivers, redundant processing units, external disk drive arrays, RAID systems, tape drives, and data backup storage systems.

[0089] Through the above description of the embodiments, those skilled in the art will readily understand that the exemplary embodiments described in this invention can be implemented by software or by combining software with necessary hardware. Therefore, the technical solutions according to the embodiments of this invention can be embodied in the form of a software product, which can be stored in a computer-readable storage medium (such as a CD-ROM, USB flash drive, external hard drive, etc.) or on a network, including several instructions to cause a computing device (such as a personal computer, server, or network device, etc.) to execute the method described above according to this invention. When the computer program is executed by a data processing device, it enables the computer-readable medium to implement the method described above, i.e.: as... Figure 1 The method shown.

[0090] Figure 6 This is a schematic diagram of a computer-readable medium provided for embodiments of this specification.

[0091] accomplish Figure 1 The computer program of the method shown can be stored on one or more computer-readable media. A computer-readable medium can be a readable signal medium or a readable storage medium. A readable storage medium can be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination thereof. More specific examples of readable storage media (a non-exhaustive list) include: an electrical connection having one or more wires, a portable disk, a hard disk, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage device, magnetic storage device, or any suitable combination thereof.

[0092] The computer-readable storage medium may include data signals propagated in baseband or as part of a carrier wave, carrying readable program code. Such propagated data signals may take various forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination thereof. The readable storage medium may also be any readable medium other than a readable storage medium, capable of transmitting, propagating, or transmitting programs for use by or in connection with an instruction execution system, apparatus, or device. The program code contained on the readable storage medium may be transmitted using any suitable medium, including but not limited to wireless, wired, optical fiber, RF, etc., or any suitable combination thereof.

[0093] Program code for performing the operations of this invention can be written in any combination of one or more programming languages, including object-oriented programming languages ​​such as Java and C++, and conventional procedural programming languages ​​such as C or similar languages. The program code can execute entirely on the audience's computing device, partially on the audience's device, as a standalone software package, partially on the audience's computing device and partially on a remote computing device, or entirely on a remote computing device or server. In cases involving remote computing devices, the remote computing device can be connected to the audience's computing device via any type of network, including a local area network (LAN) or a wide area network (WAN), or it can be connected to an external computing device (e.g., via the Internet using an Internet service provider).

[0094] In summary, the present invention can be implemented in hardware, or as software modules running on one or more processors, or a combination thereof. Those skilled in the art will understand that in practice, general-purpose data processing devices such as microprocessors or digital signal processors (DSPs) can be used to implement some or all of the functions of some or all of the components according to the embodiments of the present invention. The present invention can also be implemented as a device or apparatus program (e.g., a computer program and computer program product) for performing part or all of the methods described herein. Such programs implementing the present invention can be stored on a computer-readable medium or can be in the form of one or more signals. Such signals can be downloaded from an Internet website, provided on a carrier signal, or provided in any other form.

[0095] The specific embodiments described above further illustrate the purpose, technical solution, and beneficial effects of the present invention. It should be understood that the present invention is not inherently related to any specific computer, virtual device, or electronic device, and various general-purpose devices can also implement the present invention. The above descriptions are merely specific embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

[0096] The various embodiments in this specification are described in a progressive manner. The same or similar parts between the various embodiments can be referred to each other. Each embodiment focuses on describing the differences from other embodiments.

[0097] The above description is merely an embodiment of this application and is not intended to limit the scope of this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of the claims of this application.

Claims

1. A thermopile infrared thermometry method resistant to thermal shock, characterized in that, include: Acquire a first voltage signal and a second voltage signal from a thermopile-type infrared detector chip; wherein, the thermopile-type infrared detector chip includes a first thermopile pixel and a second thermopile pixel integrated on the same substrate and sharing a cold junction isothermal structure, the first voltage signal is output from the first thermopile pixel, and the second voltage signal is output from the second thermopile pixel. Perform a differential operation on the first voltage signal and the second voltage signal to obtain a differential signal; The temperature value of the target being measured is calculated based on the differential signal.

2. The infrared thermometry method for thermal shock resistant thermopile as described in claim 1, characterized in that, The thermopile infrared detector chip includes a packaging base and an optimized thermal resistance structure. The optimized thermal resistance structure is disposed between the substrate and the packaging base, and is enlarged by the back-side release process, so that the substrate and the packaging base are in partial contact or suspended support state; The substrate is further provided with a thermal capacity enhancement structure, which is used to increase the thermal capacity of the substrate, including a silicon wall structure formed on the substrate and retained or thickened.

3. The infrared thermometry method for thermal shock resistant thermopile as described in claim 1, characterized in that, The cold-end isothermal structure includes a metal isothermal layer; The metal isothermal layer achieves high in-plane thermal conductivity through one or a combination of the following methods: thickening the top metal layer to act as a heat diffuser, or using a combination of multiple metal layers and a dense array of vias, wherein the dense array of vias forms a vertical heat conduction channel in the cold end anchor region; the metal isothermal layer is also used to reflect impact heat radiation from the inner wall of the package.

4. The infrared thermometry method for thermal shock resistant thermopile as described in claim 1, characterized in that, The common-mode components canceled by the differential operation include temperature drift components caused by external thermal shock that simultaneously act on the cold ends of the first and second thermopile pixels; wherein, the thermal shock pseudo-signal generated by the isothermal changes between the hot and cold ends caused by the thermal shock satisfies: The pseudo-signal is canceled out as a common-mode component in the differential operation; where, For the number of thermocouple pairs, The equivalent Seebeck coefficient, This refers to the hot end temperature. This refers to the cold end temperature.

5. The infrared thermometry method for thermal shock resistant thermopile as described in claim 1, characterized in that, The shared cold-end isothermal structure ensures that the cold-end temperatures of the two pixels meet the following conditions under thermal shock: Therefore, the differential signal is approximately V. diff =V1 V2≈ S (T h1 T h2 The chip contains two thermopile pixels, ensuring that the first noise amplitude of the output after differential operation satisfies σ. out1 ≈ σ, and the output second noise amplitude of the four-pixel differential architecture satisfies σ. out2 ≈2σ; where, This refers to the cold end temperature of the first thermopile pixel. σ represents the cold end temperature of the second thermopile pixel, and σ represents the noise amplitude of a single pixel.

6. The infrared thermometry method for thermal shock resistant thermopile as described in claim 1, characterized in that, The chip is packaged using vacuum packaging or inert gas filling to reduce the impact of heat convection on temperature measurement.

7. The infrared thermometry method for thermal shock resistant thermopile as described in claim 1, characterized in that, The inner wall of the chip's packaging cap is plated with a gold layer to reduce the radiative thermal shock of the inner wall of the packaging.

8. A thermopile infrared temperature measuring device resistant to thermal shock, characterized in that, include: An acquisition module is used to acquire a first voltage signal and a second voltage signal from a thermopile-type infrared detector chip; wherein, the thermopile-type infrared detector chip includes a first thermopile pixel and a second thermopile pixel integrated on the same substrate and sharing a cold junction isothermal structure, the first voltage signal is output by the first thermopile pixel, and the second voltage signal is output by the second thermopile pixel. The transport module is used to perform a differential operation on the first voltage signal and the second voltage signal to obtain a differential signal; The calculation module is used to calculate the temperature value of the target being measured based on the differential signal.

9. An electronic device, wherein, The electronic device includes: A processor; and a memory storing computer-executable instructions, which, when executed, cause the processor to perform the method according to any one of claims 1-7.

10. A computer-readable storage medium, wherein, The computer-readable storage medium stores one or more programs that, when executed by a processor, implement the method of any one of claims 1-7.

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