Interference-resistant Bode plot test fixture and interference-resistant Bode plot test system

Abstract

This invention discloses an interference-resistant Bod plot test fixture and an interference-resistant Bod plot test system, relating to the field of hardware testing technology. The interference-resistant Bod plot test fixture, manufactured using PCB technology, includes: differential lines, probes, SMA connectors, and reserved test connectors; the reserved test connectors include test pins or test hooks; the probes are connected to the starting point of the differential lines, the reserved test connectors are located between the starting and ending points of the differential lines, and the SMA connectors are connected to the ending point of the differential lines. The technical solution of this invention can improve the testing efficiency of high-density circuit boards, reduce test interference, and effectively improve the accuracy of test results.

Description

Technical Field

[0001] This invention relates to the field of hardware testing technology, and more particularly to an interference-resistant Bodé plot test fixture and an interference-resistant Bodé plot test system. Background Technology

[0002] like Figure 1 As shown, traditional Bode plot testing typically involves injecting a signal using a test clip, and the injected signal needs to be connected to both ends of the injection resistor via a 1:1 test probe. Whether using a test probe or a test clip, wiring is required on the board for testing.

[0003] However, with the increasing density of GPU (Graphics Processing Unit) boards, the number of physical test points that can be injected for Bode plot testing is getting smaller and smaller. For example, 0201 resistors are difficult to solder, making high-density boards not only inefficient to test but also difficult to test. Secondly, the close proximity of power supplies at different load points generates a large amount of interference signals. Traditional test solutions have long leads without shielding, making the injected signals susceptible to interference and causing errors in the test results. Summary of the Invention

[0004] This invention provides an interference-resistant Bode plot test fixture and an interference-resistant Bode plot test system to solve the problems of high difficulty in testing existing circuit boards and the susceptibility of injected signals to interference.

[0005] According to one aspect of the present invention, an interference-resistant Bod plot test fixture is provided, which is manufactured using PCB (Printed Circuit Board) technology and includes: differential lines, probes, SMA (Sub-Miniature version A Connector) heads, and reserved test connectors; wherein the reserved test connectors include test pins or test hooks; The probe is connected to the starting point of the differential line, the reserved test connector is located between the starting and ending points of the differential line, and the SMA connector is connected to the ending point of the differential line.

[0006] According to another aspect of the present invention, an interference-resistant Bode plot testing system is provided, comprising: an interference-resistant Bode plot testing fixture and a network analyzer in any embodiment; The SMA head of the anti-interference Bodplot test fixture is connected to the signal receiving interface of the network analyzer; the injected signal of the network analyzer is connected to the reserved test connector through the test clip; the probe is used to perform point testing on the test points of the PCB board under test.

[0007] According to another aspect of the present invention, an interference-resistant Bod graph testing method is provided, executed by a network analyzer in an interference-resistant Bod graph testing system, comprising: After the probes of the Bodetu test fixture in the Bodetu test system are connected to the test points of the PCB board under test, the network analyzer is set to single scan mode and the test parameters of the network analyzer are configured. Based on the acquisition signals from the SMA head of the Bode plot test fixture and the reserved test connector in the Bode plot test system, a Bode plot is plotted.

[0008] The technical solution of this invention utilizes PCB manufacturing processes to create an interference-resistant Bode plot test fixture. The probes in the Bode plot test fixture are connected to the starting points of the differential lines, and a reserved test connector is located between the starting and ending points of the differential lines. An SMA connector is connected to the ending point of the differential lines. In this solution, the probes of the Bode plot test fixture have a higher compatibility with increasingly smaller test points on high-density boards, reducing testing difficulty and effectively improving testing efficiency. Furthermore, the separated layout of the reserved test connector and the SMA connector in the Bode plot test fixture can significantly shield interference caused by long leads in a physical dimension, solving the problems of high testing difficulty and susceptibility to interference with injected signals in existing boards. This improves the testing efficiency of high-density boards, reduces test interference, and effectively enhances the accuracy of test results.

[0009] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0010] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0011] Figure 1 This is a schematic diagram of a traditional Bode plot test scenario; Figure 2 The PCB layout diagram for the Bode plot test fixture; Figure 3 This is a schematic diagram of an anti-interference Bode plot test system provided in Embodiment 2 of the present invention; Figure 4 A schematic diagram of a network analyzer that can be used to implement embodiments of the present invention is shown. Detailed Implementation

[0012] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0013] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0014] Example 1 The anti-interference Bod plot test fixture is suitable for high-density boards and other challenging testing scenarios. It is manufactured using PCB technology and includes: differential lines, probes, SMA connectors, and reserved test connectors. The reserved test connectors may include test pins or test hooks. The probes are connected to the starting point of the differential lines, the reserved test connectors are located between the starting and ending points of the differential lines, and the SMA connectors are connected to the ending point of the differential lines.

[0015] The differential lines can be traces in a Bode plot test fixture that lead out P and N signals. The P signal is a positive-phase differential signal, and the N signal is an inverted differential signal. The reserved test connector can be a component reserved between the start and end points of the differential lines for connection to external devices. For example, the reserved test connector can be used to connect to a test clip that outputs an injected signal from an external device.

[0016] In this embodiment of the invention, an interference-resistant Bodplot test fixture can be manufactured using PCB manufacturing processes. The Bodplot test fixture includes differential lines, probes, SMA connectors, and pre-installed test connectors. Multiple probes, SMA connectors, and pre-installed test connectors are available, and the specific number can be flexibly adjusted according to test connection requirements. The two ends of the differential lines in the Bodplot test fixture are connected to the probes and SMA connectors, respectively, and test pins or test hooks are symmetrically installed at the middle positions of the differential lines (not the start and end points).

[0017] In an optional embodiment of the present invention, the interference-resistant Bode plot test fixture may include: a top layer, a first inner layer, a second inner layer, and a bottom layer; wherein the top layer, the bottom layer, and the second inner layer are ground layers, and the differential lines are located in the first inner layer.

[0018] The first inner layer and the second inner layer are two adjacent layers in the anti-interference Bode plot test fixture.

[0019] In this embodiment of the invention, the anti-interference Bode plot test fixture has a four-layer printed circuit board structure, consisting of a top layer, a first inner layer, a second inner layer, and a bottom layer from top to bottom. The top layer, bottom layer, and second inner layer of the Bode plot test fixture are ground layers, and differential lines are laid on the first inner layer.

[0020] Optionally, the top layer, first inner layer, second inner layer, and bottom layer can be copper-free substrates, and differential lines can be generated in the first inner layer using chemical copper plating.

[0021] In an alternative embodiment of the invention, an interference-resistant Bode plot test fixture is provided with a grounding via punched around the differential line.

[0022] In this embodiment of the invention, the anti-interference Bod plot test fixture has uniformly grounded vias punched around the differential lines to improve the signal's anti-interference capability.

[0023] An exemplary PCB layout of a Bod plot test fixture for interference suppression with grounding vias around differential lines can be found in [reference needed]. Figure 2 .

[0024] In an alternative embodiment of the invention, the top and bottom layers of the interference-resistant Bode plot test fixture are copper-clad.

[0025] In an optional embodiment of the invention, the characteristic impedance of the differential lines in the interference-resistant Bode plot test fixture can be 50 ohms.

[0026] The characteristic impedance is the AC transient impedance.

[0027] In an optional embodiment of the invention, the number of probes is three, and the three probes are used to extract the differential signal and the fixture ground signal.

[0028] The differential signal includes the P signal and the N signal. The fixture ground signal is the GND signal.

[0029] In this embodiment of the invention, the Bode plot test fixture may have three probes. The three probes are used to extract the P signal, N signal, and fixture ground signal, respectively.

[0030] In an optional embodiment of the present invention, the spacing between the probes of the anti-interference Bode plot test fixture is consistent with the spacing between the reserved test points of the PCB board under test, and the number of reserved test points of the PCB board under test is three.

[0031] The PCB board under test can be a board tested using a Bode plot test fixture. Reserved test points can be pre-drilled test points on the PCB board under test that will contact the probes of the Bode plot test fixture. Optionally, the reserved test points on the PCB board under test may include P-signal test points, N-signal test points, and grounding points.

[0032] In this embodiment of the invention, the number of reserved test points on the PCB board under test is three. The spacing between the probes of the anti-interference Bode plot test fixture is consistent with the spacing between the reserved test points on the PCB board under test, so that the probes of the Bode plot test fixture can be connected to the reserved test points on the PCB board under test.

[0033] The technical solution of this invention utilizes PCB manufacturing processes to create an interference-resistant Bode plot test fixture. The probes in the Bode plot test fixture are connected to the starting points of the differential lines, and a reserved test connector is located between the starting and ending points of the differential lines. An SMA connector is connected to the ending point of the differential lines. In this solution, the probes of the Bode plot test fixture have a higher compatibility with increasingly smaller test points on high-density boards, reducing testing difficulty and effectively improving testing efficiency. Furthermore, the separated layout of the reserved test connector and the SMA connector in the Bode plot test fixture can significantly shield interference caused by long leads in a physical dimension, solving the problems of high testing difficulty and susceptibility to interference with injected signals in existing boards. This improves the testing efficiency of high-density boards, reduces test interference, and effectively enhances the accuracy of test results.

[0034] Example 2 Embodiment 2 of the present invention provides an interference-resistant Bod graph testing system, the specific implementation of which can be found in the following embodiments. Technical terms that are the same as or corresponding to those in the above embodiments will not be repeated here. Figure 3 This is a schematic diagram of an anti-interference Bode plot test system provided in Embodiment 2 of the present invention, as shown below. Figure 3 As shown, the interference-resistant Bod graph test system includes: an interference-resistant Bod graph test fixture and a network analyzer.

[0035] The SMA head of the anti-interference Bodplot test fixture is connected to the signal receiving interface of the network analyzer; the injected signal of the network analyzer is connected to the reserved test connector through the test clip; the probe can be used to perform point tests on the reserved test points of the PCB board under test.

[0036] Among them, the network analyzer is a high-precision electronic measuring instrument used to analyze the signal transmission and reflection characteristics of each port in radio frequency and microwave networks.

[0037] In this embodiment of the invention, an anti-interference Bodé plot test fixture and a network analyzer can constitute an anti-interference Bodé plot test system. The two SMA heads of the Bodé plot test fixture in the anti-interference Bodé plot test system are connected to the T signal (incident wave emitted through the test port) and R signal (reflected wave detected by the receiver after passing through the device under test) ports of the network analyzer, respectively. The reserved test connectors of the Bodé plot test fixture receive the injection signal transmitted by the network analyzer through the test clamp. When performing board testing based on the anti-interference Bodé plot test system, the probes of the Bodé plot test fixture are connected one-to-one with the reserved test points of the PCB board under test.

[0038] The interference-resistant Bod graph testing method, executed by a network analyzer in an interference-resistant Bod graph testing system, may include: after connecting the probes of the Bod graph test fixture in the Bod graph testing system to the reserved test points of the PCB board under test, setting the network analyzer to single-scan mode and configuring the test operating parameters of the network analyzer; and drawing a Bod graph based on the acquisition signals from the SMA head of the Bod graph test fixture and the reserved test connectors in the Bod graph testing system.

[0039] The test operating parameters can be the operating parameters configured for the network analyzer. Optionally, the test operating parameters may include, but are not limited to, power and frequency sweep range.

[0040] In this embodiment of the invention, after connecting the probe of the Bode plot test fixture in the Bode plot test system to the reserved test points of the PCB board under test, the network analyzer in the Bode plot test system can draw the Bode plot of the PCB board under test based on the acquisition signals of the SMA head of the Bode plot test fixture and the reserved test connector in the Bode plot test system.

[0041] In an optional embodiment of the present invention, after drawing a Bode plot based on the acquisition signals of the SMA head of the Bode plot test fixture and the reserved test connector in the Bode plot test system, the process may include: marking the gain margin and phase margin in the Bode plot based on the cursor point to obtain the target Bode plot; and storing the target Bode plot as a comma-separated value file or an image file.

[0042] Gain margin and phase margin are two key indicators used to measure the relative stability of a system. A target Bode plot can be a Bode plot with a cursor pointing to the selected position corresponding to the gain margin and phase margin.

[0043] In this embodiment of the invention, the network analyzer in the anti-interference Bode plot testing system displays a Bode plot on its display screen. When the cursor selects a specific position in the Bode plot curve, the gain margin and phase margin corresponding to the cursor position are determined based on the data cursor function of the network analyzer. The gain margin and phase margin corresponding to the cursor point are marked on the Bode plot to obtain the target Bode plot. The target Bode plot is then stored as a comma-separated value file (CSV file) or an image file.

[0044] In a specific example, the test uses a PCIe (PCI Express, high-speed serial computer expansion bus standard) card. The card has many power supplies, and the phase nodes of the power supplies will generate a lot of interference signals. Therefore, there are many sources of interference on the test card.

[0045] Table 1 shows the comparison of test results after verification. Using the traditional test scheme, the soldered leads were too close to the interference source, causing changes in the high-frequency trace trends of gain and phase, indicating severe signal interference in the high-frequency section and leading to incorrect test results. However, the test results with the soldered leads adjusted were consistent with those using the Bode plot test fixture of this scheme. This demonstrates that using the Bode plot test fixture of this scheme can achieve the same test results as adjusting the soldered leads. In other words, using the Bode plot test fixture in this scheme can effectively improve anti-interference capabilities, reduce test result errors caused by improper operation by testers, and improve test efficiency by eliminating the need for soldering.

[0046] Table 1 Comparison of Results from Different Test Methods In an optional embodiment of the present invention, an interference-resistant Bod graph testing device is configured in a network analyzer within an interference-resistant Bod graph testing system, comprising: a configuration module, configured to set the network analyzer to single-scan mode and configure the test operating parameters of the network analyzer after the probes of the Bod graph test fixture in the Bod graph testing system are connected to the reserved test points of the PCB board under test; and a Bod graph drawing module, configured to draw a Bod graph based on the acquisition signals from the SMA head of the Bod graph test fixture and the reserved test connectors in the Bod graph testing system.

[0047] The interference-resistant Bode plot testing device also includes a Bode plot storage module, which is used to mark the gain margin and phase margin in the Bode plot based on the cursor point to obtain the target Bode plot; and to store the target Bode plot as a comma-separated value file or an image file.

[0048] The technical solution of this invention involves fabricating an interference-resistant Bodé plot test fixture using PCB manufacturing processes. The probes in the Bodé plot test fixture are connected to the starting points of the differential lines. A reserved test connector is located between the starting and ending points of the differential lines, and an SMA connector is connected to the ending point of the differential lines. An interference-resistant Bodé plot test system is constructed from the interference-resistant Bodé plot test fixture and a network analyzer. The SMA connector of the interference-resistant Bodé plot test fixture is connected to the signal receiving interface of the network analyzer, and the injected signal from the network analyzer is connected to the reserved test connector via the test clamp. Then, the probes perform point tests on the reserved test points of the PCB board under test. In this solution, the probes of the Bode plot test fixture are more compatible with the increasingly smaller test points on boards with high component density, making testing easier and effectively improving testing efficiency. Furthermore, the reserved test connectors and the separate layout of the SMA head in the Bode plot test fixture can greatly shield interference caused by long leads in a physical dimension, solving the problems of high testing difficulty and easy interference of injected signals in existing boards. This can improve the testing efficiency of high-density boards, reduce test interference, and effectively improve the accuracy of test results.

[0049] Example 3 Figure 4 A schematic diagram of a network analyzer that can be used to implement embodiments of the present invention is shown. The components shown herein, their connections and relationships, and their functions are merely examples and are not intended to limit the implementation of the invention described and / or claimed herein.

[0050] like Figure 4 As shown, the electronic device 10 includes at least one processor 11 and a memory, such as ROM 12, RAM 13, etc., communicatively connected to the at least one processor 11. The memory stores computer programs executable by the at least one processor. The processor 11 can perform various appropriate actions and processes based on the computer program stored in the ROM 12 or loaded into the RAM 13 from the storage unit 18. The RAM 13 can also store various programs and data required for the operation of the electronic device 10. The processor 11, ROM 12, and RAM 13 are interconnected via a bus 14. An I / O interface 15 is also connected to the bus 14. The ROM 12 is a read-only memory, the RAM 13 is a random access memory, and the I / O interface 15 is an input / output interface.

[0051] Multiple components in electronic device 10 are connected to I / O interface 15, including: input unit 16, such as keyboard, mouse, etc.; output unit 17, such as various types of displays, speakers, etc.; storage unit 18, such as disk, optical disk, etc.; and communication unit 19, such as network card, modem, wireless transceiver, etc. Communication unit 19 allows electronic device 10 to exchange information / data with other devices through computer networks such as the Internet and / or various telecommunications networks.

[0052] Processor 11 can be a variety of general-purpose and / or special-purpose processing components with processing and computing capabilities. Some examples of processor 11 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various special-purpose artificial intelligence (AI) computing chips, various processors running machine learning model algorithms, a digital signal processor (DSP), and any suitable processor, controller, microcontroller, etc. Processor 11 performs the various methods and processes described above, such as the interference-resistant Bode plot testing method.

[0053] In some embodiments, the interference-resistant Bodgraph testing method may be implemented as a computer program tangibly contained in a computer-readable storage medium, such as storage unit 18. In some embodiments, part or all of the computer program may be loaded and / or installed on electronic device 10 via ROM 12 and / or communication unit 19. When the computer program is loaded into RAM 13 and executed by processor 11, one or more steps of the interference-resistant Bodgraph testing method described above may be performed. Alternatively, in other embodiments, processor 11 may be configured to perform the interference-resistant Bodgraph testing method by any other suitable means (e.g., by means of firmware).

[0054] Various embodiments of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), application-specific standard products (ASSPs), systems-on-a-chip (SoCs), payload-programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various embodiments may include implementations in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which may be a dedicated or general-purpose programmable processor, capable of receiving data and instructions from a storage system, at least one input device, and at least one output device, and transmitting data and instructions to the storage system, the at least one input device, and the at least one output device.

[0055] Computer programs used to implement the methods of the present invention may be written in any combination of one or more programming languages. These computer programs may be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device, such that when executed by the processor, the computer programs cause the functions / operations specified in the flowcharts and / or block diagrams to be performed. The computer programs may be executed entirely on a machine, partially on a machine, or as a standalone software package, partially on a machine and partially on a remote machine, or entirely on a remote machine or server.

[0056] In the context of this invention, a computer-readable storage medium can be a tangible medium that may contain or store a computer program for use by or in conjunction with an instruction execution system, apparatus, or device. A computer-readable storage medium may include, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination of the foregoing. Alternatively, a computer-readable storage medium may be a machine-readable signal medium. More specific examples of machine-readable storage media include electrical connections based on one or more wires, portable computer disks, hard disks, RAM, ROM, erasable programmable read-only memory (EPROM or flash memory), optical fibers, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination of the foregoing.

[0057] To provide interaction with a user, the systems and techniques described herein can be implemented on an electronic device having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to the user; and a keyboard and pointing device (e.g., a mouse or trackball) through which the user provides input to the electronic device. Other types of devices can also be used to provide interaction with the user; for example, feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including sound input, voice input, or tactile input).

[0058] The systems and technologies described herein can be implemented in computing systems that include backend components (e.g., as data servers), or middleware components (e.g., application servers), or frontend components (e.g., user computers with graphical user interfaces or web browsers through which users can interact with implementations of the systems and technologies described herein), or any combination of such backend, middleware, or frontend components. The components of the system can be interconnected via digital data communication of any form or medium (e.g., communication networks). Examples of communication networks include local area networks (LANs), wide area networks (WANs), blockchain networks, and the Internet.

[0059] A computing system can include clients and servers. Clients and servers are generally located far apart and typically interact through communication networks. The client-server relationship is created by computer programs running on the respective computers and having a client-server relationship with each other. The server can be a cloud server, also known as a cloud computing server or cloud host, which is a hosting product within the cloud computing service system to address the shortcomings of traditional physical hosts and VPS servers, such as high management difficulty and weak business scalability.

[0060] This application also discloses a computer program product, which includes a computer program that, when executed by a processor, implements the anti-interference Bode plot testing method provided in any embodiment of this application. This program product belongs to the same inventive concept as the anti-interference Bode plot testing method disclosed in the embodiments of this application, and therefore will not be described in detail here.

[0061] It should be understood that the various forms of processes shown above can be used, with steps reordered, added, or deleted. For example, the steps described in this invention can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this invention can be achieved, and this is not limited herein.

[0062] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. An anti-interference Bode plot test fixture, characterized in that, Manufactured using printed circuit board (PCB) technology, it includes: differential lines, probes, SMA connectors, and reserved test connectors; wherein, the reserved test connectors include test pins or test hooks; The probe is connected to the starting point of the differential line, the reserved test connector is located between the starting point and the ending point of the differential line, and the SMA head is connected to the ending point of the differential line.

2. The anti-interference Bode plot test fixture according to claim 1, characterized in that, include: Top layer, first inner layer, second inner layer, and bottom layer; The top layer, the bottom layer, and the second inner layer are ground layers, and the differential line is located in the first inner layer.

3. The anti-interference Bode plot test fixture according to claim 2, characterized in that, A grounding via is drilled around the differential line.

4. The anti-interference Bode plot test fixture according to any one of claims 2-3, characterized in that, The top layer and the bottom layer are copper-clad.

5. The anti-interference Bode plot test fixture according to claim 1, characterized in that, The characteristic impedance of the differential line is 50 ohms.

6. The anti-interference Bode plot test fixture according to claim 1, characterized in that, The number of probes is three, and the three probes are used to extract differential signals and fixture ground signals.

7. The anti-interference Bode plot test fixture according to claim 1 or 6, characterized in that, The spacing between the probes is consistent with the spacing between the reserved test points on the PCB board under test, and the number of reserved test points on the PCB board under test is three.

8. An anti-interference Bod plot testing system, characterized in that, include: The anti-interference Bod plot test fixture and network analyzer as described in claim 1; The SMA head of the anti-interference Bod plot test fixture is connected to the signal receiving interface of the network analyzer; the injected signal of the network analyzer is connected to the reserved test connector through the test clip; the probe is used to perform point testing on the reserved test points of the PCB board under test.

9. A method for testing Bode plots to resist interference, characterized in that, Performed by the network analyzer in the interference-resistant Bod graph test system of claim 8, comprising: After the probes of the Bodplot test fixture in the Bodplot test system are connected to the reserved test points of the PCB board under test, the network analyzer is set to single scan mode and the test parameters of the network analyzer are configured. Based on the acquisition signals from the SMA head of the Bode plot test fixture and the reserved test connector in the Bode plot test system, a Bode plot is plotted.

10. The anti-interference Bode plot test method according to claim 9, characterized in that, After plotting the Bode plot based on the acquired signals from the SMA head of the Bode plot test fixture and the reserved test connector in the Bode plot test system, the process includes: Based on the cursor point, mark the gain margin and phase margin in the Bode plot to obtain the target Bode plot; Store the target Bode plot as a comma-separated value file or an image file.

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