Bidirectional Current Monitoring Scheme for Low-Side Current Sensing of Vertical Power MOSFETs

Abstract

A bidirectional current monitoring circuit and method for a field-effect transistor (FET) configured as a low-side power switch in a power stage is disclosed, enabling both positive and negative current detection using a voltage higher than ground. In some embodiments, the bidirectional current monitoring circuit and method measure the current flowing through the low-side power FET in the power stage using a smaller sensing FET connected in substantially parallel with the low-side power FET. Positive current detection is achieved by biasing the sensing node of the sensing FET to ground, while negative current detection is achieved by biasing the sensing node of the sensing FET to a voltage greater than the drain-source voltage of the low-side power FET. The detected positive and negative currents are combined to provide a monitoring current output signal.

Description

[0001] Cross-references to related applications This application relates to a concurrently filed U.S. patent application entitled “Current Monitoring Scheme for Low-Side Body Current Detection of Vertical Power Field-Effect Transistors” (Serial No. 19 / 054,719), which is incorporated herein by reference in its entirety. Technical Field

[0002] The present invention relates to current monitoring of field-effect transistors, and more particularly to current monitoring in field-effect transistors configured as low-side power switches. Background Technology

[0003] Power field-effect transistors (FETs) are sometimes used as switches in electronic systems to transfer energy from a power source to a load. Power FETs (also known as power switches) are typically large devices designed to handle large currents. For example, power FETs are used as the power stage in switching regulators, where the input supply voltage is converted to the desired output voltage at the voltage level required by the load.

[0004] In some examples, the switching regulator may employ pulse width modulation (PWM) control, with the power stage driven by a PWM controller or modulator. In this example, the power stage includes a pair of power FETs (or power switches), driver circuitry for the power switches, and an LC filter circuitry for generating the output voltage. The pair of power FETs includes a high-side power FET and a low-side power FET connected in series between the input supply voltage and ground. The LC filter circuitry is connected to a common node between the high-side and low-side power FETs to filter the switching voltage signal generated at the common node due to the PWM switching of the high-side and low-side power FETs. The switching regulator includes feedback control circuitry for regulating energy transfer to maintain a constant output voltage over the desired load range of the circuit.

[0005] During operation, a switching regulator can operate in positive current mode, where the power stage supplies current to the load (positive current). Alternatively, the switching regulator can operate in negative current mode, where the power stage draws current from the load (negative current). In some applications, negative current operation is used to improve the performance of the host system, for example, by performing load shedding (changing the load current from a high current value to a low current value) or performing negative voltage conversion (changing the output voltage from a high value to a low value by discharging the output node).

[0006] To support the operation of switching regulators, it is typically necessary to measure the current flowing through the power FET. Current sensing or monitoring can be achieved by measuring the inductor current flowing through the LC filter circuit inductor, or by measuring the current flowing through the low-side power FET and / or the high-side power FET. Summary of the Invention

[0007] The present invention discloses a current monitoring circuit, which is generally shown in the figures and / or described below, for example, in conjunction with at least one figure, and is set forth more fully in the claims.

[0008] In one embodiment, a bidirectional current monitoring circuit is coupled to detect current in a power MOSFET configured as a low-side power FET in a power stage, the power stage including a high-side power FET and a low-side power FET connected in series, the common node between the high-side power FET and the low-side power FET being a switching output node. The current monitoring circuit includes: a detection field-effect transistor (FET) with its drain terminal connected to the drain terminal of a low-side power FET, its gate terminal connected to the gate terminal of the low-side power FET, and its source terminal serving as a detection node, wherein the current conducted by the detection FET is used to indicate the current flowing through the low-side power FET; a positive current detection circuit coupled to the detection node to bias the detection node to a first voltage (the first voltage being the voltage of the source terminal of the low-side power FET), the positive current detection circuit detecting a first detection current flowing through the detection FET, the first detection current indicating a positive current flowing from the low-side power FET to a switch output node; a negative current detection circuit coupled to the detection node to bias the detection node to a second voltage (the second voltage being greater than the drain-source voltage of the low-side power FET), the negative current detection circuit detecting a second detection current flowing through the detection FET, the second detection current indicating a negative current flowing from the switch output node into the low-side power FET; and a detection current combination circuit coupled to receive the first and second detection currents to provide a current output signal indicating the positive and negative currents flowing through the low-side power FET.

[0009] In another embodiment, a current monitoring circuit is coupled to detect current in a power field-effect transistor (FET) configured as a low-side power FET in a power stage, the drain terminal of the low-side power FET being a switching output node. The current monitoring circuit includes: a detection FET whose drain terminal is connected to the drain terminal of the low-side power FET, its gate terminal is connected to the gate terminal of the low-side power FET, and its source terminal is a detection node; the current conducted by the detection FET is used to indicate current flowing through the low-side power FET, the current including channel current flowing through the channel region of the low-side power FET and body diode current flowing through the body diode of the low-side power FET; a current detection circuit coupled to the detection node to bias the detection node to a first voltage (the first voltage being the voltage of the source terminal of the low-side power FET), the current detection circuit detecting a first detection current flowing through the detection FET; and a gain circuit coupled to the current detection circuit to selectively adjust the gain level of the first detection current. In response to the detection of channel current in the low-side power FET, the first sense current has a first gain level; in response to the detection of body diode current in the low-side power FET, the first sense current has a second gain level. A gain circuit adjusts either the first or second gain level of the first sense current to scale the first and second gain levels to the same gain level, thereby providing a current output signal indicating the channel current or body diode current flowing through the low-side power FET.

[0010] These and other advantages, aspects and novel features of the present invention, as well as details of the embodiments shown therein, will become more fully understood from the following description and drawings. Attached Figure Description

[0011] Various embodiments of the invention are disclosed in the following detailed description and accompanying drawings. Although the drawings depict various examples of the invention, the invention is not limited to the depicted examples. It should be understood that in the drawings, the same reference numerals denote the same structural elements. Furthermore, it is understood that the descriptions in the drawings are not necessarily to scale.

[0012] Figure 1 is a schematic diagram of a power stage including a pair of power FETs in some examples.

[0013] Figure 2 shows the inductor current characteristics in the power stage of a switching regulator in some examples.

[0014] Figure 3 is a schematic diagram of a current monitoring circuit coupled to a low-side power FET to achieve bidirectional current detection in an embodiment of the present invention.

[0015] Figure 4 shows a graph illustrating the relationship between the detection node voltage and the inductor current in some embodiments.

[0016] Figure 5 shows a graph illustrating the relationship between the detection current and the inductor current in some embodiments.

[0017] Figure 6 shows a circuit diagram of a current monitoring circuit coupled to a low-side power FET to achieve bidirectional current detection in an embodiment of the present invention.

[0018] Figure 7 shows a circuit diagram of an active current mirror circuit that can be applied to the current monitoring circuit of Figure 6 in some embodiments.

[0019] Figure 8 shows a circuit diagram of a current monitoring circuit coupled to a low-side power FET to achieve bidirectional current detection in an alternative embodiment of the invention.

[0020] Figure 9 shows a circuit diagram of a current monitoring circuit coupled to a low-side power FET to achieve channel conduction and body conduction current detection in an embodiment of the present invention.

[0021] Figure 10 shows the inductor current characteristics during body braking operation in some examples. Detailed Implementation

[0022] According to embodiments of the present invention, a bidirectional current monitoring scheme for a field-effect transistor (FET) configured as a low-side power switch in a power stage can achieve both positive and negative current detection using only a voltage higher than ground. In some embodiments, the bidirectional current monitoring scheme measures the current flowing through the low-side power FET in the power stage using a smaller detection FET connected in approximately parallel with the low-side power FET. Positive current detection is achieved by biasing the detection node of the detection FET to ground, while negative current detection is achieved by biasing the detection node of the detection FET to a voltage greater than the drain-source voltage of the low-side power FET. The detected positive and negative currents are combined to provide a monitoring current output signal.

[0023] According to another aspect of the invention, a current monitoring scheme for a power FET configured as a low-side power switch in a power stage is capable of measuring or detecting the body diode current flowing through the low-side power FET when the low-side power FET is operating in body conduction mode. In some embodiments, the current monitoring scheme employs a smaller detection FET to detect both the positive current flowing through the low-side power FET and the body diode current. A gain circuit is incorporated into the scheme to adjust the gain of the detection current such that the positive current detection and the body diode detection are scaled to the same gain level and provided as a monitoring current output signal.

[0024] Figure 1 shows a schematic diagram of a power stage including a pair of power FETs in some examples. Referring to Figure 1, power stage 10 includes a pair of power FETs (or power switches) MH0, M0 connected in series and connected to the input voltage V. IN Between (node ​​12) and ground (node ​​14). Power FETs MH0 and M0, also known as high-side power FET and low-side power FET respectively, are both NMOS transistors in this embodiment. The source terminal of high-side power FET MH0 is connected to the drain terminal of low-side power FET M0, which provides the switching voltage V. SW Switching node 20. The high-side power FET MH0 and the low-side power FET M0 are alternately turned on and off by PWM signals (e.g., PWM1 and PWM2) to generate the switching voltage V. SW More specifically, PWM signals PWM1 and PWM2 are coupled to corresponding drive circuits DRV1 and DRV2 to drive the corresponding power FETs MH0 and M0. The PWM signals are typically out of phase with each other. In this way, the high-side power FET MH0 and the low-side power FET M0 are alternately turned on and off by the PWM signals. As a result, ignoring the voltage drop across the resistors in the power FETs, the switching voltage V... SW Ground voltage and input voltage V IN Switching between them. The LC filter circuit consists of an inductor L1 connected between the switching node 20 and the output node 26, and an output capacitor C connected between the output node 26 and ground. OUT Formation. The LC filter circuit provides current to output node 26 while maintaining a substantially constant output voltage V. OUT .

[0025] The high-side and low-side power FETs are driven by corresponding gate drive signals GH (node ​​16) and GL (node ​​18) to turn the power FETs on and off. In the example where both the high-side and low-side power FETs are NMOS transistors, the high-side power FET MH0 requires a sufficient gate-source voltage to turn on. Specifically, the gate drive signal GH (node ​​16) at the gate terminal of the power FET MH0 needs to have a voltage higher than the input voltage V. IN The voltage value is adjusted to turn on the NMOS transistor. In some cases, the gate-source voltage of the high-side power FET MH0 can be increased to provide sufficient gate-source voltage.

[0026] In Figure 1, both the power FET and the sensing FET are shown with their respective body diodes. For example, the low-side power FET M0 has a body diode D0, and the sensing FET M1 has a body diode D1. It should be understood that the diodes D0, D1, DH0, and DH1 depicted in the accompanying drawings are inherent body diodes in the respective FET devices, and not discrete diode devices.

[0027] Figure 2 illustrates the inductor current characteristics in a switching regulator power stage in some examples. Referring to Figure 2, during normal operation, the gate drive signals GH (curve 27) and GL (curve 28) applied to the high-side and low-side power FETs are complementary. Therefore, when the gate drive signal GL (curve 28) is at a logic high level, the gate drive signal GH (curve 27) is at a logic low level, and vice versa. It should be noted that in practical implementations, the gate drive signals GH and GL are non-overlapping, and there may be gaps between the signal transitions. For example, a low-to-high transition of the gate drive signal GH may occur for a given duration after a high-to-low transition of the gate drive signal GL. Similarly, a low-to-high transition of the gate drive signal GL may occur for a given duration after a high-to-low transition of the gate drive signal GH. The duration during which both gate drive signals GH and GL are at a logic low level is sometimes referred to as the non-overlapping period or dead time period, and is typically a very short duration between the transitions of the two gate drive signals.

[0028] Curve 29 depicts the inductor current IL, or the current flowing through the switching node 20 of power stage 10 in Figure 1. When the low-side power switch M0 is on, the inductor current IL decreases (with a negative slope). When the high-side power switch MH0 is on, the inductor current IL increases (with a positive slope). In some cases, the inductor current can decrease to below 0 A, becoming a negative current value.

[0029] In this specification, the positive current in the power stage refers to the inductor current flowing from the power switch through inductor L1 to output node 26. Similarly, the negative current in the power stage refers to the inductor current flowing from output node 26 (load) through inductor L1 to the power switch. In some applications, switching regulators use negative current to release current or voltage at the load. In practice, the current flowing through the high-side or low-side power switch can be negative. This is because the inductor current can be entirely positive, entirely negative, or cross zero current (0A). For example, when the power switch is operating under zero-load conditions, the inductor current will fluctuate around 0A, resulting in an average inductor current of 0A. During voltage transitions and after load release, the inductor current waveform may drop below 0A.

[0030] During operation, it is typically necessary to monitor the current flowing through a power FET. A conventional method for power switch current monitoring is to provide a smaller sense FET connected in roughly parallel with the power FET, thus biased by the same voltage across the power FET. The size ratio of the sense FET to the power FET can be 1:1000 or 1:10000, and the sense FET detects a portion of the current flowing through the power FET. To improve accuracy and eliminate bias, the sense FET is often integrated with the power FET, i.e., formed on the same die as the power FET. The sense FET is biased by the same voltage across the power FET, such that the current flowing through the sense FET is close to the current flowing through the power FET, multiplied by the size ratio. In most cases, the power FET adopts a vertical trench FET structure, where the substrate forms the back drain terminal of the power FET. Therefore, the integrated sense FET shares the back drain terminal with the power FET, with the substrate serving as a common drain node. That is, for a vertical trench FET structure, the drain terminals of the sense FET and the power FET are necessarily connected together.

[0031] Other methods for monitoring current in a power FET include measuring the drain-source voltage Vds across the power FET, estimating the drain-source resistance (Rds_On), and then estimating the current value.

[0032] Referring again to Figure 1, in this example, a sense FET M1 is provided for the low-side power FET M0, and a sense FET MH1 is provided for the high-side power FET MH0. In this example, the power FETs are vertical trench FETs, so the drain terminal of sense FET M1 is connected to the drain terminal of the low-side power FET M0, as are sense FET MH1 and the high-side power FET MH0. Sense FET M1 is driven by the same gate drive signal GL as the low-side power FET M0. Accordingly, sense FET M1 is biased by the same voltage as the low-side power FET M0 to detect a portion of the current flowing through the power FET M0. Sense node SNS_LS (node ​​24) provides the low-side sense current as long as sense node SNS_LS (node ​​24) is biased to the same voltage as the source of the low-side power FET M0. On the high side, sense FET MH1 is driven by the same gate drive signal GH as the high-side power FET MH0. Therefore, the sensing FET MH1 is biased with the same voltage as the high-side power FET MH0 to detect a portion of the current flowing through the power FET MH0. The sensing node SNS_HS (node ​​22) provides the high-side sensing current as long as it is biased to the same voltage as the source of the high-side power FET MH0.

[0033] With such a detection FET configured, inductor current or current flowing through a power FET can be detected or measured. This invention relates to current monitoring at the low-side power FET of a power stage. Therefore, in the following description, only current monitoring in the low-side power FET is described. It should be understood that current monitoring in the high-side power FET can be implemented using conventional techniques known to those skilled in the art.

[0034] With this configuration, the low-side sensing FET M1 is used to detect both positive and negative currents flowing through the low-side power FET M0. During positive current conduction, the source (node ​​14) of the low-side power FET is at ground voltage (0V), while the drain (node ​​20) is at a negative voltage (below 0V). Therefore, by biasing the source terminal of sensing FET M1 (sensor node SNS_LS) to 0V, sensing FET M1 can detect a scaled-down version of the positive current flowing through the low-side power FET M0. For example, the sensor node SNS_LS can be coupled to a positive supply voltage (e.g., a 5V power rail), and the sensed current flowing through sensing FET M1 is proportional to the positive current flowing through the low-side power FET M0. The sensed current can be amplified or reduced to serve as a monitoring current output signal.

[0035] On the other hand, detecting or measuring negative current in the low-side power FET is more challenging. During negative current conduction, the drain of the low-side power FET (node ​​20) is above ground voltage, i.e., a positive voltage. Conventional current sensing schemes adjust the sense node SNS_LS to 0V, which results in a negative voltage bias to provide sense current through the sense FET. In some examples, a charge pump is used to generate a negative voltage for the sense circuit so that sense current can be drawn from the 0V sense node. However, charge pump circuits are undesirable because they are typically large-size circuits with high power consumption. Other conventional techniques include using V DS Voltage sensing or offset voltage is used for negative current conduction. These other conventional techniques typically offer lower accuracy in current sensing because the sensed current is estimated rather than measured as a proportion of the actual current.

[0036] In embodiments of the present invention, a bidirectional current monitoring scheme for a field-effect transistor (FET) configured as a low-side power switch in a power stage can achieve both positive and negative current detection using a voltage higher than ground. Specifically, the current monitoring scheme of the present invention can achieve negative current detection without using a charge pump or other less accurate detection techniques. Furthermore, the current monitoring scheme of the present invention can perform separate temperature compensation for the detection current measurements of positive and negative current conduction to further improve the accuracy of the detection current.

[0037] Figure 3 shows a schematic diagram of a current monitoring circuit coupled to a low-side power FET to achieve bidirectional current detection in an embodiment of the present invention. Referring to Figure 3, a current monitoring circuit 30 including a detection FET M1 is coupled to detect the current flowing through the low-side power FET M0. In some examples, the low-side power FET M0 is part of a power stage that includes a high-side power switch and a low-side power FET M0 acting as the low-side power switch. In this figure, the high-side power switch is omitted for simplicity. The common node 20 between the high-side power switch and the low-side power switch M0 is a switching node 20, which is coupled to the inductor of an LC filter circuit that provides an output voltage to the output node, as shown in Figure 1. For simplicity, the LC filter circuit is also omitted in this figure.

[0038] The current monitoring circuit 30 is configured to detect the positive current I flowing between the inductor and the low-side power FET M0. POS and negative current I NEG As mentioned above, the positive current I POS This refers to the current flowing from the low-side power FET M0 to the inductor, specifically the negative current I. NEGThis refers to the current flowing from the inductor to the low-side power FET M0. The positive and negative currents are sometimes collectively referred to as the inductor current IL. In embodiments of the invention, the current monitoring circuit 30 separates the detection of the positive and negative current flows and detects each current separately in the same detection FET M1. The detected currents of the positive and negative current flows are then combined to provide a monitoring current output signal I. MON .

[0039] In some embodiments, the current monitoring circuit 30 includes a positive current detection circuit 32 and a negative current detection circuit 34, both coupled to bias or adjust the voltage VSNS at the detection node SNS. As a result of the corresponding bias voltage, the detected current I... SNS The current flows in the detection node SNS. The current monitoring circuit 30 includes a detection current combination circuit 35, which buffers the detection current from the positive current detection circuit or the negative current detection circuit, and combines the measured detection current to generate a monitoring current output signal I. MON .

[0040] The operation of the current monitoring circuit 30 will be described with reference to Figures 4 and 5. Figure 4 shows a graph illustrating the relationship between the detection node voltage and the inductor current in some embodiments. Figure 5 shows a graph illustrating the relationship between the detection current and the inductor current in some embodiments. In Figure 4, curve 36 shows the detection voltage V SNS Curve 38 shows the drain-source voltage V of the low-side power FET. DS As a function of the inductor current IL. In Figure 5, curve 40 shows the detection current I used for positive current detection. POS_SNS Curved section 42 shows the detection current I used for negative current detection. NEG_SNS Curve 44 shows the effect on the detected current I. NEG_SNS Modifications were made to generate the monitoring current output signal I. MON .

[0041] Referring to Figures 3, 4, and 5, according to an embodiment of the present invention, the current monitoring circuit 30 adjusts the detection node SNS to different voltage values ​​for positive current detection and negative current detection. When the inductor current IL is positive (right quadrant of the graph) and the drain-source voltage V... DS When a negative voltage value is present, the positive current detection circuit 32 is activated to bias the detection node SNS to ground voltage or 0V. On the other hand, when the inductor current IL is negative (left quadrant of the graph) and the drain-source voltage V... DSWhen a positive voltage value is present, the negative current detection circuit 34 is enabled to bias the detection node SNS to a value greater than the drain-source voltage V across the low-side power FET. DS Therefore, for positive current detection and negative current detection, the detection node SNS is adjusted to different voltage values.

[0042] As shown in Figure 4, for positive current sensing, the sensing node SNS is regulated to ground voltage (0V). For negative current sensing, the sensing node SNS is regulated to a value greater than the drain-source voltage V of the low-side power FET. DS The positive voltage. In some embodiments, for negative current detection, the detection node SNS is biased to the drain-source voltage V across the low-side power FET. DS The value is N times the value of the low-side power FET, where N is a number greater than 1. In one embodiment, for negative current detection, the detection node SNS is biased to the drain-source voltage V across the low-side power FET. DS Twice (2x). For example, the voltage value represented by curve 36 is twice the voltage value of curve 38.

[0043] During negative current conduction, by applying a voltage greater than the drain-source voltage V across the low-side power FET... DS Detection voltage V SNS The current monitoring circuit 30 essentially reverses the direction of the current flowing through the detection FET, allowing the detection FET to receive a detection current from a detection circuit biased at a voltage higher than ground. As a result, the measured detection current I... SNS It has only a positive current component, as shown in Figure 5. Referring to Figure 5, due to the voltage bias of the separated detection nodes, the measured detection current I... SNS Includes the first part I depicting the positive detection current. POS_SNS (Curve 40) and the second part I depicting the negative detection current NEG_SNS (Curve 42). For a positive inductor current, the sensed current I POS_SNS It has a positive current value (curve 40). For a negative inductor current, the sensed current I... NEG_SNS It also has a positive current value (curve 42).

[0044] In an embodiment of the present invention, the current monitoring circuit 30 includes a current detection combination circuit 35 for combining a positive detection current I. POS_SNS and negative detection current I NEG_SNS It generates a monitoring current output signal IMON. In some embodiments, the detection current combination circuit is used to surround or modify the negative detection current I NEG_SNSThe polarity of the current is adjusted to make it a negative current value (curve 44). Therefore, the monitoring current output signal IMON has the desired current value polarity for both positive and negative current detection. With this configuration, the current monitoring circuit 30 of the present invention can provide accurate current detection of the low-side power FET without the need for a high-power charge pump or any offset cancellation.

[0045] Figure 6 shows a circuit diagram of a current monitoring circuit coupled to a low-side power FET to achieve bidirectional current detection in an embodiment of the present invention. Figure 6 shows a current monitoring circuit 50, which in some embodiments can be used to implement the current monitoring circuit of Figure 3. Referring to Figure 6, the current monitoring circuit 50 includes a detection FET M1 coupled to detect the current flowing through the low-side power FET M0. Similar to Figure 3, the low-side power FET M0 is part of a power stage that includes a high-side power switch and a low-side power FET M0 acting as the low-side power switch. In this figure, the high-side power switch is omitted for simplicity. The common node 20 between the high-side power switch and the low-side power switch M0 is a switching node 20, which is coupled to the inductor of an LC filter circuit that provides an output voltage to the output node, as shown in Figure 1. For simplicity, the LC filter circuit is also omitted in this figure.

[0046] The current monitoring circuit 50 includes a positive current detection circuit 52 and a negative current detection circuit 54. The positive current detection circuit 52 includes an amplifier A0 and a FET M2 configured in a negative feedback loop. The gate terminal of the FET M2 is driven by the output signal of the amplifier A0. In this embodiment, the FET M2 is an NMOS transistor. The amplifier A0 receives ground voltage or 0V as a reference voltage at its non-inverting input. The source terminal of the FET M2 is connected to the inverting input of the amplifier A0 and connected to the detection node SNS via an optional resistor RTC_pos. With this configuration, the detection node SNS is regulated to the 0V reference voltage through the feedback loop of the amplifier A0 and the FET M2. The current flowing through the FET M2 is the positive detection current I. SNS_pos In this embodiment, the current is mirrored to the drain terminal (node ​​53) of FET M2 to mirror the positive sensing current I. SNS_posSpecifically, the current mirror is formed by diode-connected FETs M7 and M8. In this example, both FETs M7 and M8 are PMOS transistors, and their source terminals are connected to a positive supply voltage (e.g., Vcc). The drain terminal of the diode-connected FET M7 is coupled to the drain terminal of FET M2 to channel the current I... SNS_pos The current is mirrored to the drain terminal of FETM8. The mirrored current is provided to output node 58 as the monitoring current output signal I. MON Specifically, when the current flowing through the low-side power FET is positive, the current monitoring output signal I... MON It has a positive current value.

[0047] The negative current detection circuit 54 includes amplifier A2, amplifier A1, and FET M3. Amplifier A2 detects the drain-source voltage V across the low-side power FET M0 at its input. DS And apply the gain factor to the voltage V DS In this embodiment, amplifier A2 applies a gain factor of twice the input voltage, resulting in an output voltage of 2 × V provided by amplifier A2. DS Amplifier A2's 2×V DS The output voltage is supplied to the inverting input of amplifier A1 as a reference voltage. In one example, the operating voltage V... DS The voltage is 50mV, therefore the output voltage of amplifier A2 is 100mV, and this 100mV is provided to amplifier A1 as a reference voltage. Amplifier A1 and FET M3 are configured in a negative feedback loop, with the gate terminal of FET M3 driven by the output signal of amplifier A1. In this embodiment, FET M3 is a PMOS transistor, and its source terminal is connected to the positive supply voltage Vcc. The drain terminal of FET M3 is connected to the non-inverting input terminal of amplifier A1 and connected to the detection node SNS through an optional resistor RTC_neg. With this configuration, the detection node SNS is regulated to the reference voltage or 2×V through the feedback loop of amplifier A1 and FET M3. DS The current flowing through FET M3 is the negative sensing current I. SNS_neg (Node 55). In this embodiment, the negative detection current I SNS_neg First, it is copied to FET M4. FET M4 is also a PMOS transistor, with its source terminal connected to the positive power supply voltage Vcc and its gate terminal connected to the gate terminal of FET M3. Therefore, the current conducted at the drain terminal (node ​​56) of FET M4 is the negative sense current I.SNS_neg A copy.

[0048] The current is mirrored to the drain terminal (node ​​56) of FET M4 to mirror the negative sense current I. SNS_neg and the negative detection current I SNS_neg Modify to the desired polarity to correctly report negative current values. Negative sense current I SNS_neg It has a positive current value. The current mirror coupled to FET M4 is formed by diode-connected FETs M5 and M6. In this example, both FETs M5 and M6 are NMOS transistors, and their source terminals are connected to ground or 0V. The drain terminal of the diode-connected FET M5 is coupled to the drain terminal of FET M4 to conduct current I. SNS_neg The image is mirrored to the drain terminal of FET M6. The mirrored current is wrapped around the drain terminal, making the mirrored current now have a negative current value. The mirrored current is provided to output node 58 as the monitoring current output signal I. MON Specifically, when the current flowing through the low-side power FET is negative, the current monitoring output signal I... MON It has a negative current value.

[0049] In the current monitoring circuit 50, the current mirrors of FETs M7 and M8, and the current mirrors of FETs M5 and M6, form a detection current combination circuit, used to combine the positive detection current I. SNS_pos and negative detection current I SNS_neg And modify the negative detection current to provide a monitoring current output signal I with the desired current polarity. MON Furthermore, the positive detection current I can be independently set via separate current mirror circuits. SNS_pos and negative detection current I SNS_neg The gain. In this way, the positive and negative detection currents are combined into the monitoring current output signal I. MON Previously, it was individually adjusted to achieve higher detection accuracy. Specifically, due to the difference in the ratio of the detection current to the power FET current between positive and negative current operating modes, it is sometimes necessary to set different gain values ​​for the positive and negative detection currents. This difference in current ratio is caused by parasitic resistance in the transistor structures of the power FET and the detection FET. For example, in positive current operating mode, the parasitic resistance between the power FET and the detection FET is mostly matched. However, in negative current operating mode, the parasitic resistance between the power FET and the detection FET is poorly matched. Therefore, the ratio of FETs M7 and M8 can be selected for the positive detection current I... SNS_posSet the gain level; you can select the ratio of FETs M5 and M6 to determine the negative sense current I. SNS_neg Adjust the gain level to achieve higher detection accuracy.

[0050] For example, the gain of the positive current detection circuit can be IL / 1000, and the gain of the negative current detection circuit can be IL / 700. In this case, the gain of FET M8 can be 1, and the gain of FET M6 can be 7 / 10, so that the monitored current output signal I... MON Maintaining a balance between positive and negative current detection.

[0051] In embodiments of the invention, resistors RTC_pos and RTC_neg are incorporated to achieve temperature compensation for the positive and negative detection currents. Specifically, in vertical power FET designs, the current ratio between the low-side power FET and the detection FET does not perfectly track temperature variations. This is because not all components of the on-resistance Rds_On (e.g., channel resistance, substrate resistance, metal resistance) scale by the same magnitude. Therefore, the detection current is corrected to compensate for inaccuracies caused by temperature variations. In embodiments of the invention, resistor RTC_pos is connected to the source terminal of the detection node SNS and the FET M2 of the positive current detection circuit to linearize the positive detection current over temperature variations. Simultaneously, resistor RTC_neg is connected to the drain terminal of the detection node SNS and the FET M3 of the negative current detection circuit to linearize the negative detection current over temperature variations. Resistors RTC_pos and RTC_neg are optional and may be omitted in other embodiments of the invention.

[0052] In some embodiments, amplifiers A0 and A1 are low-offset, high-bandwidth amplifiers. Current monitoring circuitry 50 uses amplifiers A0 and A1 to drive the sense node SNS to a corresponding voltage value to detect either a positive or negative current flowing in the low-side power FET. The sense current is the current required to drive the sense node SNS to the desired voltage. Each of the positive and negative sense currents is independently gain-adjusted and then mirrored to provide a sense current output signal that is an accurate proportional version of the current flowing through the low-side power FET. An optional temperature linearization resistor may be added to compensate for temperature-dependent shifts in the current sensing ratio between the low-side power FET and the sense FET.

[0053] In the embodiment shown in Figure 6, the current monitoring circuit uses a passive current mirror to buffer and replicate the positive and negative sense currents to generate a sense current output signal. In other embodiments of the invention, the current monitoring circuit is incorporated into an active current mirror circuit. Figure 7 is a circuit diagram of an active current mirror circuit implementation applicable to the current monitoring circuit of Figure 6 in some embodiments. In particular, the active current mirror circuit of Figure 7 can be incorporated into the current monitoring circuit 50 to replace the passive current mirrors of FETs M7 / M8 and FETs M5 / M6. The advantage of an active current mirror is that it provides accuracy over a wide range of current values.

[0054] Referring to Figure 7, an active current mirror circuit 60 is provided for buffering and mirroring a positive detection current; an active current mirror circuit 65 is provided for buffering and mirroring a negative detection current. Each active current mirror circuit 60, 65 is implemented using an amplifier and a FET configured in a negative feedback loop. Specifically, for the active current mirror circuit 60 for positive detection current, amplifier 62 is coupled to drive a PMOS transistor M10, wherein amplifier 62 and PMOS transistor M10 are configured in a negative feedback loop. The source terminal of PMOS transistor M10 is connected to the positive supply voltage through resistor R3. For the active current mirror circuit 65 for negative detection current, amplifier 66 is coupled to drive an NMOS transistor M12, wherein amplifier 66 and NMOS transistor M12 are configured in a negative feedback loop. The source terminal of NMOS transistor M12 is connected to ground through resistor R5.

[0055] In this embodiment, the positive detection current I detected from the low-side power FET SNS_LS_pos Coupled to the non-inverting input of amplifier 62 via resistor divider R1 / R2 and switch S1. In this embodiment, the positive detection current I detected from the high-side power FET... SNS_HS_pos It is also coupled to the resistor divider R1 / R2. The resistance values ​​of the resistor divider R1 / R2 are selected to provide the desired gain scaling of the positive sense current from the high-side power FET and the low-side power FET. In this embodiment, the switch S1 and capacitor C1 in the active current mirror circuit 60 implement a switched-capacitor circuit, which is used to detect the blanking of the current report, for example, during the switching of the power FET. The operation of the switched-capacitor circuit will be described in more detail below.

[0056] In this embodiment, the negative detection current I detected from the low-side power FET SNS_LS_negCoupled to the non-inverting input of amplifier 66 via resistor divider R4 / R5 and switch S2. In this embodiment, the negative sense current I detected from the high-side power FET... SNS_HS_neg It is also coupled to the resistor divider R4 / R5. The resistance values ​​of the resistor divider R4 / R5 are selected to provide the desired gain scaling for the negative sense current from the high-side power FET and the low-side power FET. In this embodiment, the switch S2 and capacitor C2 in the active current mirror circuit 65 implement a switched-capacitor circuit for blanking the sense current report, which will be described in more detail below.

[0057] Figure 8 shows a circuit diagram of a current monitoring circuit coupled to a low-side power FET to achieve bidirectional current detection in an alternative embodiment of the invention. Specifically, Figure 8 shows a simplified implementation of the current monitoring circuit 50 of Figure 6. Referring to Figure 8, the current monitoring circuit 70 includes an amplifier A2 that detects the drain-source voltage V across the low-side power FET M0 at its input. DS And apply the gain factor to the voltage V DS In this embodiment, amplifier A2 applies a gain factor of twice the input voltage, resulting in an output voltage of 2 × V provided by amplifier A2. DS The current monitoring circuit 70 also includes amplifier A0 and FET M2 configured in the negative feedback loop, the gate terminal of FET M2 being driven by the output signal of amplifier A0. In this embodiment, FET M2 is an NMOS transistor. Amplifier A0 receives a reference voltage provided by maximum selector 72 at its non-inverting input. Maximum selector 72 receives ground voltage (0V) and 2×V of amplifier A2. DS The output voltage is selected, and the larger of the two voltages is chosen as the reference voltage for amplifier A0. During positive current conduction, the drain voltage has a negative value, so the maximum value selector 72 will select ground voltage (0V) as the reference voltage. The feedback loop of amplifier A0 and FET M2 will bias the sense node SNS to ground voltage (0V). During negative current conduction, the drain voltage has a positive value, so the maximum value selector 72 will select 2×V. DS The voltage is used as a reference voltage. The feedback loop of amplifier A0 and FET M2 biases the sensing node SNS to 2×V. DS Voltage. In this way, the detection node SNS is biased accordingly for positive or negative current detection. In this embodiment, a resistor RTC is coupled between the source terminal of FET M2 and the detection node SNS to linearize the detection current over a temperature range.

[0058] The current monitoring circuit 70 includes a switch S3, whose first and second switching positions are selected by the direction of current flowing through the low-side power FET. For example, switch S3 can be controlled by a signal from amplifier A2 indicating the drain-source voltage V detected by the amplifier. DS It has a positive or negative voltage value. It responds to the drain-source voltage V. DS With a negative voltage, switch S3 is connected to the first switch position (node ​​74), and a positive current I is being detected. SNS_pos Coupled to a current mirror formed by PMOS transistors M17 and M18. The mirror current is provided to output node 75 as a monitoring current output signal. This is in response to the drain-source voltage V. DS With a positive voltage, switch S3 is connected to the second switch position (node ​​75), and a negative detection current I... SNS_neg It is directly coupled to the output node as a monitoring current output signal.

[0059] In the above embodiments, current sensing of the low-side power FET during channel conduction is described. During channel conduction, the power FET is boosted or turned on so that current flows through the channel region of the power FET. In channel conduction mode, both positive and negative currents flow through the channel region of the power FET. In some applications, the power FET may operate in body diode conduction mode, where the power FET is not turned on, but current is directed through the body diode of the power FET. Body diode conduction, also known as body braking, is used to increase the voltage across the inductor and accelerate the decrease of the inductor current, for example, during load release. During body braking, the inductor current value may be very high, and the high inductor current is rapidly reduced to a low current value. The output voltage and current may experience large overshoots until the inductor current has sufficiently decreased and the current can be regulated again. In body diode conduction mode, the power switch typically cannot report the body diode current. Instead, conventional current monitoring schemes may provide some form of simulation of the desired body diode current. For example, current monitoring can use an estimate of the desired current ramp rate and extrapolate backwards regardless of the actual current conditions. In one example, the design could assume the forward voltages of the inductor and diode, and use the assumed / measured output voltage V. OUT To predict the slope ratio dI / dt = (V) using horizontal methods OUT +0.7V) / L. Traditional current monitoring schemes do not provide detection data based on the actual current value during the conduction period of the body diode.

[0060] According to another aspect of the invention, a current monitoring scheme for a power FET configured as a low-side power switch in a power stage is capable of measuring or detecting the body diode current flowing through the low-side power FET when the low-side power FET is operating in body conduction mode. In some embodiments, the current monitoring scheme employs a smaller detection FET to detect both the positive current flowing through the low-side power FET and the body diode current. A gain circuit is incorporated into the scheme to adjust the gain of the detection current such that the channel current detection and the body diode detection are scaled to the same gain level and provided as a monitoring current output signal.

[0061] Figure 9 shows a circuit diagram of a current monitoring circuit coupled to a low-side power FET in an embodiment of the present invention to achieve channel conduction and body conduction current detection. Referring to Figure 9, a current monitoring circuit 90 including a detection FET M1 is coupled to detect the current flowing through the low-side power FET M0. Similar to Figure 3, the low-side power FET M0 is part of a power stage. The power stage may include high-side circuitry coupled to the low-side power FET M0. The high-side circuitry may be a diode (e.g., implementing an asynchronous buck converter), or it may be a power switch (e.g., implementing a synchronous buck converter). The specific implementation of the high-side circuitry is not critical to the implementation of the present invention. In some embodiments, the power stage is configured as shown in Figure 1, including a high-side power FET MH0 coupled in series with the low-side power FET M0. In other embodiments, the power stage may be configured with other circuit elements for the high-side circuitry. In the illustration shown in Figure 9, the high-side circuitry is omitted for simplicity. The common node 20 between the high-side circuit and the low-side power switch M0 is the switching node 20, which couples to the inductor of the LC filter circuit, which provides the output voltage to the output node, as shown in Figure 1. For simplicity, the LC filter circuit is also omitted in this figure.

[0062] The current monitoring circuit 90 includes a current sensing circuit for detecting the positive current flowing through the low-side power FET M0 and the body diode current. Specifically, the positive current flows in the channel region of the low-side power FET M0, while the body diode current flows in the body diode D0 of the low-side power FET M0. As described above, during the positive current mode, the drain voltage of the low-side power FET has a negative voltage value. During the body diode conduction mode, the drain voltage of the low-side power FET is the forward voltage of the body diode, i.e., -0.7V. Since the detection FET M1 has the same drain and gate voltages across its terminals, a portion of the positive current is conducted in the channel region of the detection FET M1, or a portion of the body diode current is conducted in the body diode D1 associated with the detection FET M1.

[0063] The current sensing circuit includes an amplifier A0 and a FET M2 configured in a negative feedback loop. The gate terminal of FET M2 is driven by the output signal of amplifier A0. In this embodiment, FET M2 is an NMOS transistor. Amplifier A0 receives ground voltage or 0V as a reference voltage at its non-inverting input. The source terminal of FET M2 is connected to the inverting input of amplifier A0 and then connected to the sensing node SNS. With this configuration, the sensing node SNS is regulated to the 0V reference voltage through the feedback loop of amplifier A0 and FET M2. The current flowing through FET M2 is the sensing current I. SNS .

[0064] The current monitoring circuit 90 also includes a gain circuit for selectively adjusting the gain level of the sense current ISNS. Specifically, the ratio between the channel current in the low-side power FET and the channel current in the sense FET when the FET is on differs from the ratio between the body current in the low-side power FET and the body current in the sense FET when the FET is off and the body diode is on. Therefore, an additional gain term is introduced to maintain a constant gain for the monitored current output signal. In other words, a gain term is applied to ensure that the sense current ISNS is constant when both the channel and body diode are on. SNS With inductor current I L The ratios are roughly equal.

[0065] In this embodiment, the gain circuit includes FET M13 and FET M14. FET M13 is an NMOS transistor coupled between the drain terminal of FET M2 and a current mirror. FET M13 conducts the sense current ISNS detected by FET M2 to regulate the sense node to ground. FET M14 is another NMOS transistor whose source terminal is coupled to the drain terminal of FET M2, and the drain terminal is connected to the positive supply voltage Vcc via switch S4. The gate terminals of FETs M13 and M14 are driven by a bias voltage Vbias. The voltage Vbias is selected to provide sufficient voltage margin for FETs M13 and M14 relative to the positive supply voltage Vcc and ground.

[0066] With this configuration, when switch S4 is open, the current I is detected. SNS Only current flows through FET M13, and is mirrored by the current mirrors of PMOS transistors M27 and M28 to provide to output node 96 as the monitoring current output signal I. MONOn the other hand, with switch S4 closed, FET M14 and FET M13 share a portion of the current from FET M2. The remaining current in FET M13 is mirrored by the current mirrors of PMOS transistors M27 and M28 to provide to output node 96 as the monitoring current output signal I. MON In this embodiment, when the current flowing through the low-side power FET is the positive channel current or the body diode current, the current output signal I is monitored. MON It has a positive current value.

[0067] Switch S4 can be controlled by the host system, which determines when the low-side power FET will operate in channel-on mode or body diode-on mode. In some embodiments, the gain of the current sensing signal during body diode-on mode is greater than the gain of the current sensing signal during channel-on mode. Therefore, when the low-side power FET operates in channel-on mode, switch S4 can be turned off, and FET M14 does not participate in the current sensing path of the current monitoring circuit. Thus, the gain of the current sensing signal in channel-on mode is a function of the total current in the current sensing path (current from FET M2). Simultaneously, when the low-side power FET operates in body diode-on mode, switch S4 can be closed, and FET M14 diverts a certain amount of current from the current sensing path (FET M2) of the current monitoring circuit. Therefore, the gain of the current sensing signal in body diode-on mode is reduced. In this way, the gain level of the current sensing signal is adjusted individually according to the conduction mode of the low-side power switch. Thus, channel current sensing and body diode sensing are scaled to the same gain level and provided as the monitoring current output signal.

[0068] In other embodiments, the gain of the current sensing signal during channel conduction can be greater than the gain of the current sensing signal during body diode conduction mode. In this case, the logic control of switch S4 can be reversed. That is, when the low-side power FET operates in body diode conduction mode, switch S4 is open, and the gain of the current sensing signal is greater. Simultaneously, when the low-side power FET operates in channel conduction mode, switch S4 is closed, and the gain of the current sensing signal is reduced. In this way, channel current sensing and body diode sensing are scaled to the same gain level and provided as the monitoring current output signal. It should be noted that the logic behavior of switch S4 is not critical to the implementation of the invention. In implementation, opening switch S4 can increase the gain of the current sensing signal, closing switch S4 can decrease the gain of the current sensing signal, and the host system can configure the control of switch S4 according to the characteristics of the current sensing signal in different conduction modes.

[0069] In the embodiment shown in FIG9, the current monitoring circuit 90 includes detection circuitry for measuring the positive current of the low-side power FET M0 and the body diode current. In other embodiments, the current monitoring circuit 90 may further include detection circuitry for measuring the negative current in the low-side power FET M0, as shown in FIG6 and described above.

[0070] Figure 10 shows the inductor current characteristics in some examples of body braking operation. At a given time point, the inductor current I... L (Curve 100) may be at a high current value, for example, when powering a heavy load. Then, changes in load conduction may cause a reduction in the required inductor current. Control circuitry (e.g., switching regulator control circuitry) can control the power stage to operate in a body braking mode to rapidly reduce the inductor current from a high level to a low level. For example, the low-side power switch and the high-side power switch can be turned off. Referring to Figure 10, the power stage initially operates in channel-on mode to provide a high current level inductor current I. L (Curve 100). Changes in load conditions reduce current demand, and the power stage operates the low-side power switch in body diode conduction mode (or body braking mode), for example, by turning off the low-side power switch to quickly reduce the inductor current, as shown in Figure 10. Once the inductor current has sufficiently decreased, the power stage can again control the low-side power switch and the high-side circuitry to regulate the output voltage.

[0071] During body braking, it is still desirable for the current monitoring circuit to report the actual measured value of the diode current, rather than using a simulated or predicted current value. In embodiments of the invention, the current monitoring circuit is capable of measuring the body diode current during body conduction to provide a monitoring current output signal that reflects the actual value of the body diode current flowing through the low-side power FET.

[0072] In embodiments of the invention, the current monitoring circuit can apply blanking to the monitored current output signal when entering and exiting the body diode conduction mode to avoid large current overshoot and allow the detected current value to stabilize before being reported to the output signal. In some embodiments, the current monitoring circuit applies blanking to the monitored current output signal during the transition from the low-side power FET to the body diode conduction mode or to the channel conduction mode. The monitored current output signal can hold the last current value before blanking and jump to a new current value after the blanking period ends. For example, Figure 10 shows two blanking windows where the inductor current measurement can be blanked. The first blanking window is applied when the inductor current transitions to the body diode conduction mode, and the second blanking window is applied when the inductor current transitions out of the body diode conduction mode and into the channel conduction mode.

[0073] In some embodiments, a switched-capacitor circuit can be used to apply blanking to the monitored current output signal. Referring to FIG7, in the active mirror circuit 60, capacitor C1 and switch S1 are used to apply blanking to the positive current detection signal. When switch S1 is closed, the voltage across resistors R1 and R2 sets the capacitor voltage (with a low time constant), and the detected current is mirrored to output node 70 as the monitored current output signal I. MON When switch S1 is open, capacitor C1 maintains its last known voltage, independent of the detected current input. Therefore, the monitored current output signal I... MON The signal is blanked until switch S1 closes again. The switched capacitor circuits of C2 and S2 in the active mirror circuit 65 operate in the same way to blank the negative current detection signal.

[0074] In this detailed description, the processing steps described in one embodiment may be used in different embodiments, even if the processing steps are not explicitly described in that different embodiment. When a method is referred to herein as including two or more defined steps, the defined steps may be performed in any order or simultaneously unless the context otherwise requires or is specifically stated herein. Furthermore, unless the context otherwise requires or is explicitly stated herein, the method may also include one or more other steps performed before any defined step, between two defined steps, or after all defined steps.

[0075] In this detailed description, various embodiments or examples of the invention can be implemented in a variety of ways, including as processes, apparatuses, systems, and material compositions. A detailed description of one or more embodiments of the invention, along with accompanying drawings illustrating the principles of the invention, has been provided above. The invention has been described in conjunction with these embodiments, but is not limited to any particular embodiment. Many modifications and variations are possible within the scope of the invention. The scope of the invention is defined only by the claims, and the invention covers many alternatives, modifications, and equivalents. Numerous specific details are set forth in the description to provide a thorough understanding of the invention. These details are provided for illustrative purposes, and the invention can be practiced according to the claims without requiring some or all of these specific details. For clarity, technical materials known in the art related to the invention have not been described in detail so as not to unnecessarily obscure the invention. The invention is defined by the appended claims.

Claims

1. A bidirectional current monitoring circuit coupled to detect current in a power field-effect transistor (FET) configured as a low-side power field-effect transistor (FET) in a power stage, the power stage including a high-side power FET and the low-side power FET connected in series, the common node between the high-side power FET and the low-side power FET being a switching output node, the current monitoring circuit comprising: A detection field-effect transistor (FET) has its drain terminal connected to the drain terminal of the low-side power FET, its gate terminal connected to the gate terminal of the low-side power FET, and its source terminal serving as a detection node. The current conducted by the detection FET is used to indicate the current flowing through the low-side power FET. A positive current sensing circuit is coupled to the sensing node to bias the sensing node to a first voltage, the first voltage being the voltage of the source terminal of the low-side power FET, the positive current sensing circuit detecting a first sensing current flowing through the sensing FET, the first sensing current indicating a positive current flowing from the low-side power FET to the switching output node; A negative current detection circuit is coupled to the detection node to bias the detection node to a second voltage greater than the drain-source voltage of the low-side power FET. The negative current detection circuit detects a second detection current flowing through the detection FET, the second detection current indicating a negative current flowing into the low-side power FET from the switch output node. as well as A current sensing combination circuit coupled to receive the first sense current and the second sense current to provide a current output signal indicating the positive and negative currents flowing through the low-side power FET.

2. The bidirectional current monitoring circuit according to claim 1, wherein the positive current detection circuit biases the detection node to the first voltage, the first voltage being ground voltage, to detect positive current flowing from the low-side power FET to the switch output node.

3. The bidirectional current monitoring circuit according to claim 1, wherein the negative current detection circuit biases the detection node to the second voltage to detect the negative current flowing through the low-side power FET from the switch output node, wherein the second voltage is N times the drain-source voltage of the low-side power FET, where N is a number greater than 1.

4. The bidirectional current monitoring circuit according to claim 3, wherein the negative current detection circuit biases the detection node to the second voltage, the second voltage being twice the drain-source voltage of the low-side power FET.

5. The bidirectional current monitoring circuit according to claim 2, wherein the positive current detection circuit comprises: A first amplifier has its non-inverting input coupled to ground voltage, its inverting input coupled to the detection node, and has an output terminal; as well as A first FET has its gate terminal coupled to the output of the first amplifier, its source terminal coupled to the inverting input of the first amplifier and the detection node and providing the first detection current, and its drain terminal coupled to a current source circuit.

6. The bidirectional current monitoring circuit according to claim 5, wherein the inverting input terminal of the first amplifier and the source terminal of the first FET are connected together and coupled to the detection node through a first resistor, the resistance value of the first resistor being selected to provide temperature compensation to the first detection current.

7. The bidirectional current monitoring circuit according to claim 5, wherein the negative current detection circuit comprises: A second amplifier has its non-inverting input coupled to the drain terminal of the low-side power FET, its inverting input coupled to the source terminal of the low-side power FET, and its output providing a voltage output signal that is N times the voltage signal between the non-inverting and inverting inputs. A third amplifier, having its inverting input coupled to receive a voltage output signal from the second amplifier, and having both an inverting input and an output; as well as A second FET has its gate terminal coupled to the output of the third amplifier, its source terminal coupled to a first power supply voltage, and its drain terminal coupled to the non-inverting input of the third amplifier and the detection node of the detection FET, the drain terminal providing the second detection current.

8. The bidirectional current monitoring circuit according to claim 7, wherein the non-inverting input terminal of the third amplifier and the drain terminal of the second FET are connected together and coupled to the detection node through a second resistor, the resistance value of the second resistor being selected to provide temperature compensation to the second detection current.

9. The bidirectional current monitoring circuit according to claim 7, wherein the first FET is an N-type field-effect transistor and the second FET is a P-type field-effect transistor.

10. The bidirectional current monitoring circuit of claim 7 further includes a third FET, the gate terminal of which is coupled to the gate terminal of the second FET, the source terminal of which is coupled to the first power supply voltage, and the drain terminal of which provides a current indicating the second detection current.

11. The bidirectional current monitoring circuit according to claim 1, wherein the positive current detection circuit is coupled to the detection node through a first resistor, the resistance value of the first resistor being selected to provide temperature compensation to the first detection current; the negative current detection circuit is coupled to the detection node through a second resistor, the resistance value of the second resistor being selected to provide temperature compensation to the second detection current; wherein, The resistance values ​​of the first resistor and the second resistor are selected respectively to provide temperature compensation to the corresponding first detection current and second detection current.

12. The bidirectional current monitoring circuit of claim 1, wherein the low-side power FET includes a vertical trench FET formed on a substrate, the substrate being a back drain terminal; the detection FET is formed on the same substrate as the vertical trench FET and shares the back drain terminal.

13. The bidirectional current monitoring circuit according to claim 1, wherein, The current detection circuit includes: A first current mirror, which receives the first detected current and provides a first output current at its output node indicating the first detected current as the current output signal, the first current mirror being powered by a first power rail; and A second current mirror receives a current indicating the second detected current and provides a second output current at the output node indicating the second detected current as the current output signal, the second current mirror being powered by a second power rail; Wherein, the first current mirror image is of a first polarity type, and the second current mirror image is of a second polarity type opposite to the first polarity type.

14. The bidirectional current monitoring circuit according to claim 13, wherein the first current mirror comprises a P-type field-effect transistor, and the first power rail comprises a positive power supply voltage; the second current mirror comprises an N-type field-effect transistor, and the second power rail comprises a ground voltage or a negative power supply voltage.

15. The bidirectional current monitoring circuit of claim 13, wherein the first current mirror and the second current mirror include active current mirrors, each active current mirror including an amplifier and a field-effect transistor configured as a negative feedback structure to provide the first output current and the second output current at the output node.

16. A method for current monitoring of a power field-effect transistor (FET) configured as a low-side power field-effect transistor (FET) in a power stage, the power stage including a high-side power FET and the low-side power FET connected in series, the common node between the high-side power FET and the low-side power FET being a switching output node, the method comprising: A detection field-effect transistor (FET) is provided, wherein its drain terminal is connected to the drain terminal of the low-side power FET, its gate terminal is connected to the gate terminal of the low-side power FET, and its source terminal is a detection node, wherein the current conducted by the detection FET is used to indicate the current flowing through the low-side power FET; The detection node is biased to a first voltage of the source terminal voltage of the low-side power FET to detect a first detection current flowing through the detection FET, the first detection current indicating a positive current flowing from the low-side power FET to the switch output node; The detection node is biased to a second voltage greater than the drain-source voltage of the low-side power FET to detect a second detection current flowing through the detection FET, the second detection current indicating a negative current flowing into the low-side power FET from the switch output node; The first and second detection currents are combined to provide a current output signal indicating the positive and negative currents flowing through the low-side power FET.

17. The method of claim 16, further comprising: The detection node is biased to ground voltage to detect positive current flowing from the low-side power FET to the switch output node; as well as The detection node is biased to a second voltage that is N times the drain-source voltage of the low-side power FET, where N is an integer greater than 1, to detect negative current flowing through the low-side power FET from the switch output node.

18. The method of claim 17, wherein biasing the detection node to a second voltage that is N times the drain-source voltage of the low-side power FET comprises: The detection node is biased to a second voltage that is twice the drain-source voltage of the low-side power FET.

19. The method of claim 16, wherein combining the first detection current and the second detection current comprises: The first detected current is mirrored by a first current of a first polarity type powered by a first power rail to generate a first output current at the output node as the current output signal. as well as The second detected current is mirrored by a second current of a second polarity type that is powered by a second power rail and is opposite to the first polarity type, in order to generate a second output current at the output node as the current output signal.

20. The method of claim 16, further comprising: The detection node is biased to a first voltage via a first resistor, the value of which is selected to provide temperature compensation for the first detection current; as well as The detection node is biased to a second voltage via a second resistor, the value of which is selected to provide temperature compensation for the second detection current.

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