Parallel data acquisition methods, systems, semiconductor testing equipment, and storage media

Abstract

This application relates to the field of semiconductor chip testing technology, and provides a parallel data acquisition method, system, semiconductor testing equipment, and storage medium. The method includes: generating multiple sampling clocks within a programmable logic unit based on delay taps formed by cascading carry logic units; sampling and latching data on a parallel data bus using the multiple sampling clocks to obtain multiple sets of sampling register data corresponding to each sampling clock; within a preset statistical time window, pairing and comparing the multiple sets of sampling register data at adjacent sampling phase positions, performing an XOR operation bit-by-bit on each pair of sampling register data, and counting and accumulating the XOR results bit-by-bit to obtain multiple difference count values; determining the sampling clock corresponding to the minimum value among the multiple difference count values ​​as the target sampling clock, and outputting the sampling register data corresponding to the target sampling clock as the parallel data acquisition result. This scheme can improve the accuracy of parallel data acquisition.

Description

Technical Field

[0001] This application belongs to the field of semiconductor chip testing technology, and in particular relates to a parallel data acquisition method, system, semiconductor testing equipment and storage medium. Background Technology

[0002] In the field of semiconductor chip testing technology, parallel data acquisition is a crucial step in obtaining multi-channel output information from the chip under test (DUT), and is widely used in mass production testing, factory testing, and functional verification. For example, for DUTs with high-speed parallel output, test equipment typically needs to receive multiple bits of parallel data simultaneously through multiple signal lines and complete sampling and judgment within the test cycle. In some applications, this parallel data may also correspond to image data or other high-bandwidth service data. With the increase in chip interface speed, parallel bit width, and the tendency for test cycle compression, the requirements for sampling timing matching and sampling accuracy in test systems are further increasing.

[0003] In real-world testing environments, factors such as variations in test board wiring length, connector and cable characteristics, temperature changes, and device manufacturing process deviations can cause inconsistencies in the arrival times of data bits on the parallel bus at the test end. This leads to a shift in the relative position of the sampling edge and the valid data window, introducing sampling errors and affecting the stability of the test results. To ensure data acquisition reliability, timing debugging and calibration are typically required in engineering. However, with continuously increasing interface speeds and greater variations in the field environment, the debugging process often becomes more complex and places higher demands on system adaptability. Summary of the Invention

[0004] In view of this, embodiments of this application provide a parallel data acquisition method, system, semiconductor testing equipment, and storage medium, which can automatically select the target sampling phase through XOR difference counting, thereby improving the accuracy and reliability of parallel data acquisition.

[0005] A first aspect of this application provides a parallel data acquisition method applied to a parallel data acquisition system, the system including at least a programmable logic unit; the method includes: Within the programmable logic unit, multiple sampling clocks are generated based on delay taps formed by cascading carry logic units. These multiple sampling clocks have the same frequency and correspond to different sampling phase positions within the same clock cycle. The parallel data bus is sampled and latched using the multi-channel sampling clocks respectively, to obtain multiple sets of sampling register data corresponding to each sampling clock. Within a preset statistical time window, multiple sets of sampling register data at adjacent sampling phase positions are compared in pairs. For each pair of sampling register data, an XOR operation is performed bit by bit, and the XOR result is counted and accumulated bit by bit to obtain multiple difference count values. The difference count values ​​are used to characterize the degree of difference between the corresponding paired sets of sampling register data. The sampling clock corresponding to the minimum value among the multiple difference counts is determined as the target sampling clock, and the sampling register data corresponding to the target sampling clock is output as the parallel data acquisition result.

[0006] In this embodiment, firstly, multiple sampling clocks are generated within the programmable logic unit based on delay taps formed by cascading carry logic units, enabling multiple selectable sampling phase positions within the same clock cycle. Based on this, the parallel data bus is sampled and latched using these multiple sampling clocks, obtaining multiple sets of sampling register data for the same data stream at different sampling phase positions. Subsequently, within a preset statistical time window, the sampling register data at adjacent sampling phase positions are compared, and an XOR operation is performed bit by bit. The XOR results are then counted and accumulated bit by bit to obtain multiple difference count values, thereby converting the sampling stability under different sampling phases into a quantifiable statistical indicator. Finally, the sampling clock corresponding to the smallest difference count value is determined as the target sampling clock, and the sampling register data corresponding to this target sampling clock is output as the parallel data acquisition result. Therefore, this application can automatically select a stable sampling phase through statistical comparison when there is inconsistency or drift in the arrival time of parallel data signals, improving the correctness, adaptability, and reliability of parallel data acquisition. Furthermore, it can achieve adaptive adjustment of the sampling position without relying on continuously phase-locked loops or additional board-level delay devices.

[0007] In one possible implementation, the programmable logic unit internally comprises a carry delay chain consisting of multiple cascaded carry logic units; the generation of multiple sampling clocks based on the delay taps formed by the cascaded carry logic units within the programmable logic unit includes: Obtain the input clock signal; The target phase interval is determined based on the period of the input clock signal; The number of cascaded stages of the carry logic unit is determined based on the target phase interval, and the length of the carry delay chain is configured according to the number of cascaded stages; The input clock signal is cascaded and propagated in multiple carry logic units using the carry delay chain, with each level's output node serving as a delay tap. Based on the different delay positions corresponding to the multiple delay taps within the same input clock cycle, a multi-channel sampling clock is generated.

[0008] In this implementation, a carry delay chain is used to form a delay tap and generate multiple sampling clocks, which can provide multiple sampling phase selection capabilities with fine-grained phase intervals within the FPGA, thereby improving the resolution and feasibility of sampling phase adjustment.

[0009] In one possible implementation, the step of sampling and latching the parallel data bus with the multiple sampling clocks to obtain multiple sets of sampling register data corresponding to each sampling clock includes: The parallel data bus is sampled independently using the multi-channel sampling clock; The sampling results of each channel are latched separately to obtain multiple sets of sampling register data that correspond one-to-one with the sampling clock of each channel.

[0010] In this implementation, multiple independent samples are taken from the parallel data bus and latched separately, enabling parallel observation of the same data at multiple sampling phases, providing a data basis for subsequent difference statistics and optimal sampling phase selection.

[0011] In one possible implementation, within a preset statistical time window, multiple sets of sampling register data at adjacent sampling phase positions are compared in pairs. A bitwise XOR operation is performed on each pair of sampling register data, and the XOR results are counted and accumulated bit by bit to obtain multiple difference count values, including: Within the preset statistical time window, the sampling register data corresponding to the adjacent sampling phase positions are paired up to obtain at least one pairing relationship and the sampling register data group corresponding to the pairing relationship; Perform an XOR operation on the sample register data pairs in each sample register data group to obtain the XOR result; The XOR result is counted bit by bit and accumulated within the preset statistical time window to obtain multiple difference count values ​​that correspond one-to-one with each pairing relationship.

[0012] In this implementation, by pairing and XORing adjacent phase sampled data within a statistical window and accumulating the count, sampling instability can be quantified into a difference count value, thereby improving the objectivity and robustness of the optimal sampling phase determination.

[0013] In one possible implementation, the sampling clock is four-channel, with a 90-degree phase difference between adjacent sampling clock channels; the XOR operation performed on the sampling register data pairs in each sampling register data group to obtain the XOR result includes: Pair the first sampling register data group corresponding to the first sampling clock with the second sampling register data group corresponding to the second sampling clock, and perform an XOR operation bit by bit to obtain the first XOR result; Pair the second sampling register data group with the third sampling register data group corresponding to the third sampling clock, and perform an XOR operation bit by bit to obtain the second XOR result; Pair the third sampling register data group with the fourth sampling register data group corresponding to the fourth sampling clock, and perform an XOR operation bit by bit to obtain the third XOR result; The fourth sampling register data group is paired with the first sampling register data group, and an XOR operation is performed bit by bit to obtain the fourth XOR result.

[0014] In this implementation, four sampling clocks are defined with an adjacent phase difference of 90 degrees, and four sets of XOR relationships are specified. This enables uniform phase comparison coverage within one cycle, improving the ability to capture changes in the effective data window position and the accuracy of phase selection.

[0015] In one possible implementation, the step of counting the XOR results bit by bit and accumulating them within the preset statistical time window to obtain multiple difference count values ​​corresponding one-to-one with each pairing relationship includes: Within the preset statistical time window, the first XOR result, the second XOR result, the third XOR result, and the fourth XOR result are obtained for each sampling time. The first XOR result, the second XOR result, the third XOR result and the fourth XOR result are traversed bit by bit, and the number of bits in each XOR result that are at the preset logic value are counted to obtain the bit difference count corresponding to each XOR result at the sampling time. The position difference counts of each XOR result within the preset statistical time window are accumulated to obtain the first difference count value, the second difference count value, the third difference count value, and the fourth difference count value, which correspond one-to-one with the first XOR result, the second XOR result, the third XOR result, and the fourth XOR result.

[0016] In this implementation, counting each bit of the XOR result and accumulating them within a statistical window to form a difference count value can suppress the influence of instantaneous jitter or occasional errors, making the difference assessment more stable.

[0017] In one possible implementation, determining the sampling clock corresponding to the minimum value among the plurality of difference count values ​​as the target sampling clock, and outputting the sampling register data corresponding to the target sampling clock as the parallel data acquisition result, includes: Compare the magnitudes of the multiple difference count values; The sampling clock corresponding to the minimum difference count value is determined as the target sampling clock; The sampling register data corresponding to the target sampling clock is output as the parallel data acquisition result.

[0018] In this embodiment, by comparing the difference count values ​​and using the sampling clock corresponding to the minimum value as the target sampling clock output, a more stable sampling phase can be automatically locked, thereby reducing sampling errors and improving the reliability of parallel data acquisition.

[0019] A second aspect of this application provides a parallel data acquisition system, the system comprising at least a programmable logic unit; the system further comprising: The clock generation module is used to generate multiple sampling clocks within the programmable logic unit based on the delay taps formed by the cascading carry logic units. The multiple sampling clocks have the same frequency and correspond to different sampling phase positions within the same clock cycle. The sampling module is used to sample and latch the parallel data bus with the multiple sampling clocks respectively, and to obtain multiple sets of sampling register data corresponding to each sampling clock. The difference counting module is used to compare multiple sets of sampling register data at adjacent sampling phase positions within a preset statistical time window. It performs an XOR operation bit by bit on each pair of sampling register data and counts and accumulates the XOR results bit by bit to obtain multiple difference count values. The difference count values ​​are used to characterize the degree of difference between the corresponding paired two sets of sampling register data. The target determination module is used to determine the sampling clock corresponding to the minimum value among the multiple difference count values ​​as the target sampling clock, and output the sampling register data corresponding to the target sampling clock as the parallel data acquisition result.

[0020] A third aspect of this application provides a semiconductor testing device, which includes at least the parallel data acquisition system described in the second aspect, wherein the parallel data acquisition system includes at least a programmable logic unit; the parallel data acquisition system is used to perform the method described in the first aspect.

[0021] A fourth aspect of this application provides a computer-readable storage medium storing a computer program that, when executed by a processor, implements the method described in the first aspect above.

[0022] A fifth aspect of this application provides a computer program product that, when run on a semiconductor testing device, causes the semiconductor testing device to perform the method described in the first aspect.

[0023] For the beneficial effects of the second to fifth aspects mentioned above, please refer to the first aspect mentioned above, which will not be repeated here. Attached Figure Description

[0024] To more clearly illustrate the technical solutions in the embodiments of this application, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0025] Figure 1 This is a flowchart illustrating a parallel data acquisition method provided in an embodiment of this application; Figure 2 This is a schematic diagram illustrating the generation of the four sampling clocks provided in an embodiment of this application; Figure 3 This is a signal relationship diagram of the four sampling clocks provided in an embodiment of this application; Figure 4 This is a schematic diagram of the structure of a parallel data acquisition system provided in an embodiment of this application; Figure 5 This is a structural block diagram of the parallel data acquisition system provided in the embodiments of this application; Figure 6 This is a schematic diagram of the structure of the semiconductor testing equipment provided in the embodiments of this application. Detailed Implementation

[0026] In the following description, specific details such as particular system architectures and techniques are set forth for illustrative purposes and not for limitation, in order to provide a thorough understanding of the embodiments of this application. However, those skilled in the art will understand that this application may also be implemented in other embodiments without these specific details. In other instances, detailed descriptions of well-known systems, apparatuses, circuits, and methods have been omitted so as not to obscure the description of this application with unnecessary detail.

[0027] It should be understood that, when used in this application specification and the appended claims, the term "comprising" indicates the presence of the described features, integrals, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components and / or a collection thereof.

[0028] It should also be understood that the term “and / or” as used in this application specification and the appended claims means any combination of one or more of the associated listed items and all possible combinations, and includes such combinations.

[0029] As used in this application specification and the appended claims, the term "if" may be interpreted, depending on the context, as "when," "once," "in response to determination," or "in response to detection." Similarly, the phrase "if determined" or "if detected [the described condition or event]" may be interpreted, depending on the context, as meaning "once determined," "in response to determination," "once detected [the described condition or event]," or "in response to detection [the described condition or event]."

[0030] Furthermore, in the description of this application and the appended claims, the terms "first," "second," "third," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0031] It should be understood that the sequence number of each step in this embodiment does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of this application embodiment.

[0032] In the field of semiconductor chip testing technology, parallel data acquisition is a crucial step in obtaining multi-channel output information from the chip under test (DUT), and is widely used in mass production testing, factory testing, and functional verification. For example, for DUTs with high-speed parallel output, test equipment typically needs to receive multiple bits of parallel data simultaneously through multiple signal lines and complete sampling and judgment within the test cycle. In some applications, this parallel data may also correspond to image data or other high-bandwidth service data. With the increase in chip interface speed, parallel bit width, and the tendency for test cycle compression, the requirements for sampling timing matching and sampling accuracy in test systems are further increasing.

[0033] In real-world testing environments, factors such as variations in test board wiring length, connector and cable characteristics, temperature changes, and device manufacturing process deviations can cause inconsistencies in the arrival times of data bits on the parallel bus at the test end. This leads to a shift in the relative position of the sampling edge and the valid data window, introducing sampling errors and affecting the stability of the test results. To ensure data acquisition reliability, timing debugging and calibration are typically required in engineering. However, with continuously increasing interface speeds and greater variations in the field environment, the debugging process often becomes more complex and places higher demands on system adaptability.

[0034] To address the aforementioned issues, this application provides a parallel data acquisition method, system, semiconductor testing equipment, and storage medium. In this method, firstly, multiple sampling clocks are generated within a programmable logic unit based on delay taps formed by cascading carry logic units, creating multiple selectable sampling phase positions within the same clock cycle. Then, the parallel data bus is sampled and latched using these multiple sampling clocks to obtain multiple sets of sampling register data for the same data stream at different sampling phase positions. Subsequently, within a preset statistical time window, the sampling register data at adjacent sampling phase positions are compared and paired, performing an XOR operation bit by bit and accumulating the XOR results bit by bit to obtain multiple difference count values, thereby converting the sampling stability under different sampling phases into a quantifiable statistical indicator. Finally, the sampling clock corresponding to the smallest difference count value is determined as the target sampling clock, and the sampling register data corresponding to this target sampling clock is output as the parallel data acquisition result. Therefore, this application can automatically select a stable sampling phase through statistical comparison when there is inconsistency or drift in the arrival time of parallel data signals, thereby improving the correctness, adaptability and reliability of parallel data acquisition, and can achieve adaptive adjustment of the sampling position without relying on a continuously phase-locked loop or additional board-level delay devices.

[0035] The parallel data acquisition method, system, semiconductor testing equipment, storage medium, and computer program provided in the embodiments of this application will be described in detail below with reference to the accompanying drawings.

[0036] See Figure 1 The diagram shows a flowchart of a parallel data acquisition method provided in an embodiment of this application; the method is a parallel data acquisition system, the system including at least a programmable logic unit.

[0037] like Figure 1 As shown, the method may include the following steps: Step 101: Within the programmable logic unit, a multi-channel sampling clock is generated based on the delay tap formed by the cascading carry logic units.

[0038] Among them, programmable logic units refer to hardware logic circuit units used to implement configurable digital logic functions, such as programmable logic resources in field-programmable gate arrays, which can implement functions such as clock generation, data sampling, logic operation and register control without changing the hardware.

[0039] The carry logic unit refers to the basic logic structure inside the programmable logic unit used to implement fast carry propagation. It has a definite propagation delay characteristic and can be used to construct a delay structure with fine-grained delay resolution.

[0040] Among them, the delay tap refers to the multiple output nodes selected on the delay structure formed by cascading multiple carry logic units. Each output node corresponds to a different propagation delay of the input signal after cascading propagation, thereby providing multiple signals at different delay positions within the same period as a reference for subsequent timing construction.

[0041] Among them, the multiple sampling clocks have the same frequency and correspond to different sampling phase positions within the same clock cycle.

[0042] In the specific execution of step 101, the programmable logic unit first receives the input clock signal and internally calls a delay structure composed of multiple cascaded carry logic units, causing the input clock signal to propagate sequentially along the cascade direction. As the input clock signal propagates in the cascaded structure, the signal arrival time of each output node increases progressively. Therefore, multiple output nodes can be selected as delay taps in this cascaded structure. Subsequently, using the different delay positions corresponding to the multiple delay taps within the same input clock cycle, a multi-channel sampling clock is constructed, so that the multiple sampling clocks fall at different sampling phase positions within the same cycle, thereby providing a clock basis for subsequent multi-phase sampling of parallel data.

[0043] In one possible implementation, the programmable logic unit (PLU) internally includes a carry delay chain composed of multiple cascaded carry logic units; within the PLU, multiple sampling clocks are generated based on the delay taps formed by the cascaded carry logic units, including: Obtain the input clock signal; Determine the target phase interval based on the period of the input clock signal; The number of cascaded stages of the carry logic unit is determined based on the target phase interval, and the length of the carry delay chain is configured according to the number of cascaded stages; The carry delay chain is used to cascade the input clock signal through multiple carry logic units, and the output nodes of each stage are used as delay taps. Multiple sampling clocks are generated based on the different delay positions corresponding to multiple delay taps within the same input clock cycle.

[0044] For example, Figure 2 A schematic diagram of the generation of four sampling clocks provided in an embodiment of this application is shown. In this embodiment, the carry chain resources built into the FPGA are utilized, and the carry chain is designed in a cascaded mode to form a carry delay chain, so as to generate multiple sampling clocks without introducing external delay devices. By controlling the cascade length of the carry chain, the multiple clock signals derived from the same input clock are kept at the same frequency as the input clock signal, but different in phase, thereby providing candidate sampling clocks for subsequent observation of parallel data at different sampling phase positions.

[0045] The specific execution process is as follows: The programmable logic unit first acquires the input clock signal CLK. To form four phase points within one clock cycle, this implementation sets the target phase interval to one-quarter of the input clock cycle. Subsequently, the number N of carry chains that need to be cascaded is calculated based on the period T of the input clock signal. The number N of carry chains to be cascaded depends on the clock signal period and satisfies the following relationship: N = T / 4 100 / 65.2 Where T is the clock signal period, and it is equal to the reciprocal of the frequency, i.e., T = 1 / f, where f is in MHz. Based on the calculated N, the cascade length of the carry delay chain is configured so that the input clock signal propagates in the carry chain and generates a delay corresponding to a quarter cycle.

[0046] like Figure 2 As shown, the input clock signal CLK is divided into multiple paths within the FPGA: one path serves as a zero-delay path to output clock signal CLK_0; the remaining paths pass through carry chains of different cascade lengths to obtain different delay taps. For example, one path outputs clock signal CLK_90 after cascading through N carry chains, another path outputs clock signal CLK_180 after cascading through 2N carry chains, and yet another path outputs clock signal CLK_270 after cascading through 3N carry chains. Since the selection of N is related to the input clock period T, and the delay introduced by the N-stage carry chains is close to one-quarter of the input clock period, each output clock has a different phase offset relative to CLK_0, ultimately resulting in four clock signals with the same frequency but different phases, used for subsequent parallel data sampling and adaptive phase selection processing.

[0047] Step 102: Sample and latch the parallel data bus using multiple sampling clocks to obtain multiple sets of sampling register data corresponding to each sampling clock.

[0048] Parallel data bus refers to a data transmission channel composed of multiple data lines in parallel. Each data line transmits one bit of data at the same time, and the simultaneous transmission of multiple data lines forms multiple bits of parallel data, which is used to achieve high-speed data output and reception in scenarios such as semiconductor chip testing.

[0049] The sampling clock refers to the clock signal used to trigger sampling of the parallel data bus. In this application, it is a multi-channel sampling clock generated inside the programmable logic unit. Each sampling clock has the same frequency but corresponds to a different sampling phase position, which is used to observe the same parallel data stream at different sampling phase positions.

[0050] Data latching refers to the process of writing the level state of the parallel data bus into a register at the trigger edge of the sampling clock and keeping it unchanged, so as to facilitate subsequent difference statistics and output selection, and avoid the data from continuing to change after sampling, which would cause uncertainty in the reading.

[0051] In this embodiment, after the programmable logic unit generates multiple sampling clocks in step 101, it uses each sampling clock as a trigger signal for an independent sampling domain to perform parallel sampling and latching operations on the same parallel data bus. Specifically, the programmable logic unit configures a corresponding sampling register data group for each sampling clock. When any sampling clock reaches a preset trigger edge, it synchronously samples each bit of data on the parallel data bus at that trigger edge and writes the sampling result into the sampling register data group to complete the latching.

[0052] Since multiple sampling clocks correspond to different sampling phase positions within the same clock cycle, the same parallel data will be latched into different sampling register data groups at different sampling phase positions, thus obtaining multiple sets of sampling register data that correspond one-to-one with each sampling clock. In this way, the programmable logic unit can perform parallel observation of the same parallel data stream at multiple sampling phase positions without changing the external input signal, providing basic data for subsequent pairing comparison and selection of the target sampling clock within the statistical time window.

[0053] For example, in a parallel data reception scenario for semiconductor chip testing, the chip under test (DUT) outputs multiple bits of test data via a parallel data bus, while simultaneously providing an input clock signal for the receiver to reference. The programmable logic unit (PLU) internally generates multiple sampling clocks based on this input clock and samples the parallel data bus using these clocks: when the trigger edge of the first sampling clock arrives, the first set of sampling register data is latched; when the trigger edge of the second sampling clock arrives, the second set of sampling register data is latched; and so on for the remaining sampling clocks. In this way, within each input clock cycle, the PLU can obtain multiple sets of latched data at different sampling phase positions. Subsequently, statistical analysis can be performed based on these latched data to select a more stable sampling phase, thereby improving the accuracy and reliability of parallel data acquisition.

[0054] In one possible implementation, the parallel data bus is sampled and latched using multiple sampling clocks to obtain multiple sets of sampling register data corresponding to each sampling clock, including: The parallel data bus is sampled independently using multiple sampling clocks; The sampling results of each channel are latched separately to obtain multiple sets of sampling register data that correspond one-to-one with the sampling clock of each channel.

[0055] In this embodiment, after the programmable logic unit (PLU) internally generates multiple sampling clocks, it sets up a corresponding data sampling channel and sampling register for each sampling clock on the parallel data bus, so that each data sampling channel is driven by its corresponding sampling clock and works independently. When any sampling clock reaches a preset trigger edge, the PLU synchronously samples each bit of data on the parallel data bus at that trigger edge and writes the sampled parallel data into the corresponding sampling register to complete data latching. The latched register data remains stable for subsequent processing. In this way, the sampling results of the parallel data bus at different sampling phase positions are latched into different sampling registers, thereby obtaining multiple sets of sampling register data corresponding one-to-one with each sampling clock.

[0056] In a specific implementation, the multi-sampling clock includes four clock signals with different phases, each used to independently acquire data from the parallel data bus and form four sets of sampling register data: The data acquired and latched by clock signal CLK_0 is denoted as sample_reg_0, the data acquired and latched by clock signal CLK_90 is denoted as sample_reg_90, the data acquired and latched by clock signal CLK_180 is denoted as sample_reg_180, and the data acquired and latched by clock signal CLK_270 is denoted as sample_reg_270. Thus, the programmable logic unit can obtain multiple sets of latched results at different sampling phase positions on the same data stream, providing basic data for subsequent difference statistics and target sampling phase selection.

[0057] Step 103: Within the preset statistical time window, pair and compare multiple sets of sampling register data at adjacent sampling phase positions, perform an XOR operation bit by bit on each pair of sampling register data, and count and accumulate the XOR results bit by bit to obtain multiple difference count values.

[0058] The preset statistical time window refers to the time interval used for difference statistics. Within this time interval, the sampling results are continuously accumulated to obtain a statistically significant difference count value. This time window can be generated by the internal timing of the programmable logic unit or configured by external control logic. For example, the statistical time window can be set to one second.

[0059] Among them, adjacent sampling phase positions refer to two adjacent sampling phase positions when multiple sampling phase positions corresponding to multiple sampling clocks are arranged in phase order within the same input clock cycle; adjacent sampling phase positions are used to form a pairing comparison relationship to evaluate the degree of change of sampling results when the phase interval is small.

[0060] Among them, pair comparison refers to the process of determining two sets of sampling register data that meet a preset relationship (such as adjacent sampling phase positions) as a pair of comparison objects, and performing difference calculation and count accumulation on the pair of data within the same statistical time window.

[0061] The bitwise XOR operation refers to performing an XOR logical operation on the corresponding bits of the two sets of sampled register data to obtain a logical result of whether each bit is consistent; when the corresponding bits are the same, the XOR result is the first logical value, and when the corresponding bits are different, the XOR result is the second logical value.

[0062] Bit-by-bit counting and accumulation refers to counting the number of bits in the XOR operation result that are at a preset logical value, and summing the count results within the statistical time window to obtain a difference count value that reflects the degree of difference between the two sets of sampled register data.

[0063] The difference count value refers to the cumulative result obtained by performing a bitwise XOR operation and counting bitwise on a pair of sampled register data within a preset statistical time window. It is used to characterize the degree of difference between the pair of sampled register data. The smaller the difference count value, the more consistent the two are.

[0064] In this embodiment, after obtaining multiple sets of sampling register data, the programmable logic unit starts statistical logic and enters a preset statistical time window. Within this time window, the pairing relationship between the multiple sets of sampling register data is first determined according to the adjacent sampling phase positions. That is, two sets of sampling register data with adjacent phase sequences are regarded as a pair of comparison objects, and a corresponding difference count register is established for each pair of comparison objects for cumulative statistics.

[0065] Subsequently, at each sampling moment within the statistical time window, the programmable logic unit performs a bitwise XOR operation on the data of each pair of sampling registers to obtain an XOR result vector. Then, it iterates through the XOR result vector bit by bit, counting the number of bits that fall within a preset logic value to obtain the current difference count, and adds this current difference count to the corresponding difference count register. As the statistical time window continues to advance, the difference count registers of each pair of comparison objects are continuously updated until the statistical time window ends, ultimately yielding multiple difference count values ​​corresponding one-to-one with each pairing relationship.

[0066] In one possible implementation, within a preset statistical time window, multiple sets of sampling register data at adjacent sampling phase positions are compared in pairs. A bitwise XOR operation is performed on each pair of sampling register data, and the XOR results are counted and accumulated bit by bit to obtain multiple difference count values, including: Within a preset statistical time window, the sampling register data corresponding to adjacent sampling phase positions are paired up to obtain at least one pairing relationship and the sampling register data group corresponding to the pairing relationship. Perform an XOR operation on the sample register data pairs in each sample register data group to obtain the XOR result; The XOR result is counted bit by bit and accumulated within a preset statistical time window to obtain multiple difference count values ​​that correspond one-to-one with each pairing relationship.

[0067] Specifically, after obtaining multiple sets of sampling register data, the programmable logic unit starts the statistical logic and enters a preset statistical time window. Within the preset statistical time window, the sampling register data corresponding to adjacent sampling phase positions are first paired according to the order of sampling phase positions to obtain at least one pairing relationship, and the two sets of sampling register data corresponding to each pairing relationship are determined as a sampling register data group.

[0068] Subsequently, an XOR operation is performed on the corresponding data bits of the two sets of sample register data in each sample register data group to obtain an XOR result indicating whether the corresponding data bits are consistent. Further, the XOR result is counted bit by bit, and the count results are accumulated within a preset statistical time window to obtain multiple difference count values ​​corresponding one-to-one with each pairing. The difference count values ​​are used to characterize the degree of difference between the two sets of sample register data in the corresponding pair within the statistical time window, providing a basis for subsequent sampling clock selection.

[0069] The following explanation uses an example of four sampling clocks with a 90-degree phase difference between adjacent sampling clocks to illustrate the above implementation. For the specific phase relationship of the four sampling clocks, please refer to [link to relevant documentation]. Figure 3 The diagram shows the signal relationship between the four sampling clocks.

[0070] First, perform an XOR operation on the sample register data pairs in each sample register data group to obtain the XOR result, including: Pair the first sampling register data group corresponding to the first sampling clock with the second sampling register data group corresponding to the second sampling clock, and perform an XOR operation bit by bit to obtain the first XOR result; Pair the second sampling register data group with the third sampling register data group corresponding to the third sampling clock, and perform an XOR operation bit by bit to obtain the second XOR result; Pair the third sampling register data group with the fourth sampling register data group corresponding to the fourth sampling clock, and perform an XOR operation bit by bit to obtain the third XOR result; Pair the fourth sampling register data group with the first sampling register data group, and perform an XOR operation bit by bit to obtain the fourth XOR result.

[0071] Secondly, the XOR results are counted bit by bit and accumulated within a preset statistical time window to obtain multiple difference count values ​​corresponding one-to-one with each pairing relationship, including: Within a preset statistical time window, the first XOR result, the second XOR result, the third XOR result, and the fourth XOR result are obtained for each sampling time. The first, second, third, and fourth XOR results are traversed bit by bit, and the number of bits in each XOR result that are at the preset logic value is counted to obtain the bit difference count corresponding to each XOR result at the sampling time. The positional difference counts of each XOR result within a preset statistical time window are accumulated to obtain the first difference count value, the second difference count value, the third difference count value, and the fourth difference count value, which correspond one-to-one with the first XOR result, the second XOR result, the third XOR result, and the fourth XOR result.

[0072] Specifically, in this embodiment, after the programmable logic unit completes multi-phase sampling and latches the data of four sets of sampling registers, it performs a statistical evaluation of the stability of each sampling data within a preset statistical time window, and selects the clock with the best phase as the final data acquisition clock accordingly. In this embodiment, the preset statistical time window is set to 1 second.

[0073] The stability of the acquired data is evaluated using a statistical method based on the number of inconsistencies between adjacent phase sampling results. Let the bit width of the parallel acquisition data be n, i.e., the number of data transmission wires be n; let "^" represent the XOR logical operation, with the rule that 0^0 equals 0, 1^1 equals 0, 0^1 equals 1, and 1^0 equals 1. Within a 1-second statistical window, an XOR operation is performed bit-by-bit on the data of adjacent sampling registers, and the XOR results are accumulated bit-by-bit to obtain the corresponding inconsistency count.

[0074] First, count the number of inconsistent CLK_0 and CLK_90 sampling data within 1 second: sample_reg_0[0] ^ sample_reg_90[0]= sum_1[0]; sample_reg_0[1] ^ sample_reg_90[1]= sum_1[1]; ... sample_reg_0[n-1] ^ sample_reg_90[n-1]= sum_1[n-1]; sample_reg_0[n] ^ sample_reg_90[n]= sum_1[n]; Summing the XOR results of each bit, we get: sum_1[0] + sum_1[1] + ... + sum_1[n-1] + sum_1[n] = sum_diff1.

[0075] Second, count the number of instances where CLK_90 and CLK_180 sampling data are inconsistent within 1 second: sample_reg_90[0] ^ sample_reg_180[0]= sum_2[0]; sample_reg_90[1] ^ sample_reg_180[1]= sum_2[1]; ... sample_reg_90[n-1] ^ sample_reg_180[n-1]= sum_2[n-1]; sample_reg_90[n] ^ sample_reg_180[n]= sum_2[n]; Summing the XOR results of each bit, we get: sum_2[0] + sum_2[1] + ... + sum_2[n-1] + sum_2[n] = sum_diff2.

[0076] Third, count the number of inconsistent CLK_180 and CLK_270 sampling data within 1 second: sample_reg_180[0] ^ sample_reg_270[0]= sum_3[0]; sample_reg_180[1] ^ sample_reg_270[1]= sum_3[1]; ... sample_reg_180[n-1] ^ sample_reg_270[n-1]= sum_3[n-1]; sample_reg_180[n] ^ sample_reg_270[n]= sum_3[n]; Summing the XOR results of each digit gives: sum_3[0] + sum_3[1] + ... + sum_3[n-1] + sum_3[n] = sum_diff3.

[0077] Fourth, count the number of instances where the CLK_270 and CLK_0 sampling data are inconsistent within 1 second: sample_reg_270[0] ^ sample_reg_0[0]= sum_4[0]; sample_reg_270[1] ^ sample_reg_0[1]= sum_4[1]; ... sample_reg_270[n-1] ^ sample_reg_0[n-1]= sum_4[n-1]; sample_reg_270[n] ^ sample_reg_0[n]= sum_4[n]; Summing the XOR results of each bit, we get: sum_4[0] + sum_4[1] + ... + sum_4[n-1] + sum_4[n] = sum_diff4.

[0078] After completing the above statistics, the programmable logic unit obtained four difference count values, namely sum_diff1, sum_diff2, sum_diff3 and sum_diff4.

[0079] Step 104: Determine the sampling clock corresponding to the minimum value among multiple difference counts as the target sampling clock, and output the sampling register data corresponding to the target sampling clock as the parallel data acquisition result.

[0080] In this embodiment, after the programmable logic unit has obtained multiple difference count values ​​corresponding one-to-one with each pairing relationship in step 103, it enters the phase selection and output stage. Specifically, the programmable logic unit compares the multiple difference count values, determines the minimum difference count value, and determines the sampling clock corresponding to the minimum difference count value as the target sampling clock, assuming that the sampling phase corresponding to the target sampling clock is in a more stable sampling region.

[0081] Subsequently, the programmable logic unit selects and outputs the sampling register data corresponding to the target sampling clock as the parallel data acquisition result based on the one-to-one correspondence between the target sampling clock and the sampling register data. At the same time, the target sampling clock is used as the final data acquisition clock for subsequent parallel data acquisition, so that the system uses this sampling phase for data output and processing in subsequent work, thereby realizing adaptive determination and stable acquisition of the sampling phase.

[0082] In one possible implementation, the sampling clock corresponding to the minimum value among multiple difference counts is determined as the target sampling clock, and the sampling register data corresponding to the target sampling clock is output as the parallel data acquisition result, including: Compare the magnitudes of multiple difference counts; The sampling clock corresponding to the minimum difference count value is determined as the target sampling clock; The sampling register data corresponding to the target sampling clock is output as the parallel data acquisition result.

[0083] For example, the programmable logic unit compares the magnitudes of sum_diff1, sum_diff2, sum_diff3, and sum_diff4, determines the minimum value, and uses the sampling clock corresponding to the minimum value as the final data acquisition clock: when sum_diff1 is the minimum, the sampling data corresponding to CLK_0 is selected as the final acquisition data; when sum_diff2 is the minimum, the sampling data corresponding to CLK_90 is selected as the final acquisition data; when sum_diff3 is the minimum, the sampling data corresponding to CLK_180 is selected as the final acquisition data; and when sum_diff4 is the minimum, the sampling data corresponding to CLK_270 is selected as the final acquisition data. In this way, the optimal phase clock can be automatically selected within a 1-second statistical window based on the stability of the four different clock acquisition data, achieving adaptive determination of the final data acquisition clock.

[0084] Based on the above method embodiments, this application first generates multiple sampling clocks within a programmable logic unit using delay taps formed by cascading carry logic units, enabling multiple selectable sampling phase positions within the same clock cycle. Then, it samples and latches data onto the parallel data bus using these multiple sampling clocks, obtaining multiple sets of sampling register data for the same data stream at different sampling phase positions. Subsequently, within a preset statistical time window, it pairs and compares the sampling register data at adjacent sampling phase positions, performing an XOR operation bit by bit and accumulating the XOR results bit by bit to obtain multiple difference count values, thereby converting the sampling stability under different sampling phases into a quantifiable statistical indicator. Finally, it determines the sampling clock corresponding to the smallest difference count value as the target sampling clock and outputs the sampling register data corresponding to this target sampling clock as the parallel data acquisition result. Therefore, this application can automatically select a stable sampling phase through statistical comparison when there are inconsistencies or drifts in the arrival time of parallel data signals, improving the correctness, adaptability, and reliability of parallel data acquisition, and achieving adaptive adjustment of the sampling position without relying on continuously phase-locked loops or additional board-level delay devices.

[0085] See Figure 4 The diagram shows a schematic of a parallel data acquisition system provided in an embodiment of this application; the system is configured in a semiconductor testing device and includes at least a programmable logic unit.

[0086] For ease of explanation, only the parts relevant to the embodiments of this application are shown.

[0087] The parallel data acquisition system 400 may specifically include: The clock generation module 401 is used to generate multiple sampling clocks within a programmable logic unit based on the delay taps formed by cascading carry logic units. The multiple sampling clocks have the same frequency and correspond to different sampling phase positions within the same clock cycle. The sampling module 402 is used to sample and latch the parallel data bus with multiple sampling clocks to obtain multiple sets of sampling register data corresponding to each sampling clock. The difference counting module 403 is used to perform pairing comparisons on multiple sets of sampling register data at adjacent sampling phase positions within a preset statistical time window. It performs an XOR operation bit by bit on each pair of sampling register data and counts and accumulates the XOR result bit by bit to obtain multiple difference count values. The difference count values ​​are used to characterize the degree of difference between the corresponding pair of two sets of sampling register data. The target determination module 404 is used to determine the sampling clock corresponding to the minimum value among multiple difference count values ​​as the target sampling clock, and output the sampling register data corresponding to the target sampling clock as the parallel data acquisition result.

[0088] In this embodiment, the programmable logic unit internally comprises a carry delay chain consisting of multiple cascaded carry logic units; the clock generation module 401 specifically includes: A clock signal acquisition unit is used to acquire the input clock signal; The phase interval determination unit is used to determine the target phase interval based on the period of the input clock signal; A length configuration unit is used to determine the number of cascaded stages of the carry logic unit based on the target phase interval, and to configure the length of the carry delay chain according to the number of cascaded stages. The delay tap determination unit is used to cascade the input clock signal through multiple carry logic units using a carry delay chain, and to use the output nodes of each stage as delay taps respectively. The multi-channel clock determination unit is used to generate multiple sampling clocks based on the different delay positions corresponding to multiple delay taps within the same input clock period.

[0089] In this embodiment of the application, the sampling module 402 may specifically include: Independent sampling units are used to independently sample the parallel data bus using multiple sampling clocks; The data latch unit is used to latch the sampling results of each channel separately to obtain multiple sets of sampling register data that correspond one-to-one with each sampling clock.

[0090] In this embodiment, the difference counting module 403 may specifically include: The pairing unit is used to pair up the sampling register data corresponding to adjacent sampling phase positions within a preset statistical time window to obtain at least one pairing relationship and the sampling register data group corresponding to the pairing relationship. The XOR calculation unit is used to perform an XOR operation on the sample register data pairs in each sample register data group to obtain the XOR result. The counting unit is used to count the XOR result bit by bit and accumulate it within a preset statistical time window to obtain multiple difference count values ​​that correspond one-to-one with each pairing relationship.

[0091] In this embodiment, there are four sampling clocks, with a 90-degree phase difference between any two adjacent sampling clocks; the XOR calculation unit can specifically be used for: Pair the first sampling register data group corresponding to the first sampling clock with the second sampling register data group corresponding to the second sampling clock, and perform an XOR operation bit by bit to obtain the first XOR result; Pair the second sampling register data group with the third sampling register data group corresponding to the third sampling clock, and perform an XOR operation bit by bit to obtain the second XOR result; Pair the third sampling register data group with the fourth sampling register data group corresponding to the fourth sampling clock, and perform an XOR operation bit by bit to obtain the third XOR result; Pair the fourth sampling register data group with the first sampling register data group, and perform an XOR operation bit by bit to obtain the fourth XOR result.

[0092] In this embodiment of the application, the counting unit can specifically be used for: Within a preset statistical time window, the first XOR result, the second XOR result, the third XOR result, and the fourth XOR result are obtained for each sampling time. The first, second, third, and fourth XOR results are traversed bit by bit, and the number of bits in each XOR result that are at the preset logic value is counted to obtain the bit difference count corresponding to each XOR result at the sampling time. The positional difference counts of each XOR result within a preset statistical time window are accumulated to obtain the first difference count value, the second difference count value, the third difference count value, and the fourth difference count value, which correspond one-to-one with the first XOR result, the second XOR result, the third XOR result, and the fourth XOR result.

[0093] In this embodiment of the application, the target determination module 404 may specifically include: A comparison unit is used to compare the magnitudes of multiple difference count values; The determining unit is used to determine the sampling clock corresponding to the minimum difference count value as the target sampling clock; The output unit is used to output the sampling register data corresponding to the target sampling clock as the parallel data acquisition result.

[0094] The parallel data acquisition system 400 provided in this application embodiment can be applied to the parallel data acquisition method provided in the foregoing embodiments. For details, please refer to the description of the parallel data acquisition method provided in the above embodiments, which will not be repeated here.

[0095] See Figure 5 The diagram shows a structural block diagram of a parallel data acquisition system provided in an embodiment of this application. The parallel data acquisition system can be installed in a semiconductor testing device. The system includes at least a programmable logic unit for processing the input clock signal CLK and the data signal D to achieve adaptive acquisition of parallel data.

[0096] In this embodiment, the programmable logic unit includes a clock generation module, a clock signal acquisition module, a difference counting module, and a target determination module. The connection relationships of each module are as follows: Figure 5 As shown.

[0097] The clock generation module receives the input clock signal CLK and generates multiple sampling clocks within the programmable logic unit. These multiple sampling clocks have the same frequency as the input clock signal CLK but correspond to different sampling phase positions. Figure 5 In the example shown, the multi-channel sampling clocks include CLK_0, CLK_90, CLK_180 and CLK_270. The clock generation module outputs the multi-channel sampling clocks to the clock signal acquisition module.

[0098] The clock signal acquisition module is used to receive the data signal D, and to sample and latch the data signal D with multiple sampling clocks to obtain multiple sets of sampling register data corresponding to each sampling clock. The multiple sets of sampling register data are then output to the difference counting module.

[0099] The difference counting module is used to pair and compare the sampling register data at adjacent sampling phase positions within a preset statistical time window. It performs an XOR operation bit by bit on each pair of sampling register data and accumulates the XOR results bit by bit to obtain multiple difference count values. These difference count values ​​characterize the degree of difference between the two paired sets of sampling register data. The difference counting module outputs these multiple difference count values ​​to the target determination module.

[0100] The target determination module compares multiple difference count values, determines the sampling clock corresponding to the smallest difference count value as the target sampling clock, and outputs the sampling register data corresponding to the target sampling clock as the parallel data acquisition result. Based on this, the target sampling clock can be used as the data acquisition clock for subsequent output and processing to achieve adaptive determination of the sampling phase.

[0101] The aforementioned parallel data acquisition system can improve the accuracy, adaptability, and reliability of parallel data acquisition by generating multiple sampling clocks and obtaining multiple sets of latched sampling data within the programmable logic unit when there are inconsistencies or drifts in the arrival timing of parallel data signals. Furthermore, it can automatically determine the target sampling clock and output the corresponding acquisition data based on the difference counting results of sampling data at adjacent sampling phase positions. At the same time, it can complete the adaptive adjustment of the sampling phase without relying on external continuous phase modulation devices or additional board-level delay devices.

[0102] join Figure 6 This diagram illustrates the structure of a semiconductor testing device provided in an embodiment of this application. Figure 6 As shown, the semiconductor testing equipment 600 of this embodiment includes a parallel data acquisition system, wherein the parallel data acquisition system includes: at least one processor 610 ( Figure 6 (Only one is shown in the diagram), memory 620, programmable logic unit 630, and computer program 621 stored in the memory 620 and executable on the programmable logic unit 630. When the parallel data acquisition system executes the computer program 621, it implements the above-mentioned parallel data acquisition method.

[0103] The semiconductor testing equipment 600 can be a server, physical server, or computing device, etc. This semiconductor testing equipment may include, but is not limited to, a processor 610, a memory 620, and a programmable logic unit 630. Those skilled in the art will understand that... Figure 6 This is merely an example of semiconductor test equipment 600 and does not constitute a limitation on semiconductor test equipment 600. It may include more or fewer components than shown, or combine certain components, or use different components.

[0104] The processor 610 can be a central processing unit (CPU), or it can be other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor can be a microprocessor or any conventional processor.

[0105] In some embodiments, the memory 620 may be an internal storage unit of the semiconductor testing equipment 600, such as a hard disk or memory of the semiconductor testing equipment 600. In other embodiments, the memory 620 may be an external storage device of the semiconductor testing equipment 600, such as a plug-in hard disk, smart media card (SMC), secure digital (SD) card, flash card, etc., equipped on the semiconductor testing equipment 600. Furthermore, the memory 620 may include both internal and external storage units of the semiconductor testing equipment 600. The memory 620 is used to store operating systems, applications, bootloaders, data, and other programs, such as the program code of computer programs. The memory 620 can also be used to temporarily store data that has been output or will be output.

[0106] The programmable logic unit 630 can be an off-the-shelf field-programmable gate array (FPGA) or other programmable logic devices. The programmable logic unit is internally configured with a carry delay chain composed of multiple cascaded carry logic units. The carry delay chain is used to propagate the input clock signal in multiple cascaded carry logic units, and each output node is used as a delay tap. Based on the different delay positions corresponding to the multiple delay taps within the same input clock period, multiple sampling clocks are generated.

[0107] In specific implementations, the processor 610, memory 620, programmable logic unit 630, and computer program 621 described in the embodiments of this application can execute the embodiments of the parallel data acquisition method of this application, which will not be repeated here.

[0108] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the above-described division of functional units and modules is merely an example. In practical applications, the above functions can be assigned to different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above. The functional units and modules in the embodiments can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit. Furthermore, the specific names of the functional units and modules are only for easy differentiation and are not intended to limit the scope of protection of this application. The specific working process of the units and modules in the above system can be referred to the corresponding process in the foregoing method embodiments, and will not be repeated here.

[0109] In the above embodiments, the descriptions of each embodiment have different focuses. For parts that are not described in detail or recorded in a certain embodiment, please refer to the relevant descriptions of other embodiments.

[0110] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0111] In the embodiments provided in this application, it should be understood that the disclosed apparatus / semiconductor testing equipment and methods can be implemented in other ways. For example, the apparatus / semiconductor testing equipment embodiments described above are merely illustrative. For instance, the division of modules or units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the mutual coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between apparatuses or units may be electrical, mechanical, or other forms.

[0112] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0113] Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0114] If the integrated module / unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, all or part of the processes in the methods of the above embodiments can also be implemented by a computer program instructing related hardware. The computer program can be stored in a computer-readable storage medium, and when executed by a processor, it can implement the steps of the various method embodiments described above. The computer program includes computer program code, which can be in the form of source code, object code, executable files, or certain intermediate forms. The computer-readable medium can include: any entity or device capable of carrying the computer program code, recording media, USB flash drives, portable hard drives, magnetic disks, optical disks, computer memory, read-only memory (ROM), random access memory (RAM), electrical carrier signals, telecommunication signals, and software distribution media, etc. It should be noted that the content included in the computer-readable medium can be appropriately added or removed according to the requirements of legislation and patent practice in the jurisdiction. For example, in some jurisdictions, according to legislation and patent practice, computer-readable media do not include electrical carrier signals and telecommunication signals.

[0115] The implementation of all or part of the processes in the methods of the above embodiments can also be accomplished by a computer program product. When the computer program product is run on a semiconductor testing device, the semiconductor testing device can implement the steps in the various method embodiments described above.

[0116] The embodiments described above are only used to illustrate the technical solutions of this application, and are not intended to limit it. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.

Claims

1. A parallel data acquisition method, characterized in that, The method is applied to a parallel data acquisition system, wherein the system includes at least a programmable logic unit; the method includes: Within the programmable logic unit, multiple sampling clocks are generated based on delay taps formed by cascading carry logic units. These multiple sampling clocks have the same frequency and correspond to different sampling phase positions within the same clock cycle. The parallel data bus is sampled and latched using the multi-channel sampling clocks respectively, to obtain multiple sets of sampling register data corresponding to each sampling clock. Within a preset statistical time window, multiple sets of sampling register data at adjacent sampling phase positions are compared in pairs. For each pair of sampling register data, an XOR operation is performed bit by bit, and the XOR result is counted and accumulated bit by bit to obtain multiple difference count values. The difference count values ​​are used to characterize the degree of difference between the corresponding paired sets of sampling register data. The sampling clock corresponding to the minimum value among the multiple difference counts is determined as the target sampling clock, and the sampling register data corresponding to the target sampling clock is output as the parallel data acquisition result.

2. The method as described in claim 1, characterized in that, The programmable logic unit is internally configured with a carry delay chain consisting of multiple cascaded carry logic units; The generation of multiple sampling clocks based on delay taps formed by cascading carry logic units within the programmable logic unit includes: Obtain the input clock signal; The target phase interval is determined based on the period of the input clock signal; The number of cascaded stages of the carry logic unit is determined based on the target phase interval, and the length of the carry delay chain is configured according to the number of cascaded stages; The input clock signal is cascaded and propagated in multiple carry logic units using the carry delay chain, with each level's output node serving as a delay tap. Based on the different delay positions corresponding to the multiple delay taps within the same input clock cycle, a multi-channel sampling clock is generated.

3. The method as described in claim 1, characterized in that, The process of sampling and latching the parallel data bus using the multiple sampling clocks to obtain multiple sets of sampling register data corresponding to each sampling clock includes: The parallel data bus is sampled independently using the multi-channel sampling clock; The sampling results of each channel are latched separately to obtain multiple sets of sampling register data that correspond one-to-one with the sampling clock of each channel.

4. The method as described in claim 1, characterized in that, Within a preset statistical time window, multiple sets of sampling register data at adjacent sampling phase positions are compared in pairs. A bitwise XOR operation is performed on each pair of sampling register data, and the XOR result is counted and accumulated bit by bit to obtain multiple difference count values, including: Within the preset statistical time window, the sampling register data corresponding to the adjacent sampling phase positions are paired up to obtain at least one pairing relationship and the sampling register data group corresponding to the pairing relationship; Perform an XOR operation on the sample register data pairs in each sample register data group to obtain the XOR result; The XOR result is counted bit by bit and accumulated within the preset statistical time window to obtain multiple difference count values ​​that correspond one-to-one with each pairing relationship.

5. The method as described in claim 4, characterized in that, The sampling clock consists of four channels, with a 90-degree phase difference between adjacent sampling clock channels; the XOR operation is performed on the sampling register data pairs in each sampling register data group to obtain the XOR result, including: Pair the first sampling register data group corresponding to the first sampling clock with the second sampling register data group corresponding to the second sampling clock, and perform an XOR operation bit by bit to obtain the first XOR result; Pair the second sampling register data group with the third sampling register data group corresponding to the third sampling clock, and perform an XOR operation bit by bit to obtain the second XOR result; Pair the third sampling register data group with the fourth sampling register data group corresponding to the fourth sampling clock, and perform an XOR operation bit by bit to obtain the third XOR result; The fourth sampling register data group is paired with the first sampling register data group, and an XOR operation is performed bit by bit to obtain the fourth XOR result.

6. The method as described in claim 5, characterized in that, The step of counting the XOR results bit by bit and accumulating them within the preset statistical time window yields multiple difference count values ​​that correspond one-to-one with each pairing relationship, including: Within the preset statistical time window, the first XOR result, the second XOR result, the third XOR result, and the fourth XOR result are obtained for each sampling time. The first XOR result, the second XOR result, the third XOR result and the fourth XOR result are traversed bit by bit, and the number of bits in each XOR result that are at the preset logic value are counted to obtain the bit difference count corresponding to each XOR result at the sampling time. The position difference counts of each XOR result within the preset statistical time window are accumulated to obtain the first difference count value, the second difference count value, the third difference count value, and the fourth difference count value, which correspond one-to-one with the first XOR result, the second XOR result, the third XOR result, and the fourth XOR result.

7. The method as described in claim 1, characterized in that, The step of determining the sampling clock corresponding to the minimum value among the plurality of difference count values ​​as the target sampling clock, and outputting the sampling register data corresponding to the target sampling clock as the parallel data acquisition result, includes: Compare the magnitudes of the multiple difference count values; The sampling clock corresponding to the minimum difference count value is determined as the target sampling clock; The sampling register data corresponding to the target sampling clock is output as the parallel data acquisition result.

8. A parallel data acquisition system, characterized in that, The system includes at least a programmable logic unit; the system also includes: The clock generation module is used to generate multiple sampling clocks within the programmable logic unit based on the delay taps formed by the cascading carry logic units. The multiple sampling clocks have the same frequency and correspond to different sampling phase positions within the same clock cycle. The sampling module is used to sample and latch the parallel data bus with the multiple sampling clocks respectively, and to obtain multiple sets of sampling register data corresponding to each sampling clock. The difference counting module is used to compare multiple sets of sampling register data at adjacent sampling phase positions within a preset statistical time window. It performs an XOR operation bit by bit on each pair of sampling register data and counts and accumulates the XOR results bit by bit to obtain multiple difference count values. The difference count values ​​are used to characterize the degree of difference between the corresponding paired two sets of sampling register data. The target determination module is used to determine the sampling clock corresponding to the minimum value among the multiple difference count values ​​as the target sampling clock, and output the sampling register data corresponding to the target sampling clock as the parallel data acquisition result.

9. A semiconductor testing device, characterized in that, The semiconductor testing equipment includes at least the parallel data acquisition system as described in claim 8, wherein the parallel data acquisition system includes at least a programmable logic unit; The parallel data acquisition system is used to perform the method as described in any one of claims 1 to 7.

10. A computer-readable storage medium storing a computer program, characterized in that, When the computer program is executed by a processor, it implements the method as described in any one of claims 1 to 7.

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