A test circuit and method for a smart fixture test chip

Abstract

This application relates to the field of integrated circuit testing technology, and in particular to a test circuit and method for testing chips using an intelligent fixture. The test circuit includes a main control module, a probe contact detection module, a constant current calibration module, and a charge / discharge protection test module. The test method includes, in response to a test start command, the power supply linkage equalization module switches the power supply environment under test from a parallel equalization state to an isolated test state; the probe contact voltage fed back by the probe contact detection module determines the contact state of the test probes; when the test probe contact state is qualified, parameter calibration tests, protection function tests, and power consumption tests are performed on the chip under test according to preset test execution commands to obtain the corresponding test results; after receiving a test end command, the power supply linkage equalization module is controlled to return to the parallel equalization state. This application has the effect of improving the automation level and measurement accuracy of chip testing.

Description

Technical Field

[0001] This application relates to the field of integrated circuit testing technology, and in particular to a test circuit and method for a smart fixture test chip. Background Technology

[0002] Currently, battery management system chips require functional verification and parameter calibration using automated test fixtures during the manufacturing process to ensure the safety and accuracy of the chips in practical applications.

[0003] Existing test fixtures, when executing automated test sequences, typically proceed directly to the programming or parameter measurement stage after the probes are depressed, lacking pre-verification of the contact quality between the probes and the pins of the chip under test. Because test probes are prone to mechanical wear, surface oxidation, or positional misalignment during long-term use, abnormal contact resistance can easily occur, leading to deviations in the feedback voltage acquired by the system. Continuing to perform subsequent calibration or protection function tests under these conditions will result in numerous misjudgments and invalid programming, severely impacting the accuracy of test results and production yield; therefore, there is room for improvement. Summary of the Invention

[0004] To improve the automation and measurement accuracy of chip testing, this application provides a test circuit and method for testing chips using an intelligent fixture.

[0005] The above-mentioned objective of this application is achieved through the following technical solution:

[0006] A test circuit for an intelligent fixture test chip includes a main control module, a probe contact detection module, a constant current calibration module, and a charge / discharge protection test module;

[0007] The probe contact detection module includes a multi-channel signal detection amplification circuit. The input terminal of each signal detection amplification circuit is connected to the corresponding cell interface, and the output terminal of each signal detection amplification circuit is connected to the main control module for feedback of probe contact voltage.

[0008] The constant current calibration module includes a buck controller, a feedback operational amplifier, a power switch, and a sampling resistor network. The enable terminal of the buck controller is connected to the main control module, the input terminal of the feedback operational amplifier is connected to both ends of the sampling resistor network, and the output terminal of the feedback operational amplifier is connected to the control terminal of the power switch. It is used to output a constant calibration load current to the chip under test by adjusting the conduction level of the power switch.

[0009] The charge / discharge protection test module includes a buck-boost conversion circuit and a current monitoring and conditioning circuit. The buck-boost conversion circuit includes a boost circuit and a buck circuit that work together. It is controlled by the main control module to output a simulated charging voltage or a simulated cell voltage. The output of the current monitoring and conditioning circuit is connected to the main control module and is used to determine the protection status of the chip under test under the simulated charging voltage or simulated cell voltage by observing the change in the feedback loop current.

[0010] By adopting the above technical solutions, the signal detection and amplification circuit in the probe contact detection module feeds back the probe contact voltage, enabling real-time monitoring of the physical contact quality between the test probe and the pads of the chip under test. This effectively avoids test data distortion or misjudgment caused by excessive contact resistance, improving the reliability of test results. The constant current calibration module outputs a calibration load current to the chip under test via a buck controller, feedback operational amplifier, power switch, and sampling resistor network, constructing a high-precision closed-loop constant current source to provide a stable current reference for the chip. The charge / discharge protection test module simulates operating conditions and feeds back the protection status through a buck-boost conversion circuit and current monitoring and conditioning circuit, ensuring the effectiveness of the chip's safety protection functions.

[0011] In a preferred embodiment, the test circuit may be further configured such that it includes a power consumption measurement module.

[0012] The power consumption measurement module includes a multi-channel switching relay group and a current monitoring amplifier. The multi-channel switching relay group is connected in the power supply circuit of the chip under test and is used to selectively switch the power supply circuit of the chip under test to different operating modes.

[0013] The input terminal of the current monitoring amplifier is connected to both ends of the resistor under test, and is used to feed back the power consumption bit value of the chip under test in different operating modes to the main control module by collecting the voltage drop generated by the resistor under test.

[0014] By adopting the above technical solution, the power supply path can be selectively switched to different working modes through the multi-channel switching relay group in the power consumption measurement module, and the power consumption bit value can be fed back by the current monitoring amplifier, so as to realize the current measurement of the chip under different operating conditions and improve the accuracy of energy efficiency assessment.

[0015] In a preferred embodiment, the test circuit may be further configured such that it includes a power supply linkage equalization module.

[0016] The power supply linkage equalization module includes multiple battery cell interfaces and multiple equalization relay groups. The normally closed contacts of each relay in the equalization relay group are connected to the corresponding battery cell interface. The coil terminal of each relay is connected to an external power supply. The relay is used to form a parallel equalization circuit through the normally closed contacts when the coil terminal is de-energized, and to disconnect the parallel equalization circuit when the coil terminal is energized to switch to an isolated test state.

[0017] By adopting the above technical solution, the normally closed contacts of each relay in the power-linked equalization module form a parallel equalization circuit in the power-off state, and disconnect the parallel circuit in the power-on state to switch to the isolated test state of mutual isolation. This can automatically level the potential of the simulated cell during non-test intervals, thereby ensuring that each chip under test is in a consistent initial electrical environment before the test begins, which significantly improves the consistency and comparability of test data.

[0018] In a preferred embodiment, the test circuit may be further configured such that it includes a MOS driving module.

[0019] The MOS driving module includes multiple switching transistors and gate current-limiting resistors. The control terminal of the switching transistor is connected to the main control module through the corresponding gate current-limiting resistor. The input terminal of the switching transistor is connected to the coil terminal of the relay in the power consumption measurement module. It is used to respond to the level output by the main control module and switch between different test circuits by driving the corresponding relay to turn on or off.

[0020] By adopting the above technical solution, the switching transistor in the MOS driver module responds to the level output by the main control module to drive the corresponding relay to engage or disengage, thereby improving the automation level and response speed of the system when switching between different test items.

[0021] The second objective of this invention is achieved through the following technical solution:

[0022] A testing method for a smart fixture test chip, applied to a test circuit of the smart fixture test chip as described above, the testing method for the smart fixture test chip includes:

[0023] In response to the test start command, the power supply linkage equalization module activates, switching the power supply environment under test from the parallel equalization state to the isolated test state of mutual isolation;

[0024] The probe contact state is determined by using the probe contact detection module to feed back the probe contact voltage and the relationship between the probe contact voltage and a preset threshold.

[0025] When the test probe is in a qualified contact state, the chip under test is tested according to the preset test execution command to obtain the corresponding test results. The test includes at least parameter calibration test by controlling the constant current calibration module to apply calibration load current to the chip under test, protection function test by controlling the charge and discharge protection test module to simulate battery conditions, and power consumption test by controlling the power consumption measurement module to switch power supply paths.

[0026] Upon receiving the test end command, the power supply linkage equalization module is controlled to return to the parallel equalization state.

[0027] By adopting the above technical solution, the power supply environment is switched from a parallel balanced state to an isolated test state in response to the test start command, providing a voltage environment that conforms to the actual application scenario for the chip under test and ensuring the authenticity of the test conditions. By using the probe contact detection module to determine the contact state of the test probes, a physical self-test can be performed before formal testing, thereby reducing the test interruption rate caused by probe mechanical failure. By sequentially executing parameter calibration tests, protection function tests, and power consumption tests, a comprehensive performance evaluation of the chip can be completed with one-click operation, thereby greatly improving production testing efficiency. By restoring to the parallel balanced state after the test, the environment can be automatically reset, thus preparing for the next round of cycle testing.

[0028] In a preferred embodiment, this application can be further configured such that the step of determining the contact state of the test probe specifically includes:

[0029] Obtain the probe contact voltage output by the signal detection amplifier circuit for each signal, and determine the preset reference voltage threshold.

[0030] Calculate the voltage difference between the probe contact voltage and the preset reference voltage threshold. If the voltage difference is within the preset range, the corresponding test probe contact state is determined to be qualified.

[0031] If the voltage difference exceeds the preset range, the corresponding test probe contact state is determined to be unqualified, and a probe poor contact alarm command is triggered to interrupt the test process.

[0032] By adopting the above technical solution, the electrical performance of the contact point can be quantitatively evaluated by calculating the voltage difference between the probe contact voltage and the preset reference voltage threshold and determining whether it is within the preset range, thereby identifying the contact state of the test probe.

[0033] In a preferred embodiment, this application can be further configured such that, prior to the step of testing the chip under test according to a preset test execution instruction, the test method further includes:

[0034] The relay in the charge / discharge protection test module is driven to close for a preset duration to apply a wake-up level signal to the chip under test;

[0035] After the chip under test is woken up, the reset signal of the chip under test is pulled low, and the target firmware program is written to the chip under test via the communication bus. The written target firmware program is then verified to generate the firmware burning result.

[0036] By adopting the above technical solution, a wake-up level signal is applied by driving the relay in the charge and discharge protection test module to close for a preset time, which can activate the chip under test from the initial inactive state, ensuring that each power domain and logic unit of the chip is in a working state; by pulling the reset signal of the chip under test low and writing the target firmware program after the chip is woken up, the success rate of firmware burning in complex circuit environments is significantly improved, and communication handshake failure caused by chip inactivation is avoided.

[0037] In a preferred embodiment, this application can be further configured such that the parameter calibration test step specifically includes:

[0038] The linear constant current circuit in the constant current calibration module is controlled to output a constant current with a preset range as the calibration load current.

[0039] The internal current measurement value fed back by the chip under test is read through the communication bus, and the calibration coefficient is calculated based on the calibration load current and the internal current measurement value. The calibration coefficient is written into the non-volatile memory of the chip under test to generate parameter calibration test results.

[0040] By adopting the above technical solution, the calibration coefficient is calculated and written into non-volatile memory by controlling the constant current calibration module to output a constant current and reading the chip feedback value. This can eliminate systematic measurement deviations and significantly improve the sampling accuracy of the chip under test in practical applications.

[0041] In a preferred embodiment, this application can be further configured such that the protection function test step specifically includes:

[0042] The relay in the power supply linkage equalization module is controlled to operate in series with a fixed resistance circuit, and the current monitoring and conditioning circuit in the charge and discharge protection test module is used to monitor the current in the discharge test circuit. Based on the current, the undervoltage protection test result is generated.

[0043] The buck-boost conversion circuit in the charge-discharge protection test module is controlled to output a simulated charging voltage signal, and a relay is connected in series with a fixed resistance circuit to form a simulated charging current. The time interval from the output of the simulated charging current to the feedback current from the current monitoring and conditioning circuit reaching a preset current threshold is recorded. Based on the time interval, an overvoltage protection test result is generated.

[0044] By adopting the above technical solution, the response speed of the chip's protection function can be quantitatively evaluated by controlling the relay action to simulate the cell disconnection state and using the current monitoring and conditioning circuit to monitor the change of discharge current. By recording the time interval from the output of the simulated overvoltage signal to the current shutdown, it is possible to determine whether the chip meets the strict safety timing specifications.

[0045] In a preferred embodiment, this application can be further configured such that the power consumption test step specifically includes:

[0046] Drive the multiplexer relay group in the power consumption measurement module to operate;

[0047] The power consumption bit value output by the current monitoring amplifier in the power consumption measurement module is collected, and the power consumption bit value is compared with a preset power consumption judgment threshold to generate a power consumption test result.

[0048] By adopting the above technical solution, driving a multi-channel switching relay group, and collecting power consumption bit values ​​for threshold comparison, the power management performance of the chip can be comprehensively evaluated, thereby improving the ability to screen for low-power quality chips.

[0049] In summary, this application includes at least one of the following beneficial technical effects:

[0050] 1. By feeding back the probe contact voltage through the signal detection and amplification circuit in the probe contact detection module, the physical contact quality between the test probe and the pads of the chip under test can be monitored in real time, thereby effectively avoiding test data distortion or misjudgment caused by excessive contact resistance and improving the reliability of test results; by outputting a calibration load current to the chip under test through the buck controller, feedback operational amplifier, power switch and sampling resistor network in the constant current calibration module, a high-precision closed-loop constant current source can be constructed, thereby providing a stable current reference for the chip; by simulating the working conditions and feeding back the protection status through the buck-boost conversion circuit and current monitoring and conditioning circuit in the charge and discharge protection test module, the logic response of the chip under overvoltage or undervoltage conditions can be dynamically verified, thereby ensuring the effectiveness of the chip's safety protection function;

[0051] 2. By responding to the test start command, the power supply environment is switched from a parallel balanced state to an isolated test state, providing the chip under test with a voltage environment that matches the actual application scenario and ensuring the authenticity of the test conditions. By using the probe contact detection module to determine the contact state of the test probes, a physical self-test can be performed before formal testing, thereby reducing the test interruption rate caused by probe mechanical failure. By sequentially executing parameter calibration tests, protection function tests, and power consumption tests, a comprehensive performance evaluation of the chip can be completed with one-click operation, thereby greatly improving production testing efficiency. By restoring to the parallel balanced state after the test, the environment can be automatically reset, thus preparing for the next round of cycle testing. Attached Figure Description

[0052] Figure 1 This is a schematic diagram of the test circuit of an intelligent fixture test chip provided in an embodiment of this application;

[0053] Figure 2 A schematic diagram of the circuit structure of a test circuit connector for an intelligent fixture test chip provided in an embodiment of this application;

[0054] Figure 3 A circuit diagram of one detection path in the probe contact detection module provided in the embodiments of this application;

[0055] Figure 4 A circuit diagram of the constant current calibration module provided in an embodiment of this application;

[0056] Figure 5 A circuit diagram of the buck-boost conversion circuit in the charge / discharge protection test module provided in this application embodiment;

[0057] Figure 6 A circuit diagram of the current monitoring and conditioning circuit in the charge and discharge protection test module provided in this application embodiment;

[0058] Figure 7 This is a circuit diagram of the multi-channel switching relay group in the power consumption measurement module provided in the embodiments of this application;

[0059] Figure 8 A circuit diagram of the current monitoring amplifier in the power consumption measurement module provided in this application embodiment;

[0060] Figure 9 A circuit diagram of the power supply linkage equalization module provided in an embodiment of this application;

[0061] Figure 10 A circuit diagram of the MOS driving module provided in an embodiment of this application;

[0062] Figure 11This is a flowchart illustrating the implementation of a testing method for an intelligent fixture test chip in one embodiment of this application.

[0063] Figure 12 A circuit diagram for activating the chip under test provided in an embodiment of this application;

[0064] Figure 13 This is another circuit diagram for activating the chip under test provided in an embodiment of this application. Detailed Implementation

[0065] The following embodiments will help those skilled in the art to further understand the function of this application, but do not limit this application in any way. It should be noted that those skilled in the art can make several modifications and improvements without departing from the concept of this application. These all fall within the protection scope of this application.

[0066] In the following description, specific details such as particular system architectures and techniques are set forth for illustrative purposes and not for limitation, in order to provide a thorough understanding of the embodiments of this application. However, those skilled in the art will understand that this application may also be implemented in other embodiments without these specific details. In other instances, detailed descriptions of well-known systems, apparatuses, circuits, and methods have been omitted so as not to obscure the description of this application with unnecessary detail.

[0067] The terminology used in the following embodiments of this application is for the purpose of describing particular embodiments only and is not intended to be limiting of this application. As used in the specification and appended claims of this application, the singular expressions “a,” “an,” “the,” “the,” “the,” and “this” are intended to include the plural expressions as well, unless the context clearly indicates otherwise. It should also be understood that the term “and / or” as used in this application refers to and includes any or all possible combinations of one or more of the listed items.

[0068] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as implying or suggesting relative importance or implicitly indicating the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature, and in the description of the embodiments of this application, unless otherwise stated, "multiple" means two or more.

[0069] The present application will be further described in detail below with reference to the accompanying drawings.

[0070] Please refer to Figure 1 , Figure 1This is a schematic diagram of the test circuit of an intelligent fixture test chip provided in an embodiment of this application. The test circuit includes a main control module, a probe contact detection module, a constant current calibration module, and a charge / discharge protection test module.

[0071] In this embodiment, the main control module serves as the central processing unit of the entire test circuit, including a first control unit and a second control unit as the core. The processing chip can be an STM32F407ZGT6. The first control unit and the second control unit are synchronized via SPI or I2C bus. The first control unit is responsible for executing the core test algorithm and acquiring high-precision analog signals. Its ADC pin is connected to the output of each detection module, namely the probe contact detection module, the constant current calibration module, and the charge and discharge protection test module. The second control unit is responsible for system-level power enable, communication management, and interaction with the host computer.

[0072] The probe contact detection module includes multiple signal detection and amplification circuits. The input of each signal detection and amplification circuit is connected to the corresponding cell interface, and the output of the signal detection and amplification circuit is connected to the main control module to provide feedback on the probe contact voltage.

[0073] In this embodiment, the probe contact detection module is used to verify the physical contact between the probe and the test point of the chip under test at the beginning of the testing process. This module includes multiple signal detection and amplification circuits based on the TPA191A5 chip. The TPA191A5 chip is an operational amplifier. The non-inverting input terminal IN+ (pin 4) of the operational amplifier is connected to the cell interface such as B1++, B2++, etc. through a current-limiting resistor and a filter capacitor. Its inverting input terminal IN- (pin 5) is connected to signals such as A1C, A2C, etc. through a current-limiting resistor and a filter capacitor. Signals A1C, etc., are detected by a reference... Figure 2 The connector U28 shown inputs a reference or comparison potential. Its reference pin REF (pin 1) is connected to a reference voltage such as 1.65V, and its output pin OUT (pin 6) is connected to the corresponding ADC pin of the first control unit, such as ADC-A1+, ADC-A2+, etc. The operational amplifier conditions and amplifies the weak potential difference at the probe contact point, and the feedback voltage generated at its output pin 6 is sent to the ADC pin of the first control unit. Taking the ADC-A1+ probe detection path as an example, refer to... Figure 3 As shown, the first control unit reads the probe contact voltage corresponding to the ADC-A1+ signal through the corresponding ADC pin. If the probe contact voltage value is within the preset range of 1.65V±0.2V, i.e. 1.45V to 1.85V, it is determined that a good electrical contact has been formed between the probe and the pad; otherwise, it is determined to be a poor contact and an alarm is triggered.

[0074] The constant current calibration module includes a buck controller, a feedback operational amplifier, a power switch, and a sampling resistor network. The enable terminal of the buck controller is connected to the main control module, the input terminal of the feedback operational amplifier is connected to both ends of the sampling resistor network, and the output terminal of the feedback operational amplifier is connected to the control terminal of the power switch. It is used to output a constant calibration load current to the chip under test by adjusting the conduction level of the power switch.

[0075] In this embodiment, refer to Figure 4 As shown, the constant current calibration module provides a high-precision 2A current reference for the chip under test. This module includes a buck controller U4, a feedback operational amplifier U6, a power switch Q1, and a sampling resistor network. The buck controller can be a JW5068A, the feedback operational amplifier can be a TP1281L1, and the power switch Q1 is a JMSL0303AG. The enable pin EN (pin 11) of the buck controller is connected to the second control unit, receiving a 1.4V-EN signal from it. The sampling resistor network is connected in series in the current output path. The buck controller U4, through its SW pins (pins 6, 19, and 20) in conjunction with the external inductor L6 and filter capacitor, performs energy conversion, generating a stable DC operating voltage at the output, which is then supplied to the drain of the power switch Q1. The input terminals of the feedback operational amplifier (pins 3 and 4) are connected across the sampling resistor network, and its output pin (pin 1) is connected to the gate of the power switch Q1. Furthermore, when the second control unit issues an enable command such as the 1.4V-EN command, the feedback operational amplifier U6 adjusts the drive voltage output to the gate of the power switch Q1 in real time to control the channel conduction of the power switch Q1, thereby compensating for load fluctuations or voltage drift and ensuring that a constant calibration load current of 2A is output to the chip under test at the P1+ and PX- terminals of the interface J22.

[0076] The charge / discharge protection test module includes a buck-boost conversion circuit and a current monitoring and conditioning circuit. The buck-boost conversion circuit includes a boost circuit and a buck circuit that work together and are controlled by the main control module to output a simulated charging voltage or a simulated cell voltage. The output of the current monitoring and conditioning circuit is connected to the main control module and is used to determine the protection status of the chip under test under simulated charging voltage or simulated cell voltage by observing the changes in the feedback loop current.

[0077] In this embodiment, refer to Figures 5 to 6As shown, the charge / discharge protection test module constructs a controlled analog power supply system through the cooperation of a boost circuit based on the TPS55340 chip and a buck circuit based on the JW5117C chip. It also includes a current monitoring and conditioning circuit. During overvoltage protection testing, the main control module first starts the analog power supply system using enable signals BUCK-EN and EN-BUCK-16.8V. The boost circuit U10 increases the 12V bus voltage, and then the buck circuit U11 precisely adjusts it to a preset overvoltage test point, such as 16.8V, simulating the high-voltage output condition of a charger. This voltage is then applied to the power terminal of the chip under test via relay K38. Furthermore, during undervoltage protection or discharge testing, the main control module controls the relays K35 (F-EN) and K60 (H1) in the discharge load circuit to conduct, thereby connecting the chip under test to the discharge path composed of the power MOSFET Q38 and the sampling resistor R163. The input pins of the current monitoring and conditioning circuit, namely pins 4 and 5, are connected to the interface nodes JP+ and JP- of the power terminal of the chip under test, respectively. Its output pin, namely pin 6, is connected to the Isns pin of the first control unit. When the first control unit activates the discharge or charging path by controlling the on / off state of the external relays, and monitors the timing of the current returning to zero in the Isns signal in real time through the current monitoring and conditioning circuit, if the current reflected in the Isns signal disappears within a preset response time (i.e., drops below 0.03A) after the simulated overvoltage signal is output, or after the undervoltage state of the battery cell is simulated through the power supply linkage equalization module, then the overvoltage protection or undervoltage protection logic of the chip under test is determined to have executed correctly. Thus, the first control unit can determine whether the chip under test has successfully executed the overvoltage or undervoltage protection action based on the time interval of the current disappearance.

[0078] Based on the above embodiments, as an optional embodiment, the test circuit further includes a power consumption measurement module;

[0079] The power consumption measurement module includes a multiplex relay group and a current monitoring amplifier. The multiplex relay group is connected to the power supply circuit of the chip under test and is used to selectively switch the power supply circuit of the chip under test to different operating modes.

[0080] The input of the current monitoring amplifier is connected to both ends of the resistor under test. It is used to collect the voltage drop generated by the resistor under test and feed back the power consumption bit value of the chip under test in different operating modes to the main control module.

[0081] In this embodiment, refer to Figure 7 and Figure 8As shown, the power consumption measurement module uses a multi-channel switching relay group, such as relays K39 and K40, in conjunction with a sampling resistor array, such as resistors R183, R39, and R40, to achieve precise measurement of the power supply circuit current of the chip under test. The first control unit drives relay K39 or relay K40 to engage according to the current power consumption mode being measured, such as power-down power consumption or operating power consumption, thereby switching the power supply circuit of the chip under test to the sampling resistor path of the corresponding range. Furthermore, a current monitoring amplifier U14 (model TPA191A5) is used. The input terminals IN+ and IN- of the current monitoring amplifier U14 are connected across the currently selected sampling resistor to collect the weak voltage drop signal generated when current flows through the sampling resistor in real time. After linearly amplifying this voltage drop signal, the current monitoring amplifier U14 outputs a bit signal I-ID reflecting the power consumption magnitude to the ADC pin of the first control unit. The first control unit converts the acquired bit values ​​into actual current values ​​based on a preset scaling factor, such as 0.305uA / bit, and performs a logical comparison with a preset power consumption threshold to generate test results for power-down power consumption, operating power consumption, and sleep power consumption.

[0082] Based on the above embodiments, as an optional embodiment, the test circuit further includes a power supply linkage equalization module;

[0083] The power supply linkage equalization module includes multiple battery cell interfaces and multiple equalization relay groups. The normally closed contacts of each relay in the equalization relay group are connected to the corresponding battery cell interface, and the coil terminal of each relay is connected to an external power supply. It is used to form a parallel equalization circuit through the normally closed contacts when the coil terminal is de-energized, and to disconnect the parallel equalization circuit to switch to the isolated test state when the coil terminal is energized.

[0084] In this embodiment, refer to Figure 9 As shown, the equalization relay group specifically includes multiple relays of models K42 to K57. The normally closed contact (pin 2) of each relay is used to interconnect the cell interfaces of the chip under test, such as A1+ / A1- to B4+ / B4-. This connection method ensures that, in the initial state where the relay coils are not energized, all cell interfaces form a low-impedance parallel circuit through the normally closed contacts, thereby achieving potential equalization. One end of each relay coil is connected to the VCC_12V power supply, and the other end is grounded and connected to the other end of the coil through a freewheeling diode. In the non-test state, the relay coils are de-energized, and the system is in a parallel equalization state. After the test begins, the main control module drives the switching transistor to conduct, energizing the relay coils and opening the normally closed contacts, thus switching the test environment to an isolated test state.

[0085] Based on the above embodiments, as an optional embodiment, the test circuit further includes a MOS driving module;

[0086] The MOS driver module includes multiple switching transistors and gate current-limiting resistors. The control terminal of the switching transistor is connected to the main control module through the corresponding gate current-limiting resistor. The input terminal of the switching transistor is connected to the coil terminal of the relay in the power consumption measurement module. It is used to respond to the level output by the main control module and switch between different test circuits by driving the corresponding relay to turn on or off.

[0087] In this embodiment, refer to Figure 10 As shown, the MOS driver module includes multiple 2N7002K-7 switching transistors. The control terminal (gate) of the switching transistors is connected to the control terminal of the first control unit through a current-limiting resistor, and the drain is connected to the low potential terminal of the relay coil in the corresponding power consumption measurement module. Thus, the first control unit controls the saturation and cutoff of the switching transistors by outputting high and low levels, thereby achieving control.

[0088] In one embodiment, such as Figure 11 As shown, this application discloses a testing method for an intelligent fixture test chip, applied to the test circuit of the aforementioned intelligent fixture test chip. The testing method specifically includes the following steps:

[0089] S10. In response to the test start command, the power supply linkage equalization module activates, switching the power supply environment under test from the parallel equalization state to the isolated test state.

[0090] Specifically, after receiving the one-key test start command, the coils of relays K42 to K57 in the power supply linkage equalization module are energized and engaged in the first control unit of the main control module. In the initial state where the coils are not energized, the interfaces of each cell, such as A1+ / A1- to B4+ / B4-, are interconnected through the normally closed contact pin 2 of the relay to form a low-impedance parallel circuit. This circuit is used to introduce an external equalization power supply to achieve automatic potential equalization between each analog cell.

[0091] Furthermore, when the relay engages, the normally closed contact opens, and the physical connection between the cell interfaces is severed, thus switching the power supply environment under test from an initial interconnected state to an isolated test state. In the isolated test state, the cell interfaces no longer have a direct parallel connection, and the main control module configures these isolated interfaces as series test conditions through external circuitry. This switching action from "interconnection" to "isolation" eliminates interference from the equalization circuit on the sampling signal, thereby simulating a battery pack voltage environment consistent with the real-world application scenario of the BMS chip, providing a foundation for subsequent high-precision electrical parameter tests.

[0092] S20. Using the probe contact voltage fed back by the probe contact detection module, determine the contact state of the test probe based on the relationship between the probe contact voltage and the preset threshold.

[0093] Specifically, the probe contact detection module uses multiple signal detection and amplification circuits based on the TPA191A5 chip to acquire the potential of the contact points between each test probe and the pads of the chip under test in real time. The operational amplifier TPA191A5 performs gain conditioning and impedance transformation on the weak voltage signal from the probe contact points, and the analog voltage signal generated at its output pin 6 is fed back to the ADC pin of the first control unit. The first control unit converts this analog voltage into a digital quantity through its built-in analog-to-digital converter and performs a logical comparison with a preset 1.65V reference threshold, thereby verifying the electrical continuity of the test circuit at the physical level.

[0094] S30. When the test probe contact state is qualified, the chip under test is tested according to the preset test execution instructions to obtain the corresponding test results. The test includes at least the parameter calibration test by controlling the constant current calibration module to apply the calibration load current to the chip under test, the protection function test by controlling the charge and discharge protection test module to simulate the battery working conditions, and the power consumption test by controlling the power consumption measurement module to switch the power supply path.

[0095] Specifically, after confirming good contact of the test probes, the main control module controls the constant current calibration module to output a standard current of 2A to calibrate the current sampling accuracy of the chip under test (DUT) according to the preset test execution instructions. Subsequently, it controls the boost or buck circuit in the charge / discharge protection test module to simulate overvoltage or undervoltage battery conditions. In the overvoltage simulation, a controlled simulated charging voltage is generated through a boost-then-buck circuit composed of the boost and buck circuits to verify the high-voltage shutdown logic of the DUT. In the undervoltage or discharge simulation, the system uses a linear constant current discharge circuit for testing. The main control module drives the power transistor Q38 to amplify its output and controls the fixed-value resistor connected in series in the discharge path. In this embodiment, the fixed-value resistor is preferably a 1-ohm resistor. This verifies the protection action timing of the DUT. Simultaneously, using the switching matrix in the power consumption measurement module, the power supply path of the DUT is switched to different operating modes to measure its static current consumption under different operating conditions. This series of tests comprehensively covers the functionality, accuracy, and reliability indicators of the DUT.

[0096] S40. After receiving the test end command, control the power supply linkage equalization module to restore it to the parallel equalization state.

[0097] Specifically, after all test items are completed or a stop command is triggered, the first control unit removes the enable signal to the power supply linkage equalization module via the MOS drive module, causing relays K4 to K18 to disconnect. At this time, the moving contacts of the relays reset under spring pressure and reconnect with the normally closed contact pin 2, allowing each cell interface to re-enter the interconnected parallel state. Through this automatic recovery mechanism, the potential of each simulated cell can be balanced and corrected using an external equalization power supply, ensuring that the next chip under test starts testing under the same initial electrical environment.

[0098] In one embodiment, step S20, namely the step of determining the contact state of the test probe, specifically includes:

[0099] S21. Obtain the probe contact voltage output by each signal detection amplifier circuit and determine the preset reference voltage threshold.

[0100] Specifically, the first control unit reads the ADC channels connected to each output pin 6 of the probe contact detection module through high-speed polling to obtain real-time voltage data reflecting the physical characteristics of each contact point; the preset reference voltage threshold is set to 1.65V, which is a static level reference point determined based on the REF pin of the operational amplifier TPA191A5 being connected to the precision reference source U18.

[0101] S22. Calculate the voltage difference between the probe contact voltage and the preset reference voltage threshold. If the voltage difference is within the preset range, the corresponding test probe contact state is determined to be qualified.

[0102] Specifically, the first control unit subtracts 1.65V from the real-time probe contact voltage and takes the absolute value to obtain the offset voltage reflecting the influence of contact resistance. The preset range is set to ±0.2V, that is, when the detection voltage is between 1.45V and 1.85V, it is determined that the contact resistance between the probe and the pad is at an extremely low level, which can ensure the lossless transmission of the test signal, and therefore the contact state is determined to be qualified.

[0103] S23. If the voltage difference exceeds the preset range, the corresponding test probe contact state is determined to be unqualified, and a probe poor contact alarm command is triggered to interrupt the test process.

[0104] Specifically, if the calculated voltage deviation is too large, resulting in a detection voltage below 1.45V or above 1.85V, it indicates that the probe channel has problems such as mechanical deformation, excessively thick surface oxide layer, or insufficient downward pressure, leading to abnormal contact resistance. In this case, the first control unit immediately determines that the probe contact state is unqualified, stops subsequent power-on or programming operations, and issues an alarm through an alarm module such as a buzzer driven by the Alarm pin, thereby effectively avoiding chip misjudgment or hardware damage caused by poor contact.

[0105] In one embodiment, before step S30, that is, before the step of testing the chip under test according to the preset test execution instructions, the test method further includes:

[0106] S301, the relay in the drive charge and discharge protection test module is closed for a preset duration to apply a wake-up level signal to the chip under test.

[0107] Specifically, refer to Figure 12 As shown, after confirming that the probe contact is qualified, the main control module first performs a wake-up action. The main control module drives the peripheral relay K3 in the charge and discharge protection test module to close for 1 second. A stable high-level pulse signal is applied to the specific wake-up pin A20 of the chip under test through the hardware link as a wake-up level signal to wake up the chip under test.

[0108] S302. After the chip under test is woken up, the reset signal of the chip under test is pulled low, and the target firmware program is written to the chip under test via the communication bus. The target firmware program after writing is verified to generate the firmware burning result.

[0109] Specifically, refer to Figure 13 As shown, after the chip is successfully woken up, the main control module drives the reset relay K41 to conduct. Since the chip under test is integrated on the PCBA (PCBA), the reset signal of the chip under test is pulled low, that is, the reset signal MCU Reset of the MCU in the PCBA under test is pulled low, causing it to enter the predetermined download or programming mode. Subsequently, the first control unit performs the firmware download action through the I2C communication bus composed of SMBC and SMBD, and writes the HEX or BIN format firmware program required by the chip under test into the memory of the PCBA under test according to the preset burning protocol. After the writing is completed, the system performs cyclic redundancy check to ensure the integrity of the code transmission. If the check data is completely consistent with the original file, the check passes, and a firmware burning result of successful burning is generated. Then, the reset signal is released, allowing the MCU of the PCBA under test to load and run the new firmware.

[0110] In one embodiment, step S30, namely the parameter calibration test step, specifically includes:

[0111] S31. Control the linear constant current circuit in the constant current calibration module to output a constant current with a preset range as the calibration load current.

[0112] Specifically, the second control unit 4 outputs a 1.4V-EN high-level command to enable the buck controller U4 in the constant current calibration module. U4 provides a stable DC operating voltage to the drain of the power switch Q1. At this time, the feedback operational amplifier U6 acquires the voltage drop signal across the sampling resistor network R28 in real time and adjusts the drive voltage output to the gate of the power switch Q1 in real time according to the signal, so that the power switch Q1 is in the amplification state, that is, the power switch Q1 enters the linear operating region. Through this linear constant current mechanism based on the negative feedback of the operational amplifier to adjust the conduction degree of the power transistor channel, the system can output a calibration load current with a constant range of 2A from the P1+ and PX- terminals of interface J22.

[0113] S32. Read the internal current measurement value fed back by the chip under test through the communication bus, calculate the calibration coefficient based on the calibration load current and the internal current measurement value, and write the calibration coefficient into the non-volatile memory of the chip under test to generate parameter calibration test results.

[0114] Specifically, when a constant current of 2A flows through the chip under test (DUT), the first control unit reads the raw reading from the chip's internal current sensing circuit via the communication bus. The main control module calculates the gain error between this reading and the standard 2A, derives a calibration coefficient, and writes this coefficient into the DUT's EEPROM. This method eliminates measurement deviations caused by component tolerances in the DUT.

[0115] In one embodiment, step S30, namely the protection function test step, specifically includes:

[0116] S311, the relay in the control power supply linkage equalization module is activated to enter the fixed resistance circuit, and the current monitoring and conditioning circuit in the charge and discharge protection test module is used to monitor the current in the discharge test circuit. Based on the current, the undervoltage protection test result is generated.

[0117] Specifically, during protection function verification, the main control module drives a specific group of relays to operate, connecting a fixed-value resistor, such as a 1-ohm power resistor, in series with the discharge test circuit to cut off the path of a cell in the simulated battery pack. This simulates the undervoltage fault condition or high-current discharge condition when the battery is depleted on the chip under test side. Simultaneously, the current monitoring and conditioning circuit U15 in the charge / discharge protection test module monitors the feedback voltage of the Isns pin. If the first control unit detects that the discharge current reflected by the Isns signal rapidly drops below 0.03A within a preset time, corresponding to an ADC value of approximately 2048 bits, it indicates that the undervoltage protection algorithm of the chip under test has correctly identified the fault and cut off the discharge MOSFET, thus generating a test result indicating that the undervoltage protection has passed.

[0118] S312, control the buck-boost conversion circuit in the charge-discharge protection test module to output the simulated charging voltage signal, and control the relay to be connected in series with the fixed resistance circuit to form the simulated charging current and record the time interval from the output of the simulated charging voltage signal to the feedback current of the current monitoring and conditioning circuit reaching the preset current threshold. Based on the time interval, generate the overvoltage protection test result.

[0119] Specifically, during the overvoltage protection test, the main control module activates a boost circuit based on the TPS55340 chip and a buck circuit based on the JW5117C chip, forming a boost-then-buck circuit to generate a simulated charging voltage, such as 16.8V, higher than the battery's rated voltage. Simultaneously, the main control module controls the corresponding control relay to connect a 1-ohm fixed-value resistor in series with the charging circuit. Due to the high voltage difference, a simulated charging current is generated in the circuit, simulating a real overvoltage fault scenario where the charger charges the battery pack under specific internal resistance conditions. Furthermore, the first control unit starts timing while outputting the simulated charging voltage and uses the current monitoring and conditioning circuit U15 to monitor the Isns pin in real time. The system continuously monitors the Isns signal to observe the on / off state of the charging circuit. When the charging current is detected to drop sharply from its normal value to below the preset current threshold of 0.03A, timing stops. The main control module determines whether this timing duration is within the preset safe response time of 2S-3.5S. If it is, the chip's overvoltage protection function and response speed are deemed qualified, and an overvoltage protection pass result is generated. In one embodiment, step S30, namely the power consumption test step, specifically includes:

[0120] S3111, the multiplex relay group in the drive power consumption measurement module is activated.

[0121] Specifically, the first control unit drives the relays K39 or K40 in the power consumption measurement module to engage according to the power consumption test item to be executed, such as power-down mode, working mode or sleep mode.

[0122] S3112: Collect the power consumption bit value output by the current monitoring amplifier, and compare the power consumption bit value with the preset power consumption judgment threshold to generate power consumption test results.

[0123] Specifically, the current monitoring amplifier U14 amplifies the voltage drop and outputs a bit signal I-ID to the first control unit. The first control unit calculates the actual power consumption based on a ratio of 0.305uA / bit and compares it with preset thresholds. For example, the preset threshold for operating power consumption is 1311 bits, and the preset threshold for sleep power consumption is 1639 bits. If the actual bit value is within the preset error range, a test result indicating that the power consumption is qualified is generated.

[0124] It should be understood that the sequence number of each step in the above embodiments does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.

[0125] The above-described embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.

Claims

1. A test circuit for an intelligent fixture test chip, characterized in that, It includes a main control module, a probe contact detection module, a constant current calibration module, and a charge / discharge protection test module; The probe contact detection module includes a multi-channel signal detection amplification circuit. The input terminal of each signal detection amplification circuit is connected to the corresponding cell interface, and the output terminal of each signal detection amplification circuit is connected to the main control module for feedback of probe contact voltage. The constant current calibration module includes a buck controller, a feedback operational amplifier, a power switch, and a sampling resistor network. The enable terminal of the buck controller is connected to the main control module, the input terminal of the feedback operational amplifier is connected to both ends of the sampling resistor network, and the output terminal of the feedback operational amplifier is connected to the control terminal of the power switch. It is used to output a constant calibration load current to the chip under test by adjusting the conduction level of the power switch. The charge / discharge protection test module includes a buck-boost conversion circuit and a current monitoring and conditioning circuit. The buck-boost conversion circuit includes a boost circuit and a buck circuit that work together. It is controlled by the main control module to output a simulated charging voltage or a simulated cell voltage. The output of the current monitoring and conditioning circuit is connected to the main control module and is used to determine the protection status of the chip under test under the simulated charging voltage or simulated cell voltage by observing the change in the feedback loop current.

2. The test circuit according to claim 1, characterized in that, The test circuit also includes a power consumption measurement module; The power consumption measurement module includes a multi-channel switching relay group and a current monitoring amplifier. The multi-channel switching relay group is connected in the power supply circuit of the chip under test and is used to selectively switch the power supply circuit of the chip under test to different operating modes. The input terminal of the current monitoring amplifier is connected to both ends of the resistor under test, and is used to feed back the power consumption bit value of the chip under test in different operating modes to the main control module by collecting the voltage drop generated by the resistor under test.

3. The test circuit according to claim 1, characterized in that, The test circuit also includes a power supply linkage equalization module; The power supply linkage equalization module includes multiple battery cell interfaces and multiple equalization relay groups. The normally closed contacts of each relay in the equalization relay group are connected to the corresponding battery cell interface. The coil terminal of each relay is connected to an external power supply. The relay is used to form a parallel equalization circuit through the normally closed contacts when the coil terminal is de-energized, and to disconnect the parallel equalization circuit when the coil terminal is energized to switch to an isolated test state.

4. The test circuit according to claim 1, characterized in that, The test circuit also includes a MOS drive module; The MOS driving module includes multiple switching transistors and gate current-limiting resistors. The control terminal of the switching transistor is connected to the main control module through the corresponding gate current-limiting resistor. The input terminal of the switching transistor is connected to the coil terminal of the relay in the power consumption measurement module. It is used to respond to the level output by the main control module and switch between different test circuits by driving the corresponding relay to turn on or off.

5. A testing method for an intelligent fixture test chip, applied to a test circuit for an intelligent fixture test chip as described in any one of claims 1-4, characterized in that, The testing method for the intelligent fixture test chip includes: In response to the test start command, the power supply linkage equalization module activates, switching the power supply environment under test from the parallel equalization state to the isolated test state of mutual isolation; The probe contact state is determined by using the probe contact detection module to feed back the probe contact voltage and the relationship between the probe contact voltage and a preset threshold. When the test probe is in a qualified contact state, the chip under test is tested according to the preset test execution command to obtain the corresponding test results. The test includes at least parameter calibration test by controlling the constant current calibration module to apply calibration load current to the chip under test, protection function test by controlling the charge and discharge protection test module to simulate battery conditions, and power consumption test by controlling the power consumption measurement module to switch the power supply path. Upon receiving the test end command, the power supply linkage equalization module is controlled to return to the parallel equalization state.

6. The test method according to claim 5, characterized in that, The step of determining the contact state of the test probe specifically includes: Obtain the probe contact voltage output by the signal detection amplifier circuit for each signal, and determine the preset reference voltage threshold. Calculate the voltage difference between the probe contact voltage and the preset reference voltage threshold. If the voltage difference is within the preset range, the corresponding test probe contact state is determined to be qualified. If the voltage difference exceeds the preset range, the corresponding test probe contact state is determined to be unqualified, and a probe poor contact alarm command is triggered to interrupt the test process.

7. The test method according to claim 5, characterized in that, Before the step of testing the chip under test according to the preset test execution instructions, the test method further includes: The relay in the charge / discharge protection test module is driven to close for a preset duration to apply a wake-up level signal to the chip under test; After the chip under test is woken up, the reset signal of the chip under test is pulled low, and the target firmware program is written to the chip under test via the communication bus. The written target firmware program is then verified to generate the firmware burning result.

8. The test method according to claim 5, characterized in that, The parameter calibration test steps specifically include: The linear constant current circuit in the constant current calibration module is controlled to output a constant current with a preset range as the calibration load current. The internal current measurement value fed back by the chip under test is read through the communication bus, and the calibration coefficient is calculated based on the calibration load current and the internal current measurement value. The calibration coefficient is written into the non-volatile memory of the chip under test to generate parameter calibration test results.

9. The test method according to claim 5, characterized in that, The steps for the protection function test specifically include: The relay in the power supply linkage equalization module is controlled to operate in series with a fixed resistance circuit, and the current monitoring and conditioning circuit in the charge and discharge protection test module is used to monitor the current in the discharge test circuit. Based on the current, the undervoltage protection test result is generated. The buck-boost conversion circuit in the charge-discharge protection test module is controlled to output a simulated charging voltage signal, and a relay is connected in series with a fixed resistance circuit to form a simulated charging current. The time interval from the output of the simulated charging current to the feedback current from the current monitoring and conditioning circuit reaching a preset current threshold is recorded. Based on the time interval, an overvoltage protection test result is generated.

10. The test method according to claim 5, characterized in that, The power consumption test steps specifically include: Drive the multiplexer relay group in the power consumption measurement module to operate; The power consumption bit value output by the current monitoring amplifier in the power consumption measurement module is collected, and the power consumption bit value is compared with a preset power consumption judgment threshold to generate a power consumption test result.

Images