Method, device and equipment for grading test of DRAM particle linkage margin and medium

Abstract

The application discloses a DRAM particle linkage margin grading test method, device, equipment and medium. The method comprises the following steps: selecting a to-be-determined grade, obtaining a target frequency, a reference timing, voltage and temperature grades, a grade sequence and determination requirements; taking the target frequency and the reference grade as a test reference point, performing voltage timing and voltage temperature tests, determining voltage, timing and temperature boundaries based on the reference point and a passing area; determining the grade span in three directions, taking the maximum span as the linkage margin path grade, constructing a low-to-high linkage test point, determining the voltage, timing and temperature grades of each test point according to the proportion of each grade span and the path grade; testing the linkage test point, determining the path continuous passing proportion; when the grade span and the path continuous passing proportion meet the requirements, it is determined that the to-be-tested DRAM particle meets the to-be-determined grade. The application can consider the stability evaluation when multiple working conditions change together, and improve the grading accuracy on the basis of controlling the test scale.

Description

Technical Field

[0001] This application relates to the field of semiconductor memory testing technology, specifically to a method for graded testing of DRAM chip linkage margin. Background Technology

[0002] Before DRAM chips are assembled into memory modules, storage products or other electronic devices, they usually need to be graded according to their stability under different operating conditions, so as to provide a basis for subsequent chip selection, product configuration and quality control.

[0003] In related technologies, DRAM chips are typically subjected to different operating frequencies, voltages, timings, or temperatures to obtain test results under those conditions, and the performance level of the chip is determined accordingly. Some solutions also evaluate the chip's operating margin based on the pass range under different test conditions.

[0004] However, existing solutions typically focus on evaluating the performance of DRAM chips under a single test condition change direction, making it difficult to take into account the combined impact of multiple operating condition changes on chip stability. This may result in performance rating results that do not accurately reflect the stability of the chips under actual operating conditions.

[0005] Therefore, how to more accurately evaluate the performance margin of DRAM chips under various operating conditions while controlling the complexity of testing has become a technical problem that needs to be solved in this field. Summary of the Invention

[0006] The purpose of this application is to provide a DRAM chip linkage margin grading test method, apparatus, equipment and medium to solve the technical problem in the prior art that it is difficult to accurately reflect the stability of DRAM chips when multiple operating conditions change together because the performance level is determined based solely on independent test results under different operating conditions.

[0007] Firstly, this application provides a DRAM chip linkage margin grading test method for determining the performance level of the DRAM chip under test, including: Select the current performance level to be judged from multiple preset performance levels, and obtain the target frequency, reference timing level, reference voltage level, reference temperature level, voltage level sequence, timing level sequence, temperature level sequence, as well as the minimum level span requirements and path continuity ratio requirements in the voltage direction, timing direction, and temperature direction corresponding to the current performance level to be judged. Using the target frequency, reference timing range, reference voltage range, and reference temperature range as test reference points, voltage timing tests and voltage temperature tests are performed respectively. The voltage timing test includes: testing the combination of voltage range sequences and timing range sequences at the target frequency and reference temperature range to generate a voltage timing test graph; determining the first reference point connectivity region containing the test reference point within the voltage timing test graph; and determining the voltage boundary and timing boundary based on the first reference point connectivity region. The voltage temperature test includes: testing the combination of voltage range sequences and temperature range sequences at the target frequency and reference timing range to generate a voltage temperature test graph; determining the second reference point connectivity region containing the test reference point within the voltage temperature test graph; and determining the temperature boundary based on the second reference point connectivity region. Based on the voltage boundary, timing boundary, and temperature boundary, determine the voltage range span between the reference voltage range and the voltage boundary, the timing range span between the reference timing range and the timing boundary, and the temperature range span between the reference temperature range and the temperature boundary, respectively. The maximum value among the voltage range, timing range, and temperature range is used as the level of the linkage margin path. A linkage margin path is constructed, including a test reference point and multiple linkage test points arranged from low to high. The voltage range, timing range, and temperature range corresponding to each linkage test point are determined according to the proportion of each range to the level of the linkage margin path. According to the linkage margin path from low to high, each linkage test point is tested to determine the highest linkage test point level that can be continuously passed from the test benchmark point. The continuous passage ratio of the path is determined based on the ratio of the highest linkage test point level to the linkage margin path level. When the voltage range, timing range, and temperature range are not less than the corresponding minimum range requirement, and the path continuity ratio is not less than the path continuity ratio requirement, the DRAM chip under test is determined to meet the current judgment level.

[0008] Secondly, this application provides a DRAM chip linkage margin grading test device, comprising: The grade configuration acquisition module is used to select the current grade to be judged from multiple preset performance grades, and obtain the target frequency, reference timing level, reference voltage level, reference temperature level, voltage level sequence, timing level sequence, temperature level sequence, as well as the minimum level span requirements and path continuity ratio requirements in the voltage direction, timing direction and temperature direction corresponding to the current grade to be judged. The two-dimensional testing module is used to perform voltage timing tests and voltage-temperature tests, using the target frequency, reference timing range, reference voltage range, and reference temperature range as test reference points. The voltage timing test includes: testing a combination of voltage range sequences and timing range sequences at the target frequency and reference temperature range to generate a voltage timing test graph; determining a first reference point connectivity region containing the test reference point within the voltage timing test graph; and determining voltage and timing boundaries based on the first reference point connectivity region. The voltage-temperature test includes: testing a combination of voltage range sequences and temperature range sequences at the target frequency and reference timing range to generate a voltage-temperature test graph; determining a second reference point connectivity region containing the test reference point within the voltage-temperature test graph; and determining temperature boundaries based on the second reference point connectivity region. The boundary determination module is used to determine the voltage range between the reference voltage range and the voltage boundary, the timing range between the reference timing range and the timing boundary, and the temperature range between the reference temperature range and the temperature boundary, respectively, based on the voltage boundary, timing boundary, and temperature boundary. The linkage path construction module is used to construct a linkage margin path that includes a test reference point and multiple linkage test points arranged from low to high, using the maximum value among the voltage range, timing range, and temperature range as the level of the linkage margin path. According to the proportion of each range range to the level of the linkage margin path, the voltage range, timing range, and temperature range corresponding to each linkage test point are determined. The linkage test module is used to test each linkage test point in order from low to high linkage margin path, determine the highest linkage test point level that can be continuously passed from the test benchmark point, and determine the path continuous passage ratio based on the ratio of the highest linkage test point level to the linkage margin path level. The grade determination module is used to determine whether the DRAM chip under test meets the current grade requirement when the voltage range, timing range, and temperature range are not less than the corresponding minimum range requirement, and the path continuity ratio is not less than the path continuity ratio requirement.

[0009] Thirdly, this application provides an electronic device, including a processor and a memory, wherein a computer program is stored in the memory, and when the computer program is executed by the processor, the electronic device performs the above-described DRAM chip linkage margin classification test method.

[0010] Fourthly, this application provides a computer-readable storage medium storing a computer program thereon, which, when executed by a processor, causes the processor to perform the aforementioned DRAM chip linkage margin grading test method.

[0011] The DRAM chip linkage margin grading test method provided in this application selects the current level to be judged from multiple preset performance levels, and obtains the target frequency, reference timing level, reference voltage level, reference temperature level, sequence of each level, minimum level span requirement in three directions, and path continuity ratio requirement corresponding to the current level to be judged; the target frequency, reference timing level, reference voltage level, and reference temperature level constitute the test reference point, and voltage timing test and voltage temperature test are performed respectively. In the voltage timing test diagram, the voltage boundary and timing boundary are determined based on the connected area of ​​the first reference point containing the test reference point, and in the voltage temperature test diagram, the temperature boundary is determined based on the connected area of ​​the second reference point containing the test reference point, thereby obtaining the voltage direction, timing direction, and... The temperature range is determined; then, the maximum value of the range in the three directions is used as the level of the linkage margin path. Multiple linkage test points are constructed from low to high according to the proportion of each range to the number of linkage margin path levels. The voltage, timing, and temperature levels corresponding to each linkage test point are determined so that the test conditions in each direction can change together with the linkage margin path. Tests are then performed in ascending order of the linkage margin path. The path continuity ratio is determined based on the highest number of linkage test points continuously passed from the test reference point. The range in each of the three directions is compared with the corresponding lowest range requirement, and the path continuity ratio is compared with the path continuity ratio requirement to determine whether the DRAM chip under test meets the current judgment level. This application can solve the problem that performance level determination based solely on independent test results under different operating conditions is difficult to accurately reflect the stability of DRAM chips when multiple operating conditions change together. It has the effect of taking into account independent and linked margins in three directions: voltage, timing and temperature, reducing the risk of insufficient margins in one direction masking insufficient margins in other directions, and improving the accuracy of DRAM chip performance level determination by avoiding traversal testing of all combinations of conditions. Attached Figure Description

[0012] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0013] Figure 1 A flowchart of the DRAM chip linkage margin classification test method provided in the embodiments of this application is shown.

[0014] Figure 2 A flowchart illustrating the voltage boundary and timing boundary determination provided in an embodiment of this application is shown.

[0015] Figure 3 A flowchart illustrating the temperature boundary determination process provided in an embodiment of this application is shown.

[0016] Figure 4 The present application provides a flowchart of the current test conditions test process.

[0017] Figure 5 A flowchart illustrating the linkage margin path construction process provided in an embodiment of this application is shown.

[0018] Figure 6 A flowchart illustrating the process of determining the gear corresponding to the linkage test point provided in an embodiment of this application is shown.

[0019] Figure 7 A flowchart illustrating the path continuity ratio determination provided in an embodiment of this application is shown.

[0020] Figure 8 A schematic diagram of the DRAM chip linkage margin classification test device provided in an embodiment of this application is shown.

[0021] Figure 9 A schematic diagram of an electronic device provided in an embodiment of this application is shown.

[0022] Figure 10 A schematic diagram of a computer-readable storage medium provided in an embodiment of this application is shown. Detailed Implementation

[0023] To enable those skilled in the art to better understand the technical solutions of this application, the technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. Other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are all within the scope of protection of this application.

[0024] It should be noted that the relational terms such as "first" and "second" used in this article are only used to distinguish one entity, operation, or state from another entity, operation, or state, and are not used to limit the existence of actual relationships, order, or differences in importance between these entities, operations, or states.

[0025] The terms “comprising,” “including,” and any variations thereof are intended to cover non-exclusive inclusion, such that a process, method, apparatus, device, or system that comprises a list of elements may include not only those elements expressly listed, but also other elements not expressly listed, or elements inherent to that process, method, apparatus, device, or system. Unless otherwise specified, an element defined by the phrase “comprising one…” does not exclude the presence of other identical elements in the process, method, apparatus, device, or system that includes that element.

[0026] In this article, "multiple" refers to two or more.

[0027] In one embodiment, the DRAM chip linkage margin grading test method provided in this application can be applied to scenarios such as DRAM chip factory screening, memory module pre-assembly grading, or chip performance evaluation during the manufacturing process of storage products. The DRAM chip under test can be a packaged single DRAM chip, used to determine its performance level before being assembled into a memory module, storage product, or other electronic device.

[0028] During testing, the DRAM chip under test establishes a test connection with the DRAM chip testing system. The DRAM chip testing system can configure the corresponding operating frequency, voltage level, and timing level for the DRAM chip under test under a preset temperature environment, perform read / write tests, and obtain test results. The DRAM chip testing system pre-stores multiple performance levels and the corresponding test configurations for each performance level. The DRAM chip testing system may include test execution equipment for establishing the test connection and performing read / write tests, temperature control equipment for providing a temperature environment, and a data processing unit for storing test configurations and processing test results. The specific structure of the above equipment or units is not the focus of this application's improvement.

[0029] The DRAM chip linkage margin grading test method provided in this application is used to determine the performance level of the DRAM chip under test. Figure 1 A flowchart of the DRAM chip linkage margin classification test method provided in the embodiments of this application is shown, as follows: Figure 1 As shown, the method includes: S100: Select the current performance level to be judged from multiple preset performance levels, and obtain the target frequency, reference timing level, reference voltage level, reference temperature level, voltage level sequence, timing level sequence, temperature level sequence, and the minimum level span requirement and path continuity ratio requirement in the voltage direction, timing direction, and temperature direction corresponding to the current performance level to be judged. The multiple preset performance levels are used to characterize the operating conditions and margin conditions that the DRAM chip under test should meet under different performance requirements. Each performance level can be pre-associated with a set of level test configurations. The target frequency, reference timing level, reference voltage level, and reference temperature level in the level test configuration together constitute the basic test conditions under that performance level; the voltage level sequence, timing level sequence, and temperature level sequence are used to provide discrete levels that can be selected when further changing the operating conditions on the basis of the basic test conditions; the minimum level span requirement and path continuity ratio requirement in the three directions are used to judge the level of subsequent test results.

[0030] The current performance level to be determined can be any of a set of preset performance levels. After obtaining the level test configuration corresponding to the current performance level to be determined, the input data required for subsequent two-dimensional testing, boundary determination, linkage margin path construction, and level determination can be generated.

[0031] In some embodiments, the voltage level sequence includes multiple voltage levels arranged from the reference voltage level towards lower voltage, the temperature level sequence includes multiple temperature levels arranged from the reference temperature level towards higher temperature, and the timing level sequence includes multiple timing levels arranged from the reference timing level towards tight timing; wherein each timing level is matched with the target frequency and meets the datasheet, test mode, and test platform configuration requirements of the DRAM chip under test; as the timing level number increases, the actual waiting time corresponding to at least one timing parameter involved in the adjustment is shortened, while the actual waiting time corresponding to other timing parameters involved in the adjustment remains unchanged or is shortened.

[0032] In the voltage level sequence, the reference voltage level can be used as the starting voltage level, and subsequent voltage levels correspond to lower supply voltages in turn; in the temperature level sequence, the reference temperature level can be used as the starting temperature level, and subsequent temperature levels correspond to higher temperature conditions in turn; in the timing level sequence, the reference timing level can be used as the starting timing level, and subsequent timing levels correspond to tighter timing conditions in turn.

[0033] Specifically, a timing level can be represented by one or more timing parameters involved in the adjustment. When a timing level, relative to the previous timing level, shortens the actual latency of at least one of the timing parameters involved in the adjustment, the timing pressure of that timing level increases relative to the previous timing level; other timing parameters involved in the adjustment can remain unchanged, or their corresponding actual latency can be shortened synchronously. This ensures that the timing level sequence progresses along the tightest timing direction, without the increased timing pressure being offset by an increase in latency corresponding to other timing parameters involved in the adjustment.

[0034] Optionally, each gear in the voltage gear sequence, timing gear sequence, and temperature gear sequence can be numbered according to a preset order. To facilitate the calculation of the subsequent linkage margin path, the base gear in each sequence can be recorded as gear 0, and the gears progressing along the low-voltage direction, tight timing direction, or high-temperature direction can be recorded as gear 1, gear 2, and so on until the corresponding boundary gear.

[0035] As one implementation method, multiple preset performance levels can be arranged from high to low according to performance requirements. After completing the performance level determination for a current performance level to be determined, the next performance level can be selected as the current performance level to be determined for testing; after completing the determination of multiple performance levels in sequence, the first performance level that meets the corresponding level determination conditions can be determined as the final performance level of the DRAM chip under test.

[0036] The target frequency, reference timing range, reference voltage range, reference temperature range, and range sequence obtained in step S100 are used as inputs for establishing test reference points and performing two-dimensional tests in step S200.

[0037] S200: Using the target frequency, the reference timing range, the reference voltage range, and the reference temperature range as test reference points, voltage timing tests and voltage temperature tests are performed respectively; wherein, the voltage timing test includes: at the target frequency and the reference temperature range, testing the combination of the voltage range sequence and the timing range sequence to generate a voltage timing test map, determining a first reference point connectivity region containing the test reference point in the voltage timing test map, and determining voltage boundaries and timing boundaries based on the first reference point connectivity region; the voltage temperature test includes: at the target frequency and the reference timing range, testing the combination of the voltage range sequence and the temperature range sequence to generate a voltage temperature test map, determining a second reference point connectivity region containing the test reference point in the voltage temperature test map, and determining temperature boundaries based on the second reference point connectivity region.

[0038] Based on the target frequency, reference timing level, reference voltage level, and reference temperature level obtained in step S100, a test reference point is established. The test reference point is the common starting condition for the margin evaluation in each direction under the current level to be determined. The corresponding test results are used to determine the connected passage area in the subsequent two-dimensional test diagram and serve as the starting test point in the subsequent linkage margin path.

[0039] During voltage timing tests, the target frequency and reference temperature range are kept constant, and tests are performed on each combination of test conditions within the voltage and timing range sequences. Each test condition combination corresponds to one voltage range and one timing range, and the test result can be either a pass or fail result. Based on each test condition combination and its corresponding test result, a voltage timing test diagram is generated.

[0040] The voltage timing test chart and the voltage-temperature test chart can be implemented using two-dimensional data tables, two-dimensional matrices, two-dimensional coordinate graphs, or other data structures capable of representing different combinations of test conditions and their test results. One test point in the voltage timing test chart corresponds to a combination of a voltage level and a timing level; one test point in the voltage-temperature test chart corresponds to a combination of a voltage level and a temperature level.

[0041] In some embodiments, the first reference point connected through region includes: in the voltage timing test diagram, a region formed by continuously connecting multiple adjacent through test points along the voltage direction or timing direction, starting from the through test point corresponding to the test reference point; the second reference point connected through region includes: in the voltage temperature test diagram, a region formed by continuously connecting multiple adjacent through test points along the voltage direction or temperature direction, starting from the through test point corresponding to the test reference point.

[0042] In the voltage timing test diagram, the voltage direction corresponds to the progressive direction of the voltage range sequence, and the timing direction corresponds to the progressive direction of the timing range sequence; in the voltage-temperature test diagram, the voltage direction corresponds to the progressive direction of the voltage range sequence, and the temperature direction corresponds to the progressive direction of the temperature range sequence.

[0043] Specifically, for any two test points passing through the voltage timing test diagram, if they are adjacent only in voltage range and have the same timing range, or if they are adjacent only in timing range and have the same voltage range, they can be considered to be adjacent along the voltage direction or the timing direction. For any two test points passing through the voltage temperature test diagram, if they are adjacent only in voltage range and have the same temperature range, or if they are adjacent only in temperature range and have the same voltage range, they can be considered to be adjacent along the voltage direction or the temperature direction.

[0044] Therefore, both the first and second reference point connected regions are formed by expanding step-by-step from the corresponding test points of the test reference points. Isolated test points that are not continuous with the region of the test reference point, even if their own test results are passing, are not used as the basis for determining the corresponding boundaries.

[0045] In some embodiments, Figure 2 A flowchart illustrating the voltage boundary and timing boundary determination provided in an embodiment of this application is shown, as follows: Figure 2 As shown, determining the voltage boundary and timing boundary based on the first reference point's connected region includes: while keeping the reference timing level unchanged, determining the last consecutively passed test point in the first reference point's connected region along the direction of gradually decreasing voltage from the test reference point, and determining the voltage level corresponding to the last consecutively passed test point as the voltage boundary; while keeping the reference voltage level unchanged, determining the last consecutively passed test point in the first reference point's connected region along the direction of gradually increasing timing pressure from the test reference point, and determining the timing level corresponding to the last consecutively passed test point as the timing boundary.

[0046] In some embodiments, Figure 3 A flowchart illustrating the temperature boundary determination process provided in an embodiment of this application is shown, as follows: Figure 3 As shown, determining the temperature boundary based on the connected area of ​​the second reference point includes: while keeping the reference voltage level unchanged, determining the last continuously passing test point in the connected area of ​​the second reference point along the direction of gradually increasing temperature from the test reference point, and determining the temperature level corresponding to the last continuously passing test point as the temperature boundary.

[0047] When determining the voltage boundary, only multiple test points corresponding to the reference timing range are considered. Starting from the voltage range corresponding to the reference test point, test points that still belong to the region connected by the first reference point are sequentially determined along the direction of gradually decreasing voltage. The voltage range corresponding to the last test point that still meets this condition is the voltage boundary.

[0048] When determining the timing boundary, only multiple test points corresponding to the reference voltage range are considered. Along the direction of gradually increasing timing pressure, starting from the timing range corresponding to the test reference point, test points that still belong to the connected area of ​​the first reference point are determined sequentially. The timing range corresponding to the last test point that still meets this condition is the timing boundary.

[0049] When determining the temperature boundary, only multiple test points corresponding to the reference voltage range are considered. Along the direction of gradual temperature increase, starting from the temperature range corresponding to the test reference point, test points that still belong to the area connected by the second reference point are determined sequentially. The temperature range corresponding to the last test point that still meets this condition is the temperature boundary.

[0050] In some embodiments, Figure 4 The following is a flowchart illustrating the current test conditions provided in an embodiment of this application: Figure 4 As shown, the voltage timing test and the voltage temperature test both include the following steps for testing the current test conditions: restoring the DRAM chip under test to the same initial test state according to the same state recovery rule; configuring the voltage level, timing level and temperature level corresponding to the current test conditions, and completing the initialization and test mode configuration; and performing the test using the same read / write pressure test sequence corresponding to the current level to be determined.

[0051] The same state recovery rule is used to ensure that the DRAM chips under test are in a comparable initial state before different test points begin testing. State recovery can include restoring to the same test address range, preset data state, initialization state, or test mode state, or performing other processing methods that enable different test points to meet the comparison conditions. After state recovery is completed, the voltage level, timing level, and temperature level corresponding to the current test conditions are configured, and the initialization and test mode configuration corresponding to the current test conditions are completed before the read / write stress test sequence is executed.

[0052] Specifically, the same read / write stress test sequence is maintained throughout the voltage timing test and voltage-temperature test for the current assessment level. The read / write stress test sequence can include preset data write operations, data read operations, and read / write result verification operations. By using the same state recovery rules and the same read / write stress test sequence at each valid test point, the impact of initial state differences and test load differences on the two-dimensional test results is reduced.

[0053] As one implementation method, when performing voltage-temperature testing, before testing the voltage and temperature combinations at the current temperature level, the temperature is brought to the set value corresponding to that temperature level and stabilized. After the temperature stabilizes, the refresh conditions at that temperature level are configured according to the datasheet of the DRAM chip under test and the current test mode; all test points at the same temperature level use the same refresh configuration. This ensures that the test results corresponding to different voltage levels at the same temperature level are comparable.

[0054] As another implementation, if the current test point in a voltage timing test or voltage-temperature test does not yield a valid test result, the current test point can be retested within a preset number of retests. If a valid test result is still not obtained within the preset number of retests, the performance level determination for the current pending level is paused. This process avoids directly using abnormal interruptions, abnormal test connections, or other results that do not form a valid conclusion as pass or fail test results in subsequent processing.

[0055] The voltage boundary, timing boundary, and temperature boundary obtained in step S200 serve as the basis for determining the span of the three gear positions in step S300.

[0056] S300: Based on the voltage boundary, the timing boundary, and the temperature boundary, determine the voltage range between the reference voltage range and the voltage boundary, the timing range between the reference timing range and the timing boundary, and the temperature range between the reference temperature range and the temperature boundary, respectively.

[0057] Based on the voltage boundary, timing boundary, and temperature boundary determined in step S200, the number of ranges spanned along the corresponding range sequence between the reference range and the corresponding boundary range is calculated to obtain the voltage range span, timing range span, and temperature range span.

[0058] Among them, the voltage range is used to characterize the range of voltage levels that the DRAM chip under test can continuously reach from the reference voltage level to the low voltage level; the timing range is used to characterize the range of timing levels that the DRAM chip under test can continuously reach from the reference timing level to the tight timing level; and the temperature range is used to characterize the range of temperature levels that the DRAM chip under test can continuously reach from the reference temperature level to the high temperature level.

[0059] Specifically, when the reference range number is recorded as 0, the boundary range number in a certain direction can be directly used as the range span in that direction. If the voltage range number corresponding to the voltage boundary is 4, then the voltage range span is 4; if the timing range number corresponding to the timing boundary is 3, then the timing range span is 3; if the temperature range number corresponding to the temperature boundary is 2, then the temperature range span is 2.

[0060] The range of the gears in the three directions reflects the continuous passage capability of the DRAM chip under test in the corresponding individual direction, and also serves as the basic data for constructing the linkage margin path in step S400.

[0061] S400: Using the maximum value among the voltage range, timing range, and temperature range as the level of the linkage margin path, construct a linkage margin path including the test reference point and multiple linkage test points arranged from low to high. Determine the voltage range, timing range, and temperature range corresponding to each linkage test point according to the proportion of each range to the level of the linkage margin path.

[0062] Based on the voltage range, timing range, and temperature range obtained in step S300, the maximum value is selected as the level of the linkage margin path. The test reference point serves as the starting point of the linkage margin path, and multiple linkage test points arranged from low to high are constructed after the test reference point.

[0063] The linkage margin path does not directly treat the independent test boundaries in the three directions as a common passage area. Instead, it generates multiple linkage test conditions that simultaneously include voltage, timing, and temperature ranges based on the range span in the three directions, and determines whether these linkage test conditions pass through subsequent actual tests.

[0064] Based on the proportion of the range of each direction to the number of levels in the linkage margin path, corresponding voltage, timing, and temperature ranges are assigned to each linkage test point. Thus, as the linkage margin path progresses from low to high, directions with a range greater than zero can gradually enter stronger test conditions; directions with smaller ranges remain at the corresponding boundary range after reaching it, while directions with larger ranges continue to advance towards the corresponding boundary range.

[0065] In some embodiments, Figure 5 A flowchart illustrating a specific implementation of step S400 provided in an embodiment of this application is shown. Figure 5 As shown, the method of constructing a linkage margin path, using the maximum value among the voltage range, the timing range, and the temperature range as the level of the linkage margin path, includes the test reference point and multiple linkage test points arranged from low to high, comprising: S410: The voltage range, the timing range, and the temperature range are respectively denoted as Nv', Np', and Nt'.

[0066] S420: Determine the maximum value among Nv', Np', and Nt' as the linkage margin path level M.

[0067] S430: Construct a linkage margin path including linkage test points from level 0 to level M, wherein the linkage test point of level 0 is the test reference point.

[0068] Wherein, Nv' is the voltage range determined based on the voltage boundary, Np' is the timing range determined based on the timing boundary, and Nt' is the temperature range determined based on the temperature boundary. All three belong to the calculation results obtained in step S300; M is the linkage margin path level determined by the maximum value among Nv', Np', and Nt'; k is the level of the k-th linkage test point, with a value range from 1 to M.

[0069] In some embodiments, Figure 6 A flowchart illustrating another specific implementation of step S400 provided in the embodiments of this application is shown. For example... Figure 6 As shown, determining the voltage level, timing level, and temperature level corresponding to each linkage test point according to the proportion of each level's span to the number of linkage margin path stages includes: S440: For the k-th level linkage test point, the voltage range number is determined as ceil (k×Nv' / M), the timing range number is determined as ceil (k×Np' / M), and the temperature range number is determined as ceil (k×Nt' / M).

[0070] S450: Based on the voltage level number, the timing level number, and the temperature level number, determine the voltage level, timing level, and temperature level corresponding to the k-th level linkage test point from the voltage level sequence, the timing level sequence, and the temperature level sequence, respectively.

[0071] Optionally, the indices of the reference voltage level, reference timing level, and reference temperature level in their respective level sequences are set to 0, and the level indices are sequentially increased along the low-voltage direction, tight timing direction, and high-temperature direction. Thus, the calculated voltage level indices, timing level indices, and temperature level indices are used to locate specific levels from the three level sequences; the located voltage level, timing level, and temperature level together constitute the actual test conditions corresponding to the k-th level linkage test point.

[0072] Where k is an integer not less than 1 and not greater than M, and ceil represents rounding up. By using the rounding up method, the direction with a gear span greater than zero enters the corresponding progressive gear during the advancement of the linkage margin path, without lingering in the lower pressure gear for too many levels due to rounding down.

[0073] For any direction where Nv', Np', and Nt' are zero, it indicates that the boundary of that direction is the same as the reference gear, and therefore that direction maintains the corresponding reference gear in all linkage test points. For any direction where Nv', Np', and Nt' are less than M, it indicates that the boundary gear corresponding to that direction is reached earlier than the maximum span direction during the linkage margin path advancement; after that direction reaches the corresponding boundary gear, it maintains the boundary gear in subsequent linkage test points.

[0074] In one implementation, when Nv'=4, Np'=3, Nt'=2 and M=4, the voltage range number of the third-level linkage test point is 3, the timing range number is 3, and the temperature range number is 2. Therefore, the third voltage range from the voltage range sequence, the third timing range from the timing range sequence, and the second temperature range from the temperature range sequence together constitute the actual test conditions for the third-level linkage test point.

[0075] The multiple linked test points and their corresponding test conditions obtained in step S400 are used as the objects for actual testing in step S500.

[0076] S500: Test each linkage test point in the order of low to high according to the linkage margin path, determine the highest linkage test point level that can be continuously passed from the test benchmark point, and determine the path continuous passage ratio according to the ratio of the highest linkage test point level to the linkage margin path level.

[0077] Based on the linkage margin path constructed in step S400, the voltage level, timing level and temperature level corresponding to each linkage test point are configured in order from low to high according to the linkage test points, and the test results of each linkage test point are obtained by using the aforementioned read and write pressure test sequence.

[0078] In some embodiments, the testing of each linked test point, including testing the test conditions corresponding to the current linked test point, includes: restoring the DRAM chip under test to the same initial test state according to the same state recovery rule; configuring the voltage level, timing level and temperature level corresponding to the current linked test point, and completing the initialization and test mode configuration; and performing the test using the same read / write pressure test sequence corresponding to the current level to be determined.

[0079] The test conditions corresponding to the current linkage test point are determined in step S400. By using the same state recovery rules and the same read / write stress test sequence for the linkage test point and the two-dimensional test, the linkage test results can be made comparable to the aforementioned two-dimensional test results.

[0080] As one implementation method, if a valid test result is not obtained for the current linkage test point, the current linkage test point can be retested within a preset number of retests. If a valid test result is still not obtained within the preset number of retests, the performance level determination of the current pending level is suspended. For linkage test points that have obtained failed test results, they are processed according to the retest rules of the first subsequently failed test point.

[0081] The testing sequence, from low to high, means first testing the lower-level linkage test points closest to the test baseline, and then testing the subsequent higher-level linkage test points with stronger corresponding test conditions. This method allows for the determination of the pass rate across consecutive levels starting from the test baseline, and avoids substituting the result of a single high-pressure test point for the overall continuous linkage margin evaluation.

[0082] In some embodiments, Figure 7 A flowchart illustrating a specific implementation of step S500 provided in an embodiment of this application is shown. Figure 7 As shown, the step of testing each linkage test point in ascending order of the linkage margin path, determining the highest number of linkage test point levels continuously passed from the test benchmark point, and determining the path continuity ratio based on the ratio of the highest linkage test point level to the linkage margin path level, includes: S510: Use the test result of the test benchmark point as the test result of the level 0 linkage test point.

[0083] S520: When the k-th linkage test point is the first linkage test point that fails the test in the order from low to high along the linkage margin path, and fails the test again after being retested under the same test conditions, and k is greater than zero, k-1 is determined as the highest linkage test point level.

[0084] S530: When all linkage test points from level 0 to level M pass the test, the highest linkage test point level is determined to be equal to M.

[0085] S540: The ratio of the highest linkage test point level to M is determined as the continuous passage ratio of the path.

[0086] The test reference point has already obtained the test result in the two-dimensional test in step S200. Therefore, the test result can be reused as the test result of the level 0 linkage test point, and there is no need to repeat the linkage test for the same test reference point.

[0087] When the k-th linkage test point is the first linkage test point to fail in the ascending order, it is retested under the same test conditions. If it still fails after retesting, the (k-1)-th level is taken as the highest linkage test point level that passes consecutively from the test reference point. If all linkage test points from level 0 to level M pass the test, it indicates that the DRAM chip under test passes consecutively along the entire linkage margin path, and the highest linkage test point level is M.

[0088] After determining the highest level of linkage test points, the path continuity ratio can be determined using the following formula: Rc = Nc / M Wherein, Nc represents the highest linkage test point level, which is a calculation result determined based on the linkage test results; M represents the linkage margin path level; and Rc represents the path continuous passage ratio, which is a calculation result used for subsequent level determination.

[0089] As one implementation method, if a certain linkage test point fails the initial test but passes the retest, then this linkage test point is not considered the first linkage test point to fail the test, and subsequent tests continue in ascending order of linkage margin path. If a linkage test point still fails the test after retesting, the process of moving to a higher-level linkage test point is stopped, and the previous level linkage test point is taken as the endpoint for continuous success.

[0090] The path continuity ratio obtained in step S500 is used as input for determining the current level to be determined in step S600.

[0091] S600: When the voltage range, timing range, and temperature range are not less than the corresponding minimum range requirement, and the path continuous passage ratio is not less than the path continuous passage ratio requirement, the DRAM chip under test is determined to meet the current judgment level.

[0092] Based on the voltage range, timing range, and temperature range obtained in step S300, they are compared with the minimum voltage range requirement, the minimum timing range requirement, and the minimum temperature range requirement corresponding to the current level to be determined, respectively; based on the path continuity ratio obtained in step S500, they are compared with the path continuity ratio requirement corresponding to the current level to be determined.

[0093] Among them, the DRAM chip under test is determined to meet the current judgment level only when the voltage range, timing range, and temperature range all meet the minimum range requirements of their respective categories, and the path continuity ratio meets the path continuity ratio requirements.

[0094] Specifically, the minimum span requirements in the three directions are used to limit the independent continuous margin of the DRAM chip under test in the low-voltage direction, tight timing direction, and high-temperature direction, respectively; the path continuity ratio requirement is used to limit the continuous passage capability of the DRAM chip under test along the linked margin path enhanced by multiple operating conditions. By simultaneously meeting the minimum span requirements and path continuity ratio requirements in the three directions, the situation where a large margin in one direction masks insufficient margin in another direction is avoided.

[0095] As one implementation method, suppose that under the current level to be determined, the voltage boundary, timing boundary and temperature boundary correspond to the 4th level in the voltage level sequence, the 3rd level in the timing level sequence and the 2nd level in the temperature level sequence, respectively. Then Nv'=4, Np'=3, Nt'=2, and the linkage margin path level M=4.

[0096] In this embodiment, the test reference point is designated as the 0th level linkage test point. The voltage range number, timing range number, and temperature range number corresponding to the 1st to 4th level linkage test points are as follows: Level 1 linkage test points: 1, 1, 1; Level 2 linkage test points: 2, 2, 1; Level 3 linkage test points: 3, 3, 2; Level 4 linkage test points: 4, 3, 2.

[0097] If all linkage test points from level 0 to level 3 pass the test, and the level 4 linkage test point fails the test after being retested under the same test conditions, then the highest linkage test point level Nc is 3, and the path continuous pass rate Rc is 3 / 4.

[0098] Furthermore, if the minimum voltage range requirement is 3, the minimum timing range requirement is 2, the minimum temperature range requirement is 1, and the path continuity requirement is 0.75, then Nv', Np', and Nt' in the above implementation meet the corresponding requirements, and Rc equals 0.75. Therefore, it can be determined that the DRAM chip under test meets the current assessment level.

[0099] Using the above method, a test reference point is constructed with the target frequency, reference timing range, reference voltage range, and reference temperature range. Voltage timing tests and voltage temperature tests are performed respectively. The voltage boundary, timing boundary, and temperature boundary can be determined based on the passage area connected to the test reference point, thereby obtaining the range span in the voltage direction, timing direction, and temperature direction. Based on this, the maximum value of the range span in the three directions is used as the level of the linkage margin path. The voltage range, timing range, and temperature range corresponding to each linkage test point are determined according to the proportion of each range span to the linkage margin path level. Actual tests are performed on the linkage test points arranged from low to high to obtain the path continuity ratio.

[0100] Therefore, it is possible not only to evaluate the independent margins of the DRAM chip under test in the low-voltage, tight-timing, and high-temperature directions, but also to evaluate the continuous throughput capability when multiple operating conditions change simultaneously. By comparing the range of the three directions with the corresponding minimum range requirement, and comparing the continuous throughput ratio with the required continuous throughput ratio, the problem of a large margin in one direction masking insufficient margins in other directions can be avoided. This solves the technical problem that performance level determination based solely on independent test results under different operating conditions is difficult to accurately reflect the stability of DRAM chips when multiple operating conditions change simultaneously. At the same time, it eliminates the need to test all combinations of voltage, timing, and temperature, which helps to improve the accuracy of performance level determination while controlling the test scale.

[0101] This application also provides a DRAM chip linkage margin grading test device. Figure 8 A schematic diagram of the DRAM chip linkage margin grading test device provided in an embodiment of this application is shown, as follows: Figure 8 As shown, the device includes a level configuration acquisition module, a two-dimensional testing module, a boundary determination module, a linkage path construction module, a linkage testing module, and a level determination module.

[0102] Among them, the level configuration acquisition module is used to select the current level to be judged from multiple preset performance levels, and obtain the target frequency, reference timing level, reference voltage level, reference temperature level, voltage level sequence, timing level sequence, temperature level sequence, as well as the minimum level span requirements and path continuity ratio requirements in the voltage direction, timing direction and temperature direction corresponding to the current level to be judged. The two-dimensional testing module is used to perform voltage timing tests and voltage temperature tests, respectively, using the target frequency, reference timing range, reference voltage range, and reference temperature range as test reference points. The voltage timing test includes: testing a combination of voltage range sequences and timing range sequences at the target frequency and reference temperature range to generate a voltage timing test graph; determining a first reference point connectivity region containing the test reference point within the voltage timing test graph; and determining voltage and timing boundaries based on the first reference point connectivity region. The voltage temperature test includes: testing a combination of voltage range sequences and temperature range sequences at the target frequency and reference timing range to generate a voltage temperature test graph; determining a second reference point connectivity region containing the test reference point within the voltage temperature test graph; and determining temperature boundaries based on the second reference point connectivity region. The boundary determination module is used to determine the voltage range between the reference voltage range and the voltage boundary, the timing range between the reference timing range and the timing boundary, and the temperature range between the reference temperature range and the temperature boundary, respectively, based on the voltage boundary, timing boundary, and temperature boundary. The linkage path construction module is used to construct a linkage margin path that includes a test reference point and multiple linkage test points arranged from low to high, using the maximum value among the voltage range, timing range, and temperature range as the level of the linkage margin path. According to the proportion of each range range to the level of the linkage margin path, the voltage range, timing range, and temperature range corresponding to each linkage test point are determined. The linkage test module is used to test each linkage test point in order from low to high linkage margin path, determine the highest linkage test point level that can be continuously passed from the test benchmark point, and determine the path continuous passage ratio based on the ratio of the highest linkage test point level to the linkage margin path level. The grade determination module is used to determine that the DRAM chip under test meets the current grade requirement when the voltage range, timing range, and temperature range are not less than the corresponding minimum range requirement, and the path continuity ratio is not less than the path continuity ratio requirement.

[0103] The above modules can be implemented using software programs, hardware circuits, programmable logic devices, or a combination thereof. These modules can be executed by the same processing unit or by multiple processing units working together. Module names are only used to distinguish different processing functions and do not limit the independent configuration of each module's physical structure.

[0104] This application also provides an electronic device, such as... Figure 9 As shown, the electronic device 90 includes a processor 91 and a memory 92. The memory 92 stores a computer program. When the computer program is executed by the processor 91, the electronic device 90 performs the above-mentioned DRAM chip linkage margin classification test method.

[0105] The processor executes the computer program to perform processes such as selecting the current level to be determined, acquiring the test configuration, performing voltage timing tests, voltage and temperature tests, determining boundaries, determining the range, constructing the linkage margin path, performing linkage tests, and determining the level. The memory stores the computer program, as well as data such as test configurations, test results, and calculation results used in the above processes.

[0106] This application also provides a computer-readable storage medium, such as... Figure 10 As shown, a computer program 101 is stored on a computer-readable storage medium 100. When the computer program 101 is executed by the processor, the processor performs the above-described DRAM chip linkage margin classification test method.

[0107] Computer-readable storage media can be tangible storage media capable of storing computer programs, including disk storage, flash memory, read-only memory, random access memory, or other non-volatile storage media.

[0108] The above description, in conjunction with specific embodiments, provides a further detailed explanation of this application and should not be construed as limiting the specific implementation of this application to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of this application, and all such modifications and substitutions should be considered within the scope of protection of this application.

Claims

1. A method for grading the linkage margin of DRAM chips, characterized in that, Used for performance rating determination of DRAM chips under test, including: Select the current performance level to be judged from multiple preset performance levels, and obtain the target frequency, reference timing level, reference voltage level, reference temperature level, voltage level sequence, timing level sequence, temperature level sequence, as well as the minimum level span requirement and path continuity ratio requirement in the voltage direction, timing direction and temperature direction corresponding to the current performance level to be judged. Using the target frequency, the reference timing range, the reference voltage range, and the reference temperature range as test reference points, voltage timing tests and voltage temperature tests are performed respectively. The voltage timing test includes: at the target frequency and the reference temperature range, testing the combination of the voltage range sequence and the timing range sequence to generate a voltage timing test graph; determining a first reference point connectivity region containing the test reference point in the voltage timing test graph; and determining voltage boundaries and timing boundaries based on the first reference point connectivity region. The voltage temperature test includes: at the target frequency and the reference timing range, testing the combination of the voltage range sequence and the temperature range sequence to generate a voltage temperature test graph; determining a second reference point connectivity region containing the test reference point in the voltage temperature test graph; and determining temperature boundaries based on the second reference point connectivity region. Based on the voltage boundary, the timing boundary, and the temperature boundary, the voltage range between the reference voltage range and the voltage boundary, the timing range between the reference timing range and the timing boundary, and the temperature range between the reference temperature range and the temperature boundary are determined respectively. Using the maximum value among the voltage range, timing range, and temperature range as the level of the linkage margin path, a linkage margin path is constructed, including the test reference point and multiple linkage test points arranged from low to high. According to the proportion of each range range to the level of the linkage margin path, the voltage range, timing range, and temperature range corresponding to each linkage test point are determined. According to the linkage margin path from low to high, each linkage test point is tested to determine the highest linkage test point level that can be continuously passed from the test benchmark point. The continuous passage ratio of the path is determined according to the ratio of the highest linkage test point level to the linkage margin path level. When the voltage range, timing range, and temperature range are not less than the corresponding minimum range requirement, and the path continuous passage ratio is not less than the path continuous passage ratio requirement, the DRAM chip under test is determined to meet the current judgment level.

2. The DRAM chip linkage margin classification test method according to claim 1, characterized in that, The voltage level sequence includes multiple voltage levels arranged from the reference voltage level towards the low voltage direction; the temperature level sequence includes multiple temperature levels arranged from the reference temperature level towards the high temperature direction; and the timing level sequence includes multiple timing levels arranged from the reference timing level towards the tight timing direction. Each timing level is matched with the target frequency and meets the datasheet, test mode and test platform configuration requirements of the DRAM chip under test. As the timing level number increases, the actual waiting time corresponding to at least one timing parameter involved in the adjustment is shortened, while the actual waiting time corresponding to other timing parameters involved in the adjustment remains unchanged or is shortened.

3. The DRAM chip linkage margin classification test method according to claim 1, characterized in that, The first reference point connected through area includes: in the voltage timing test diagram, a region formed by continuously connecting multiple adjacent through test points along the voltage direction or timing direction, starting from the through test point corresponding to the test reference point; The second reference point connection area includes: in the voltage and temperature test diagram, a region formed by continuously connecting multiple adjacent test points along the voltage direction or temperature direction, starting from the test point corresponding to the test reference point.

4. The DRAM chip linkage margin classification test method according to claim 1, characterized in that, The step of determining voltage and timing boundaries based on the connectivity of the first reference point through the region includes: While keeping the reference timing level unchanged, from the test reference point along the direction of gradually decreasing voltage, determine the last continuously passing test point in the region connected by the first reference point, and determine the voltage level corresponding to the last continuously passing test point as the voltage boundary. While keeping the reference voltage level unchanged, from the test reference point along the direction of gradually increasing timing pressure, determine the last continuously passing test point in the area connected by the first reference point, and determine the timing level corresponding to the last continuously passing test point as the timing boundary; The determination of temperature boundaries based on the connectivity of the region through the second reference point includes: While keeping the reference voltage level unchanged, from the test reference point along the direction of gradually increasing temperature, determine the last continuously passing test point in the area connected by the second reference point, and determine the temperature level corresponding to the last continuously passing test point as the temperature boundary.

5. The DRAM chip linkage margin classification test method according to claim 1, characterized in that, The voltage timing test, the voltage temperature test, and the test of each linked test point all include testing the current test conditions, which includes: The DRAM chip under test was restored to the same initial test state according to the same state recovery rules. Configure the voltage range, timing range, and temperature range corresponding to the current test conditions to complete the initialization and test mode configuration; The test is performed using the same read / write stress test sequence corresponding to the current level to be determined.

6. The DRAM chip linkage margin classification test method according to claim 1, characterized in that, The method of constructing a linkage margin path by using the maximum value among the voltage range, the timing range, and the temperature range as the level of the linkage margin path, including the test reference point and multiple linkage test points arranged from low to high, includes: The voltage range, the timing range, and the temperature range are respectively denoted as Nv', Np', and Nt'; The maximum value among Nv', Np', and Nt' is determined as the linkage margin path level M; Construct a linkage margin path including linkage test points from level 0 to level M, wherein the level 0 linkage test point is the test reference point; The determination of the voltage range, timing range, and temperature range corresponding to each linkage test point based on the proportion of each range's span to the number of linkage margin path levels includes: For the k-th level linkage test point, the voltage range number is determined as ceil (k×Nv' / M), the timing range number is determined as ceil (k×Np' / M), and the temperature range number is determined as ceil (k×Nt' / M). Based on the voltage level number, the timing level number, and the temperature level number, the voltage level, timing level, and temperature level corresponding to the k-th level linkage test point are determined from the voltage level sequence, the timing level sequence, and the temperature level sequence, respectively. Where k is an integer not less than 1 and not greater than M, and ceil represents rounding up; for any direction of zero among Nv', Np' and Nt', the direction is kept at the corresponding baseline gear in all linkage test points; for any direction of less than M among Nv', Np' and Nt', the direction is kept at the corresponding boundary gear in subsequent linkage test points after reaching the boundary gear.

7. The DRAM chip linkage margin classification test method according to claim 1, characterized in that, The step of testing each linkage test point in ascending order of the linkage margin path, determining the highest number of linkage test point levels continuously passed from the test benchmark point, and determining the path continuity ratio based on the ratio of the highest linkage test point level to the linkage margin path level, includes: The test results of the aforementioned benchmark point are used as the test results of the level 0 linkage test point. When the k-th linkage test point is the first linkage test point to fail the test in the order from low to high along the linkage margin path, and fails the test again after being retested under the same test conditions, and k is greater than zero, k-1 is determined as the highest linkage test point level. When all linkage test points from level 0 to level M pass the test, the highest linkage test point level is determined to be equal to M. The ratio of the highest linkage test point level to M is determined as the continuous passage ratio of the path.

8. A DRAM chip linkage margin classification test device, characterized in that, include: The grade configuration acquisition module is used to select the current grade to be judged from multiple preset performance grades, and obtain the target frequency, reference timing level, reference voltage level, reference temperature level, voltage level sequence, timing level sequence, temperature level sequence, as well as the minimum level span requirement and path continuity ratio requirement in the voltage direction, timing direction and temperature direction corresponding to the current grade to be judged. A two-dimensional testing module is used to perform voltage timing tests and voltage temperature tests, respectively, using the target frequency, the reference timing range, the reference voltage range, and the reference temperature range as test reference points. The voltage timing test includes: at the target frequency and the reference temperature range, testing the combination of the voltage range sequence and the timing range sequence to generate a voltage timing test graph; determining a first reference point connectivity region containing the test reference point in the voltage timing test graph; and determining voltage boundaries and timing boundaries based on the first reference point connectivity region. The voltage temperature test includes: at the target frequency and the reference timing range, testing the combination of the voltage range sequence and the temperature range sequence to generate a voltage temperature test graph; determining a second reference point connectivity region containing the test reference point in the voltage temperature test graph; and determining temperature boundaries based on the second reference point connectivity region. The boundary determination module is used to determine, based on the voltage boundary, the timing boundary, and the temperature boundary, the voltage range between the reference voltage range and the voltage boundary, the timing range between the reference timing range and the timing boundary, and the temperature range between the reference temperature range and the temperature boundary, respectively. The linkage path construction module is used to construct a linkage margin path including the test reference point and multiple linkage test points arranged from low to high, using the maximum value among the voltage range, the timing range, and the temperature range as the level of the linkage margin path. The module determines the voltage range, timing range, and temperature range corresponding to each linkage test point according to the proportion of each range to the level of the linkage margin path. The linkage test module is used to test each linkage test point in the order of low to high according to the linkage margin path, determine the highest linkage test point level that can be continuously passed from the test benchmark point, and determine the path continuous passage ratio according to the ratio of the highest linkage test point level to the linkage margin path level. The grade determination module is used to determine that the DRAM chip under test meets the current grade to be determined when the voltage range, the timing range, and the temperature range are not less than the corresponding minimum range requirement, and the continuous pass ratio of the path is not less than the continuous pass ratio requirement of the path.

9. An electronic device, characterized in that, The device includes a processor and a memory, wherein the memory stores a computer program, and when the computer program is executed by the processor, the electronic device performs the DRAM chip linkage margin classification test method according to any one of claims 1 to 7.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the processor, the processor performs the DRAM chip linkage margin classification test method according to any one of claims 1 to 7.

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