Test method for transmission delay time of digital logic circuits

Abstract

This invention discloses a method for testing the transmission delay time of digital logic circuits, including step S0: calibrating the slope and zero point before testing; step S1: configuring the test system before testing, including electrical condition configuration, delay compensation configuration, and function table configuration; step S2: applying excitation and generating a Start signal to determine the timing start point; step S3: responding to the device under test (DUT) and generating a Stop signal to determine the timing end point; step S4: calculating the transmission delay time; step S5: correcting the measurement results; and step S6: judging the results. This invention's method for testing the transmission delay time of digital logic circuits addresses the problems in the prior art, enabling nanosecond-level time measurement while possessing excellent noise suppression capabilities and high system integration. It features stable and reliable testing, high testing accuracy, high speed, convenient programming, and the ability to perform batch testing.

Description

Technical Field

[0001] This invention belongs to the field of automated test technology (ATE) for integrated circuits, and specifically relates to a method for testing the propagation delay time of digital logic circuits. Background Technology

[0002] In digital logic integrated circuits, the propagation delay time parameter of the 74 series, 54 series, and 4000 series is a core indicator for measuring their speed performance, directly determining the upper limit of the system's operating frequency and response speed. It not only defines the inherent time required for a signal to travel from the input to the output, but also determines whether the device can meet the setup and hold time requirements of high-speed sequential logic. Especially in multi-stage cascaded or complex combinational logic circuits, the accumulation of propagation delay directly affects the system's stability and reliability. Designers must match the operating speed of different devices according to this parameter to ensure timing synchronization and avoid race conditions. Due to cost and technical complexity, most small and medium-sized digital circuit test systems on the market cannot test the propagation delay time of digital circuits. While high-end test systems can test this parameter, they are expensive and require complex test program writing. Summary of the Invention

[0003] The main objective of this invention is to provide a method for testing the transmission delay time of digital logic circuits, thereby solving the problems in the prior art. This method enables nanosecond-level time measurement while possessing excellent noise suppression capabilities and high system integration. It features stable and reliable testing, high accuracy, high speed, convenient programming, and the ability to perform batch testing.

[0004] To achieve the above objectives, the present invention provides a method for testing the transmission delay time of digital logic circuits, comprising the following steps: Step S0: Test preparation and calibration. Before the test, the slope and zero point need to be calibrated regularly: power on and preheat for a preset time, adjust the potentiometer, and calibrate the delay slope and the measurement slope to the preset values ​​respectively.

[0005] Step S1: Test system pre-test configuration, including electrical condition configuration, delay compensation configuration, and function table configuration; Step S2: Apply excitation and generate the Start signal to determine the timing start point; Step S3: The device under test (DUT) responds and a Stop signal is generated to determine the timing endpoint; Step S4: Calculate the transmission delay time; Step S5: Measurement result correction; Step S6: Result judgment. Compare the measured transmission delay time with the nominal value in the datasheet of the device under test (DUT) to determine whether it is qualified.

[0006] As a further preferred embodiment of the above technical solution, the correction of the slope and zero point in step S0 specifically includes: For the delay ramp integrator, set the DAC output voltage to make the high-speed comparator input threshold voltage Vth1, apply a trigger signal to the input of inverter IC1F, and use an oscilloscope to measure the actual time T1 from the signal trigger to the high-speed comparator output transition; set the DAC output voltage to make the high-speed comparator input threshold voltage Vth2, and use an oscilloscope to measure the actual time T2, and calculate the actual slope Kdelay=(Vth2-Vth1) / (T2-T1); adjust potentiometer P2 to make the actual slope Kdelay the preset value, thus completing the slope adjustment of the delay ramp integrator; using the calibrated slope Kdelay, select a known measurement point and calculate the zero-point time T0; For measuring the ramp integrator, set the DAC output voltage to make the high-speed comparator input threshold voltage Vth1, apply trigger signals to the input terminals of inverters IC1A and IC1F simultaneously, and read the output voltage Vout1 after the sample-and-hold unit to obtain the actual time T1; set the DAC output voltage to make the high-speed comparator input threshold voltage Vth2, apply trigger signals to the input terminals of inverters IC1A and IC1F simultaneously, and read the output voltage Vout2 after the sample-and-hold unit to obtain the actual time T2; calculate the actual slope Kmeas = (Vth2 - Vth1) / (T2 - T1); adjust potentiometer P1 to make the actual slope Kmeas the preset value, thus completing the slope adjustment of the ramp integrator; using the calibrated slope Kmeas, select a known measurement point and calculate the zero-point time T0.

[0007] As a further preferred technical solution to the above technical solution, for step S1: Electrical configuration: According to the datasheet of the device under test (DUT), enter the function table of the DUT in the menu programming interface, set the working power supply, input logic level, output judgment level, and set the threshold voltage of the first high-speed comparator and the second high-speed comparator to determine the Start / Stop trigger point; Delay compensation configuration: Configure the 8-bit DAC output voltage as a fixed threshold voltage to enable the delay ramp integrator to generate a fixed and precise delay, which is used to actively avoid the nonlinear region at the beginning of the integration circuit and to offset the inherent delay of the time measurement circuit itself.

[0008] As a further preferred technical solution of the above technical solution, for step S2: test system operation function table, a steep edge logic excitation signal is output to the input pin of the device under test (DUT) through a bidirectional read / write channel. The excitation signal passes through the signal selector MUXA, the high-speed buffer unit, and the first high-speed comparator, and then serves as the Start signal to trigger the start of the measurement ramp integrator and the sample-and-hold unit. The measurement integration capacitor C2 is linearly charged, which is the timing start point.

[0009] As a further preferred technical solution to the above technical solution, step S3 is specifically implemented as follows: Step S3.1: Starting from the timing start point, after a delay of tpLH or tpHL, there is a rising or falling output signal on the output pin of the device under test. This output signal passes through the signal selector MUXB, the high-speed buffer unit, and the second high-speed comparator, and then triggers the delay ramp integrator as a Stop signal to start, and the delay integration capacitor C8 is linearly charged. Step S3.2: The delay integrating capacitor C8 is linearly charged, and the integration point voltage gradually increases. When the voltage is greater than the preset value, the output of the high-speed comparator flips, controlling the analog switch to cut off the charging path of the measuring integrating capacitor C2. The sample and hold unit locks the current voltage value, which is the timing end point.

[0010] As a further preferred technical solution to the above technical solution, in step S3.1, when the output signal is a rising edge signal, the measured parameter is tpLH; when the output signal is a falling edge signal, the measured parameter is tpHL; the specific selection can be made freely through function table editing and menu programming.

[0011] As a further preferred technical solution of the above technical solution, for step S4: the voltmeter reads the output voltage Vout of the sample-and-hold unit, and according to the preset slope Kmeas at the output of the measured ramp integrator, the total time difference is obtained according to the formula td=Vout / K. Then, the fixed precise delay of the delayed ramp integrator mentioned in step S1 and the zero-point offset calculated in step S0 are subtracted to calculate the transmission delay time tpLH or tpHL.

[0012] As a further preferred technical solution to the above technical solution, for step S5: establish a calibration value Cal.Value using standard devices to offset the error caused by the difference between the load capacitance of the test system and the standard load.

[0013] As a further preferred technical solution to the above technical solution, the testing system includes: A bidirectional read / write channel is used to connect the input / output pins of the device under test. Signal selectors MUXA and MUXB are used to bring out specific pin signals of the DUT; A high-speed buffer unit, whose first input terminal Start is connected to the output terminal of the signal selector MUXA, and whose first input terminal Stop is connected to the output terminal of the signal selector MUXB; The first high-speed comparator and the second high-speed comparator, with the two output terminals of the high-speed buffer unit respectively connected to the input terminals of the first high-speed comparator and the second high-speed comparator; The delay time measurement unit has its second input terminal Start connected to the output terminal of the first high-speed comparator, and its second input terminal Stop connected to the output terminal of the second high-speed comparator. A sample-and-hold unit, the input of which is connected to the output of the delay time measurement unit; A voltmeter, the input of which is connected to the output of the sample-and-hold unit.

[0014] As a further preferred embodiment of the above technical solution, the delay time measurement unit includes: A measurement ramp integrator is provided, with its input terminal serving as the second input terminal Start. The measurement ramp integrator includes an operational amplifier IC2, a transistor T1, a resistor R3, a measurement integration capacitor C2, and an inverter IC1A. The inverter IC1A is an open-collector output inverter and does not have a pull-up resistor connected. Analog switch IC5, whose input terminal is connected to the output terminal of the measuring ramp integrator; The measuring integration capacitor C2 and the first buffer are both connected to the output terminal of the analog switch IC5, and the output terminal of the first buffer is connected to the sample and hold unit. The delay ramp integrator has its input terminal serving as the second input terminal (Stop), and its output terminal is connected to the delay integration capacitor C8 and the non-inverting input terminal of the high-speed comparator. The output terminal of the high-speed comparator is connected to the control input terminal of the analog switch IC5. The delay ramp integrator includes an operational amplifier IC6, a transistor T2, a resistor R10, a delay integration capacitor C8, and an inverter IC1F. The inverter IC1F is an open-collector output inverter and does not have a pull-up resistor connected. An 8-bit DAC, the output of which is connected to the inverting input of the high-speed comparator via a second buffer.

[0015] The beneficial effects of this invention are as follows: 1. High Measurement Reliability and Accuracy: This method employs dual-slope integration time-to-voltage conversion technology. Start / Stop signals trigger the measurement slope integrator and the delay slope integrator respectively, converting the time interval into voltage for measurement, enabling precise measurement of nanosecond-level transmission delays. Specifically, this method utilizes an 8-bit DAC to configure a fixed, precise delay, actively avoiding the nonlinear region at the start of the integration circuit and the inherent delay of the measurement circuit itself, further improving the accuracy and reliability of the measurement results.

[0016] 2. Strong anti-interference capability and stable measurement: In terms of hardware implementation, this method adopts open-circuit gate isolation, independent power supply and decoupling filter network for key integration circuits, which can significantly reduce the interference of power supply ripple and digital noise on measurement results and ensure the stability and reliability of the measurement process.

[0017] 3. Wide applicability and can be integrated into multiple test platforms: Steps S0 to S6 of this method can be implemented based on various hardware architectures, including but not limited to 24 digital channels, DC parameter measurement units and AC time parameter measurement functions, to meet the full parameter testing needs of small and medium-sized digital circuits.

[0018] 4. Simple operation and high testing efficiency: This method uses menu-driven programming to configure test conditions (step S1), eliminating the need for complex code writing; the ramp integral measurement time is short, and with the combination of sample-and-hold and voltmeter reading, the testing speed is fast, making it suitable for R&D verification and batch automated production testing.

[0019] 5. Measurement results are calibrable and have good consistency: This method establishes calibration values ​​through standard devices (step S5), which can effectively offset the error caused by the difference between the load capacitance of the test system and the standard load, and ensure the consistency of measurement results between different test systems. Attached Figure Description

[0020] Figure 1 This is a schematic diagram of the overall system structure provided in an embodiment of the present invention; Figure 2 A schematic diagram of a bidirectional digital channel provided in an embodiment of the present invention; Figure 3 A schematic diagram of a delay time measurement unit provided in an embodiment of the present invention; Figure 4 A circuit diagram of a measuring ramp integrator provided in an embodiment of the present invention; Figure 5 A circuit diagram of a delay ramp integrator provided in an embodiment of the present invention; Figure 6 A voltage regulator circuit diagram provided for an embodiment of the present invention; Figure 7 A+5V voltage regulator circuit diagram provided in an embodiment of the present invention; Figure 8 A-5V voltage regulator circuit diagram provided in the embodiment of the present invention; Figure 9 The diagram shows the menu programming interface and function table configuration of the SN74LS74A provided in this embodiment of the invention.

[0021] Figure 10 The image shows the test results of SN74LS74A provided in an embodiment of the present invention.

[0022] Figure 11 This is a flowchart of the method of the present invention. Detailed Implementation

[0023] The following description is intended to disclose the present invention and enable those skilled in the art to implement it. The preferred embodiments described below are merely examples, and other obvious variations will occur to those skilled in the art. The basic principles of the invention defined in the following description can be applied to other embodiments, modifications, improvements, equivalents, and other technical solutions that do not depart from the spirit and scope of the invention.

[0024] In the preferred embodiments of the present invention, those skilled in the art should note that the device under test (DUT), high-speed comparator, etc. involved in the present invention can be regarded as prior art.

[0025] Preferred embodiment.

[0026] like Figure 11 As shown, taking the device under test SN74LS74A as an example, this invention discloses a method for testing the propagation delay time of digital logic circuits, characterized by including the following steps: Step S0: Test preparation and calibration. Before the test, the slope and zero point need to be calibrated regularly: power on and preheat for a preset time (at least 15 minutes), adjust the potentiometer, and calibrate the delay slope and the measurement slope to the preset values ​​respectively.

[0027] The calibration of the delayed slope and the measured slope is as follows: See Figure 3 and Figure 5First, calibrate the delay ramp integrator: Set the DAC output voltage to make the high-speed comparator input threshold voltage Vth1, apply a trigger signal to the input of inverter IC1F, and use an oscilloscope to measure the actual time T1 from the signal trigger to the high-speed comparator output transition; set the DAC output voltage to make the high-speed comparator input threshold voltage Vth2, and use an oscilloscope to measure the actual time T2, and calculate the actual slope Kdelay=(Vth2-Vth1) / (T2-T1); adjust potentiometer P2 to make the actual slope Kdelay 1V / us, thus completing the slope adjustment of the delay ramp integrator; using the calibrated slope Kdelay, select a known measurement point (such as Vth1 and T1), and calculate the zero-point time T0: T0=T1-(Vth1 / Kdelay).

[0028] See Figure 3 Figure 4 and Figure 5 Next, calibrate the measurement ramp integrator: Set the DAC output voltage so that the high-speed comparator input threshold voltage is Vth1. Simultaneously apply trigger signals to the input terminals of inverters IC1A and IC1F, and read the output voltage Vout1 after the sample-and-hold unit. Therefore, T1 = 10V / us * Vout1. Set the DAC output voltage so that the high-speed comparator input threshold voltage is Vth2. Simultaneously apply trigger signals to the input terminals of inverters IC1A and IC1F, and read the output voltage Vout2 after the sample-and-hold circuit. Therefore, T2 = 10V / us * Vout2. Calculate the actual slope Kmeas = (Vth2 - Vth1) / (T2 - T1). Adjust potentiometer P1 so that the actual slope Kmeas is 10V / us, thereby completing the slope adjustment of the measurement ramp integrator. Using the calibrated slope Kmeas, select a known measurement point (such as Vth1 and T1) and calculate the zero-point time T0: T0 = T1 - (Vth1 / Kmeas). Step S1: Test system pre-test configuration, including electrical condition configuration, delay compensation configuration, and function table configuration; For step S1: See Figure 9Electrical configuration: According to the datasheet of the device under test (DUT), in the menu programming interface, input the function table of the DUT, set the operating power supply (U1 / U2 / U5), input logic level (VIL / VIH), output judgment level (VOL / VOH), and set the threshold voltages U3 (Start Level) and U4 (Stop Level) of the first and second high-speed comparators to determine the Start / Stop trigger points; for example, for the DUT SN74LS74A, set U1=VD1=5V, VIL=0.0V, VIH=3V, U3=1.5V (Start Level), U4=1.5V (Stop Level). After the system is powered on, first set these voltages; See Figure 3 Delay compensation configuration: The DAC output voltage is set to 0.6V, which is equivalent to setting the threshold voltage of the inverting input of the high-speed comparator to 0.6V. This is equivalent to setting the delay of the delay ramp integrator to Tdelay = 600ns (the slope of the delay ramp integrator is 1V / µs). This is used to eliminate the influence of the nonlinear region at the beginning of the measurement integration circuit and the inherent delay of the time measurement circuit itself on the test results, ensuring that the edge of the signal under test always falls in the middle section of the measurement integration ramp where the linearity is best, thereby improving measurement accuracy. The total time difference is obtained from the output voltage of the sample-and-hold unit, and then the fixed precise delay of 600ns and the zero-point offset are subtracted to obtain the final measurement result. Step S2: Apply excitation and generate the Start signal to determine the timing start point; For step S2: see Figure 9 The test system runs function tables Line 1 to Line 2. When the function table reaches line AfterLine+1, see [reference needed]. Figure 1 Figure 3 and Figure 4 The DUT's From Pin input pin receives a rising or falling excitation signal from a specific read / write channel. This excitation signal, after passing through the signal selector MUXA, a high-speed buffer unit, and a first high-speed comparator, serves as the Start signal to trigger the measurement ramp integrator and sample-and-hold unit. The measurement integrating capacitor C2 charges linearly, marking the start of the timing process. See [link to relevant documentation] Figure 9 For the tpLH / Clk to Q test of the device under test SN74LS74A, the function table is run from line 11 to line 20. When the function table reaches line 13, the third pin (the input pin CLK) of the device under test SN74LS74A has a rising edge signal.

[0029] Specifically: See Figure 3 and Figure 4When the inverter IC1A input has not yet received a start trigger signal, the measuring integration capacitor C2 discharges and resets to ground. When the start trigger signal is received at the IC1A input, the constant current Iconstant in the collector of T1 charges C2, generating a linear ramp voltage. The circuit uses an operational amplifier to drive a transistor constant current source. The non-inverting input of operational amplifier IC2 sets the reference voltage through a resistor divider. Due to the virtual short characteristic of the operational amplifier, it controls the base of transistor T1 through its output, thus fixing the emitter voltage of T1. The current flowing through the emitter resistor... Ie constant, This generates a stable constant current Iconstant at the collector; at this time, analog switch IC5 is in measurement state, so this current is injected into the measurement integrating capacitor C2, according to the integration formula... : ; Voltage V With time t It exhibits an absolutely linear relationship, with a slope of .

[0030] The inverter IC1A utilizes the high-impedance characteristic of open-collector output (OC): in the low-level state, it discharges current to reset the capacitor; in the high-impedance state, current is instantaneously injected into the capacitor to begin integration. During integration, the digital system is completely disconnected from the analog node to prevent digital system noise from interfering with measurement accuracy. Furthermore, no pull-up resistor is connected to prevent stray current from the power supply to the capacitor, ensuring a stable, straight charging slope. Operational amplifier IC2 uses a high-input-impedance op-amp to prevent input shunt from affecting reference accuracy. T1 is a PNP transistor, and C2 is the integration capacitor for the measurement path; its capacitance determines the voltage slope. Fine-tuning resistors P1 and R1 are used to precisely adjust the voltage slope over time, ensuring the output meets the set requirements. Resistor R3 determines the magnitude of the constant current. Inductor L1, resistor R3, and capacitor C1 together form a decoupling filter network to filter out high-frequency noise from the +5V power supply, improving the stability of the measurement slope.

[0031] To achieve optimal linearity, the voltage slope at the output of IC3 is set to 10V / us Therefore, the slope of the voltage change of capacitor C2 over time is 5V / µs. Given that C2 = 560pF, set the slope... ,according to : ; ; ; Where Iconstant is the charging current. Vsupply is the voltage drop across the emitter resistor R3 (R3 = 100Ω), Vsupply is the circuit supply voltage +5V, V+ is the voltage at the non-inverting input terminal of IC2, and V- is the voltage at the inverting input terminal of IC2. The above calculation utilizes the virtual short characteristic of the op-amp and ignores the influence of L1. ; ; Where R1 = 681Ω, R2 = 20kΩ, This is the actual resistance value of the fine-tuning resistor P1 (i.e., potentiometer). The actual circuit adjusts the depth of V+ through P1 to precisely match the voltage slope of IC3's output at 10V / ... us This is used to calibrate the time measurement circuit, see step S0; Step S3: The device under test (DUT) responds and a Stop signal is generated to determine the timing endpoint; Step S3 is implemented as follows, see Figure 1 , Figure 3 , Figure 4 , Figure 5 and Figure 9 : Step S3.1: Starting from the timing start point, after a delay of tpLH or tpHL, a rising or falling output signal is generated on the (To Pin) output pin of the device under test. This output signal simultaneously passes through the signal selector MUXB, the high-speed buffer unit, and the second high-speed comparator, and then serves as the Stop signal to trigger the delay ramp integrator to start, causing the delay integration capacitor C8 to charge linearly. Here, if the output signal is a rising edge signal, the measured parameter is tpLH; if it is a falling edge signal, the measured parameter is tpHL. The specific selection can be freely made through function table editing and menu programming. See [link to relevant documentation]. Figure 9 For testing the parameter tpLH / Clk to Q of the device under test SN74LS74A, there is a rising edge signal at the fifth pin (output pin Q) of the device under test. Step S3.2: The delay integrating capacitor C8 is linearly charged, and the integration point voltage gradually increases. When the voltage is greater than the preset value (0.6V), the output of the high-speed comparator flips, controlling the analog switch to cut off the charging path of the measuring integrating capacitor C2. The sample and hold unit locks the current voltage value, which is the timing end point.

[0032] Specifically: See Figure 3 and Figure 5 When the inverter IC1F input has not yet received a stop trigger signal, the integrating capacitor C8 discharges to ground. From the moment the stop trigger signal is received at the IC1F input, the constant current Iconstant in the collector of T2 charges the delay path integrating capacitor C8, according to the integration formula... : ; Voltage V exhibits an absolutely linear relationship with time t, with a slope of .

[0033] The inverter IC1F utilizes the high-impedance characteristic of open-collector output (OC): in the low-level state, it discharges current to reset the capacitor; in the high-impedance state, current is instantaneously injected into the capacitor to begin integration. During integration, the digital system is completely disconnected from the analog node, preventing digital system noise from interfering with measurement accuracy. Furthermore, no pull-up resistor is connected to prevent stray current from the power supply to the capacitor, ensuring a stable, straight charging slope. Operational amplifier IC6 uses a high-input-impedance op-amp to prevent input shunt from affecting reference accuracy. T2 is a PNP transistor, and C8 is the delay path integration capacitor, whose capacitance determines the voltage slope. Fine-tuning resistor P2 (i.e., potentiometer) and resistor R8 are used to precisely adjust the voltage slope over time, ensuring the output meets the set requirements. Resistor R10 determines the magnitude of the constant current. Inductor L2, resistor R10, and capacitor C1' together form a decoupling filter network to filter out high-frequency noise from the +5V power supply, improving the stability of the delay slope.

[0034] The voltage slope of the delay integration capacitor C8 is set to 1V / us Given C8 = 1nF, set the slope ,according to : ; ; ; Where Iconstant is the charging current. Vsupply is the voltage drop across the emitter resistor R10 (R10=499Ω), Vsupply is the circuit supply voltage +5V, V+ is the voltage at the non-inverting input terminal of IC6, and V- is the voltage at the inverting input terminal of IC6. The above calculation utilizes the virtual short characteristic of the op-amp and ignores the influence of L2. ; ; Where R8 = 1kΩ, R9 = 10kΩ, The actual resistance value of the fine-tuning resistor P2 is set. In the actual circuit, the depth of V+ is adjusted through P2 to precisely match the voltage slope of capacitor C8 to 1V / µs, which is used to calibrate the time measurement circuit. See step S0. Step S4: Calculate the transmission delay time (tpLH or tpHL); For step S4: The voltmeter reads the output voltage Vout of the sample-and-hold unit. Based on the preset slope Kmeas at the output of the measured ramp integrator (K=10V / μs in this embodiment), the total time difference is obtained according to the formula td=Vout / Kmeas. Then, the fixed precise delay of 600ns (Tdelay) of the delay ramp integrator mentioned in step S1 and the zero offset calculated in step S0 are subtracted to calculate the transmission delay time tpLH or tpHL.

[0035] Step S5: Measurement result correction; For step S5: Establish a calibration value Cal.Value using a standard device (precisely calibrated with an oscilloscope) to compensate for the error caused by the difference between the test system's load capacitance and the standard load (CL=15pF / 50pF). Transmission delay time (tpHL) or tpLH tests are typically measured under specified load capacitances, such as CL=15pF or 50pF, RL=2K. However, the final load capacitance on the DUT of the test system differs significantly from the specified load parameters, and the measurement results are also affected by other factors. Therefore, the measurement results need to be corrected. Specifically, a standard device is needed, whose various delay parameters have been precisely measured with an oscilloscope. These parameters have a difference from the measurement results of this test system. This difference is entered into the Cal.Value field in the menu programming interface. The final measurement result will be subtracted from the Cal.Value value. See [link to documentation]. Figure 9 , is the Cal.Value value added in the tpLH / ClktoQ menu programming of the SN74LS74A device under test.

[0036] Step S6: Result Judgment. Compare the measured transmission delay time with the nominal value in the datasheet of the device under test (DUT) to determine whether it is qualified; see [link to relevant documentation]. Figure 10 The image shows the test results of the SN74LS74A provided in an embodiment of the present invention.

[0037] Specifically, the testing system includes, see [link / reference] Figure 1 : 24 bidirectional read / write channels, connected to the input / output pins of the device under test (DUT); Signal selectors MUXA and MUXB are used to bring out specific pin signals (from the connection line between the DUT and the bidirectional read / write channel). A high-speed buffer unit, whose first input terminal Start is connected to the output terminal of the signal selector MUXA, and whose first input terminal Stop is connected to the output terminal of the signal selector MUXB; The first high-speed comparator (i.e., high-speed comparator control 1) and the second high-speed comparator (i.e., high-speed comparator control 2) are connected to the inputs of the first high-speed comparator and the second high-speed comparator, respectively. The delay time measurement unit has its second input terminal Start connected to the output terminal of the first high-speed comparator, and its second input terminal Stop connected to the output terminal of the second high-speed comparator. A sample-and-hold unit, the input of which is connected to the output of the delay time measurement unit; A voltmeter, the input of which is connected to the output of the sample-and-hold unit.

[0038] The power supply terminals of the device under test (DUT) are connected to programmable power supplies U1, U5, and U2, respectively. The input and output pins of the DUT are connected to 24 bidirectional read / write channels PD1 to PD24, and can also be connected to signal selectors MUXB and MUXA. The output terminal of MUXB is connected to the first terminal of switch K5, and the output terminal of MUXA is connected to the first terminal of switch K7. The leakage current measurement unit is connected to the second terminals of switches K5 and K6. The voltmeter unit is connected to the first terminal of switch K6, and the third terminal of switch K6 is connected to the third terminal of switch K7. The second terminal of switch K7 is connected to the first input terminal Start of the high-speed buffer unit, and the third terminal of switch K5 is connected to the first input terminal Stop of the high-speed buffer unit. Programmable power supplies U3 and U4 are connected to the other input terminals of the first and second high-speed comparators, respectively, as the threshold voltages of the comparators. The data bus is connected to MUXB, MUXA, and the 24 bidirectional read / write channels.

[0039] Specifically, such as Figure 2 As shown, this is a bidirectional digital channel PDn, and each channel in the bidirectional read / write channel includes: The first switch Kn_1 and the second switch Kn_2 are used to configure the pin as an input or an output; the first terminal of the first switch Kn_1 and the first terminal of the second switch Kn_2 are both connected to the pin PDn. A first high-speed analog switch SWn_1 and a second high-speed analog switch SWn_2 are connected, with the first terminal of the first high-speed analog switch SWn_1 and the first terminal of the second high-speed analog switch SWn_2 both connected to the second terminal of the first switch Kn_1. The second terminals of the first high-speed analog switch SWn_1 and the second high-speed analog switch SWn_2 are respectively connected to the programmable power supply U7 (as VIL) and the programmable power supply U8 (as VIH) to provide the input low level VIL and the input high level VIH to the pins of the device under test. The window comparator has its input terminal connected to the second terminal of the second switch Kn_2, and its threshold voltage input terminal connected to the programmable power supply U3 and programmable power supply U4. The programmable power supply U3 and U4 are connected to the window comparator as threshold voltages (VOL and VOH) to detect and determine the high and low levels of the output. The system includes a Write Unit and a Read Unit. The Write Unit is connected to the control terminals of the first high-speed analog switch SWn_1 and the second high-speed analog switch SWn_2, respectively. The Read Unit is connected to the output terminal of the window comparator. Both the Write Unit and the Read Unit are connected to the Data bus. The Write Unit is also connected to the S+H Start input signal and the output terminal of the serial input unit. The input terminal of the serial input unit is connected to a 1MHz clock and a T1 timer.

[0040] As a supplement, 24 bidirectional read / write channels are connected to the pins of the Device Under Test (DUT). Each channel is used as an input or output by controlling Kn_1 and Kn_2. The write unit connects the input high level VIH or input low level VIL to the DUT input pin as a logic excitation signal via SET-VIL-PDn and SET-VIH-PDn signals. The application of high-speed analog switches ensures that the logic excitation signal applied to the DUT input pin has a very fast rise and fall time. The read unit monitors the DUT output level through a window comparator and determines the correctness of the logic result based on preset output high level VOH and output low level VOL thresholds. All read and write operations are controlled and transmitted via a data bus. The circuit integrates precision measurement functions for DUT parameter testing: a leakage current measurement unit measures the minute leakage current of the DUT pins at specific voltages via K5 and MUXB; a voltmeter unit is used for testing parameters such as high and low output voltages; and a current source unit provides a programmable constant current for measuring the clamping diode characteristics of input pins or the load capacity of output pins.

[0041] More specifically, such as Figure 3 As shown, the delay time measurement unit includes: The input terminal of the ramp integrator is used as the second input terminal, Start. Analog switch IC5, whose input terminal is connected to the output terminal of the measuring ramp integrator; The measuring integration capacitor C2 and the first buffer (i.e., buffer 1) are both connected to the output terminal of the analog switch IC5, and the output terminal of the first buffer is connected to the sample and hold unit. The delay ramp integrator has its input terminal as the second input terminal (Stop), and its output terminal is connected to the delay integration capacitor C8 and the non-inverting input terminal of the high-speed comparator. The output terminal of the high-speed comparator is connected to the control input terminal of the analog switch IC5. The delay ramp integrator, in conjunction with the 8-bit DAC and the high-speed comparator, is used to generate a fixed and accurate delay, so that the measurement process avoids the influence of the nonlinear region at the beginning of the integration circuit and the inherent delay of the time measurement circuit itself on the test results. An 8-bit DAC, the output of which is connected to the inverting input of the high-speed comparator via a second buffer (buffer 2).

[0042] Furthermore, such as Figure 4 As shown, the measurement ramp integrator includes: operational amplifier IC2, transistor T1, resistor R3, measurement integration capacitor C2, and inverter IC1A, wherein: The input of inverter IC1A is connected to the Start signal output from the first high-speed comparator, and its output is connected to the non-inverting input of analog switch IC5, measuring integrating capacitor C2, and operational amplifier IC3, respectively. The output of operational amplifier IC3 is connected to SH-IN (connected to a voltmeter via a sample-and-hold unit). The non-inverting input of operational amplifier IC2 is connected to a voltage divider resistor network, and its output is connected to the base of transistor T1. Its inverting input is connected to the emitter of transistor T1. The collector of transistor T1 is connected to the input of analog switch IC5. The specific connections are as follows: the non-inverting input of op-amp IC2 is connected to the second terminal of resistor R1 and the first terminal of resistor R2; the inverting input of op-amp IC2 is connected to the second terminal of inductor L1 and the emitter of transistor T1; the output of op-amp IC2 is connected to the base of transistor T1; the positive and negative power supply pins of op-amp IC2 are connected to power supply U5+15V and power supply U5-15V respectively; the non-inverting input of op-amp IC3 is connected to the first terminal of capacitor C2, the output of inverter IC1A, and pins 1, 3, and 13 of analog switch IC5; the input of inverter IC1A is connected to the signal terminal Start; and the second terminal of capacitor C2 is connected to the ground terminal AGND. The inverting input of op-amp IC3 is connected to the second terminal of resistor R6 and the first terminal of resistor R7. The output of op-amp IC3 is connected to the second terminal of resistor R7 and the output terminal SH-IN. The positive power supply pin of op-amp IC3 is connected to the power supply U5 +15V and the second terminal of capacitor C3. The first terminal of capacitor C3 is connected to ground AGND. The negative power supply pin of op-amp IC3 is connected to the power supply U5 -15V and the first terminal of capacitor C5. The second terminal of capacitor C5 is connected to ground AGND. Pin 4 of analog switch IC5 is connected to the collector of transistor T1. Pins 9, 10, and 11 of analog switch IC5 are connected to the signal terminal Delayed. Stop. Pins 2, 5, 6, 8, and 12 of analog switch IC5 are all connected to the ground terminal AGND. Pin 16 of analog switch IC5 is connected to the positive power supply A+5V. Pin 7 of analog switch IC5 is connected to the negative power supply A-5V. The first end of resistor R1 is connected to the second end of potentiometer P1. The second end of resistor R2 is connected to the ground terminal AGND. The first end of resistor R3 is connected to the power supply STAB+5V, the first end of capacitor C1, and the first and third ends of potentiometer P1. The second end of resistor R3 is connected to the first end of inductor L1. The second end of capacitor C1 is connected to the ground terminal AGND. The first end of resistor R6 is connected to the ground terminal AGND.

[0043] Furthermore, such as Figure 5 As shown, the delay ramp integrator includes: operational amplifier IC6, transistor T2, resistor R10, delay integration capacitor C8, and inverter IC1F (an open-collector output inverter without pull-up resistors), wherein: The input of inverter IC1F is connected to the Stop signal output by the second high-speed comparator, and its output is connected to the collector of transistor T2, the delay integration capacitor C8, and the non-inverting input of the high-speed comparator, respectively. The non-inverting input of operational amplifier IC6 is connected to a voltage divider resistor network, its output is connected to the base of transistor T2, and its inverting input is connected to the emitter of transistor T2. The specific connection description is as follows: The STAB+5V power supply terminal is connected to the first terminal of the adjustable resistor P2, the third terminal of the adjustable resistor P2, and the first terminal of the resistor R10. The second terminal of the adjustable resistor P2 is connected to the first terminal of the resistor R8. The second terminal of the resistor R8 is connected to the non-inverting input terminal of the op-amp IC6 and the first terminal of the resistor R9. The second terminal of the resistor R9 is connected to the ground terminal AGND. The second terminal of the resistor R10 is connected to the first terminal of the inductor L2. The second terminal of the inductor L2 is connected to the inverting input terminal of the op-amp IC6 and the emitter of the transistor T2. The output terminal of the op-amp IC6 is connected to the base of the transistor T2. The collector of the transistor T2 is connected to the output terminal of the inverter IC1F, the first terminal of the capacitor C8, and connected to the non-inverting input terminal of the high-speed comparator. The second terminal of the capacitor C8 is connected to the ground terminal AGND. The input terminal of the inverter IC1F is connected to the signal terminal Stop.

[0044] Preferably, such as Figure 6 As shown, it also includes a (STAB+5V) voltage regulator circuit for powering the measurement ramp integrator and the delay ramp integrator. The voltage regulator circuit includes a voltage regulator IC11, an operational amplifier IC12, a transistor T3, and capacitors C11, C12, and C13, wherein: The first terminal of capacitor C11 is connected to pin 3 of voltage regulator IC11 and power supply U5+15V. Pin 7 of op-amp IC12 is connected to the collector of transistor T3 and power supply U5+15V. Pin 4 of op-amp IC12 is connected to power supply U5-15V. The second terminal of capacitor C11, pin 2 of voltage regulator IC11, the second terminal of capacitor C12, and the negative terminal of capacitor C13 are connected to ground AGND. The first terminal of capacitor C12 is connected to the positive terminal of electrolytic capacitor C13, pin 1 of voltage regulator IC11, and the non-inverting input of op-amp IC12. The inverting input of op-amp IC12 is connected to the emitter of transistor T3 and outputs a stable voltage of STAB+5V. The output terminal of op-amp IC12 is connected to the base of transistor T3.

[0045] like Figure 7 The diagram shown is an A+5V voltage regulator circuit, including regulator IC15, electrolytic capacitor C15, electrolytic capacitor C16, and capacitor C17. The positive terminal of capacitor C15 is connected to pin 1 of voltage regulator IC15 and to power supply U5+15V. The negative terminal of capacitor C15, pin 2 of voltage regulator IC15, the negative terminal of capacitor C16, and the second terminal of capacitor C17 are connected to ground terminal AGND. The first terminal of capacitor C17 is connected to the positive terminal of electrolytic capacitor C16 and pin 3 of voltage regulator IC15, and outputs a stable voltage of A+5V.

[0046] like Figure 8 The diagram shown is an A-5V voltage regulator circuit, including regulator IC16, electrolytic capacitor C18, and electrolytic capacitor C19. The negative terminal of capacitor C18 is connected to pin 2 of voltage regulator IC16 and to power supply U5-15V. The positive terminal of capacitor C18, pin 1 of voltage regulator IC16, and the positive terminal of capacitor C19 are connected to ground terminal AGND. The negative terminal of capacitor C19 is connected to pin 3 of voltage regulator IC15 and outputs a stable voltage of A-5V.

[0047] like Figure 6-8 As shown, STAB+5V is used to power the measurement ramp integrator and the delay ramp integrator, while A+5V and A-5V are used to power the analog switch IC5. STAB+5V uses a reference, operational amplifier, and transistor structure to provide a voltage with very low ripple and high stability, ensuring the absolute linearity and stability of the integrator charging ramp. At the same time, the analog switch power supply (A+5V / A-5V) is independently separated from the two integrator power supplies (STAB+5V) to prevent switching noise from polluting the measurement ramp and reduce measurement jitter.

[0048] Preferably, it also includes a leakage current measurement unit, a voltmeter unit, and a programmable current source for DC parameter testing.

[0049] Preferably, it also includes a menu programming interface for configuring the input excitation level VIH / VIL, the output judgment threshold VOH / VOL, and the delay time measurement conditions.

[0050] Figure 9-10 The following diagrams are provided for the SN74LS74A device under test (SUT) menu programming interface (parameters tpLH / Clk to Q), function table configuration diagram, and test result diagram of the SN74LS74A digital logic device under test, which are provided for embodiments of this utility model.

[0051] It is worth mentioning that for time parameter measurements (AC measurements), signals from specific input and output pins are routed to a high-speed processing link via MUXA and MUXB to provide the rising or falling signals from the input and output pins required for testing transmission delay time. A high-speed buffer unit is used to achieve high input impedance and isolation from the device under test (DUT), while maintaining signal edge sharpness and minimizing measurement jitter. The first / second high-speed comparators, whose outputs are initially high, flip to form falling-edge triggered Start and Stop signals when they receive rising or falling signals from the DUT's input and output pins, and are loaded into subsequent circuits. This allows the DUT's tpHL or tpLH to be tested via subsequent circuits. Here, by comparing the input signal with preset thresholds (U3 and U4), the exact voltage point (e.g., 50% amplitude) at which Start and Stop are triggered can be precisely set, thus accurately locating the start and end times of timing and ensuring measurement accuracy. The measurement ramp integrator uses a precision constant current source to linearly charge the capacitor, converting the time interval into a linearly proportional analog voltage signal. The delay ramp integrator, in conjunction with an 8-bit... The DAC and high-speed comparator generate a fixed, precise delay, ensuring that the measurement process avoids the nonlinear region at the start of the integrator circuit and the inherent delay of the time measurement circuit itself; while the analog switch is responsible for high-speed switching between measurement, hold, and reset states, precisely controlling the current path and locking the final measured voltage value. See also Figure 2 S+H Start is the start signal of the sample-and-hold unit, which is completely synchronized with the excitation signal received at the input of the device under test (DUT).

[0052] Preferably, parasitic capacitance and inductance in each unit of the system have a significant impact on the measurement results. During PCB design, the input / output pins of the device under test (DUT) should be as close as possible to the bidirectional digital channel, and the output path of the high-speed analog switch should also be as close as possible to the input / output pins of the DUT to minimize signal overshoot, ringing, and signal delay caused by parasitic capacitance and inductance. While ensuring impedance control, use thinner traces to reduce parasitic capacitance. Isolation rings should be placed around the leakage current measurement unit and the signal lines from MUXA / MUXB, as well as around the time-voltage conversion nodes of the measurement ramp integrator and delay ramp integrator, and connected to an equipotential reference point to prevent PCB leakage current interference and reduce the impact of parasitic capacitance on the measurement results. Integrating capacitors C2 and C8 should be made of C0G / NP0 material to ensure temperature stability, and the integrating capacitors should be placed close to the constant current source output and the analog switch input.

[0053] It is worth mentioning that the technical features of the device under test (DUT), high-speed comparator, etc. involved in this patent application should be regarded as prior art. The specific structure, working principle, and possible control methods and spatial arrangement of these technical features can be adopted using conventional choices in the field and should not be regarded as the inventive point of this patent. This patent will not be further elaborated in detail.

[0054] For those skilled in the art, modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this invention should be included within the protection scope of this invention.

Claims

1. A method for testing the transmission delay time of digital logic circuits, characterized in that, Includes the following steps: Step S0: Test preparation and calibration. Before the test, the slope and zero point need to be calibrated regularly: power on and preheat for a preset time and adjust the potentiometer to calibrate the delay slope and the measurement slope to the preset values ​​respectively. Step S1: Test system pre-test configuration, including electrical condition configuration, delay compensation configuration, and function table configuration; Step S2: Apply excitation and generate the Start signal to determine the timing start point; Step S3: The device under test (DUT) responds and a Stop signal is generated to determine the timing endpoint; Step S4: Calculate the transmission delay time; Step S5: Measurement result correction; Step S6: Result judgment. Compare the measured transmission delay time with the nominal value in the datasheet of the device under test (DUT) to determine whether it is qualified.

2. The method for testing the transmission delay time of digital logic circuits according to claim 1, characterized in that, The specific steps in step S0 for correcting the slope and zero point include: For the delay ramp integrator, set the DAC output voltage to make the high-speed comparator input threshold voltage Vth1, apply a trigger signal to the input of inverter IC1F, and use an oscilloscope to measure the actual time T1 from the signal trigger to the high-speed comparator output transition; set the DAC output voltage to make the high-speed comparator input threshold voltage Vth2, and use an oscilloscope to measure the actual time T2, and calculate the actual slope Kdelay=(Vth2-Vth1) / (T2-T1); adjust potentiometer P2 to make the actual slope Kdelay the preset value, thus completing the slope adjustment of the delay ramp integrator; using the calibrated slope Kdelay, select a known measurement point and calculate the zero-point time T0; For measuring the ramp integrator, set the DAC output voltage to make the high-speed comparator input threshold voltage Vth1, apply trigger signals to the input terminals of inverters IC1A and IC1F simultaneously, and read the output voltage Vout1 after the sample-and-hold unit to obtain the actual time T1; set the DAC output voltage to make the high-speed comparator input threshold voltage Vth2, apply trigger signals to the input terminals of inverters IC1A and IC1F simultaneously, and read the output voltage Vout2 after the sample-and-hold unit to obtain the actual time T2; calculate the actual slope Kmeas = (Vth2 - Vth1) / (T2 - T1); adjust potentiometer P1 to make the actual slope Kmeas the preset value, thus completing the slope adjustment of the ramp integrator; using the calibrated slope Kmeas, select a known measurement point and calculate the zero-point time T0.

3. The method for testing the transmission delay time of a digital logic circuit according to claim 1, characterized in that, For step S1: Electrical configuration: According to the datasheet of the device under test (DUT), enter the function table of the DUT in the menu programming interface, set the working power supply, input logic level, output judgment level, and set the threshold voltage of the first high-speed comparator and the second high-speed comparator to determine the Start / Stop trigger point; Delay compensation configuration: Configure the 8-bit DAC output with a fixed threshold voltage to enable the delay ramp integrator to generate a fixed and precise delay, which is used to actively avoid the nonlinear region at the beginning of the integration circuit and to offset the inherent delay of the time measurement circuit itself.

4. The method for testing the transmission delay time of a digital logic circuit according to claim 1, characterized in that, For step S2: The test system runs the function table and outputs a steep edge logic excitation signal to the input pin of the device under test (DUT) through the bidirectional read / write channel. This excitation signal passes through the signal selector MUXA, the high-speed buffer unit, and the first high-speed comparator, and then serves as the Start signal to trigger the measurement ramp integrator and the sample-and-hold unit to start. The measurement integration capacitor C2 is linearly charged, which is the timing start point.

5. The method for testing the transmission delay time of a digital logic circuit according to claim 4, characterized in that, Step S3 is implemented as follows: Step S3.1: Starting from the timing start point, after a delay of tpLH or tpHL, there is a rising or falling output signal on the output pin of the device under test. This output signal passes through the signal selector MUXB, the high-speed buffer unit, and the second high-speed comparator, and then triggers the delay ramp integrator as a Stop signal to start, and the delay integration capacitor C8 is linearly charged. Step S3.2: The delay integrating capacitor C8 is linearly charged, and the integration point voltage gradually increases. When the voltage is greater than the preset value, the output of the high-speed comparator flips, controlling the analog switch IC5 to cut off the charging path of the measuring integrating capacitor C2. The sample and hold unit locks the current voltage value, which is the timing end point.

6. The method for testing the transmission delay time of digital logic circuits according to claim 5, characterized in that, In step S3.1, when the output signal is a rising edge signal, the measured parameter is tpLH; when the output signal is a falling edge signal, the measured parameter is tpHL; the specific selection can be made freely through function table editing and menu programming.

7. The method for testing the transmission delay time of a digital logic circuit according to claim 5, characterized in that, For step S4: The voltmeter reads the output voltage Vout of the sample-and-hold unit. Based on the preset slope Kmeas at the output of the measured ramp integrator, the total time difference is obtained according to the formula td=Vout / K. Then, the fixed precise delay of the delayed ramp integrator mentioned in step S1 and the zero offset calculated in step S0 are subtracted to calculate the transmission delay time tpLH or tpHL.

8. The method for testing the transmission delay time of a digital logic circuit according to claim 1, characterized in that, For step S5: Use standard devices to establish a calibration value Cal.Value to offset the error caused by the difference between the load capacitance of the test system and the standard load.

9. A method for testing the transmission delay time of a digital logic circuit according to any one of claims 1-8, characterized in that, The testing system includes: A bidirectional read / write channel is used to connect the input / output pins of the device under test. Signal selectors MUXA and MUXB are used to bring out signals from specific pins; A high-speed buffer unit, whose first input terminal Start is connected to the output terminal of the signal selector MUXA, and whose first input terminal Stop is connected to the output terminal of the signal selector MUXB; The first high-speed comparator and the second high-speed comparator, with the two output terminals of the high-speed buffer unit respectively connected to the input terminals of the first high-speed comparator and the second high-speed comparator; The delay time measurement unit has its second input terminal Start connected to the output terminal of the first high-speed comparator, and its second input terminal Stop connected to the output terminal of the second high-speed comparator. A sample-and-hold unit, the input of which is connected to the output of the delay time measurement unit; A voltmeter, the input of which is connected to the output of the sample-and-hold unit.

10. A method for testing the transmission delay time of a digital logic circuit according to claim 9, characterized in that, The delay time measurement unit includes: A measurement ramp integrator is provided, with its input terminal serving as the second input terminal Start. The measurement ramp integrator includes an operational amplifier IC2, a transistor T1, a resistor R3, a measurement integration capacitor C2, and an inverter IC1A. The inverter IC1A is an open-collector output inverter and does not have a pull-up resistor connected. Analog switch IC5, whose input terminal is connected to the output terminal of the measuring ramp integrator; The measuring integration capacitor C2 and the first buffer are both connected to the output terminal of the analog switch IC5, and the output terminal of the first buffer is connected to the sample and hold unit. The delay ramp integrator has its input terminal serving as the second input terminal (Stop), and its output terminal is connected to the delay integration capacitor C8 and the non-inverting input terminal of the high-speed comparator. The output terminal of the high-speed comparator is connected to the control input terminal of the analog switch IC5. The delay ramp integrator includes an operational amplifier IC6, a transistor T2, a resistor R10, a delay integration capacitor C8, and an inverter IC1F. The inverter IC1F is an open-collector output inverter and does not have a pull-up resistor connected. An 8-bit DAC, the output of which is connected to the inverting input of the high-speed comparator via a second buffer.

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