A multi-mode closed-loop locking method for NMOR atomic magnetometer resonance signals based on FPGA

Abstract

This invention relates to the field of magnetic field measurement technology, specifically to a multi-mode closed-loop locking method for the resonance signal of an NMOR atomic magnetometer based on FPGA. The method includes: acquiring the optical rotation detection signal of the NMOR atomic magnetometer; performing orthogonal demodulation and digital phase detection processing on the optical rotation detection signal to obtain the phase detection error and demodulation amplitude; determining the working mode based on the phase detection error, switching between a limiting oscillation mode and a linear closed-loop control mode; in the limiting oscillation mode, outputting a gated maximum modulation frequency step constant corresponding to the polarity of the phase detection error; compensating and preloading the integral state of the linear closed-loop controller during mode switching; identifying the lock-out based on the demodulation amplitude, and restoring closed-loop locking after performing a frequency sweep search in the lock-out state. This invention satisfies the requirements of fast tracking under high disturbances and extremely low noise suppression in steady state, improving the continuous measurement capability and reliability of the NMOR atomic magnetometer.

Description

Technical Field

[0001] This invention relates to the field of magnetic field measurement technology, and specifically to a multi-mode closed-loop locking method for resonance signals of an NMOR atomic magnetometer based on FPGA. Background Technology

[0002] Atomic magnetometers based on the nonlinear magneto-optical rotation (NMOR) effect have been widely used in recent years in fields such as geomagnetic navigation, mineral resource exploration, industrial non-destructive testing, biomagnetic field measurement, and magnetic anomaly detection on unmanned platforms due to their high sensitivity, lack of need for cryogenic refrigeration, simple structure, and ability to operate directly in geomagnetic environments. NMOR atomic magnetometers typically utilize the polarization moment resonance effect generated by an atomic ensemble under the influence of a modulated optical field, and invert the external magnetic field strength by detecting the phase change of the optical rotation signal.

[0003] To improve the dynamic measurement range and real-time tracking capability of NMOR atomic magnetometers, existing systems generally employ a closed-loop locking architecture combining a digital lock-in amplifier and a proportional-integral (PI) controller. This architecture continuously measures changes in the external magnetic field by tracking the atomic Larmor precession frequency in real time. In this type of closed-loop system, the error signal output from the phase detector is adjusted by the PI controller and used to dynamically correct the drive frequency, thereby maintaining the system near the atomic resonance state. The system's measurement accuracy, dynamic response capability, and steady-state noise level are all closely related to the closed-loop control performance.

[0004] However, the resonance signal of the NMOR atomic magnetometer itself exhibits significant nonlinear characteristics. When the external magnetic field undergoes a large step change, the detuning between the driving frequency and the true Larmor precession frequency increases rapidly, causing the phase detection output to enter the nonlinear saturation region. In this region, the sensitivity of the phase detection signal to frequency deviation decreases significantly, making it difficult for traditional linear PI controllers to quickly adjust the driving frequency, resulting in insufficient dynamic tracking capability of the system. Increasing the PI control gain to improve the response speed easily introduces a large amount of high-frequency noise, raising the noise floor of the closed-loop system and reducing the magnetic field measurement sensitivity. Therefore, the traditional single PI closed-loop control structure cannot simultaneously achieve both fast response capability under large dynamic disturbances and steady-state low-noise measurement performance.

[0005] Furthermore, in applications such as UAV-borne magnetic detection and complex industrial environment monitoring, the system is frequently affected by sudden attitude changes, magnetic anomalies, and environmental noise, which can easily disrupt the atomic polarization resonance state, leading to physical loss of lock. Once lost, existing systems typically cannot automatically recapture the resonance frequency, requiring manual frequency rescanning and reset. This not only affects measurement continuity but also reduces the system's reliability and autonomous operation capability in complex environments.

[0006] Meanwhile, some existing digital closed-loop control schemes, when implemented on FPGAs, suffer from complex computational logic, high hardware multiplier resource consumption, and significant control latency, making it difficult to meet the engineering application requirements of high-speed real-time control and low resource consumption. Summary of the Invention

[0007] The purpose of this invention is to provide an FPGA-based multi-mode closed-loop locking method for the resonance signal of an NMOR atomic magnetometer, which satisfies the requirements of fast tracking under high disturbance and extremely low noise suppression under steady state, has low-level lock-out identification and self-recovery capabilities, and improves the continuous measurement capability and reliability of the NMOR atomic magnetometer.

[0008] The objective of this invention can be achieved through the following technical solutions: A multi-mode closed-loop locking method for NMOR atomic magnetometer resonance signals based on FPGA, the method comprising: S1. Acquire the optical rotation detection signal from the NMOR atomic magnetometer, perform quadrature demodulation and digital phase detection on the optical rotation detection signal, and obtain the phase detection error and demodulation amplitude. S2. Based on the phase detection error, determine the working mode. When the phase detection error exceeds the preset upper limit threshold, switch to the extreme slewing mode. When the phase detection error is lower than the preset lower limit threshold, switch to the linear closed-loop control mode. And maintain the current working mode unchanged between the upper limit threshold and the lower limit threshold. S3. Under the extreme slewing mode, output the maximum modulation frequency step constant in the corresponding direction according to the polarity of the phase detection error. S4. When switching from the extreme pressure swing mode to the linear closed-loop control mode, the integral state of the control signal of the linear closed-loop controller is compensated and preloaded to make the control output before and after the switch continuous. S5. Real-time monitoring of demodulation amplitude. When the demodulation amplitude is continuously lower than the preset amplitude threshold, the system is determined to be in a unlocked state. Closed-loop feedback is disconnected and frequency sweep search is performed. Closed-loop locking is restored after the frequency corresponding to the maximum value of demodulation amplitude is detected.

[0009] Furthermore, step S1 includes: S11. Convert the current signal output by the photoelectric detection circuit into a voltage signal, perform analog-to-digital conversion on the voltage signal, and obtain the digital sampling signal corresponding to the optical rotation detection signal.

[0010] Furthermore, step S1 also includes: S12. The digital sampled signal is digitally mixed with the reference sine signal and the reference cosine signal respectively. The digitally mixed signal is then low-pass filtered to obtain the in-phase component and the quadrature component. S13. Calculate the phase detection error and demodulation amplitude based on the in-phase component and the quadrature component.

[0011] Furthermore, step S2 includes: presetting a first error threshold and a second error threshold in the FPGA internal register, wherein the first error threshold is greater than the second error threshold; when the absolute value of the phase detection error is greater than the first error threshold, the operating mode is switched to the extreme slew mode; when the absolute value of the phase detection error is less than the second error threshold, the operating mode is switched to the linear closed-loop control mode; when the absolute value of the phase detection error is between the first error threshold and the second error threshold, the operating mode of the previous clock cycle is maintained.

[0012] Furthermore, step S3 includes: under the extreme slewing mode, suspending the linear closed-loop controller, extracting the sign bit of the phase detection error, selecting one of the maximum positive modulation frequency step constant and the maximum negative modulation frequency step constant according to the sign bit, and superimposing the selected modulation frequency step constant onto the current driving frequency.

[0013] Furthermore, the linear closed-loop control mode includes: performing proportional-integral calculations based on the phase detection error to obtain the frequency adjustment amount, adjusting the driving frequency of the atomic magnetometer based on the frequency adjustment amount, and storing the integral calculation result in the integral accumulator register.

[0014] Furthermore, step S4 includes: at the rising edge of the clock when switching from the extreme slew mode to the linear closed-loop control mode, reading the control output, current phase detection error, and phase change rate of the previous clock cycle before the switch, calculating the compensation integral value based on the control output, current phase detection error, and phase change rate, and writing the compensation integral value into the integral accumulation register of the linear closed-loop controller.

[0015] Furthermore, step S5 includes: presetting an amplitude threshold and a timeout count threshold inside the FPGA; starting a count when the demodulation amplitude is lower than the amplitude threshold; and determining that the system is in a unlocked state when the continuous count value reaches the timeout count threshold.

[0016] Furthermore, step S5 includes: after determining that the system is in a unlocked state, disconnecting the closed-loop feedback based on the phase detection error, configuring the integral accumulator of the linear closed-loop controller as a sweep frequency phase accumulator, outputting a sweep frequency drive signal within a preset frequency range according to a preset sweep frequency step size, and using the frequency point corresponding to the maximum amplitude value when the demodulation amplitude reaches the frequency point, as the closed-loop locking frequency.

[0017] Furthermore, the FPGA is internally configured with a quadrature demodulation and digital phase detection unit, a multi-mode state machine decision unit, a multiplexed high-speed slewing unit, a disturbance-free switching closed-loop control unit, and a lock-out monitoring and autonomous frequency sweeping unit. The input terminal of the quadrature demodulation and digital phase detection unit is connected to the input terminal of the digital sampling signal. The quadrature demodulation and digital phase detection unit is used to perform quadrature demodulation and digital phase detection processing on the digital sampling signal, and outputs the error phase and demodulation amplitude to the multi-mode state machine decision unit. The output terminal of the quadrature demodulation and digital phase detection unit is also connected to the unlock monitoring and autonomous frequency sweep unit. The multimodal state machine decision unit is used to make working mode decisions based on the error phase. The output of the multimodal state machine decision unit is connected to the multiplexed high-speed slewing unit, the disturbanceless switching closed-loop control unit, and the lock-out monitoring and autonomous frequency sweeping unit, respectively, and controls the working state of the multiplexed high-speed slewing unit, the disturbanceless switching closed-loop control unit, and the lock-out monitoring and autonomous frequency sweeping unit, respectively. The outputs of both the multiplexed high-speed slewing unit and the disturbance-free switching closed-loop control unit are connected to the drive frequency control terminal; The unlock monitoring and autonomous frequency sweep unit is used to determine whether the system is in an unlocked state based on the demodulation amplitude. The output of the unlock monitoring and autonomous frequency sweep unit is connected to the drive frequency control terminal, and outputs a frequency sweep drive signal in the unlocked state.

[0018] Compared with the prior art, the present invention has the following beneficial effects: (1) This invention utilizes the FPGA hardware multiplexer pass-through mechanism to construct the extreme slewing mode. When the system faces a large step disturbance and enters the phase nonlinear saturation region, it can bypass complex mathematical operations and directly provide the maximum hardware response speed, thus solving the problem of slow response speed of traditional control methods in this phase saturation region.

[0019] (2) By outputting a hardware setpoint of pure combinational logic under the extreme slewing mode, this invention avoids the introduction of high-frequency noise. Traditional methods of increasing the PI parameter to improve response speed will introduce high-frequency noise, while this invention achieves fast tracking with a constant step rate, thus resolving the contradiction between fast tracking capability for large steps and steady-state measurement sensitivity while ensuring sensitivity.

[0020] (3) To address the issue of sudden changes in control signals during mode switching, this invention introduces a disturbance-free switching mechanism. By dynamically reconstructing the historical parameters of the controller, the output voltage of the drive signal is forced to be equal before and after the switching, eliminating the jump in the control signal, ensuring a smooth transition of the drive frequency, avoiding the system from instantly leaving the resonant tracking state, and achieving smooth continuous locking.

[0021] (4) To address the high-frequency oscillation phenomenon occurring at the mode switching boundary, this invention introduces a collaborative judgment mechanism between the anti-shake hysteresis comparison interval and the multi-modal state machine. This mechanism can avoid frequent reversals of the control state at the boundary, thereby improving the stability of the control system during large dynamic tracking.

[0022] (5) To address the lock-out problem caused by abnormal disturbances, the system of this invention constructs a lock-out identification and autonomous relocking mechanism based on the reduction of demodulation amplitude. By disconnecting the failed closed loop and using the internal frequency synthesizer to perform automatic frequency search at a constant rate, this invention achieves rapid and stable relocking of the resonant frequency without manual intervention, thereby improving the reliability of continuous measurement of the magnetometer. Attached Figure Description

[0023] Figure 1 This is a schematic diagram of a multi-mode closed-loop locking method for NMOR atomic magnetometer resonance signals based on FPGA according to an embodiment of the present invention. Figure 2 This is a schematic diagram of the multimodal state machine mode switching and disturbance-free compensation control logic according to an embodiment of the present invention; Figure 3 This is a phase hysteresis comparison control logic diagram in an embodiment of the present invention; Figure 4 This is a block diagram of the loss-of-lock identification and autonomous frequency sweeping logic based on demodulation amplitude monitoring in an embodiment of the present invention. Detailed Implementation

[0024] The present invention will now be described in detail with reference to the accompanying drawings and specific embodiments. These embodiments are based on the technical solution of the present invention and provide detailed implementation methods and specific operating procedures. However, the scope of protection of the present invention is not limited to the following embodiments.

[0025] like Figures 1 to 4 The method shown is a multi-mode closed-loop locking method for NMOR atomic magnetometer resonance signals based on FPGA. The method includes: S1. Acquire the optical rotation detection signal from the NMOR atomic magnetometer, perform quadrature demodulation and digital phase detection processing on the optical rotation detection signal to obtain the phase detection error and demodulation amplitude, which are used to obtain the real-time resonance state information of the atomic magnetometer and provide input parameters for subsequent working mode decision, drive frequency adjustment and lockout identification; Step S1 specifically includes: S11. The current signal output from the photoelectric detection circuit is converted into a voltage signal. The voltage signal is then converted from analog to digital to obtain the digital sampling signal corresponding to the optical rotation detection signal. The photoelectric detection circuit in the atomic magnetometer probe outputs a weak current signal characterizing the atomic optical rotation effect. Due to the small amplitude of the weak current signal, it is first converted from current to voltage by a transimpedance amplifier to obtain the corresponding analog voltage signal. The analog voltage signal is then discretely sampled by a high-speed analog-to-digital converter according to the system sampling clock to obtain a digital sampling signal. This digital sampling signal is then input to the quadrature demodulation and digital phase detection unit inside the FPGA. The transimpedance amplifier is used to increase the voltage amplitude of the photoelectric detection signal, and the analog-to-digital converter is used to convert the continuous analog signal into a digital signal for digital processing by the FPGA.

[0026] S12. Inside the FPGA, the quadrature demodulation and digital phase detector unit receives the digital sampled signal and performs digital multiplication mixing with the reference sine and reference cosine signals respectively. The reference sine and reference cosine signals are generated by a digital frequency synthesizer and are synchronized with the current driving frequency. After digital mixing, the mixing result is low-pass filtered and decimation filtered to remove high-frequency components, obtaining the corresponding in-phase and quadrature components.

[0027] S13. The CORDIC algorithm is called within the FPGA to iteratively calculate the in-phase and quadrature components, obtaining the phase detection error and demodulation amplitude of the current system. The phase detection error characterizes the phase deviation between the current driving frequency and the atomic true Larmor precession frequency, while the demodulation amplitude characterizes the intensity of the current polarization moment resonance signal.

[0028] S2. Based on the phase detection error, determine the operating mode. When the phase detection error exceeds a preset upper threshold, switch to the extreme sway mode; when the phase detection error is below a preset lower threshold, switch to the linear closed-loop control mode, and maintain the current operating mode between the upper and lower thresholds. Figure 2 and Figure 3 As shown, step S2 specifically includes: setting up a multimodal state machine decision unit inside the FPGA, and presetting a first error threshold and a second error threshold in the register, where the first error threshold is greater than the second error threshold. When the absolute value of the phase detection error is less than the second error threshold, the multimodal state machine decision unit determines that the system has entered the linear closed-loop control interval and switches the current working mode to the linear closed-loop control mode; when the absolute value of the phase detection error is between the first error threshold and the second error threshold, the multimodal state machine decision unit maintains the working mode of the previous clock cycle unchanged. The first and second error thresholds are set based on the effective linewidth of the polarization moment resonance signal of the NMOR atomic magnetometer. By setting a dual-threshold hysteresis comparison interval, the switching conditions between the limiting slewing mode and the linear closed-loop control mode are constrained to reduce frequent switching near the mode boundary.

[0029] S3. In the extreme sway mode, output the maximum modulation frequency step constant in the corresponding direction according to the polarity of the phase detection error. Step S3 specifically includes: in the extreme sway mode, suspending the linear closed-loop controller, extracting the sign bit of the phase detection error, selecting one of the maximum positive modulation frequency step constant and the maximum negative modulation frequency step constant based on the sign bit, and superimposing the selected modulation frequency step constant onto the current driving frequency. During operation, the multi-modal state machine decision unit reads the absolute value of the current phase detection error in real time. The system determines the operating mode based on the absolute value of the phase detection error. When faced with a large step magnetic field disturbance, causing the phase detection error phase to enter the nonlinear saturation region, and the absolute value of the phase detection error exceeds the first error threshold, the multi-mode state machine decision unit determines that the system has entered a large detuning state and switches the current operating mode to the extreme slewing mode. In this mode, the system directly skips linear PI calculations, completely abandons the hardware multiplier, and adopts a simplified control logic with a "zero multiplier," saving internal resources. The FPGA directly extracts the most significant bit (MSB), represented in two's complement form, from the error phase data bus output by the CORDIC, and hardwires this sign bit to the channel control terminal of the underlying 2-to-1 multiplexer (MUX). If the sign bit is 0 (representing a positive phase deviation), the MUX directly selects the maximum forward modulation frequency step constant preset in the ROM. If the sign bit is 1 (representing a negative phase deviation), then the maximum negative modulation frequency step constant is selected. This execution path consists solely of pure combinational logic, avoiding the amplification of high-frequency noise by the multiplier. The system thus leverages the maximum hardware response speed to quickly traverse the phase nonlinearity saturation region, enhancing its dynamic tracking capabilities.

[0030] S4. When switching from the extreme oscillation mode to the linear closed-loop control mode, the integral state of the linear closed-loop controller's control signal is compensated and preloaded to ensure continuous control output before and after the switch. The linear closed-loop control mode includes: performing proportional-integral calculations based on the phase detection error to obtain the frequency adjustment amount; adjusting the atomic magnetometer drive frequency based on the frequency adjustment amount; and storing the integral calculation result in the integral accumulation register. During mode transition, a disturbance-free switching control law is adopted to eliminate the abrupt electrical jump at the moment of control handover. At the rising edge of the clock when switching from the extreme oscillation mode to the linear closed-loop control mode, the control output, current phase detection error, and phase change rate of the previous clock cycle are read. The compensation integral value is calculated based on the control output, current phase detection error, and phase change rate, and written to the integral accumulation register of the linear closed-loop controller. Specifically, at the rising edge of the single clock cycle when the state machine switches from the extreme oscillation mode back to the linear closed-loop control mode, because the PI controller was previously in a suspended state, its integral accumulation register has a historical state mismatch. Direct intervention would trigger a sudden change in the control signal, affecting the system state. Therefore, the FPGA triggers state compensation logic: using a single-step delay register to extract the phase change rate. The initial integral value is calculated by the arithmetic logic unit (ALU) and preloaded into the integral accumulator register of the PI controller. Its underlying preloading model is as follows: in, To preload integration values, To switch to the actual hard-wired control value of the previous step, The proportional gain of the linear PI controller. To switch the error phase of the current shot, This is a compensation factor calibrated based on the polarization moment resonant linewidth. This compensation mechanism ensures that the first output of the PI controller is strictly equal to the previous output in the switching state. This completely eliminates abrupt changes in the drive signal, preventing the system from leaving the resonant tracking state at the critical point and achieving smooth, continuous locking switching.

[0031] S5. Real-time monitoring of the demodulation amplitude. When the demodulation amplitude continuously falls below a preset amplitude threshold, the system is determined to be in a unlocked state. Closed-loop feedback is disconnected, and a frequency sweep search is performed. Closed-loop locking is restored after the frequency corresponding to the maximum demodulation amplitude is detected. Step S5 specifically includes: preseting an amplitude threshold and a timeout count threshold within the FPGA. When the demodulation amplitude falls below the amplitude threshold, counting begins. When the continuous count value reaches the timeout count threshold, the system is determined to be in a unlocked state. After determining the system is in a unlocked state, the closed-loop feedback based on phase detection error is disconnected. The integral accumulator of the linear closed-loop controller is configured as a frequency sweep phase accumulator. A frequency sweep drive signal is output within a preset frequency range according to a preset frequency sweep step size. When the demodulation amplitude reaches the frequency point corresponding to the maximum amplitude, this frequency point is used as the closed-loop locking frequency. Figure 4 As shown, this embodiment addresses the lock-out problem caused by attitude changes and magnetic anomalies in practical application scenarios. This embodiment constructs a lock-out identification and autonomous reacquisition mechanism based on demodulation amplitude monitoring within the FPGA. A threshold for the amplitude decrease of the polarization moment resonance signal is preset within the FPGA. It also configures a clock-driven timeout debounce counter. During runtime, when continuous detection... When the time exceeds the preset polarization attenuation physical characteristic, the system identifies it as non-transient noise interference, indicating that the atomic polarization resonance state has been disrupted, leading to a real physical loss of lock. At this point, the system state machine ignores the current chaotic phase state and forcibly switches to the "autonomous recapture mode." In this mode, the system completely disconnects the closed-loop phase detection feedback on the data link and directly reuses the previously idle PI controller integrator accumulator as the sweep phase accumulator for the digital frequency synthesizer (DDS). The system outputs a digital waveform with a fixed step size. When the FPGA detects that the demodulation amplitude has reached its maximum value, it determines that the polarization moment resonance signal has been recaptured, and the state machine will perform closed-loop locking to its resonance frequency.

[0032] Specifically, such as Figure 1 and Figure 2 As shown, the FPGA is internally configured with a signal acquisition and processing unit, a modulation driving unit, a quadrature demodulation and digital phase detection unit, a multi-mode state machine decision unit, a multiplexing high-speed slewing unit, a disturbance-free switching closed-loop control unit, and a lockout monitoring and autonomous frequency sweeping unit. The FPGA, serving as the system's logic control core, connects to the host computer via a data communication interface to enable real-time transmission of low-level control parameters and system status feedback. The signal acquisition and processing unit is physically connected to the photoelectric detection circuit of the atomic magnetometer probe and the FPGA's data input terminal. Since the photoelectric detection circuit outputs a weak current signal characterizing the atomic optical rotation effect, the signal acquisition and processing unit includes a low-noise transimpedance amplifier and a high-speed analog-to-digital converter to convert the weak current signal into a voltage signal. It also acquires and detects the optical rotation signal in real-time according to the system sampling clock, converting it into a discrete digital input to the FPGA. The modulation drive unit is physically connected to the FPGA's data output terminal and an external electro-optic modulator. It includes a high-speed digital-to-analog converter to convert the digital sine wave generated by the FPGA's internal digital frequency synthesizer into an analog radio frequency drive signal, thereby driving the EOM to perform controllable amplitude modulation of the laser.

[0033] The quadrature demodulation and digital phase detection unit is connected to the output stream of the signal acquisition and processing unit. It is used within the FPGA to call the CORDIC algorithm IP core to construct a deep pipeline structure, calculating the current phase detection error and demodulation amplitude. The multi-mode state machine decision unit is connected to the quadrature demodulation and digital phase detection unit, used for real-time single-clock-cycle decision-making and switching control of the working mode based on a preset dual threshold system. The multiplexed high-speed slew rate unit, as the actuator to avoid phase nonlinear saturation under large errors, directly outputs the maximum hardware slew rate. The disturbance-free switching closed-loop control unit, as the steady-state actuator under small errors, is used to achieve high-precision, low-noise locking of the atomic magnetometer. The lock-out monitoring and autonomous frequency sweep unit monitors the demodulation amplitude and phase, controlling the frequency output after system lock-out. Through centralized management of the FPGA's internal global clock, a complete high-performance digital lock-in amplifier is constructed. Specifically, from the high-speed sampling input of the ADC, the mixing and low-pass filtering of the input signal, to the extraction of phase and amplitude features of the CORDIC algorithm, to the state machine decision-making and execution of the multi-mode control law, the digital waveform is finally synthesized by the DDS and output by the DAC, forming a digital control loop.

[0034] The quadrature demodulation and digital phase detector unit extracts the signal characteristics of the NMOR atomic magnetometer. The digital lock-in amplifier first performs digital multiplication and mixing of the digital signal with magnetic field information acquired by the ADC and the reference sine and cosine signals generated by the DDS. Then, it passes through filters for decimation and low-pass filtering to obtain high signal-to-noise ratio in-phase and quadrature components. Subsequently, within the FPGA, the CORDIC algorithm IP core based on displacement and addition operations is invoked to perform iterative coordinate rotation calculations on the extracted in-phase and quadrature components.

[0035] The multimodal state machine decision unit reads the phase detection error in real time and determines the working mode based on a preset error threshold. The unlock monitoring and autonomous frequency sweep unit reads the demodulation amplitude in real time and determines whether the system is in an unlocked state based on the demodulation amplitude. The output of the multimodal state machine decision unit is connected to the multiplexed high-speed slewing unit, the disturbance-free switching closed-loop control unit, and the unlock monitoring and autonomous frequency sweep unit, respectively. When the multimodal state machine decision unit determines that the system is in the extreme slewing mode, it controls the multiplexed high-speed slewing unit to work; when the multimodal state machine decision unit determines that the system is in the linear closed-loop control mode, it controls the disturbance-free switching closed-loop control unit to work; when the multimodal state machine decision unit determines that the system is in the autonomous reacquisition mode, it controls the unlock monitoring and autonomous frequency sweep unit to work. The system comprises three main components: a multiplexed high-speed slewing unit, which outputs a modulation frequency step constant corresponding to the phase detection error polarity; a disturbanceless switching closed-loop control unit, which performs proportional-integral calculations based on the phase detection error and compensates for the integral state during mode switching; and a loss-of-lock monitoring and autonomous frequency sweeping unit, which identifies the loss-of-lock state based on the demodulation amplitude and outputs a frequency sweeping drive signal in the loss-of-lock state. The outputs of the multiplexed high-speed slewing unit, the disturbanceless switching closed-loop control unit, and the loss-of-lock monitoring and autonomous frequency sweeping unit are all connected to a drive frequency control unit. This drive frequency control unit is connected to a digital frequency synthesizer to control the digital frequency synthesizer to output an RF drive signal of the corresponding frequency.

[0036] It should be noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the exemplary embodiments according to this application. As used herein, the singular form is intended to include the plural form as well, unless the context clearly indicates otherwise. Furthermore, it should be understood that when the terms "comprising" and / or "including" are used in this specification, they indicate the presence of features, steps, operations, devices, components, and / or combinations thereof.

[0037] It should be noted that the terms "first," "second," etc., used in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented in sequences other than those illustrated or described herein.

[0038] The present invention has been further described above with reference to specific embodiments. However, it should be understood that the specific description herein should not be construed as limiting the nature and scope of the present invention. Various modifications made to the above embodiments by those skilled in the art after reading this specification are all within the scope of protection of the present invention.

Claims

1. A multi-mode closed-loop locking method for NMOR atomic magnetometer resonance signals based on FPGA, characterized in that, The method includes: S1. Acquire the optical rotation detection signal from the NMOR atomic magnetometer, and perform orthogonal demodulation and digital phase detection processing on the optical rotation detection signal to obtain the phase detection error and demodulation amplitude. S2. Based on the phase detection error, determine the working mode. When the phase detection error exceeds the preset upper limit threshold, switch to the extreme slewing mode. When the phase detection error is lower than the preset lower limit threshold, switch to the linear closed-loop control mode. Maintain the current working mode unchanged between the upper limit threshold and the lower limit threshold. S3. Under the extreme slewing mode, output the gating maximum modulation frequency step constant in the corresponding direction according to the polarity of the phase detection error; S4. When switching from the extreme pressure swing mode to the linear closed-loop control mode, the integral state of the linear closed-loop controller control signal is compensated and preloaded to make the control output before and after the switch continuous. S5. Monitor the demodulation amplitude in real time. When the demodulation amplitude is continuously lower than the preset amplitude threshold, determine that the system is in a unlocked state, disconnect the closed-loop feedback and perform a frequency sweep search. After detecting the frequency corresponding to the maximum value of the demodulation amplitude, restore the closed-loop lock.

2. The FPGA-based multi-mode closed-loop locking method for NMOR atomic magnetometer resonance signals according to claim 1, characterized in that, Step S1 includes: S11. Convert the current signal output by the photoelectric detection circuit into a voltage signal, perform analog-to-digital conversion on the voltage signal, and obtain the digital sampling signal corresponding to the optical rotation detection signal.

3. The FPGA-based multi-mode closed-loop locking method for NMOR atomic magnetometer resonance signals according to claim 2, characterized in that, Step S1 further includes: S12. The digital sampling signal is digitally mixed with the reference sine signal and the reference cosine signal respectively, and the digitally mixed signal is low-pass filtered to obtain the in-phase component and the quadrature component. S13. Calculate the phase detection error and the demodulation amplitude based on the in-phase component and the quadrature component.

4. The FPGA-based multi-mode closed-loop locking method for NMOR atomic magnetometer resonance signals according to claim 1, characterized in that, Step S2 includes: presetting a first error threshold and a second error threshold in the FPGA internal register, wherein the first error threshold is greater than the second error threshold; when the absolute value of the phase detection error is greater than the first error threshold, switching the operating mode to the extreme slew mode; when the absolute value of the phase detection error is less than the second error threshold, switching the operating mode to the linear closed-loop control mode; and when the absolute value of the phase detection error is between the first error threshold and the second error threshold, maintaining the operating mode of the previous clock cycle.

5. The FPGA-based multi-mode closed-loop locking method for NMOR atomic magnetometer resonance signals according to claim 1, characterized in that, Step S3 includes: under the extreme slewing mode, suspending the linear closed-loop controller, extracting the sign bit of the phase detection error, selecting one of the maximum positive modulation frequency step constant and the maximum negative modulation frequency step constant according to the sign bit, and superimposing the selected modulation frequency step constant onto the current driving frequency.

6. The FPGA-based multi-mode closed-loop locking method for NMOR atomic magnetometer resonance signals according to claim 1, characterized in that, The linear closed-loop control mode includes: performing proportional-integral calculations based on the phase detection error to obtain a frequency adjustment amount, adjusting the driving frequency of the atomic magnetometer based on the frequency adjustment amount, and storing the integral calculation result in an integral accumulator register.

7. The FPGA-based multi-mode closed-loop locking method for NMOR atomic magnetometer resonance signals according to claim 1, characterized in that, Step S4 includes: at the rising edge of the clock when the extreme slewing mode switches to the linear closed-loop control mode, reading the control output, current phase detection error and phase change rate of the previous clock cycle before the switch, calculating the compensation integral value based on the control output, the current phase detection error and the phase change rate, and writing the compensation integral value into the integral accumulation register of the linear closed-loop controller.

8. The FPGA-based multi-mode closed-loop locking method for NMOR atomic magnetometer resonance signals according to claim 1, characterized in that, Step S5 includes: setting an amplitude threshold and a timeout count threshold inside the FPGA; starting a count when the demodulation amplitude is lower than the amplitude threshold; and determining that the system is in the unlocked state when the continuous count value reaches the timeout count threshold.

9. The FPGA-based multi-mode closed-loop locking method for NMOR atomic magnetometer resonance signals according to claim 8, characterized in that, Step S5 includes: after determining that the system is in the unlocked state, disconnecting the closed-loop feedback based on the phase detection error, configuring the integral accumulator of the linear closed-loop controller as a sweep frequency phase accumulator, outputting a sweep frequency drive signal within a preset frequency range according to a preset sweep frequency step size, and using the frequency point corresponding to the maximum amplitude value when the demodulation amplitude reaches the frequency point corresponding to the maximum amplitude value as the closed-loop locking frequency.

10. The FPGA-based multi-mode closed-loop locking method for NMOR atomic magnetometer resonance signals according to claim 1, characterized in that, The FPGA is internally configured with an orthogonal demodulation and digital phase detection unit, a multimodal state machine decision unit, a multiplexed high-speed slewing unit, a disturbance-free switching closed-loop control unit, and a lockout monitoring and autonomous frequency sweeping unit. The input terminal of the quadrature demodulation and digital phase detection unit is connected to the digital sampling signal input terminal. The quadrature demodulation and digital phase detection unit is used to perform quadrature demodulation and digital phase detection processing on the digital sampling signal, and outputs the error phase and demodulation amplitude to the multimodal state machine decision unit. The output terminal of the quadrature demodulation and digital phase detection unit is also connected to the lock-out monitoring and autonomous frequency sweeping unit. The multimodal state machine decision unit is used to make working mode decisions based on the error phase. The output of the multimodal state machine decision unit is connected to the multiplexed high-speed slewing unit, the disturbance-free switching closed-loop control unit, and the lock-out monitoring and autonomous frequency sweeping unit, respectively, and controls the working state of the multiplexed high-speed slewing unit, the disturbance-free switching closed-loop control unit, and the lock-out monitoring and autonomous frequency sweeping unit, respectively. The outputs of both the multiplexed high-speed slewing unit and the disturbance-free switching closed-loop control unit are connected to the drive frequency control terminal. The unlock monitoring and autonomous frequency sweeping unit is used to determine whether the system is in an unlocked state based on the demodulation amplitude. The output terminal of the unlock monitoring and autonomous frequency sweeping unit is connected to the drive frequency control terminal, and outputs a frequency sweeping drive signal in the unlocked state.

Images