Array substrate, display panel and LCD projector

Abstract

This disclosure provides an array substrate, a display panel, and a liquid crystal projector, belonging to the field of display technology. The array substrate includes: a substrate, one side of which includes multiple data lines and multiple gate lines, the data lines and gate lines intersecting to define multiple sub-pixel regions, each sub-pixel region including a first electrode layer; a second electrode layer located on the side of the first electrode layer away from the substrate, the second electrode layer including multiple electrode strips arranged parallel to each other and spaced apart; and an alignment layer located on the side of the second electrode layer away from the substrate, the anchoring direction of the alignment layer not orthogonally intersecting the extension direction of the electrode strips; wherein the extension direction of the data lines is parallel to the anchoring direction, and / or the film layer between the alignment layer and the data lines has a flat surface at the data lines, the surface being the surface away from the substrate.

Description

Technical Field

[0001] This disclosure relates to the field of display technology, and in particular to an array substrate, a display panel, and a liquid crystal projector. Background Technology

[0002] A TFT-LCD (Thin Film Transistor Liquid Crystal Display) comprises two substrates arranged opposite each other, and liquid crystal located between the two substrates. The liquid crystal includes positive liquid crystal and negative liquid crystal. For displays with positive liquid crystal, vertical lines may appear as poor image quality under L0 screen conditions; for example, this manifests as bright lines with light leakage at the pixel edges under a microscope.

[0003] Among them, L0 screen is black screen, which specifically refers to the screen when the grayscale value of each sub-pixel in the display panel is 0. Summary of the Invention

[0004] Based on the background art, this disclosure proposes an array substrate, a display panel, and a liquid crystal projector.

[0005] A first aspect of this disclosure provides an array substrate, comprising:

[0006] A substrate, one side of which includes multiple data lines and multiple gate lines, the data lines and the gate lines intersecting to define multiple sub-pixel regions, the sub-pixel regions including:

[0007] First electrode layer;

[0008] The second electrode layer is located on the side of the first electrode layer away from the substrate, and the second electrode layer includes a plurality of electrode strips that are parallel to each other and spaced apart.

[0009] An alignment layer is located on the side of the second electrode layer away from the substrate, and the anchoring direction of the alignment layer is not orthogonal to the extension direction of the electrode strip;

[0010] Wherein, the extension direction of the data line is parallel to the anchoring direction, and / or the film layer between the alignment layer and the data line has a flat surface at the data line, the surface being the surface facing away from the substrate.

[0011] For example, the extension direction of the data line is parallel to the anchoring direction, and the intersection angle between the electrode strip and the data line is 5° to 10°.

[0012] For example, multiple sub-pixel regions are arranged along a row and column array, and the extension direction of the data line is parallel to the anchoring direction;

[0013] Wherein, the electrode strip is orthogonal to the row direction; or, the data line is orthogonal to the row direction.

[0014] For example, the data line extends in a direction parallel to the anchoring direction;

[0015] In one of the sub-pixel regions, multiple electrode strips extend in the same direction.

[0016] For example, the electrode strip includes multiple branch electrodes connected in series, with at least two branch electrodes not orthogonally intersecting.

[0017] For example, it includes at least a first sub-pixel region and a second sub-pixel region;

[0018] Wherein, the extension direction of the electrode strip in the first sub-pixel region and the extension direction of the electrode strip in the second sub-pixel region are not orthogonal.

[0019] For example, the data line extends in a direction parallel to the anchoring direction, and the data line includes multiple corners;

[0020] Wherein, the extension direction of the portion of the data line located outside the area where the multiple corners are located is parallel to the anchoring direction, and the multiple corners are arranged along the extension direction of the electrode strip.

[0021] For example, the corner includes a right-angle corner.

[0022] For example, the data line includes a first endpoint and a second endpoint located on the boundary of the sub-pixel region along the column direction, the line connecting the first endpoint and the second endpoint being parallel to the electrode strip, and a plurality of the corners being located between the first endpoint and the second endpoint.

[0023] For example, the data line is projected onto the substrate in a sawtooth pattern.

[0024] Exemplarily, the film layer between the alignment layer and the data line has a flat surface at the data line, and the array substrate further includes:

[0025] A passivation layer is located between the first electrode layer and the second electrode layer;

[0026] A first planarization layer is located on the side of the passivation layer closest to the substrate, and the data line is located between the passivation layer and the first planarization layer;

[0027] The first planarization layer includes a groove, the orthographic projection of the groove on the substrate covers the orthographic projection of the data line on the substrate, the data line is located in the groove, and the surface of the first portion facing away from the substrate is flush.

[0028] For example, the dimension of the groove in the thickness direction of the substrate is greater than or equal to the thickness of the data line.

[0029] Exemplarily, the film layer between the alignment layer and the data line has a flat surface at the data line, and the array substrate further includes:

[0030] A passivation layer is located on the side of the data line away from the substrate and is in direct contact with the data line;

[0031] The second planarization layer is located on the side of the passivation layer away from the substrate, and the orthographic projection of the second planarization layer on the substrate does not overlap with the orthographic projections of the first electrode layer and the second electrode layer on the substrate.

[0032] The surface of the second planarization layer opposite to the substrate is flush.

[0033] Exemplarily, the film layer between the alignment layer and the data line has a flat surface at the data line, and the array substrate further includes:

[0034] A passivation layer is located on the side of the data line away from the substrate, between the first electrode layer and the second electrode layer, and in direct contact with the data line;

[0035] Wherein, the thickness of the passivation layer in the first region is less than the thickness of the passivation layer in the second region, the orthographic projection of the first region on the substrate covers the orthographic projection of the data line on the substrate, and the orthographic projection of the second region on the substrate does not overlap with the orthographic projection of the data line on the substrate.

[0036] A second aspect of this disclosure provides a display panel including a first substrate, a second substrate, and a liquid crystal layer located between the first substrate and the second substrate, wherein the first substrate is configured as an array substrate as described in any of the first aspects.

[0037] Wherein, the initial alignment of the liquid crystal in the liquid crystal layer is parallel to the data lines on the first substrate, and the data lines do not orthogonally intersect with the electrode strips on the first substrate;

[0038] Alternatively, the data line is parallel to the electrode strip, and the initial alignment is not orthogonal to either the data line or the electrode strip.

[0039] A third aspect of this disclosure provides a liquid crystal projector, comprising an array substrate as described in any of the first aspects, or comprising a display panel as described in the second aspect.

[0040] The array substrate provided in this embodiment includes a substrate and an alignment layer. One side of the substrate includes multiple data lines and multiple gate lines. The data lines and gate lines intersect to define multiple sub-pixel regions. Each sub-pixel region includes a first electrode layer and a second electrode layer located on the side of the first electrode layer away from the substrate. The second electrode layer includes multiple electrode strips. The alignment layer is located on the side of the insulating structure layer away from the substrate. The extension direction of the electrode strips is not orthogonal to the anchoring direction of the alignment layer. The extension direction of the data lines is parallel to the anchoring direction, and / or the film layer between the alignment layer and the data lines has a flat surface at the data lines.

[0041] On the one hand, since the extension direction of the electrode strip is not orthogonal to the anchoring direction of the alignment layer, and the extension direction of the data line is parallel to the anchoring direction, under the condition that the electric field direction is different from the initial orientation of the liquid crystal to drive the liquid crystal to deflect normally, since the data line is parallel to the anchoring direction, the initial orientation of the liquid crystal at the data line can be consistent with the initial orientation of the liquid crystal in the sub-pixel area. This makes the arrangement of the liquid crystal at the edge of the sub-pixel area and inside the sub-pixel area consistent. In this way, the problem of disordered arrangement of the liquid crystal at the data line caused by the slope of the insulating structure layer at the data line is avoided, thereby avoiding the light leakage bright lines generated at the pixel edge.

[0042] On the other hand, since the film layer between the alignment layer and the data line has a flat surface at the data line, the flatness of the film layer at the data line can be improved. This reduces the impact of poor flatness of the insulating structure layer near the data line on the alignment layer's alignment of the liquid crystal. This ensures the anchoring effect of the alignment layer near the data line on the liquid crystal, making the alignment of the liquid crystal near the data line and the liquid crystal in the sub-pixel area (such as the liquid crystal at the electrode strip) consistent after alignment. This also avoids the problem of disordered liquid crystal arrangement at the data line caused by the excessively steep slope of the insulating structure layer at the data line, and improves the light leakage phenomenon generated at the pixel edge.

[0043] The above description is merely an overview of the technical solution disclosed herein. In order to better understand the technical means of this disclosure and to implement it in accordance with the contents of the specification, and to make the above and other objects, features and advantages of this disclosure more apparent and understandable, specific embodiments of this disclosure are described below. Attached Figure Description

[0044] To more clearly illustrate the technical solutions in the embodiments or related technologies of this disclosure, the accompanying drawings used in the description of the embodiments or related technologies will be briefly introduced below. Obviously, the accompanying drawings described below are some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort. It should be noted that the scale in the drawings is for illustration only and does not represent the actual scale.

[0045] Figure 1 A comparison image of the edge film layers of data cables made of different materials is shown;

[0046] Figure 2 This diagram illustrates the liquid crystal molecule arrangement at the edge of the data line DL in L0 mode.

[0047] Figure 3 A schematic diagram illustrating the liquid crystal arrangement and light leakage principle is shown.

[0048] Figure 4 A schematic diagram of vertical stripe defects in the L0 screen is shown;

[0049] Figures 5A-5C Cross-sectional structural schematic diagrams of the array substrate in the embodiments of this disclosure are shown respectively;

[0050] Figure 6 , Figure 8 , Figure 10 , Figure 11 , Figure 12 and Figure 13 Two planar schematic diagrams of the data line, electrode strip, and liquid crystal are shown respectively;

[0051] Figure 7 , Figure 9 and Figure 15 Planar schematic diagrams of local areas of several array substrates are shown respectively;

[0052] Figure 14 , Figure 16 and Figure 17 Several cross-sectional schematic diagrams of the first part are shown respectively;

[0053] Figure 18 A cross-sectional structural diagram of the display panel in an embodiment of this disclosure is shown. Detailed Implementation

[0054] To make the above-mentioned objectives, features, and advantages of this disclosure more apparent and understandable, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. Based on the embodiments of this disclosure, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure.

[0055] In this specification, "electrical connection" and "coupling" include situations where components are connected together by elements that have some electrical function. There are no particular limitations on what constitutes an "electrical function," as long as it allows for the transmission and reception of electrical signals between the connected components. Examples of "electrical functions" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with various functions.

[0056] In this specification, "parallel" refers to the state where the angle formed by two straight lines is greater than or equal to -10° and less than 10°, and therefore also includes the state where the angle is greater than or equal to -5° and less than 5°. Similarly, "perpendicular" refers to the state where the angle formed by two straight lines is greater than or equal to 80° and less than 100°, and therefore also includes the state where the angle is greater than or equal to 85° and less than 95°.

[0057] Unless the context otherwise requires, throughout the specification and claims, the term "comprising" is interpreted as open and encompassing, that is, "including, but not limited to".

[0058] In this application, "same layer" refers to the relationship between multiple film layers formed from the same material after undergoing the same step (e.g., a patterning process). "Same layer" here does not always mean that multiple film layers have the same thickness or the same height in a cross-sectional view. The polygons used in this specification are not strictly defined; they can be approximate triangles, parallelograms, trapezoids, pentagons, or hexagons, and may have minor deformations due to tolerances.

[0059] In the embodiments of this application, since the source and drain of the transistor are symmetrical, their source and drain can be interchanged. In the embodiments of this application, one of the source and drain of the transistor can also be called the first electrode, and the other of the source and drain can be called the second electrode.

[0060] In related technologies, liquid crystal displays may include HADS (High Advanced Super Dimension Switch) products. In HADS products, both pixel electrodes and common electrodes are located on the array substrate. These products form a multidimensional electric field through the electric field generated at the edges of the electrodes in the same plane and the electric field generated between the electrode layers and the plate-like electrode layers, causing all liquid crystal molecules between and directly above the electrodes to rotate. The plate-like electrode layers can be either pixel electrodes or common electrodes.

[0061] In HADS products, the aperture size of subpixels is generally related to the product's resolution. For display panels of the same size, the higher the resolution, the smaller the aperture. In high-resolution HADS products, due to the smaller subpixel aperture, the overlap area between the pixel electrode and the common electrode is smaller, resulting in a lower storage capacitance (Cst) between the pixel electrode and the common electrode. To improve Cst, the vertical distance between the pixel electrode and the common electrode in the thickness direction is typically reduced. For example, the thickness of the passivation layer between the pixel electrode and the common electrode is reduced, for instance, to [amount missing]. This thickness of passivation layer cannot protect the data line located underneath it, so it is paired with a pure Mo (molybdenum) data line with higher hardness to prevent the data line from being scratched.

[0062] Reference Figure 1 As shown, Figure 1 The image shows a comparison of the edge film layers of data cables made of different materials. Figure 1 These are scanning electron microscope (SEM) images. Figure 1 In section (1), the edge film of the pure Mo (molybdenum) data line is shown. Figure 1 (2) is the edge film layer of a pure Al (aluminum) data line. Because the slope angle of a pure Mo data line is relatively high (generally ≥90°), the slope angle of an Al data line is about 60°. Therefore, the low-thickness passivation layer paired with a pure Mo data line cannot effectively smooth the surface. Compared to... Figure 1 (2) In the 100 region, such as Figure 1 (1) The flatness of the film layer in the 100 region (the edge of the data line) is extremely poor.

[0063] Because the film flatness at the edge of the data line is extremely poor, this region affects the liquid crystal alignment during liquid crystal alignment. This is particularly true for the alignment of positive liquid crystals, as shown in the reference [reference needed]. Figure 2 As shown, Figure 2 This diagram illustrates the liquid crystal molecule arrangement at the edge of the data line DL in the L0 screen, as shown below. Figure 2 As shown, the alignment direction OA of the positive liquid crystal forms a 5° angle with the data line DL direction. Due to the poor flatness of the film layer near the data line DL, its force on the liquid crystal molecules exceeds the anchoring effect of the alignment layer on the liquid crystal orientation, causing the liquid crystal axes near the data line to tend to align parallel to the data line direction, such as... Figure 2 As shown, the LCD axis near the data line is parallel to the data line.

[0064] Reference Figure 3 As shown, Figure 3 A schematic diagram illustrating the liquid crystal arrangement and light leakage principle is shown, such as... Figure 3 As shown in (1), if the aligned liquid crystal molecules are parallel or perpendicular to the absorption axis of the upper polarizer POL or the lower polarizer POL, no light leakage occurs; Figure 3As shown in (2), if the liquid crystal molecules rotate in-plane relative to the orientation direction and are no longer parallel or perpendicular to the absorption axis of the upper polarizer POL or the lower polarizer POL, light leakage will occur.

[0065] Thus, if the liquid crystal axis near the data line is parallel to the data line, the orientation of the liquid crystal molecules at this location is not parallel or perpendicular to the absorption axis of the upper or lower polarizer, resulting in light leakage. (Refer to...) Figure 4 As shown, Figure 4 This shows a schematic diagram of vertical stripe defects on the L0 screen, such as... Figure 4 As shown in (1), the macroscopic manifestation is a vertical stripe phenomenon, such as Figure 4 As shown in (2), the microscopic manifestation is a bright line at the edge of the sub-pixel.

[0066] With the widespread application of LCD products, there is a demand for fast-response gaming projectors. Positive liquid crystals, due to their wider operating temperature range and faster response time, have been used in LCD projectors. The conditions for the occurrence of the vertical stripe defect in the L0 image mentioned above happen to match the conditions of LCD projector products, such as high-resolution HADS LCD products. What's worse, this vertical stripe defect will be further amplified after projection.

[0067] In view of this, the inventors of this disclosure propose a solution to solve the vertical stripe defect in high-resolution HADS liquid crystal display products. This solution mainly improves the vertical stripe defect in L0 images by improving the structure of the array substrate.

[0068] Its main concept is as follows:

[0069] 1. Reduce the force of the film layer near the data line on the liquid crystal molecules, making it lower than the anchoring effect of the alignment layer on the liquid crystal. This allows the liquid crystal in the sub-pixel area and near the data line (edge ​​of the sub-pixel area) to be uniformly aligned under the action of the alignment layer. In this way, the liquid crystal axis near the data line is also parallel or perpendicular to the absorption axis of the upper or lower polarizer.

[0070] 2. Change the relationship between the data line and the strip electrode so that the orientation of the liquid crystal in the sub-pixel area and the liquid crystal near the data line both follow the extension direction of the data line. That is, the orientation of the liquid crystal in the sub-pixel area is parallel to the data line, and the orientation of the liquid crystal near the data line is also parallel to the data line. This makes the liquid crystal in the sub-pixel area and near the data line (the edge of the sub-pixel area) have a consistent orientation. In this case, the absorption axis of the upper or lower polarizer can be designed to be parallel or perpendicular to the liquid crystal axis, thereby improving the vertical stripe defect of the L0 screen.

[0071] 3. The combination of the above-mentioned ideas 1 and 2.

[0072] The array substrate, display panel, and liquid crystal projector proposed in the embodiments of this disclosure will now be described by way of example with reference to the accompanying drawings.

[0073] Please refer to Figures 5A-5B As shown, Figure 5A and Figure 5B The cross-sectional structural schematic diagrams of the array substrate in the embodiments of this disclosure are shown respectively, as follows: Figures 5A-5B As shown, the array substrate may include:

[0074] Substrate 11, one side of substrate 11 includes multiple data lines 19 and multiple gate lines, the data lines 19 and gate lines intersecting to define multiple sub-pixel regions; wherein, the sub-pixel regions include:

[0075] First electrode layer 17;

[0076] The second electrode layer 16 is located on the side of the first electrode layer 17 away from the substrate 11. The second electrode layer 16 includes a plurality of electrode strips 161 arranged parallel to each other and spaced apart.

[0077] Alignment layer 15 is located on the side of the second electrode layer 16 away from the substrate 11, and the anchoring direction OA of alignment layer 15 does not intersect the extension direction of electrode strip 161.

[0078] Wherein, the extension direction of the data line 19 is parallel to the anchoring direction OA, and / or the film between the alignment layer 15 and the data line 19 has a flat surface at the data line 19, which is the surface of the film between the alignment layer 15 and the data line 19 facing away from the substrate 11.

[0079] The array substrate of this embodiment can be applied to HADS or ADS type liquid crystal 21 display panels. The substrate 11 can be a glass substrate 11 or other substrates 11, such as a rigid substrate 11.

[0080] On one side of the substrate 11, there may be multiple data lines and multiple gate lines. The multiple data lines 19 and the multiple gate lines intersect to define multiple sub-pixel regions. Each sub-pixel region includes a pixel driving circuit, a pixel electrode connected to the pixel driving circuit, and a common electrode. The pixel driving circuit may include a thin-film transistor. The source of the thin-film transistor is connected to the data line 19, and the drain of the thin-film transistor is connected to the pixel electrode.

[0081] like Figure 5A and Figure 5BAs shown, the thin-film transistor includes a gate 182 located on one side of a substrate 11, an active layer 183 located on the side of the gate 182 facing away from the substrate 11, a source electrode 184 and a drain electrode 181 located on the side of the active layer 183 facing away from the substrate 11. The source electrode 184 and the drain electrode 181 are located in the non-channel region of the active layer 183, and the channel region of the active layer 183 overlaps with the orthographic projection of the gate 182 on the substrate 11. A gate insulating layer 12 is also included between the gate 182 and the active layer 183, and a planarization layer is included on the side of the source electrode 184 and the drain electrode 181 facing away from the substrate 11.

[0082] like Figure 5A and Figure 5B As shown, the sub-pixel region includes a first electrode layer 17 and a second electrode layer 16 located on the side of the first electrode layer 17 facing away from the substrate 11. An insulating structure layer is disposed between the first electrode layer 17 and the second electrode layer 16, such as... Figure 5A As shown, the insulating structure layer can be the film layer 14 between the first electrode layer 17 and the second electrode layer 16.

[0083] The data line 19 and the first electrode layer 17 can be arranged in the same layer, which means that the first electrode layer 17 and the data line 19 are formed in the same process.

[0084] In some examples, such as Figure 5A As shown, the first electrode layer 17 can be a pixel electrode, and the second electrode layer 16 can be a common electrode; or, in some other examples, such as Figure 5B As shown, the first electrode layer 17 can be a common electrode, and the second electrode layer 16 can be a pixel electrode. In this embodiment, the second electrode layer 16 may include multiple electrode strips 161, and the first electrode layer 17 may be referred to as a plate electrode.

[0085] like Figure 5A and Figure 5B As shown, the orthographic projections of the first electrode layer 17 and the second electrode layer 16 on the substrate 11 overlap. For example, the orthographic projection of the first electrode layer 17 on the substrate 11 can cover the orthographic projection of the second electrode layer 16 on the substrate 11, or the outer contour of the orthographic projection of the first electrode layer 17 on the substrate 11 intersects with the outer contour of the orthographic projection of the second electrode layer 16 on the substrate 11.

[0086] The insulating structure layer may include a single film layer or multiple film layers stacked in the thickness direction of the substrate 11. For example, the insulating structure layer may include an organic film layer, an inorganic film layer, or a film layer consisting of stacked organic and inorganic film layers.

[0087] The organic film layer is formed using organic materials, while the inorganic film layer is formed using inorganic materials.

[0088] The insulating structure layer may include a second portion F2 located in the sub-pixel region and a first portion F1 located between the sub-pixel regions. Specifically, as shown... Figure 5A and Figure 5B As shown, the orthographic projection of the insulating structure layer on the substrate 11 can cover the sub-pixel area and the orthographic projection of the data line 19 on the substrate 11. Specifically, the orthographic projection of the first part F1 on the substrate 11 covers the orthographic projection of the data line 19 on the substrate 11, and the orthographic projection of the second part F2 on the substrate 11 can cover the orthographic projection of the sub-pixel area on the substrate 11.

[0089] The first part F1 and the second part F2 may have the same film structure, for example, including the same film layer, or the first part F1 and the second part F2 may have different film structures, for example, including different numbers of film layers stacked in the thickness direction of the substrate 11.

[0090] Specifically, the orthographic projection of data line 19 on substrate 11 does not overlap with the orthographic projections of the first electrode layer 17 and the second electrode layer 16 on substrate 11. Figure 7 As shown, Figure 7 A planar schematic diagram of a portion of the array substrate is shown, such as... Figure 7 As shown, since the data line 19 and the gate line define the sub-pixel area, the data line 19 can be located at the edge of the sub-pixel area. Therefore, the first part F1 can be understood as the portion of the insulating structure layer between the sub-pixel areas.

[0091] like Figure 5A and Figure 5B As shown, the second electrode layer 16 includes an alignment layer 15 on the side opposite to the substrate 11. The alignment layer 15 can be an alignment film formed by using alignment technology, such as friction rollers to form PI (polyimide precursor solution) liquid on the outermost surface of the array substrate. It is used to pre-align the liquid crystal 21 that is subsequently injected. That is, the molecular orientation of the liquid crystal 21 fluid at the surface of the array substrate is defined by the alignment layer 15.

[0092] In this embodiment, the anchoring direction OA of the alignment layer 15 can refer to the orientation direction of the alignment layer 15 relative to the long axis of the liquid crystal 21. The liquid crystal 21 can be a positive liquid crystal 21. The anchoring direction OA can be non-orthogonal to the extension direction of the electrode strip 161. This makes the initial orientation direction of the liquid crystal 21 molecules non-perpendicular to the electric field direction between the electrode strip 161, thereby allowing the liquid crystal 21 molecules to be normally driven to rotate in the same direction.

[0093] In this embodiment, the anchoring direction OA of the alignment layer 15 may be parallel to the extension direction of the data line 19; or, the film layer between the alignment layer 15 and the data line 19 has a flat surface at the data line 19; or, the film layer between the alignment layer 15 and the data line 19 has a flat surface at the data line 19, and the anchoring direction OA of the alignment layer 15 may be parallel to the extension direction of the data line 19.

[0094] The fact that the film layer between the alignment layer 15 and the data line 19 has a flat surface at the data line 19 can mean that the first part F1 in the insulating structure layer is flat at the data line 19, such as the surface of the first part F1 facing away from the substrate 11 being flat. For example, the insulating structure layer in the sub-pixel area and the insulating structure layer between the sub-pixel areas are flush and there is no step difference. This allows the alignment layer 15 to be flat on the bottom surface near the substrate 11, thereby reducing the impact of poor film layer flatness on the alignment of the alignment layer 15 with the liquid crystal 21.

[0095] like Figure 6 and Figure 7 As shown, Figure 6 A plan view of the data line 19, electrode strip 161, and liquid crystal 21 is shown, as follows. Figure 6 and Figure 7 As shown, the anchoring direction OA of the alignment layer 15 is parallel to the extension direction of the data line 19, that is, the orientation of the subsequent liquid crystal molecules is parallel to the extension direction of the data line 19. The extension direction of the electrode strip 161 is not orthogonal to the data line 19, and is not orthogonal to the anchoring direction OA of the alignment layer 15.

[0096] When the anchoring direction OA of the alignment layer 15 is parallel to the data line 19, the orientation of the liquid crystal 21 in the sub-pixel area, such as the liquid crystal 21 on the second electrode layer 16, is also parallel to the data line 19. This makes the orientation of the liquid crystal 21 near the data line 19 consistent with the orientation of the liquid crystal 21 in the sub-pixel area. In this case, even if the flatness of the insulating structure layer near the data line 19 is poor and the orientation of the liquid crystal 21 is parallel to the data line 19 at this point, the orientation of the entire display panel is consistent because the orientation of the liquid crystal 21 on the second electrode layer 16 is also parallel to the data line 19. Therefore, there will be no bright lines at the edge of the data line 19 in the dark state, thereby improving the vertical stripe defect of the L0 screen.

[0097] like Figure 5A and Figure 5BAs shown, the film layer between the alignment layer 15 and the data line 19 has a flat surface at the data line 19. For example, the surface of the first part F1 facing away from the substrate 11 is flush. This results in a high flatness of the film layer at the data line 19, so that the poor flatness of the film layer will not exert a greater force on the liquid crystal 21 molecules than the anchoring effect of the alignment layer 15. This makes the anchoring effect of the alignment layer 15 on the liquid crystal 21 at this location approximately the same as the anchoring effect on the liquid crystal 21 in the sub-pixel area. This ensures that the orientation of the liquid crystal 21 on the second electrode layer 16 is consistent with the orientation near the data line 19. As a result, the orientation of the entire display panel is consistent, and there are no bright lines at the edge of the data line 19 in the dark.

[0098] In some examples, the anchoring direction OA of the alignment layer 15 can be parallel to the extension direction of the data line 19, and the first part F1 is flat at the data line 19. This further avoids the problem of bright lines at the edge of the data line 19 in the dark.

[0099] The exemplary embodiment in which the extension direction of the data line 19 is parallel to the anchoring direction OA will be described below.

[0100] In some embodiments, the array substrate may be directed to a positive liquid crystal 21, wherein the cross angle θ between the electrode strip 161 and the data line 19 may be 5° to 10°.

[0101] In this embodiment, as Figure 6 As shown, the extension direction of the data line 19 on the array substrate is the initial alignment of the liquid crystal 21, which is also the anchoring direction OA of the alignment layer 15. Since it is a positive liquid crystal 21, the alignment of the positive liquid crystal 21 is generally perpendicular to the vertical alignment, for example, perpendicular to the row alignment direction x of the sub-pixel area on the array substrate. Thus, when the data line 19 is parallel to the anchoring direction OA of the alignment layer 15, the angle θ between the data line 19 and the electrode strip 161 can be 5° to 10°. Therefore, the angle between the alignment direction of the alignment layer 15 and the row alignment direction x of the sub-pixel area can be 80° to 90°.

[0102] For example, the included angle between the data line 19 and the electrode strip 161 can be 5°, and the orientation direction of the alignment layer 15 can be orthogonal to the row arrangement direction x of the sub-pixel area, or it can be 85°.

[0103] For example, the angle between the data line 19 and the electrode strip 161 can be 10°, and the orientation direction of the alignment layer 15 can be orthogonal to the row alignment direction x of the sub-pixel region, or it can be 80°.

[0104] As another example, the included angle between the data line 19 and the electrode strip 161 can be 7°, and the orientation direction of the alignment layer 15 can be orthogonal to the row alignment direction x of the sub-pixel region, or it can be 83°.

[0105] In some embodiments, such as Figure 7 As shown, multiple sub-pixel regions can be arranged along the row and column array. When the extension direction of the data line 19 is parallel to the anchoring direction OA, the electrode strip 161 can be orthogonal to the row direction x, and the data line 19 and the row direction x intersect obliquely; or, the data line 19 can be orthogonal to the row direction x, and the electrode strip 161 and the row direction x intersect obliquely.

[0106] Among them, oblique intersection refers to an intersection whose intersection angle is not 90° or 270°.

[0107] In one example, such as Figure 6 and Figure 7 As shown, data line 19 intersects obliquely with the row direction x, and multiple electrode strips 161 of the second electrode layer 16 are all orthogonal to the row direction x. The angle between data line 19 and electrode strips 161 is 5° to 10°. For example, it can be 5°, 6°, 7°, 8°, or 10°. In this case, the anchoring direction OA can intersect obliquely with both the row direction x and the column direction y.

[0108] In another example, such as Figure 8 and Figure 9 As shown, Figure 8 A planar schematic diagram of the electrode strip 161 is shown, illustrating the data within three sub-pixel regions. Figure 9 It shows Figure 8 Planar schematic diagrams of the array substrate in cases (1) and (2) are shown below. Figure 8 and Figure 9 As shown, data line 19 is orthogonal to the row direction x, and multiple electrode strips 161 of the second electrode layer 16 are obliquely intersecting the row direction x. The angle between data line 19 and electrode strips 161 remains 5° to 10°. For example, it can be 5°, 6°, 7°, 8°, or 10°. In this case, data line 19 can extend along the column direction y of the sub-pixel area, and the anchoring direction OA is perpendicular to the row arrangement direction x of the sub-pixel area.

[0109] In a further embodiment, multiple electrode strips 161 within a sub-pixel region may extend in the same direction, for example, as shown below. Figure 7 and Figure 9 As shown, each of the multiple electrode strips 161 in a sub-pixel region extends in one direction, thereby making the sub-pixel region a 1P1D pixel, i.e., a single-domain pixel design.

[0110] This implementation can be adapted to embodiments where the data line 19 is diagonally intersecting the row direction x, and embodiments where the data line 19 is orthogonal to the row direction x.

[0111] In a further embodiment, the plurality of electrode strips 161 within a sub-pixel region may have multiple extending directions, for example, such as Figure 8 As shown in (3), the electrode strip 161 may include multiple branch electrodes, which are connected in series to form the electrode strip 161, and at least two branch electrodes are non-orthogonal.

[0112] In this example, electrode strip 161 may include two or three connected branch electrodes in series, at least two of which are non-orthogonal, so that the branch electrodes in a sub-pixel region have at least two extending directions, thereby forming electric fields in multiple directions within the sub-pixel region and realizing a multi-domain pixel design.

[0113] For example, such as Figure 8 As shown in (3), the electrode strip 161 may include two branch electrodes, which are connected to each other and cross each other at an angle greater than 90°, for example, 120°.

[0114] This implementation can be adapted to embodiments where the data line 19 is orthogonal to the row direction x.

[0115] In some embodiments, the extension direction of the electrode strip 161 may be different in different sub-pixel regions. For example, as... Figure 9 As shown, the multiple sub-pixel regions include at least a first sub-pixel region and a second sub-pixel region;

[0116] The extension direction of the electrode strip 161 in the first sub-pixel region and the extension direction of the electrode strip 161 in the second sub-pixel region are not orthogonal.

[0117] In this embodiment, the first sub-pixel region can be a sub-pixel region adjacent to the second sub-pixel region, for example, such as Figure 9 As shown, the two can be adjacent sub-pixel regions in the column direction y. Alternatively, in some other examples, the first sub-pixel region and the second sub-pixel region can be adjacent sub-pixel regions in the row direction x. The electrode strips 161 in multiple sub-pixel regions located in the same column can be parallel, or the electrode strips 161 in sub-pixel regions located in the same row can be parallel.

[0118] In some other examples, multiple sub-pixel regions can be divided into multiple pixel units, each pixel unit including multiple adjacent sub-pixel regions. For example, it may include sub-pixel regions with green light emission, sub-pixel regions with blue light emission, and sub-pixel regions with red light emission. The electrode strips 161 within different sub-pixel regions of the same pixel unit are parallel, while the electrode strips 161 in different pixel units are not parallel.

[0119] In some other examples, the extension directions of the electrode strips 161 between any two adjacent sub-pixel regions can be non-orthogonal across the entire array substrate.

[0120] In some embodiments, such as Figure 9 As shown, the electrode strips 161 in the first and second sub-pixel regions can be symmetrical along the column direction y or the row direction x.

[0121] In some other embodiments, such as Figure 10 As shown, Figure 10 A planar schematic diagram of a single sub-pixel region is shown, such as... Figure 10 As shown, the second electrode layer 16 includes multiple spaced electrode regions, each electrode region including multiple electrode strips 161, with the electrode strips 161 intersecting between adjacent electrode regions. In this way, multiple electric fields in different directions can be formed within the same sub-pixel region. For example, as... Figure 10 As shown, it includes 4 electrode regions. In the two diagonal electrode regions, the electrode strip 161 in one electrode region is parallel to the electrode strip 161 in the other electrode region. In the two adjacent electrode regions not on the diagonal, the electrode strip 161 in one electrode region intersects with the electrode strip 161 in the other electrode region.

[0122] Among them, in two adjacent electrode regions that are not diagonal, the electrode strips 161 in one electrode region and the electrode strips 161 in the other electrode region can be arranged symmetrically along the row direction x.

[0123] It should be noted that in the multi-domain pixel design, each electrode strip 161 is obliquely intersected with the alignment direction.

[0124] In some embodiments, when the data line 19 intersects with the electrode strip 161, the distance between different positions on the data line 19 and the electrode strip 161 is different, for example, as Figure 6 As shown, the distance between data line 19 and electrode strip 161 varies linearly.

[0125] In practice, a minimum gap needs to be maintained between the electrode strip 161 and the data line 19. When the data line 19 and the electrode strip 161 cross each other at an angle, the distance between the data line 19 and the electrode strip 161 will gradually increase based on this minimum gap. Therefore, it will occupy a portion of the horizontal (i.e., row direction x) pixel size in the sub-pixel area, thus affecting the aperture ratio of the sub-pixel area.

[0126] In a further improved example, the shape of the data line 19 can be designed so that when the data line 19 intersects with the electrode strip 161, the distance between the data line 19 and the electrode strip 161 can remain uniform.

[0127] Specifically, multiple corners 192 can be designed on the data line 19 to balance the minimum distance difference between different positions of the data line 19 and the electrode strip 161. These different positions can be different points on the data line 19.

[0128] For example, please refer to Figure 11 As shown, when the data line 19 and the electrode strip 161 do not cross each other orthogonally, the data line 19 may include multiple corners 192; wherein, the extension direction of the portion of the data line 19 located outside the region 191 where the multiple corners are located is parallel to the anchoring direction OA, and the multiple corners 192 are arranged along the extension direction of the electrode strip 161.

[0129] The corner region 191 can refer to the area within the data line 19 located between two adjacent corners 192. Generally, the data line 19 between two adjacent corners 192 is in a different orientation direction. Therefore, the distance between the corners can be small, for example, less than 1 / 20 to 1 / 10 of the size of the boundary of the sub-pixel region in the column direction y.

[0130] For example, the distance between inflection points can be 1 / 20, 1 / 18, 1 / 15, 1 / 12, or 1 / 10 of the size of the boundary of the sub-pixel region in the column direction y.

[0131] like Figure 11 As shown, the data line 19 may include at least two corners 192, which may be continuous. Multiple corners 192 may be arranged in the extension direction of the electrode strip 161. This allows the multiple corners 192 to keep the distance between the data line 19 and the electrode strip 161 approximately uniform. For example, through multiple corners 192, the distance between the data line 19 and the electrode strip 161 may be kept at approximately the minimum interval.

[0132] The distance between the data line 19 and the electrode strip 161 can be a straight line distance.

[0133] In some exemplary embodiments, multiple corners 192 allow the line connecting the two endpoints of the data line 19 at the boundary of the sub-pixel area to be parallel to the electrode strip 161. This makes the distance between the data line 19 and the electrode strip 161 relatively close, so as not to occupy too much lateral space in the sub-pixel area.

[0134] Combination Figure 11 As shown, the data line 19 includes a first endpoint and a second endpoint located on the boundary of the sub-pixel area along the column direction y. The line connecting the first endpoint and the second endpoint is parallel to the electrode strip 161, and multiple corners 192 are located between the first endpoint and the second endpoint.

[0135] The first endpoint and the second endpoint can be two endpoints located on the boundary of the sub-pixel region in the column direction y.

[0136] The line connecting the first endpoint and the second endpoint can be a straight line segment, which can be parallel to the electrode strip 161. This ensures that the distance from the first endpoint of the data line 19 to the electrode strip 161 is at least equal to the distance from the second endpoint to the electrode strip 161. In this case, since the multiple corners 192 are arranged along the extension direction of the electrode strip 161, the difference between the distances from the portion of the data line 19 between the first endpoint and the second endpoint to the electrode strip 161 is small. For example, it can be equal to the distance between the first endpoint and the electrode strip 161. Alternatively, the distance from the portion of the data line 19 between the first endpoint and the second endpoint to the electrode strip 161 can be greater than the distance between the first endpoint and the electrode strip 161, but the difference can be small, for example, less than 1 / 15 to 1 / 5 of the distance between the first endpoint and the electrode strip 161.

[0137] For example, such as Figure 12 As shown, Figure 12 A planar schematic diagram of a sub-pixel region is also shown, including multiple corners 192. The distances from the first and second ends of the data line 19 to the electrode strip 161 are equal, such that the line connecting the first and second ends is approximately parallel to the electrode strip 161. The portion between the first and second ends may include portions where the distance to the electrode strip 161 is less than the distance from the second end to the electrode strip 161, and portions where the distance to the electrode strip 161 is greater than the distance from the second end to the electrode strip 161. Overall, the distance between the data line 19 and the electrode strip 161 can fluctuate around a minimum interval, thus avoiding occupying too much lateral space in the sub-pixel region.

[0138] Furthermore, by setting the number of corners 192, the straight-line distance from different positions in the data line 19, excluding the corner area 191, to the electrode strip 161 can be made equal. This ensures that the straight-line distance from the portion of the data line 19 extending along the anchoring direction OA to the electrode strip 161 remains uniform. Thus, without affecting the orientation of the liquid crystal 21, the lateral space occupied by the data line 19 in the sub-pixel area can be reduced, guaranteeing the opening area of ​​the sub-pixel area.

[0139] In some embodiments, such as Figure 12 As shown, the angles of the multiple corners 192 mentioned above can all be right angles. The multiple right-angle corners 192 are arranged along the extension direction of the electrode strip 161. The extension direction of the data line 19, excluding the area of ​​the corners 192, is consistent with the alignment direction. The multiple right-angle corners 192 make the line connecting the first endpoint and the second endpoint of the data line 19 parallel to the electrode strip 161, and the straight-line distance from different positions of the data line 19, excluding the area of ​​the corners 192, to the electrode strip 161 is equal.

[0140] In some embodiments, when multiple right-angle corners 192 are included, the multiple right-angle corners 192 are distributed along the long side of the data line 19, and the positions of the right-angle corners 192 along the long side on opposite sides are staggered, so that the orthographic projection of the data line 19 onto the substrate 11 can be serrated. Figure 12 As shown, the edges of data line 19 are serrated.

[0141] For example, such as Figure 13 As shown, Figure 13 A partial planar schematic diagram of the array substrate is also shown, such as... Figure 13 As shown, the data line 19 includes two right-angle corners 192. The design of the right-angle corners 192 makes the difference in the straight distance between different positions in the data line 19 and the electrode strip 161 smaller, thereby avoiding excessive occupation of the horizontal space of the sub-pixel area.

[0142] In this embodiment, the liquid crystal molecules are at an angle of 90° or 0° with the data line at the corner, and the initial orientation of the liquid crystal is not affected by the direction of the data line, so there is no light leakage.

[0143] An exemplary embodiment in which the film layer between the alignment layer 15 and the data line 19 has a flat surface at the data line 19 will be described below.

[0144] In some embodiments, please refer to Figure 14 As shown, Figure 14 It shows Figure 5A A cross-sectional structural diagram of the area where F1 is located in the first part, as shown below. Figure 14 As shown, the array substrate may further include:

[0145] Passivation layer 14 is located between first electrode layer 17 and second electrode layer 16;

[0146] The first planarization layer 13 is located on the side of the data line 19 close to the substrate 11 and includes a groove, the orthographic projection of the groove on the substrate 11 covering the orthographic projection of the data line 19 on the substrate 11; wherein the data line 19 is located in the groove, and the surface of the first portion F1 facing away from the substrate 11 is flush.

[0147] The data line 19 is located between the passivation layer 14 and the first planarization layer 13.

[0148] In this embodiment, as Figure 5A As shown, the first planarization layer 13 can be a film layer between the source electrode 184 and the passivation layer 14. The first planarization layer 13 can be formed of organic material, and the passivation layer 14 can be formed of inorganic material.

[0149] The passivation layer 14 can be a film layer located between the alignment layer 15 and the data line 19. The passivation layer 14 is in direct contact with the alignment layer 15 and the data line 19. The surface of the passivation layer 14 facing away from the substrate 11 is flat at least at the data line 19.

[0150] Among them, such as Figure 14 As shown, a groove can be formed on the first planarization layer 13, and the data line 19 can be located in the groove. The width of the groove can be slightly larger than the width of the data line 19, and the depth of the groove can be greater than or equal to half the thickness of the data line 19. Thus, at least half of the data line 19 in the thickness direction of the substrate 11 is located in the groove. This reduces the step difference between the data line 19 and the first planarization layer 13, so that when the passivation layer 14 is subsequently formed, the passivation layer 14 can effectively smooth the surface and improve the flatness of the passivation layer 14.

[0151] For example, the surface of the first portion F1 in the passivation layer 14 located at the data line 19 is flush with the side facing away from the substrate 11, thereby making the surface of the passivation layer 14 flat, so that it will not exert a force on the orientation of the subsequent liquid crystal 21 in this area, and making the orientation of the liquid crystal 21 in the sub-pixel area consistent with that at the data line 19.

[0152] The depth of the groove refers to its dimension in the thickness direction of the substrate 11. For example, the thickness of the data line. The depth of the groove is also The width of the groove can be 2.6 μm.

[0153] In a further embodiment, such as Figure 14As shown, the dimension of the groove in the thickness direction of the substrate 11 is greater than or equal to the thickness of the data line 19. This allows the data line 19 to be completely located within the groove, thus enabling the passivation layer 14 to achieve a higher degree of flatness.

[0154] In this example, the size of the groove in the thickness direction of the substrate 11 can be equal to or slightly larger than the thickness of the data line 19. If the groove is larger than the thickness of the data line 19, the difference between the depth of the groove and the thickness of the data line 19 can be less than 1 / 5 to 1 / 2 of the thickness of the data line 19, so as to avoid affecting the source electrode 184 below the first planarization layer 13 when the groove depth is too deep.

[0155] In this example, the extension direction of the groove can be the same as the extension direction of the data line 19, for example, as shown below. Figure 15 As shown, Figure 15 A planar schematic diagram of a partial region of the array substrate is shown, such as... Figure 15 As shown, since the film layer at data line 19 is flat, it will not affect the alignment of alignment layer 15 with liquid crystal 21. Therefore, data line 19 can be parallel to electrode strip 161. In this case, the extension direction of data line 19 can be inconsistent with the alignment direction. For example, data line 19 has an angle of 5° to 10° with the alignment direction. The groove can be formed along the extension direction of data line 19, thereby avoiding the groove occupying too much space.

[0156] In some embodiments, flatness at the data line 19 can be achieved by increasing the thickness of the film layer above the data line 19 and below the alignment layer 15. Above the data line 19 refers to the direction of the data line 19 away from the substrate 11, and below the alignment layer 15 refers to the direction of the alignment layer 15 closer to the substrate 11.

[0157] For example, please combine Figure 16 and Figure 5C As shown, Figure 16 It shows Figure 5C A cross-sectional structural diagram of the area where F1 is located in the first part, as shown below. Figure 16 As shown, the array substrate also includes:

[0158] The passivation layer 14 is located on the side of the data line 19 away from the substrate 11 and is in direct contact with the data line 19;

[0159] The second planarization layer 20 is located on the side of the passivation layer 14 facing away from the substrate 11, wherein the orthographic projection of the second planarization layer 20 on the substrate 11 does not overlap with the orthographic projections of the first electrode layer 17 and the second electrode layer 16 on the substrate 11.

[0160] The surface of the second planarization layer 20 is flush with the side opposite to the substrate 11.

[0161] In this example, the passivation layer 14 and the second planarization layer 20 are film layers located between the alignment layer 15 and the data line 19, as shown in the figure. The passivation layer 14 is in direct contact with the data line 19 on the side closer to the substrate 11, and the second planarization layer 20 is in direct contact with the alignment layer 15 on the side away from the substrate 11. The second planarization layer 20 can be provided only at the data line 19 and not within the sub-pixel area, and the surface of the second planarization layer 20 on the side away from the substrate 11 is flat.

[0162] In this example, the thickness of the passivation layer 14 can be relatively small; for example, the thickness of the passivation layer 14 can be [missing information]. This increases the overlap capacitance between the first electrode layer 17 and the second electrode layer 16.

[0163] In this embodiment, the orthographic projection of the second planarization layer 20 on the substrate 11 can be non-overlapping with the orthographic projection of the second electrode layer 16 on the substrate 11. Thus, the second part F2 of the insulating structure layer (including the passivation layer 14) mentioned in the above embodiment can only include the passivation layer 14. That is, the orthographic projection of the passivation layer 14 on the substrate 11 covers the sub-pixel area and the orthographic projection of the data line 19 on the substrate 11.

[0164] The surface of the second planarization layer 20 facing away from the substrate 11 is flush with the surface of the second planarization layer 20. This allows the second planarization layer 20 to smooth out the step difference in the passivation layer 14 caused by the data line 19, thereby improving the flatness of this area and thus not affecting the alignment effect of the alignment layer 15 on the liquid crystal 21 at this location.

[0165] The second planarization layer 20 can be formed using organic materials. In this way, the flatness of the second planarization layer 20 can be improved by utilizing the leveling effect of organic materials.

[0166] In some other embodiments, the portion of the film layer between the alignment layer 15 and the data line 19 at the data line 19 can be thinned. For example, please refer to... Figure 17 As shown, the insulating structure layer (including passivation layer 14) is thinned in the region where the data line 19 is located, thereby giving the insulating structure layer a high degree of flatness at the data line 19. Exemplarily, the array substrate further includes:

[0167] The passivation layer 14 is located on the side of the data line 19 away from the substrate 11, and is located between the first electrode layer 17 and the second electrode layer 16, and is in direct contact with the data line 19.

[0168] The thickness of the passivation layer 14 in the first region F21 is less than the thickness of the passivation layer 14 in the second region F22. The orthographic projection of the first region F21 on the substrate 11 covers the orthographic projection of the data line 19 on the substrate 11. The orthographic projection of the second region F22 on the substrate 11 does not overlap with the orthographic projection of the data line 19 on the substrate 11.

[0169] In this design, the first region F21 is the portion of the passivation layer 14 located at the data line 19. The thickness of the first region F21 is less than the thickness of the second region F22. In one scenario where the passivation layer 14 is thinned at the location of the data line 19, the data line 19 can be exposed. In this case, the thickness of the second region F22 can be the same as the thickness of the data line 19, resulting in a flat surface film at the data line 19. That is, the alignment layer 15 can directly contact the data line 19 and the passivation layer 14 on the side closest to the substrate 11, and the surfaces of the data line 19 and the passivation layer 14 can be flush.

[0170] In this embodiment, the mask used for the passivation layer can be designed during the formation of the passivation layer, and the flatness of the film layer can be improved by removing the passivation layer above the data line.

[0171] In some embodiments, since the film layer at the data line 19 is flat, it will not affect the alignment of the alignment layer 15 with the liquid crystal 21. Therefore, the data line 19 can be parallel to the electrode strip 161. In this case, the extension direction of the data line 19 may not be consistent with the alignment direction. For example, the data line 19 has an angle of 5° to 10° with the alignment direction.

[0172] Below are some exemplary array substrates.

[0173] Array substrate A, please refer to Figure 6 and Figure 7 As shown, the array substrate includes:

[0174] Substrate 11, one side of substrate 11 includes multiple data lines 19 and multiple gate lines, the data lines 19 and gate lines intersecting to define multiple sub-pixel regions, the sub-pixel regions including:

[0175] First electrode layer 17;

[0176] The second electrode layer 16 is located on the side of the first electrode layer 17 away from the substrate 11. The second electrode layer 16 includes a plurality of electrode strips 161 that are parallel to each other and spaced apart.

[0177] The passivation layer 14 is located between the first electrode layer 17 and the second electrode layer 16. The data line 19 is located on the side of the passivation layer 14 close to the substrate 11 and is in direct contact with the passivation layer 14.

[0178] Alignment layer 15 is located on the side of the second electrode layer 16 away from the substrate 11, and the anchoring direction OA of alignment layer 15 does not intersect the extension direction of electrode strip 161.

[0179] In this configuration, multiple sub-pixel regions are arranged along rows and columns. The extension direction of data line 19 is parallel to the anchoring direction OA, and the intersection angle between it and the column direction y is 5° to 10°. Electrode strip 161 is parallel to the column direction y and orthogonal to the row direction x. Specifically, the intersection angle between the extension direction of data line 19 and the column direction y is 5°.

[0180] Array substrate B, please refer to Figure 8 and Figure 9 As shown, the array substrate B differs from the array substrate A in that the extension direction of the data line 19 in the array substrate B is parallel to the column direction y and orthogonal to the row direction x, and the intersection angle between the electrode strip 161 and the column direction y is 5° to 10°, specifically 5°.

[0181] In this design, the electrode strip 161 within the sub-pixel region has an extending direction, thus allowing for a 1P1D (single-domain pixel) design; or, as... Figure 8 Neutralize (3) Figure 9 As shown, the electrode strip 161 of a single sub-pixel region has two extending directions, which can be a 1P2D (dual-domain pixel) design.

[0182] Array substrate C, please refer to Figure 11-12 As shown, the array substrate C differs from the array substrates B and A in that the data line 19 in the array substrate C has multiple right-angle corners 192. The multiple right-angle corners 192 make the data line 19 a toothed line, thereby making the straight-line distance between different points of the data line 19 and the electrode strip 161 more uniform.

[0183] Array substrate D, please refer to Figure 14 As shown, the array substrate D includes:

[0184] Substrate 11, one side of substrate 11 includes multiple data lines 19 and multiple gate lines, the data lines 19 and gate lines intersecting to define multiple sub-pixel regions, the sub-pixel regions including:

[0185] First electrode layer 17;

[0186] The second electrode layer 16 is located on the side of the first electrode layer 17 away from the substrate 11. The second electrode layer 16 includes a plurality of electrode strips 161 that are parallel to each other and spaced apart.

[0187] The passivation layer 14 is located between the first electrode layer 17 and the second electrode layer 16. The data line 19 is located on the side of the passivation layer 14 close to the substrate 11 and is in direct contact with the passivation layer 14.

[0188] The first planarization layer 13 is located on the side of the data line 19 closest to the substrate 11;

[0189] Alignment layer 15 is located on the side of the second electrode layer 16 away from the substrate 11. The anchoring direction OA of alignment layer 15 does not intersect the extension direction of electrode strip 161. Electrode strip 161 is parallel to data line 19.

[0190] In this process, a groove is provided on the first planarization layer 13, the data line 19 is located in the groove, the extension direction of the groove is the same as the extension direction of the data line 19, the depth of the groove is the same as the thickness of the data line 19, and the surface of the passivation layer 14 facing away from the substrate 11 is flat.

[0191] Array substrate E, please refer to Figure 16 As shown, the array substrate E differs from the array substrate D in that the array substrate E also includes a second planarization layer 20 located on the side of the passivation layer 14 away from the substrate 11. The orthographic projection of the second planarization layer 20 on the substrate 11 does not overlap with the orthographic projections of the first electrode layer 17 and the second electrode layer 16 on the substrate 11. The surface of the second planarization layer 20 away from the substrate 11 is flat, while the surface of the passivation layer 14 away from the substrate 11 has a step. The second planarization layer 20 can smooth out this step.

[0192] This embodiment also provides a display panel, such as Figure 18 As shown, a cross-sectional structural diagram of the display panel is illustrated. Figure 18 As shown, the display panel may include:

[0193] A first substrate 100, a second substrate 200, and a liquid crystal layer 21 located between the first substrate 100 and the second substrate 200, wherein the first substrate 100 is configured as follows: Figures 5A-17 Any of the array substrates described above;

[0194] In the liquid crystal 21 layer, the initial alignment of the liquid crystal 21 is parallel to the data line 19 on the first substrate 100, and the data line 19 is not orthogonally intersecting with the electrode strip 161 on the first substrate 100.

[0195] Alternatively, the data line 19 is parallel to the electrode strip 161, and the initial alignment is not orthogonal to either the data line 19 or the electrode strip 161.

[0196] In this embodiment, the second substrate 200 in the display panel can be a color filter substrate.

[0197] The display panel may also include a lower polarizer located on one side of the array substrate and an upper polarizer located on one side of the second substrate 200.

[0198] When the array substrate is the array substrate A mentioned above, the initial alignment of the liquid crystal 21 in the liquid crystal 21 layer is parallel to the data line 19 on the first substrate 100. In this way, the absorption axes of the upper and lower polarizers need to match the initial alignment direction OA. For example, when the angle between the data line 19 and the column direction y is 5°, in one example, the absorption axis of the upper polarizer can be 85° (clockwise 85°) and the absorption axis of the lower polarizer can be -5° (counterclockwise 85°); in another example, the absorption axis of the upper polarizer can be -5° (counterclockwise 85°) and the absorption axis of the lower polarizer can be 85° (clockwise 85°).

[0199] When the array substrate is the array substrate B mentioned above, the initial alignment of the liquid crystal 21 in the liquid crystal 21 layer is parallel to the data line 19 on the first substrate 100. In this way, the absorption axes of the upper and lower polarizers need to match the initial alignment direction OA. In one example, the absorption axis of the upper polarizer can be 90° and the absorption axis of the lower polarizer can be 0°; in another example, the absorption axis of the upper polarizer can be 0° and the absorption axis of the lower polarizer can be 90°.

[0200] When the array substrates D and E are used, the initial alignment of the liquid crystal 21 in the liquid crystal 21 layer intersects with the data line 19 on the first substrate 100. For example, if the initial alignment is perpendicular to the row direction x, the absorption axis of the vertical polarization can be referenced to the display panel using array substrate B. In this way, the data line 19 and the electrode strip 161 can be parallel.

[0201] A support column 300 is provided between the first substrate and the second substrate to support the first substrate and the second substrate.

[0202] This embodiment also provides a liquid crystal projector, which may include the display panel described above. The display panel may include... Figures 5A-17 Any of the array substrates described above.

[0203] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.

[0204] Finally, it should be noted that in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0205] The array substrate, display panel, and liquid crystal projector provided in this disclosure have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of this disclosure. The descriptions of the above embodiments are only for the purpose of helping to understand the methods and core ideas of this disclosure. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of this disclosure. Therefore, the content of this specification should not be construed as a limitation of this disclosure.

[0206] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This disclosure is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the following claims.

[0207] It should be understood that this disclosure is not limited to the precise structures described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this disclosure is limited only by the appended claims.

[0208] The terms "an embodiment," "embodiment," or "one or more embodiments" as used herein mean that a particular feature, structure, or characteristic described in connection with an embodiment is included in at least one embodiment of this disclosure. Furthermore, please note that the examples of the phrase "in one embodiment" do not necessarily all refer to the same embodiment.

[0209] Numerous specific details are set forth in the specification provided herein. However, it will be understood that embodiments of this disclosure may be practiced without these specific details. In some instances, well-known methods, structures, and techniques have not been shown in detail so as not to obscure the understanding of this specification.

[0210] In the claims, any reference signs placed between parentheses should not be construed as limiting the claims. The word "comprising" does not exclude the presence of elements or steps not listed in the claims. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements. This disclosure can be implemented by means of hardware comprising a plurality of different elements and by means of a suitably programmed computer. In a unit claim enumerating a plurality of means, several of these means may be embodied by the same item of hardware. The use of the words first, second, and third, etc., does not indicate any order. These words may be interpreted as names.

[0211] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this disclosure, and are not intended to limit them. Although this disclosure has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this disclosure.

Claims

1. An array substrate, characterized in that, It includes multiple data lines and multiple gate lines, the data lines and the gate lines intersecting to define multiple sub-pixel regions, the sub-pixel regions including: Substrate: First electrode layer; A second electrode layer is located on the side of the first electrode layer facing away from the substrate, and the second electrode layer includes a plurality of electrode strips arranged parallel to each other and spaced apart; and, An alignment layer is located on the side of the second electrode layer away from the substrate, and the anchoring direction of the alignment layer is not orthogonal to the extension direction of the electrode strip; Wherein, the extension direction of the data line is parallel to the anchoring direction, and / or the film layer between the alignment layer and the data line has a flat surface at the data line, the surface being the surface of the film layer facing away from the substrate.

2. The array substrate according to claim 1, characterized in that, The extension direction of the data line is parallel to the anchoring direction, and the intersection angle between the electrode strip and the data line is 5° to 10°.

3. The array substrate according to claim 1, characterized in that, The multiple sub-pixel regions are arranged along a row and column array, and the extension direction of the data line is parallel to the anchoring direction; Wherein, the electrode strip is orthogonal to the row direction; or, the data line is orthogonal to the row direction.

4. The array substrate according to any one of claims 1-3, characterized in that, The data cable extends in a direction parallel to the anchoring direction; In one of the sub-pixel regions, multiple electrode strips extend in the same direction.

5. The array substrate according to any one of claims 1-3, characterized in that, The electrode strip includes multiple branch electrodes, which are connected in series, and at least two of the branch electrodes are not orthogonally intersecting.

6. The array substrate according to any one of claims 1-3, characterized in that, It includes at least a first sub-pixel region and a second sub-pixel region; Wherein, the extension direction of the electrode strip in the first sub-pixel region and the extension direction of the electrode strip in the second sub-pixel region are not orthogonal.

7. The array substrate according to any one of claims 1-3, characterized in that, The data line extends in a direction parallel to the anchoring direction, and the data line includes multiple corners; Wherein, the extension direction of the portion of the data line located outside the area where the multiple corners are located is parallel to the anchoring direction, and the multiple corners are arranged along the extension direction of the electrode strip.

8. The array substrate according to claim 7, characterized in that, The corners include right-angle corners.

9. The array substrate according to claim 7, characterized in that, The data line includes a first endpoint and a second endpoint located on the boundary of the sub-pixel area along the column direction. The line connecting the first endpoint and the second endpoint is parallel to the electrode strip, and a plurality of the corners are located between the first endpoint and the second endpoint.

10. The array substrate according to claim 7, characterized in that, The data line appears as a sawtooth shape when projected onto the substrate.

11. The array substrate according to claim 1, characterized in that, The film layer between the alignment layer and the data line has a flat surface at the data line, and the array substrate further includes: A passivation layer is located between the first electrode layer and the second electrode layer; A first planarization layer is located on the side of the passivation layer closest to the substrate, and the data line is located between the passivation layer and the first planarization layer; The first planarization layer includes a groove, the orthographic projection of the groove on the substrate covers the orthographic projection of the data line on the substrate, the data line is located in the groove, and the surface of the first portion facing away from the substrate is flush.

12. The array substrate according to claim 11, characterized in that, The dimension of the groove in the thickness direction of the substrate is greater than or equal to the thickness of the data line.

13. The array substrate according to claim 1, characterized in that, The film layer between the alignment layer and the data line has a flat surface at the data line, and the array substrate further includes: A passivation layer is located on the side of the data line away from the substrate and is in direct contact with the data line; The second planarization layer is located on the side of the passivation layer away from the substrate, and the orthographic projection of the second planarization layer on the substrate does not overlap with the orthographic projections of the first electrode layer and the second electrode layer on the substrate. The surface of the second planarization layer opposite to the substrate is flush.

14. The array substrate according to claim 1, characterized in that, The film layer between the alignment layer and the data line has a flat surface at the data line, and the array substrate further includes: A passivation layer is located on the side of the data line away from the substrate, between the first electrode layer and the second electrode layer, and in direct contact with the data line; Wherein, the thickness of the passivation layer in the first region is less than the thickness of the passivation layer in the second region, the orthographic projection of the first region on the substrate covers the orthographic projection of the data line on the substrate, and the orthographic projection of the second region on the substrate does not overlap with the orthographic projection of the data line on the substrate.

15. A display panel, characterized in that, It includes a first substrate, a second substrate, and a liquid crystal layer located between the first substrate and the second substrate, wherein the first substrate is configured as an array substrate according to any one of claims 1-14; Wherein, the initial alignment of the liquid crystal in the liquid crystal layer is parallel to the data lines on the first substrate, and the data lines do not orthogonally intersect with the electrode strips on the first substrate; Alternatively, the data line is parallel to the electrode strip, and the initial alignment is not orthogonal to either the data line or the electrode strip.

16. A liquid crystal projector, characterized in that, It includes the array substrate according to any one of claims 1-14, or the display panel according to claim 15.

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