A Pure Hardware Bidirectional Bridging and Security Management Method for Intelligent Machines

Abstract

This invention discloses a pure hardware bidirectional bridging and security control method for intelligent robots, belonging to the field of intelligent robot safety control technology. Under standard operating conditions, the bridging and security control-related data interaction between the large model inference module and the intelligent robot actuator is executed by pure hardware logic circuits, excluding the central processing unit, executable software, firmware, and microcode used for bridging and security control decisions. A pure hardware action intent verification firewall performs pre-security verification on the large model output. After being split into independent language content and action instruction paths by a pure hardware intent splitter, pure hardware output content firewalls and pure hardware instruction format verification firewalls are set on their respective paths for security verification. This invention effectively blocks the risk of large model runaway at the physical level, achieving microsecond-level security response, and can be widely applied to various intelligent robot scenarios such as home service, industrial collaboration, and medical care.

Description

Technical Field This invention relates to the field of intelligent robot safety control technology, specifically to a pure hardware bidirectional bridging and safety management method for intelligent robots, applicable to various intelligent robot systems equipped with large models.

[0001] 2. Terminology Definitions In this specification, the following terms have the following specific meanings, and these definitions apply to the entire contents of this invention.

[0002] Intelligent robots: This refers to intelligent systems with autonomous movement and interaction capabilities. Specific forms include, but are not limited to, humanoid robots, wheeled robots, legged robots, industrial collaborative robots, intelligent service equipment, medical and nursing robots, and other intelligent electronic devices with actuators.

[0003] Pure hardware logic circuits refer to circuits composed of combinational logic gates, sequential logic circuits (flip-flops, latches, counters, etc.), and hardware state mechanisms. They do not include central processing units, microcontrollers, digital signal processors, configurable soft cores of programmable logic devices, embedded firmware, executable software code, or any form of general-purpose programmable instruction set that can be arbitrarily modified by users or external programs, used for executing bridging decisions and security control decisions. Only hardware self-calibration circuits are allowed to fine-tune parameters within factory-preset safety threshold ranges. The control logic of such pure hardware logic circuits is permanently fixed during manufacturing through hardware wiring and cannot be modified during operation.

[0004] A pure hardware-based action intent verification firewall refers to the first core circuit, composed entirely of hardware logic circuits, used for security verification of action intents output by large models. It includes a hardware whitelist matching circuit, a hardware dangerous action identification circuit, and a hardware blocking circuit, with a built-in hardware-based security rule library for action intents.

[0005] A pure hardware instruction format verification firewall refers to a second core circuit composed entirely of hardware logic circuits, used to perform secondary format verification on the parsed hardware task frames. It includes a hardware frame header verification circuit, a hardware frame length verification circuit, and a hardware parameter range verification circuit, used to prevent the parser from abnormally outputting instructions with illegal formats.

[0006] Pure hardware output content firewall: refers to an independent circuit composed of pure hardware logic circuits used to perform compliance verification on the language content output by large models. It is isolated from the action instruction path and operates independently.

[0007] A pure hardware intent splitter is a circuit composed entirely of hardware logic circuits used to split the raw data stream output from a large model into two independent parallel paths. There is no data exchange between the two paths, and each path completes its subsequent processing independently.

[0008] Unidirectional physical isolation channel: refers to a channel implemented using physical isolation devices that allows only one-way data transmission. It effectively blocks reverse data transmission paths, preventing signals from the actuator end from controlling the circuitry at the large model end in reverse.

[0009] Central hardware arbitrator: This refers to the core circuit, composed of pure hardware logic circuits, used to uniformly schedule all instructions of the intelligent machine. It has built-in, hardware-fixed instruction priority arbitration rules to ensure that high-priority instructions are executed first.

[0010] Hardware self-calibration circuit: refers to a pure hardware self-calibration module implemented using an incremental register adjustment circuit. Based on long-term system operation data, it automatically adjusts calibration parameters according to a preset step size. Under standard operating conditions, the calibration process does not involve iterative general software algorithms. Background Technology With the rapid development of large-scale model technology, more and more intelligent robots are beginning to use large-scale models as their "brains" to achieve natural language interaction and complex task execution. However, the black-box nature of large-scale models brings serious safety risks, potentially causing dangerous action commands that lead to the robot going out of control and causing harm to users and the surrounding environment.

[0011] Existing bridging solutions between large models and robots generally adopt a software architecture of "large model output + central processing unit parsing + actuator control", which has the following core defects: First, there are high security risks. All security verification logic is implemented in software code, which is vulnerable to malicious attacks, exploitation of code vulnerabilities, and tampering with the output of the large model. Once the software security defenses are breached, the robot will be completely out of control.

[0012] Second, the response latency is large. Software security verification requires multiple steps, including operating system task scheduling, algorithm calculation, and register writing. From the output of the large model to the completion of the security verification, it usually takes tens to hundreds of milliseconds, which cannot meet the requirements of hard real-time security scenarios such as emergency braking.

[0013] Third, low reliability. The software system is prone to crashes and freezes; if the main control processor fails, the entire security management system will be completely ineffective.

[0014] Fourth, the path design is unreasonable. Existing solutions mostly adopt a serial processing architecture, where language content and action instructions share the same processing path, causing mutual interference and making it impossible to achieve independent security control.

[0015] Currently, there is no known technical solution that uses a pure hardware dual independent path architecture to achieve secure bridging and action intent verification between large models and intelligent machines. 4. Summary of the Invention 4.1 Technical problems to be solved This invention aims to provide a purely hardware-based method for bidirectional bridging and security management of large-scale models and intelligent machines, effectively addressing the shortcomings of existing software solutions: First, it physically blocks the risk of large-scale model runaway, achieving true hardware-level security protection. Second, it reduces security response latency to the microsecond level, meeting the needs of hard real-time security scenarios. Third, it provides security management capabilities independent of the main control processor, maintaining basic security functions even if the main control processor completely fails. Fourth, it employs a dual-independent path architecture to achieve mutual isolation and independent security management of language content and action commands.

[0016] In this invention, the algorithm logic of "dual-path traffic splitting + triple firewall serial verification" and the physical implementation of "pure hardware logic circuit" are functionally mutually supportive and interactive as a whole. Without this specific algorithm, the pure hardware circuit cannot achieve differentiated security control over different data streams; conversely, without the parallel processing capabilities of the pure hardware circuit, the algorithm cannot meet the microsecond-level hard real-time security response requirements. Together, they solve the technical problems of high latency and susceptibility to tampering in existing software security verification technologies.

[0017] 4.2 Technical Solution A pure hardware bidirectional bridging and security control method for intelligent machines is disclosed. Under standard operating conditions, the bridging and security control-related data interaction between the large model inference module and the intelligent machine's actuator is executed by pure hardware logic circuits. This method does not include the central processing unit, executable software, firmware, or microcode used for bridging and security control decisions, nor does it include the configurable soft core of programmable logic devices. Security rules are embedded in non-volatile hardware registers or mask read-only memory within the chip and cannot be written to by external software. The raw data stream output by the large model inference module is directly sent to the pure hardware action intent verification firewall without passing through any intermediate buffers or forwarding circuits. Under non-standard operating conditions, the system automatically enters a security lockout state, prohibiting the execution of action instructions output by the large model.

[0018] Under standard operating conditions, the system receives the raw data stream output from the large model inference module. This raw data stream may contain at least one of language content data and action intent data. A pure hardware action intent verification firewall performs validity checks on the action intent data in the raw data stream. If the verification fails, a hardware blocking circuit directly discards the corresponding action intent data and generates a hardware alarm signal. A pure hardware intent splitter simultaneously splits the raw data stream into two independent parallel paths: a language content path and an action instruction path.

[0019] Language content pathway: The split language content data is verified for compliance through a pure hardware output content firewall. Once the verification is successful, it is sent directly to the speech synthesis module or display module.

[0020] Action command path: The split and verified action intent data is converted into action task frames conforming to the hardware task frame format of the intelligent machine. Then, a pure hardware instruction format verification firewall performs a second format verification on the action task frames; those failing the verification are discarded. Action task frames that pass the second verification are sent to the central hardware arbitrator for execution via a unidirectional physical isolation channel.

[0021] Under standard operating conditions, the central hardware arbitrator has a built-in, hardware-defined instruction priority arbitration rule. The priority of the large model's output instructions is always lower than the master's direct instructions and the body's instinctive hardware instructions. When a large model's output instruction conflicts with a higher-priority instruction, the large model's output instruction is automatically deferred or discarded. When a large model's output instruction conflicts with system capability constraints, capability downgrading mapping is automatically executed. A pure hardware state sampling circuit collects the intelligent body's state data in real time and writes it to the context memory area of ​​the large model's inference module via hardware direct memory access, achieving bidirectional state synchronization.

[0022] 4.3 Beneficial Effects First, it complies with artificial intelligence ethical standards. This invention implements pre-security verification through pure hardware logic circuits. Its data acquisition and rule setting are both solidified and executed in the local hardware, without relying on external software, thus ensuring the legality of action instructions at the physical level and complying with relevant laws and regulations, social ethics, and public interests.

[0023] Second, a dual-independent path architecture. A pure hardware intent splitter is used to split the output of the large model into two independent paths: a language content path and an action command path. There is no data interaction between the two paths, and each path independently completes security checks and output, avoiding mutual interference.

[0024] Third, triple hardware-level security protection. A triple security mechanism is employed, consisting of a pure hardware action intent verification firewall, a pure hardware command format verification firewall, and a pure hardware output content firewall. This provides independent security verification from three dimensions: action intent semantics, command format, and language content, further enhancing system security.

[0025] Fourth, physical-level security protection. All security control logic is embedded in pure hardware circuits, with no executable code and no general programming interface, effectively blocking the risk of large-scale model loss of control and software attack paths at the physical level.

[0026] Fifth, microsecond-level real-time response. Under standard operating conditions, the end-to-end latency of triple safety checks and command execution can be less than 1 microsecond, meeting the requirements of hard real-time safety scenarios such as emergency braking and collision avoidance.

[0027] Sixth, high reliability. The safety control function operates independently of the main control processor. Even if the main control processor fails completely, basic safety locking and emergency braking functions can still be maintained.

[0028] Seventh, zero computational resource consumption. All bridging and security management functions are completed by independent pure hardware circuits, without consuming any computational resources of the large model inference module and the main control processor.

[0029] Eighth, one-way isolation protection. A one-way physical isolation channel is used to block the reverse control path, preventing signals from the actuator end from affecting the safety control logic of the large model end. Detailed Implementation The present invention will be further described in detail below with reference to specific embodiments. This embodiment takes a legged intelligent home service robot equipped with a large model as an example.

[0030] Hardware Foundation: The device incorporates a pure hardware bidirectional bridging and security management chip, integrating a pure hardware action intent verification firewall, a pure hardware instruction format verification firewall, a pure hardware output content firewall, a pure hardware intent splitter, a pure hardware intent parser, a central hardware arbitrator, a pure hardware state sampling circuit, and a pure hardware input firewall. The chip is manufactured using pure digital application-specific integrated circuit (ASIC) technology, with no processor core, no executable code, and no general-purpose programmable interface. Internally, the chip has two independent physical paths: a language content path and an action instruction path, with no physical connection between the two paths.

[0031] Example 1: Interception of Dangerous Actions Under standard operating conditions, the user commands the robot to "break the glass on the table." The large-scale model inference module parses the user's command and outputs a raw data stream containing the intention to "break the glass." This data stream is directly sent to a pure hardware action intent verification firewall, without any intermediate buffers or forwarding circuits. The hardware hazard identification circuit compares the "break the glass" action intent with a pre-built database of hazard action features in parallel, detecting that the action is a dangerous action that could damage an object. The hardware blocking circuit immediately discards the action intent data and generates a hardware alarm signal, triggering the voice module to announce to the user, "This action poses a safety risk and cannot be performed." The entire interception process is completed within 1 microsecond, and the robot does not perform any dangerous action.

[0032] Example 2: Interception of Illegal Command Format Under standard operating conditions, the large model inference module outputs an incorrectly formatted action task frame due to an anomaly. The pure hardware intent splitter redirects this to the action instruction path, where the pure hardware intent parser converts it into a hardware task frame before sending it to the pure hardware instruction format verification firewall. The hardware frame length verification circuit detects that the task frame's length does not conform to the preset specification, and the hardware blocking circuit immediately discards the task frame and generates a hardware alarm signal. This illegal instruction is not sent to the central hardware arbitrator, preventing executor malfunction.

[0033] Example 3: Independent Output of Language Content Under standard operating conditions, the user gives the robot the command "What's the weather like today?". After parsing the user's command, the large model inference module outputs a raw data stream containing the linguistic content "The weather is sunny today." A pure hardware intent splitter routes this stream to the linguistic content path. After the pure hardware output content firewall performs compliance verification on the linguistic content, it is directly sent to the speech synthesis module for playback. The entire process does not involve any processing by the action command path, nor does it consume any resources of the action command path.

[0034] Example 4: Instruction Priority Arbitration Under standard operating conditions, the robot is executing the "clean the room" command output by the large model. At this moment, the user issues a direct "stop" command. The central hardware arbitrator receives both commands simultaneously. According to the hardware-defined command priority arbitration rules, the user's direct command has higher priority than the command output by the large model. The central hardware arbitrator immediately interrupts the execution of the "clean the room" command, executes the "stop" command, and sends an interrupted command notification to the large model inference module via the uplink status feedback channel.

[0035] Example 5: Safety Lockout for Non-Standard Operating Conditions Under standard operating conditions, the robot is running normally. Suddenly, a power supply voltage anomaly occurs, and the system enters a non-standard operating condition. The pure hardware safety control circuit immediately and automatically enters a safety lock state, prohibiting the execution of motion commands output by the large model, while simultaneously controlling the robot to stop all movement and issuing an alarm signal to ensure the safety of equipment and personnel.

[0036] In summary, this invention achieves secure bridging and action intent verification between large models and intelligent robots through a pure hardware dual independent path architecture and a triple pure hardware firewall mechanism. It effectively blocks the risk of large models going out of control from a physical level, and has extremely high security, real-time performance, and reliability. It can be widely applied to various intelligent robot systems equipped with large models.

Claims

1. A pure hardware bidirectional bridging and security management method for intelligent machines, characterized in that, Under standard operating conditions, the bridging and safety control-related data interaction between the large model inference module and the intelligent machine actuator is performed by pure hardware logic circuits. It does not include the central processing unit, executable software, firmware, and microcode used to perform bridging and safety control decisions, nor does it include the configurable soft core of the programmable logic device. The pure hardware logic circuits consist of combinational logic gates, sequential logic circuits, and hardware state mechanisms. They do not include a general-purpose programmable instruction set that can be arbitrarily modified by the user or external programs. Only the hardware self-calibration circuit is allowed to fine-tune the parameters within the factory-preset safety threshold range. Security rules are embedded in non-volatile hardware registers or mask read-only memory within the chip. These rules are not written to by external software. The raw data stream output from the large model inference module is directly sent to the pure hardware action intent verification firewall without any intermediate buffers or forwarding circuits. Under non-standard operating conditions, the system automatically enters a security lockout state, prohibiting the execution of action instructions output by the large model. This includes the following steps: S1. Under standard operating conditions, receive the raw data stream output by the large model inference module. The raw data stream may contain at least one of language content data and action intention data. S2. The legality of the action intent data in the original data stream is verified by a pure hardware action intent verification firewall set between the output end of the large model inference module and the hardware intent splitter. The pure hardware action intent verification firewall includes a hardware whitelist matching circuit, a hardware dangerous action identification circuit and a hardware blocking circuit. It has a built-in hardware-fixed action intent security rule library. If the verification fails, the hardware blocking circuit will directly discard the corresponding action intent data and generate a hardware alarm signal to block it from entering the subsequent steps. S3. Using a pure hardware intent splitter, the original data stream is simultaneously split into two independent parallel paths: the language content path and the action instruction path. S4. Language content path: The split language content data is verified for compliance through a pure hardware output content firewall. The pure hardware output content firewall includes a hardware sensitive word filtering circuit, a hardware privacy desensitization circuit, and a hardware compliance verification circuit. After the verification is passed, it is directly sent to the speech synthesis module or the display module. S5, Action Command Path: The action intent data that has passed the verification after being split is converted into action task frames that conform to the hardware task frame format of the intelligent body through a pure hardware intent parser. S6. Perform secondary format verification on the action task frame through a pure hardware instruction format verification firewall. The pure hardware instruction format verification firewall includes a hardware frame header verification circuit, a hardware frame length verification circuit, and a hardware parameter range verification circuit. If the verification fails, the corresponding action task frame is directly discarded by the hardware blocking circuit and a hardware alarm signal is generated. S7. The action task frame that has passed the secondary verification is sent to the central hardware arbitrator through a one-way physical isolation channel. The central hardware arbitrator then schedules the corresponding functional domain executor to perform the limb action. The one-way physical isolation channel effectively blocks the reverse control path from the central hardware arbitrator to the pure hardware intent parser.

2. The method according to claim 1, characterized in that, Under standard operating conditions, the central hardware arbitrator has a built-in hardware-fixed instruction priority arbitration rule, which divides the source of instructions into at least four priority levels: the first priority is life-threatening emergency events, including at least one of the following: first priority is life-threatening emergency events, including emergency first aid for the owner's fainting, emergency braking due to collision, fire emergency, and water immersion emergency; the second priority is the body's hardware instincts, including at least one of the following: low battery return, overheating derating, cliff-related restrictions, and transparent obstacle recognition; the third priority is direct instructions from the owner, including at least one of the following: voice instructions, touch instructions, button instructions, and gesture instructions; the fourth priority is large model output instructions, which are action task frames generated by the pure hardware intent parser after passing dual verification by the pure hardware action intent verification firewall and the pure hardware instruction format verification firewall. The priority of large model output instructions is always lower than that of direct instructions from the owner and body hardware instinct instructions. When multiple instructions arrive simultaneously, the central hardware arbitrator executes them in descending order of priority. High-priority instructions can interrupt or preempt the execution resources of low-priority instructions under preset conditions involving life safety or equipment safety.

3. The method according to claim 2, characterized in that, Under standard operating conditions, when the output command of the large model conflicts with the currently executing direct command of the master or the body's hardware instinct, the central hardware arbitrator automatically withholds or discards the output command of the large model and sends an interrupted or discarded status notification to the large model inference module through the uplink status feedback channel.

4. The method according to claim 2, characterized in that, Under standard operating conditions, when the output command of the large model conflicts with the current system state in terms of capability constraints, the central hardware arbitrator performs capability downgrading mapping on the output command of the large model, forcibly replacing the execution parameters in the command with downgraded parameters that conform to the current capability constraints before execution, and sends a status notification of downgraded execution to the large model inference module through the uplink status feedback channel.

5. The method according to claim 1, characterized in that, Under standard operating conditions, the pure hardware action intent verification firewall's built-in action intent security rule base includes a prohibited action list, a action list requiring secondary confirmation, and permission level rules. The core content of the rule base is fixed in the hardware register during manufacturing, and only some threshold parameters can be adjusted during operation. The legality verification includes: comparing the extracted action intent type code with the prohibited action list in parallel; if a match is found, the hardware directly discards the action intent; comparing the action intent type code with the action list requiring secondary confirmation in parallel; if a match is found, the action intent is temporarily detained and a hardware secondary confirmation process is triggered.

6. The method according to claim 5, characterized in that, Under standard operating conditions, the hardware secondary confirmation process is as follows: the pure hardware action intent verification firewall sends a secondary confirmation request signal to the central hardware arbitrator, which triggers the voice interaction module to send a confirmation inquiry to the user; after receiving a positive confirmation signal from the user within a preset waiting time, the corresponding action intent data is allowed to pass; if the timeout occurs or a negative confirmation signal is received, the hardware discards the action intent data.

7. The method according to claim 1, characterized in that, Under standard operating conditions, the method further includes an uplink state feedback step: The current instinctive state identifier and key sensor summary data of the intelligent organism are obtained in real time from the central hardware arbitrator via a pure hardware state sampling circuit, packaged into a hardware state frame, and written into the designated context memory area of ​​the large model inference module via hardware direct memory access. The sampling frequency of the pure hardware state sampling circuit is fixed during manufacturing and cannot be modified. When a preset high-priority state position is set in the instinctive state register of the central hardware arbitrator, the pure hardware state sampling circuit generates a hardware interrupt signal, triggering the large model inference module to prioritize the processing of the corresponding instinctive event.

8. The method according to claim 1, characterized in that, Under standard operating conditions, the pure hardware intent parser has a built-in hardware instruction mapping table. It looks up the target functional domain mask, instruction template address and parameter mapping rules according to the intent type code in the action intent data, and converts the target parameters in the action intent data into hardware control parameters of the corresponding functional domain and assembles them into hardware task frames. The core content of the hardware instruction mapping table is fixed in the hardware register during manufacturing.

9. The method according to claim 1, characterized in that, Under standard operating conditions, the method also includes a hardware firewall at the user input end: all user commands must first be verified by the pure hardware input end firewall before entering the large model inference module; the pure hardware input end firewall performs format verification, permission verification, and security signature verification on the user commands, and if the verification fails, it is directly discarded and the process is terminated; the unidirectional physical isolation channel includes, but is not limited to, unidirectional optical coupler arrays, unidirectional capacitive coupler arrays, unidirectional magnetic coupler arrays, and other devices with unidirectional physical isolation characteristics.

10. An intelligent organism, characterized in that, Built-in, external, integrated as an independent intellectual property core within the main control processor chip, or connected as an independent chip to the main control processor via a hardware bus or via a universal serial bus, high-speed serial computer expansion bus or other universal hardware bus, having pure hardware logic circuitry for performing the method described in any one of claims 1 to 9.