Readout control system suitable for spaceborne CCDs

Abstract

This invention provides a readout control system suitable for spaceborne CCDs. The system is designed with three stacked hardware units interconnected by board-to-board connectors. The first hardware unit includes a CCD detector, a front-end signal conditioning circuit, an ADC circuit, and a drive circuit. The second hardware unit includes a power supply circuit and an FPGA main control circuit. The third hardware unit includes a power supply circuit and an interface circuit. This system enables the CCD to switch between multiple readout modes, significantly improving time resolution while maintaining excellent energy resolution, thus better meeting the needs of time-sensitive X-ray detection applications such as pulsar navigation.

Description

Technical Field

[0001] This invention relates to the field of spaceborne X-ray detection technology in astronomy, and more particularly to a readout control system suitable for spaceborne CCDs. Background Technology

[0002] Space X-ray detection, as an important technical means for astronomical observation and cosmological research, typically relies on orbital telescope satellites to collect and analyze X-rays emitted by celestial bodies. It has significant application value in fields such as exploring cosmic structures and pulsar navigation. Charge-coupled devices (CCDs), with their excellent energy spectral resolution and good space imaging performance, have become the core detection device of spaceborne low-energy X-ray detection systems.

[0003] With the development of aerospace exploration technology, dedicated X-ray detection CCDs have been gradually put into research and application. However, traditional CCD devices are designed primarily to improve energy resolution, with significant limitations in temporal resolution, making it difficult to meet the requirements of high-time-efficiency detection scenarios. Frame-transfer CCD devices, which have emerged in recent years, support multiple readout modes and can balance energy spectral resolution and temporal resolution, providing a hardware foundation for high-real-time X-ray detection. However, these CCD devices have special requirements in terms of drive timing, multi-mode switching, high-speed data acquisition, low-noise analog conditioning, and onboard power supply and integrated structure. Existing general-purpose readout control systems cannot match these requirements, making it difficult to fully utilize the detection performance of the CCD. Therefore, there is an urgent need to design a dedicated high-speed CCD readout control system to achieve precise driving of frame-transfer CCDs, flexible multi-mode configuration, and high-speed, low-noise readout, thereby meeting the engineering application requirements of high-time-efficiency onboard X-ray detection. Summary of the Invention

[0004] To address the problems existing in the prior art, this invention provides a readout control system suitable for spaceborne CCDs.

[0005] This invention provides a readout control system suitable for spaceborne CCDs, comprising three stacked hardware units interconnected by inter-board connectors, wherein; The first layer of hardware units includes a CCD detector, a front-end signal conditioning circuit, an ADC circuit, and a driver circuit; The second-layer hardware unit includes a power supply circuit and an FPGA main control circuit. The third-layer hardware unit includes power supply circuits and interface circuits; The power supply circuit and the power supply circuit are used to convert the system input voltage into the operating voltage of the CCD detector and each circuit. The front-end signal conditioning circuit and the ADC circuit are used to optimize the detection case data of the CCD detector and send the optimized detection case data to the FPGA main control circuit. The FPGA main control circuit is used to send CCD detection control commands to the driving circuit; The driving circuit is used to control the CCD working state of the CCD detector according to the CCD detection control command; The FPGA main control circuit is also used to send optimized detection case data and read the status data of the control system to the host computer through the interface circuit, and to receive control commands generated by the host computer based on the optimized detection case data and the read status data of the control system.

[0006] According to the present invention, a readout control system suitable for spaceborne CCDs is provided, wherein the power supply circuit adopts a multi-stage voltage regulation architecture with complete separation of analog power supply and digital power supply, which is used to provide operating voltage for CCD detector, front-end signal conditioning circuit, ADC circuit and FPGA main control circuit.

[0007] According to the present invention, a readout control system suitable for spaceborne CCDs is provided, wherein the power supply circuit includes a fuse, a current detection circuit, a relay, a surge suppression circuit, a first filter circuit, and a DC / DC conversion circuit, for the system input power to pass through the fuse, current detection circuit, relay, surge suppression circuit, first filter circuit, and DC / DC conversion circuit, and output a stable voltage to the power supply circuit.

[0008] According to the present invention, a readout control system suitable for spaceborne CCDs is provided, wherein the front-end signal conditioning circuit includes an I / V conversion circuit, a first isolation circuit, a first operational amplifier circuit, a second isolation circuit, a programmable common-mode modulation circuit, a second operational amplifier circuit, a voltage divider circuit, and a fully differential operational amplifier circuit, wherein: The input terminal of the I / V conversion circuit is connected to the detection event data output by the CCD detector, and the output terminal is connected to the input terminal of the first DC blocking circuit. The output terminal of the first DC blocking circuit is connected to the input terminal of the first operational amplifier circuit, the output terminal of the first operational amplifier circuit is connected to the input terminal of the second DC blocking circuit, the output terminal of the second DC blocking circuit is connected to the input terminal of the second operational amplifier circuit and the control terminal of the programmable common-mode adjustment circuit. The output terminal of the second operational amplifier circuit is connected to the input terminal of the voltage divider circuit, the output terminal of the voltage divider circuit is connected to the input terminal of the fully differential operational amplifier circuit, and the output terminal of the fully differential operational amplifier circuit outputs the differential analog voltage signal transmitted to the ADC circuit.

[0009] According to the present invention, a readout control system suitable for spaceborne CCDs is provided, wherein the programmable common-mode adjustment circuit includes a programmable resistor, which is controlled by the FPGA main control circuit.

[0010] According to the present invention, a readout control system suitable for spaceborne CCDs is provided, wherein the driving circuit includes a driving module and a suppression resistor, wherein the driving module is used to drive the CCD detector to open / close, switch modes, and operate clock signals according to CCD detection control commands; the suppression resistor is connected to the output terminal of the driving module and is used to suppress overshoot of the operating clock signal.

[0011] According to the present invention, a readout control system suitable for spaceborne CCDs is provided, wherein the interface circuit includes a receiving chip, a transmitting chip, and an LVDS transmitting chip, wherein: Panel connectors, receiver chips, board-to-board connectors, and FPGA main control circuits form the path for transmitting control commands. The FPGA main control circuit, board-to-board connectors, transmitting chips, and panel connectors form the upload route for reading the status data of the control system. The FPGA main control circuit, board-to-board connectors, LVDS transmitter chip, and panel connectors form an optimized upload path for probe event data.

[0012] According to the present invention, a readout control system suitable for spaceborne CCDs is provided, wherein the power supply circuit is connected to the CCD detector through a second filter circuit.

[0013] According to the present invention, a readout control system suitable for spaceborne CCDs is provided, wherein the status data of the readout control system includes the CCD operating status of the CCD detector, the voltage, current and temperature of the system.

[0014] According to the present invention, a readout control system suitable for spaceborne CCDs is provided, wherein the CCD detector is a full-frame transfer type CCD.

[0015] This invention provides a readout control system suitable for spaceborne CCDs. It employs a three-layer stacked hardware unit design, interconnected by inter-board connectors. The first layer includes a CCD detector, a front-end signal conditioning circuit, an ADC circuit, and a drive circuit. The second layer includes a power supply circuit and an FPGA main control circuit. The third layer includes a power supply circuit and an interface circuit. This design enables switching between multiple readout modes for the CCD, significantly improving time resolution while maintaining excellent energy resolution, thus better meeting the needs of time-sensitive X-ray detection applications such as pulsar navigation. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in this invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0017] Figure 1 This is a structural framework diagram of the readout control system for spaceborne CCDs provided by the present invention.

[0018] Figure 2 This is a schematic diagram of the power supply circuit provided by the present invention.

[0019] Figure 3 This is a schematic diagram of the interface circuit provided by the present invention.

[0020] Figure 4 This is a schematic diagram of the front-end signal conditioning circuit provided by the present invention. Detailed Implementation

[0021] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of this invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this invention. All other embodiments obtained by those skilled in the art based on the embodiments of this invention without creative effort are within the scope of protection of this invention.

[0022] Figure 1 This invention provides a schematic diagram of a readout control system suitable for spaceborne CCDs. (See attached diagram.) Figure 1 The system comprises three stacked hardware units, interconnected by inter-board connectors; The first layer of hardware units includes a CCD detector, a front-end signal conditioning circuit, an ADC circuit, and a driver circuit; The second-layer hardware unit includes a power supply circuit and an FPGA main control circuit. The third-layer hardware unit includes power supply circuits and interface circuits; The power supply circuit and power supply circuit are used to convert the system input voltage into the operating voltage of the CCD detector and various circuits; The front-end signal conditioning circuit and ADC circuit are used to optimize the detection data of the CCD detector and send the optimized detection data to the FPGA main control circuit. The FPGA main control circuit is used to send CCD detection control commands to the drive circuit. The driving circuit is used to control the CCD working state of the CCD detector according to the CCD detection control command; The FPGA main control circuit is also used to send optimized detection event data to the host computer through the interface circuit, read the status data of the control system, and receive control commands generated by the host computer based on the optimized detection event data and the status data of the control system.

[0023] It should be noted that space X-ray detection, as an important technical means for astronomical observation and cosmological research, typically relies on orbital telescope satellites to collect and analyze X-rays emitted by celestial bodies, and has significant application value in fields such as cosmological structure exploration and pulsar navigation. Charge-coupled devices (CCDs), with their excellent spectral resolution and good space imaging performance, have become the core detection device in spaceborne low-energy X-ray detection systems.

[0024] With the development of aerospace exploration technology, dedicated X-ray detection CCDs have been gradually put into research and application. However, traditional CCD devices are designed primarily to improve energy resolution, with significant limitations in temporal resolution, making it difficult to meet the requirements of high-time-efficiency detection scenarios. Frame-transfer CCD devices, which have emerged in recent years, support multiple readout modes and can balance energy spectral resolution and temporal resolution, providing a hardware foundation for high-real-time X-ray detection. However, these CCD devices have special requirements in terms of drive timing, multi-mode switching, high-speed data acquisition, low-noise analog conditioning, and onboard power supply and integrated structure. Existing general-purpose readout control systems cannot match these requirements, making it difficult to fully utilize the detection performance of the CCD. Therefore, there is an urgent need to design a dedicated high-speed CCD readout control system to achieve precise driving of frame-transfer CCDs, flexible multi-mode configuration, and high-speed, low-noise readout, thereby meeting the engineering application requirements of high-time-efficiency onboard X-ray detection.

[0025] This invention designs a readout control system suitable for spaceborne CCDs, which can realize the switching of CCD detectors in multiple readout modes. While significantly improving time resolution, it still maintains excellent energy resolution, thereby better meeting the needs of high-time-sensitive X-ray detection applications such as pulsar navigation.

[0026] This invention addresses the high-speed, high-precision readout requirements of frame-transfer CCD detectors, while simultaneously meeting the stringent requirements of long-term reliability, electromagnetic compatibility, and structural compactness for spaceborne applications. It constructs a complete and dedicated readout electronics chain. The system employs a highly integrated, stacked architecture, with an overall shape of a 100mm × 100mm × 100mm cube. Along its height, it is divided into three layers of hardware boards (i.e., three hardware units). Electrical interconnection and mechanical fixation between layers are achieved through 60-pin high-density inter-board connectors. Within a limited volume, it integrates all functions, including detection, signal conditioning, drive control, power conversion, data acquisition, and communication interfaces.

[0027] in: The first hardware unit is the detection and front-end processing layer, which integrates a CCD detector, front-end signal conditioning circuit, ADC circuit and drive circuit, and is responsible for low-noise amplification and clock driving of weak signals. The second-layer hardware unit is the core processing and power supply layer, which includes power supply circuits (i.e., secondary voltage regulation) and FPGA main control circuits, and undertakes analog / digital isolated power supply, data acquisition, digital signal processing and multi-mode control functions. The third-layer hardware unit is the primary power supply and interface layer, which realizes system overcurrent, overvoltage and electromagnetic interference protection, and ensures long-term safe and stable operation in orbit.

[0028] Through the aforementioned layered stacking and integrated design, this system significantly reduces size and weight while achieving power supply noise isolation, signal integrity optimization, and multi-module collaborative operation, fully leveraging the comprehensive performance of the CCD detector in multi-mode readout, high-speed imaging, and high energy resolution.

[0029] In this invention, the power supply circuit and the power supply circuit work together to convert the system input voltage into the operating voltage of the CCD detector and each circuit. The front-end signal conditioning circuit and ADC circuit are used to optimize the detection case data (i.e. the acquired X-ray signal) of the CCD detector and send the optimized detection case data to the FPGA main control circuit. The FPGA main control circuit is used to send CCD detection control commands to the drive circuit. The driving circuit is used to control the CCD working state of the CCD detector according to the CCD detection control command; The FPGA main control circuit is also used to send optimized detection event data to the host computer via the interface circuit, read the status data of the control system, and receive control commands generated by the host computer based on the optimized detection event data and the read status data of the control system. These control commands include CCD detection control commands and system control commands, such as shutting down or starting the system.

[0030] For further explanation of this invention, please refer to [link / reference]. Figure 2 The power supply circuit includes fuses, a current detection circuit, relays, a surge suppression circuit, a first filter circuit, and a DC / DC converter circuit. The system inputs a 42V DC voltage, which is connected to the main circuit via a panel connector. Overcurrent and short-circuit protection are achieved sequentially through fuses. The current detection circuit monitors the operating current in real time, and the relay controls the on / off state of the main circuit. Subsequent voltages pass through a surge suppression circuit to absorb transient overvoltages, a filter circuit to remove high-frequency interference, and finally, a DC / DC converter circuit to regulate and transform the voltage, outputting a stable 24V DC voltage via an inter-board connector, providing reliable power to downstream loads.

[0031] In this invention, the interface circuit includes a receiving chip, a transmitting chip, and an LVDS transmitting chip, wherein: Panel connectors, receiver chips, board-to-board connectors, and FPGA main control circuits form the path for transmitting control commands. The FPGA main control circuit, board-to-board connectors, transmitting chips, and panel connectors form the upload route for reading the status data of the control system. The FPGA main control circuit, board-to-board connectors, LVDS transmitter chip, and panel connectors form an optimized upload path for probe event data.

[0032] See Figure 3 The system is equipped with dual differential communication interfaces to realize low-speed command / telemetry interaction and high-speed probe data transmission respectively, taking into account both anti-interference capability and high-speed transmission requirements in the spaceborne environment.

[0033] After external control commands are input via the panel connector, they are received by the RS422 receiver chip as differential signals. The RS422 differential transmission has strong anti-interference capabilities and long transmission distance, ensuring stable and reliable command transmission in the harsh electromagnetic environment of spacecraft. The received command signals are sent to the FPGA main control circuit via the inter-board connector to complete command parsing and execution.

[0034] The CCD detector's operating status, system voltage, current, and temperature are acquired and encoded by the FPGA, then sent to the RS422 transmitter chip via the board connector. After being converted into differential signals, the signals are transmitted outward through the panel connector, enabling real-time uploading and remote monitoring of the system status.

[0035] The high-speed X-ray detection event data collected by the detector is processed by the FPGA and then sent to the LVDS transmitter chip via the board connector. It is output in a high-speed differential serial mode to meet the transmission requirements of large data volume, high bit rate and low bit error rate. Finally, it is sent out through the panel connector to realize the efficient and stable output of high-speed detection data.

[0036] In this invention, the power supply circuit adopts a multi-stage voltage regulation architecture that completely separates analog power supply and digital power supply, which is used to provide operating voltage for CCD detector, front-end signal conditioning circuit, ADC circuit and FPGA main control circuit.

[0037] As the foundation for stable system operation, the power supply design needs to focus on key issues such as independent power supply for analog and digital circuits, noise isolation, low dropout voltage regulation, and multiple precise power supplies to avoid digital noise crosstalk to the analog front end and ensure the accuracy of detector signal acquisition.

[0038] The analog power supply section adopts a multi-stage voltage regulation and isolated power supply architecture: Two LT8471 switching power supply chips are used for pre-conversion of the system's 24V bus voltage. One LT8471 converts 24V to ±11V, which is then regulated and filtered by linear regulators LT1129 and LT1175 to output a low-noise, high-precision ±10V analog voltage to power the operational amplifier LM6172 in the front-end signal conditioning circuit. The other LT8471 generates ±6V from 24V, which is also regulated by LT1129 and LT1175 to obtain a clean ±5V analog power supply to power the differential amplifier AD8137 and the analog-to-digital converter AD9257.

[0039] Meanwhile, an LM6142 voltage regulator is used to step down the 24V voltage to provide multiple low-current bias and auxiliary power supplies for the front-end signal conditioning circuit, including dedicated analog bias voltages such as VBB, VSS, VOG, VJ, VRD, and VDD.

[0040] For the power supply of the drive circuit, an independent voltage regulation scheme for positive and negative power supplies is adopted: the LT1129 is used to generate a positive power supply from 24V to power the positive terminal of the EL7457 in the drive circuit; the LT337 is used to generate a negative power supply from 24V to power the negative terminal of the EL7457, ensuring the output amplitude and linearity of the drive circuit.

[0041] To suppress the interference of digital circuit switching noise on the analog front end, the system adopts a completely independent design for analog and digital power supplies. The digital section does not share a voltage regulator branch with the analog power supply, but uses a separate LT8610 high-efficiency step-down chip to convert the 24V bus voltage to a 5V digital power supply, dedicated to the main control and digital interface circuits. This achieves power isolation between the analog and digital domains, significantly reduces ground noise and power coupling interference, and improves the overall signal-to-noise ratio and operational stability of the system.

[0042] In this invention, to achieve high-speed, high-precision, and multi-mode readout control of the frame-shifting CCD detector, a Field-Programmable Gate Array (FPGA) is preferred as the core control device, namely the FPGA main control circuit mentioned above. This FPGA has significant advantages such as abundant logic resources, excellent power consumption control, and controllable cost. It integrates a Double Data Rate (DDR) interface compatible with the AD9257 analog-to-digital converter chip, supporting operating frequencies up to 455 MHz, which can meet the stringent requirements of spaceborne applications for data processing speed and real-time performance.

[0043] At the data interaction level, to ensure precise alignment between the ADC sampling data and the FPGA clock, the system performs bit synchronization processing on the ADC input data through the FPGA's built-in IDELAYE2 primitive, eliminating timing offsets between different channels. At the same time, the ISERDESE2 primitive is used to implement frame synchronization, performing serial-to-parallel conversion on the ADC output serial data, ensuring bit and frame synchronization of high-speed data acquisition, laying a solid foundation for subsequent high-precision data processing.

[0044] After data access to the FPGA is synchronized, three core steps need to be executed sequentially: digital correlation double sampling (CDS) processing, background noise cancellation, and common-mode noise cancellation, in order to suppress noise interference during the CCD readout process to the greatest extent possible. First, the signal output by the CCD is differentially sampled and subtracted through digital CDS processing to effectively remove reset noise; Secondly, an adaptive threshold filtering algorithm is used to perform background noise elimination and filter out static background interference. Finally, a common-mode rejection network is used to eliminate common-mode noise, further improving the signal-to-noise ratio.

[0045] After the above noise processing, the FPGA performs event determination on the cleaned valid signal: if a physical event with a signal amplitude exceeding the set threshold is detected, the raw data of the high-speed event is quickly sent to the LVDS transmitter chip for high-speed output.

[0046] In addition, the FPGA also undertakes the core tasks of system control and status feedback: on the one hand, it parses the host computer control commands transmitted through the RS422 interface and completes the dynamic configuration of detector timing mode, programming resistor parameters, etc.; on the other hand, it collects key operating parameters such as system voltage, current, and operating temperature in real time and sends them back to the host computer through the RS422 chip, thereby realizing bidirectional communication between the system and the host computer and supporting on-orbit remote monitoring and parameter debugging.

[0047] Furthermore, the FPGA needs to enable flexible control of the detector's timing drive logic and programmable resistor network, allowing the detection system to seamlessly switch between three modes: full-frame readout mode, time-varying readout mode, and combined readout mode. This will adapt to the different requirements of time resolution and energy spectrum resolution under different observation tasks, and fully tap the comprehensive performance potential of domestic frame transfer CCDs.

[0048] The CCD detector of this invention is a full-frame transfer CCD, a high-speed, low-noise 8-channel frame transfer CCD detector designed specifically for X-ray astronomical observation and energy spectrum analysis. The chip mainly consists of three parts: (1) Illumination Area: used to receive X-ray photons and generate and integrate signal charges; (2) Storage Area: located below the Illumination Area, used to temporarily store and shield signal charges during readout; (3) Output Amplifier: located at the bottom of the chip, with a total of 8 channels, used to convert charge signals into voltage signals and output them.

[0049] To meet high-speed readout requirements, both the photosensitive area and the storage area are designed as 10×10 pixel arrays, with one column at the edge not used for output, resulting in an effective imaging area of ​​8×8 pixels. This design aims to eliminate edge effects and provide assembly tolerances for the mechanical light-blocking structure of the storage area. The physical dimensions of each pixel are 75 μm × 75 μm, consistent with mainstream international devices, facilitating optical system matching.

[0050] In this invention, to adapt to the high-speed timing drive requirements of frame-transfer CCDs and meet the high-speed timing switching specifications of spaceborne X-ray imaging detection, a four-channel MOSFET high-speed driver is selected to uniformly drive and control all multi-channel clock drive signals (I1, I2, S1, S2, RG1, RG2) of the CCD. This invention uses an integrated multi-channel driver chip to replace the traditional hybrid drive architecture built with discrete components, eliminating the shortcomings of traditional solutions such as scattered components, complex wiring, large channel timing deviations, and poor consistency. It not only effectively simplifies the board-level layout of the front-end drive circuit and reduces hardware footprint, optimizing overall wiring and electromagnetic compatibility, but also unifies the electrical characteristics and timing response characteristics of each channel driver chip, significantly improving the driving performance, edge characteristics, and timing synchronization consistency of multi-channel clock signals, ensuring the stability and reliability of the entire CCD charge transfer process.

[0051] For the signal link from the driver output to the CCD detector, a precision matching resistor is connected in series at the output of each drive signal to achieve impedance matching and signal shaping of the drive signal. In spaceborne high-speed timing drive scenarios, impedance mismatch in the drive signal can easily lead to voltage overshoot, ringing, and signal distortion, causing damage to the CCD device gate, introducing readout noise, and interfering with normal charge transfer. At the same time, the resistance value of the matching resistor cannot be too large to avoid excessively slow signal rise and fall rates, limiting the system's maximum readout speed and failing to meet the timing requirements of high-speed imaging. Combining the electrical characteristics of the device, parasitic parameters of the circuit, and CCD drive timing indicators, after multiple rounds of simulation and physical experiment verification and calibration, a 47Ω precision series resistor was finally selected as the unified matching parameter for all channels. This completely suppresses signal overshoot, eliminates transmission ringing, and protects the detector device, while also taking into account the signal edge rise rate, ensuring the steepness and transmission integrity of the high-speed clock timing, perfectly adapting to the timing drive requirements of the multi-mode high-speed readout of this system.

[0052] Before the CCD output signal (i.e., the detected event data, i.e., X-rays) enters the high-speed ADC, it needs to undergo precise analog signal conditioning to amplify weak signals, suppress noise, and provide a stable bias. This system has a dedicated front-end signal conditioning circuit designed for this purpose.

[0053] See Figure 4 The front-end signal conditioning circuit includes an I / V conversion circuit 41, a first isolation circuit 42, a first operational amplifier circuit 43, a second isolation circuit 44, a programmable common-mode modulation circuit 45, a second operational amplifier circuit 46, a voltage divider circuit 47, and a fully differential operational amplifier circuit 48, wherein: The input of the I / V conversion circuit (i.e., R1) is connected to the detection event data output by the CCD detector, and the output is connected to the input of the first DC blocking circuit (i.e., C1). The output of the first DC blocking circuit is connected to the input of the first operational amplifier circuit (i.e., R2, R3, R4 and amplifier O1), and the output of the first operational amplifier circuit is connected to the input of the second DC blocking circuit (i.e., C2). The output of the second DC blocking circuit is connected to the input of the second operational amplifier circuit (i.e., R5, R6 and amplifier O2) and the control terminal of the programmable common-mode adjustment circuit (i.e., R7, R8, R9). The output of the second operational amplifier circuit is connected to the input of the voltage divider circuit (i.e., R10, R11), and the output of the voltage divider circuit is connected to the input of the fully differential operational amplifier circuit (i.e., R12, R13, R14, R15, R16, R17 and O1). The output of the fully differential operational amplifier circuit outputs the differential analog voltage signal transmitted to the ADC circuit.

[0054] As shown in the figure, OS i is the weak current signal output by the CCD detector. The link front end first completes the I / V conversion through the precision resistor R1 to generate the corresponding voltage signal. After the DC component is filtered out by the DC blocking capacitor C1, the voltage signal is sent to the first-stage operational amplifier to complete the 14-fold gain pre-amplification, realizing the initial boost of the weak CCD signal and reducing the noise influence introduced by the subsequent link.

[0055] The signal, after being amplified in the first stage, undergoes secondary DC blocking through the DC blocking capacitor C2, further isolating the DC offset accumulated in the preceding stages. Subsequently, the programmable common-mode adjustment network composed of R7, R8, and R9 calibrates the signal common-mode voltage to the optimal range for the subsequent circuits, before sending it to the second-stage operational amplifier to complete the second-stage 14x fixed-gain amplification. The two-stage amplification links collectively achieve a total signal gain of 196x, fully matching the input amplitude requirements of the downstream ADC.

[0056] The signal, after being amplified by two stages, is compressed by a precision voltage divider circuit composed of R10 and R11, adjusting the peak-to-peak value of the signal to the linear input range of the third-stage operational amplifier. Finally, the third-stage fully differential operational amplifier completes the conversion from single-ended signal to differential signal, outputting a differential analog signal that conforms to the acquisition specifications of the AD9257 analog-to-digital converter at the back end, ensuring the accuracy and linearity of subsequent analog-to-digital conversion.

[0057] In addition, the R8 resistor in the common-mode conditioning network is a programmable device controllable by the FPGA. It can dynamically adjust the common-mode voltage reference in real time according to the signal baseline drift generated when the system switches between different operating modes, effectively suppressing the dynamic range compression problem caused by baseline fluctuations, optimizing the multi-scenario adaptability and working stability of the signal conditioning link, and significantly improving the output signal quality.

[0058] In this invention, the system uses the AD9257 analog-to-digital converter (ADC) as the core acquisition device for the eight-channel detector data. This device has a built-in on-chip sample-and-hold circuit and is specifically designed for low cost, low power consumption, small size and ease of use. It can efficiently complete the synchronous acquisition and digital conversion of analog signals from the eight-channel detectors, providing high-quality digital input signals for subsequent FPGA signal processing. It is a key core component of the entire data acquisition chain.

[0059] In terms of input range, the AD9257 employs a differential input design with an analog input voltage range of 2 Vp-p (peak-to-peak) and a common-mode voltage range of 0.5 V to 1.3 V. This allows it to meet the output signal amplitude requirements of most conventional detectors, achieving effective data acquisition without the need for additional signal conditioning and amplification modules, significantly simplifying system hardware design complexity. Simultaneously, the device boasts a 650 MHz full-power analog bandwidth, accurately capturing high-frequency components in the detector's output signal, avoiding signal distortion caused by insufficient bandwidth, ensuring the integrity and authenticity of the acquired data, and adapting to signal acquisition scenarios for various types of detectors. Furthermore, its differential input resistance is 5.2 kΩ and differential input capacitance is 3.5 pF; these excellent input characteristics effectively reduce the load impact on the detector's output signal, ensuring signal transmission stability.

[0060] In terms of core ADC capabilities, the AD9257 boasts superior conversion performance with a resolution of up to 14 bits and fully guaranteed zero-missing-code characteristics. It enables high-precision quantization of weak detector signals, effectively distinguishing subtle changes in the signal and meeting the demands of high-sensitivity detection scenarios. The device offers two conversion rate specifications: 40 MSPS and 65 MSPS, with the highest conversion rate reaching 65 MSPS. This allows for rapid synchronous acquisition of eight detector signals, avoiding data loss due to insufficient acquisition rate. Regarding dynamic performance, the AD9257 exhibits excellent performance. At the Nyquist frequency, it achieves a signal-to-noise ratio (SNR) of 75.5 dB and a spurious-free dynamic range (SFDR) of 91.6 dBc, effectively suppressing various interferences during signal acquisition and improving the SNR of the acquired data. The typical differential nonlinearity (DNL) is ±0.6 LSB, and the typical integral nonlinearity (INL) is ±1.1 LSB, ensuring the linearity of the analog-to-digital conversion and reducing the impact of quantization errors on data accuracy.

[0061] Furthermore, the AD9257 offers flexible operating characteristics, supporting serial LVDS (default ANSI-644 standard) data output. Its data clock output (DCO) operates at a frequency up to 455 MHz, perfectly compatible with the DDR interface of the XC7A35T FPGA used in the system, enabling high-speed and stable data transmission. The device operates from a single 1.8 V supply, with power consumption as low as 55 mW per channel (65 MSPS mode), and supports independent channel shutdown. Typical power consumption is less than 2 mW when all channels are disabled, meeting the system's low-power design requirements. Simultaneously, programmable control via the SPI serial port enables clock and data alignment, digital test code generation, and other functions, further enhancing the system's acquisition flexibility and scalability. It allows for flexible adjustment of acquisition parameters according to actual detection needs, adapting to eight-channel detector data acquisition tasks in different scenarios.

[0062] In this invention, to ensure the stable and reliable operation of the detector, the power supply voltage provided to the detector by the system must first undergo power supply noise reduction and decoupling processing through an RC low-pass filter circuit (i.e., the second filter circuit). The RC filter circuit, with its simple structure, low power consumption, and wide bandwidth suppression characteristics, can effectively attenuate low-frequency ripple, high-frequency switching noise, and electromagnetic interference (EMI) coupled from the power line on the power rail, filtering out stray interference components in the power supply link, and significantly improving the purity, DC stability, and transient response characteristics of the detector's power supply.

[0063] The output signal quality of the detector is directly and strongly correlated with the power supply quality: a clean and stable power supply can effectively suppress the inherent noise, dark current fluctuations, and output baseline drift introduced by power fluctuations, significantly reducing the noise floor of the entire signal acquisition link; at the same time, it can optimize the photoelectric conversion linearity of the detector, improve the detector's sensitivity to weak signals and effective dynamic range, give full play to the rated performance of the device, and provide high-quality raw input signals for the subsequent signal conditioning link and AD9257 analog-to-digital conversion link, ultimately improving the detection accuracy and data reliability of the entire acquisition system.

[0064] The readout control system for spaceborne CCDs provided by this invention is designed with three stacked hardware units interconnected by board-to-board connectors. The first hardware unit includes a CCD detector, a front-end signal conditioning circuit, an ADC circuit, and a drive circuit. The second hardware unit includes a power supply circuit and an FPGA main control circuit. The third hardware unit includes a power supply circuit and an interface circuit. This design enables the CCD to switch between multiple readout modes, significantly improving time resolution while maintaining excellent energy resolution, thus better meeting the needs of time-sensitive X-ray detection applications such as pulsar navigation.

[0065] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A readout control system suitable for spaceborne CCDs, characterized in that, It includes three stacked hardware units, interconnected between the layers via inter-board connectors, wherein; The first layer of hardware units includes a CCD detector, a front-end signal conditioning circuit, an ADC circuit, and a driver circuit; The second-layer hardware unit includes a power supply circuit and an FPGA main control circuit. The third-layer hardware unit includes power supply circuits and interface circuits; The power supply circuit and the power supply circuit are used to convert the system input voltage into the operating voltage of the CCD detector and each circuit. The front-end signal conditioning circuit and the ADC circuit are used to optimize the detection case data of the CCD detector and send the optimized detection case data to the FPGA main control circuit. The FPGA main control circuit is used to send CCD detection control commands to the driving circuit; The driving circuit is used to control the CCD working state of the CCD detector according to the CCD detection control command; The FPGA main control circuit is also used to send optimized detection case data and read the status data of the control system to the host computer through the interface circuit, and to receive control commands generated by the host computer based on the optimized detection case data and the read status data of the control system.

2. The readout control system suitable for spaceborne CCDs according to claim 1, characterized in that, The power supply circuit adopts a multi-stage voltage regulation architecture that completely separates analog power and digital power, and is used to provide operating voltage for the CCD detector, front-end signal conditioning circuit, ADC circuit and FPGA main control circuit.

3. The readout control system suitable for spaceborne CCDs according to claim 1 or 2, characterized in that, The power supply circuit includes a fuse, a current detection circuit, a relay, a surge suppression circuit, a first filter circuit, and a DC / DC conversion circuit. It is used to output a stable voltage to the power supply circuit through the system input power supply via the fuse, current detection circuit, relay, surge suppression circuit, first filter circuit, and DC / DC conversion circuit.

4. The readout control system suitable for spaceborne CCDs according to claim 3, characterized in that, The front-end signal conditioning circuit includes an I / V conversion circuit, a first isolation circuit, a first operational amplifier circuit, a second isolation circuit, a programmable common-mode modulation circuit, a second operational amplifier circuit, a voltage divider circuit, and a fully differential operational amplifier circuit, wherein: The input terminal of the I / V conversion circuit is connected to the detection event data output by the CCD detector, and the output terminal is connected to the input terminal of the first DC blocking circuit. The output terminal of the first DC blocking circuit is connected to the input terminal of the first operational amplifier circuit, the output terminal of the first operational amplifier circuit is connected to the input terminal of the second DC blocking circuit, the output terminal of the second DC blocking circuit is connected to the input terminal of the second operational amplifier circuit and the control terminal of the programmable common-mode adjustment circuit. The output terminal of the second operational amplifier circuit is connected to the input terminal of the voltage divider circuit, the output terminal of the voltage divider circuit is connected to the input terminal of the fully differential operational amplifier circuit, and the output terminal of the fully differential operational amplifier circuit outputs the differential analog voltage signal transmitted to the ADC circuit.

5. The readout control system suitable for spaceborne CCDs according to claim 4, characterized in that, The programmable common-mode regulation circuit includes a programmable resistor, which is controlled by the FPGA main control circuit.

6. The readout control system suitable for spaceborne CCDs according to claim 5, characterized in that, The driving circuit includes a driving module and a suppression resistor. The driving module is used to drive the CCD detector to open / close, switch modes, and operate clock signals according to CCD detection control commands. The suppression resistor is connected to the output terminal of the driving module and is used to suppress overshoot of the operating clock signal.

7. The readout control system suitable for spaceborne CCDs according to claim 6, characterized in that, The interface circuit includes a receiving chip, a transmitting chip, and an LVDS transmitting chip, wherein: Panel connectors, receiver chips, board-to-board connectors, and FPGA main control circuits form the path for transmitting control commands. The FPGA main control circuit, board-to-board connectors, transmitting chips, and panel connectors form the upload route for reading the status data of the control system. The FPGA main control circuit, board-to-board connectors, LVDS transmitter chip, and panel connectors form an optimized upload path for probe event data.

8. The readout control system suitable for spaceborne CCDs according to claim 7, characterized in that, The power supply circuit is connected to the CCD detector through a second filter circuit.

9. The readout control system suitable for spaceborne CCDs according to claim 1 or 8, characterized in that, The status data of the readout control system includes the CCD operating status of the CCD detector, the system voltage, current, and temperature.

10. The readout control system suitable for spaceborne CCDs according to claim 9, characterized in that, The CCD detector is a full-frame transfer type CCD.

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