A PCB intelligent manufacturing production line control system based on digital twins

Abstract

This invention relates to the field of PCB manufacturing technology, specifically to a PCB intelligent manufacturing production line control system based on digital twins. The system includes a data acquisition module for acquiring the height and coordinates of each boss on the PCB board; a twin construction module for parsing PCB design files to obtain a boss array, extracting the layout and height design of the boss array, layer stack-up structure and routing topology data, and signal integrity constraint values, thereby establishing a spatial reference grid and a digital twin, identifying signal transmission paths, and extracting the main routing direction; and a decision module for assessing the margin of signal integrity constraint values ​​based on electrical performance influence parameters, combining trend direction components with the directional correlation analysis of the main routing direction, determining the compensation priority of each grid region in the spatial reference grid, and outputting a regional orientation process compensation scheme and design optimization suggestions.

Description

Technical Field

[0001] This invention relates to the field of PCB manufacturing technology, specifically to a PCB intelligent manufacturing production line control system based on digital twins. Background Technology

[0002] A PCB smart manufacturing production line typically includes multiple process steps such as solder paste printing, component mounting, reflow soldering, optical inspection, and electrical testing. Among these, the yield and accuracy of the component mounting step directly affect the subsequent soldering quality and finished product performance.

[0003] In the device mounting process, bosses serve as a key interconnection interface structure between the chip package and the PCB substrate. They not only provide electrical conduction between the device and the substrate but also offer mechanical support. Their high consistency has become a core process indicator that determines the mounting yield and high-speed signal integrity.

[0004] Currently, the detection of boss height consistency mainly relies on optical or laser measurement equipment to obtain the measured height data of each boss, and then statistical analysis is used to make a macroscopic evaluation of the overall board quality. However, the geometric inspection data at the manufacturing end and the electrical design parameters at the PCB design end are isolated from each other. The impact assessment of boss height deviation cannot be accurately linked to the specific signal transmission path level, and the production line has difficulty in directional control of boss height deviation based on electrical design parameters, resulting in improper allocation of compensation resources.

[0005] Therefore, the present invention provides a PCB intelligent manufacturing production line control system based on digital twins. Summary of the Invention

[0006] In order to overcome the shortcomings of the prior art, at least one technical problem raised in the background art is solved.

[0007] The technical solution adopted by the present invention to solve its technical problem is: a PCB intelligent manufacturing production line control system based on digital twin, including: a data acquisition module: used to acquire the height value and coordinates of each boss on the PCB board surface;

[0008] Twin building module: used to parse PCB design files to obtain boss arrays, and extract the layout and height design, stack-up structure and routing topology data of the boss arrays, and signal integrity constraint values. Based on this, a spatial reference grid and digital twin are established, and signal transmission paths are identified and routing main directions are extracted.

[0009] Trend Analysis Module: Used to synchronize height values ​​and coordinates to the digital twin, construct the boss height field based on the spatial reference grid and perform directional trend decomposition, extracting systematic trend components and trend direction components;

[0010] The coupling mapping module is used to determine the electrical performance impact parameters caused by the aforementioned deviations on the transmission path in a digital twin, based on the spatial distribution deviation of the boss height corresponding to the systematic trend component and the individual deviation of each boss relative to the height design, combined with the wiring topology data.

[0011] The decision module assesses the margin of signal integrity constraints based on electrical performance impact parameters, combines the directional correlation analysis of trend direction components and main wiring direction, determines the compensation priority of each grid region in the spatial reference grid, and outputs regional orientation process compensation schemes and design optimization suggestions.

[0012] Preferably, the digital twin in the twin construction module is constructed in the following way:

[0013] S201. Based on the layout data of the boss array, determine the coverage area of ​​the boss array in the plate coordinate system;

[0014] S202. Divide the coverage area into regular grids according to the horizontal and vertical arrangement spacing of the protrusion array, establish the mapping relationship between the two-dimensional design coordinates of each protrusion unit and the corresponding grid nodes, and obtain the spatial reference grid.

[0015] S203. Construct a boss geometric model based on layout and height design data, construct a stacked structure model based on stacked structure data, and construct a wiring topology model based on wiring topology data. Spatially register the boss geometric model, stacked structure model, and wiring topology model through a unified board coordinate system to form a digital twin.

[0016] Preferably, the digital twin identifies the signal transmission path and extracts the main direction of wiring, specifically as follows:

[0017] First, based on the signal rate and signal type of the signal carried by the signal transmission path, the signal integrity constraint level of each signal transmission path is determined, and the signal transmission path with the strict constraint level is selected as the target signal transmission path.

[0018] The signal types include clock signals, reset signals, high-speed differential pair signals, power signals, and general data signals. Then, the two-dimensional coordinates of the center of each pad and the inflection point of the trace on the target signal transmission path are extracted and least-squares linear fitting is performed. The direction angle of the fitted straight line is used as the main routing direction of the target signal transmission path.

[0019] Preferably, the trend analysis module constructs the boss height field based on a spatial reference grid, and the specific method is as follows:

[0020] The height value and coordinates of each boss are mapped to the corresponding grid node of the spatial reference grid. For grid nodes without bosses, interpolation is performed based on the known boss height values ​​in their neighborhood using inverse distance weighting.

[0021] All grid nodes of the spatial reference grid have corresponding height values, and the two-dimensional height distribution formed by each grid node and its corresponding height value is used as the boss height field.

[0022] Preferably, the trend analysis module performs directional trend decomposition on the boss height field, specifically as follows:

[0023] The boss height field is smoothed using a two-dimensional quadratic polynomial surface containing constant terms, first-order terms, second-order terms, and cross terms; the smoothed surface is used as the systematic trend component, the gradient vector of the systematic trend component is calculated, and the direction angle of the gradient vector is used as the trend direction component.

[0024] Preferably, the electrical performance parameters in the coupling mapping module include the signal path length difference and the impedance change rate at the connection point:

[0025] The signal path length difference refers to the deviation of the actual signal transmission path length relative to the preset path length after the mounting device is spatially tilted due to the coplanarity deviation of the boss array caused by the spatial distribution deviation of the boss height.

[0026] The impedance change rate at the connection point refers to the ratio of the change in the actual impedance value at the interface relative to the preset impedance value after the effective dielectric layer thickness changes due to the equivalent height offset caused by the deviation of each individual boss at the interconnect interface; the equivalent height offset is the average absolute value of the individual deviations of each boss covered by the interconnect interface.

[0027] Preferably, the coupling mapping module is further used for:

[0028] For each of the signal transmission paths, the coplanarity deviation of the protrusion array in the region is determined based on the measured height of the protrusions in the grid area it passes through, and the signal path length difference is calculated based on the preset path length; and for each of the protrusion interconnection interfaces, the spatial distribution gradient is determined based on the individual deviation of each protrusion at the corresponding position, and the impedance change rate at the connection point is calculated based on the dielectric layer thickness.

[0029] Preferably, the decision module determines the compensation priority of each grid region in the spatial reference grid, and the specific method is as follows:

[0030] The signal integrity constraints include transmission delay constraints and impedance constraints.

[0031] The signal path length difference of each grid region in the spatial reference grid is converted into an equivalent transmission delay difference by combining the signal propagation speed in the corresponding medium layer. Then, the ratio of the equivalent transmission delay difference to the transmission delay constraint value is calculated to obtain the transmission delay dimension margin consumption.

[0032] The impedance deviation at the interface is calculated by multiplying the impedance mutation rate at the connection point by the preset impedance value of the corresponding transmission line. The impedance deviation at the interface is then compared with the upper limit of the impedance deviation allowed by the impedance constraint value to obtain the impedance dimension margin consumption.

[0033] The transmission delay dimension margin consumption and the impedance dimension margin consumption are weighted and combined to obtain the comprehensive margin consumption.

[0034] Then, the vector angle between the trend direction component and the main wiring direction is calculated to determine the directional correlation between the boss height trend direction and the signal transmission path direction; finally, the compensation priority of each grid region in the spatial reference grid is determined by combining the margin consumption degree and the directional correlation degree.

[0035] Preferably, the method for generating the region-oriented process compensation scheme in the decision-making module is as follows:

[0036] Based on the ranking result of the compensation priority, differentiated compensation parameters are configured for each grid region. The compensation parameters include compensation accuracy and process margin. The compensation parameters of each grid region are assembled into the region-oriented process compensation scheme.

[0037] Preferably, the decision module is further used for:

[0038] Based on the directional correlation analysis, the target signal transmission path affected by the boss height deviation is determined, and the margin consumption of the target signal transmission path is matched and evaluated with the compensation accuracy of the corresponding grid area.

[0039] Based on the matching evaluation results, suggestions for routing layer adjustment, routing topology reconstruction, or layer stack-up optimization for the target signal transmission path are generated and fed back to the PCB design end.

[0040] This invention provides a PCB intelligent manufacturing production line control system based on digital twins. It has the following beneficial effects:

[0041] 1. This invention constructs a digital twin that integrates manufacturing geometry information and electrical design information by spatially registering and fusing boss geometric data, stacked structure data and wiring topology data in a unified board coordinate system. This solves the problem of isolated manufacturing inspection data and electrical design data in the prior art and provides a unified computing carrier for assessing the electrical impact of boss height deviation.

[0042] 2. This invention calculates the vector angle between the trend direction of the boss height and the main direction of the signal transmission path wiring, and associates the compensation priority with the critical path with the highest signal integrity requirements. This enables the area orientation process compensation to accurately target the path area most severely affected by the boss height deviation, avoiding the misallocation of compensation resources caused by sorting only by the deviation magnitude.

[0043] 3. When the process compensation capability is insufficient to restore the signal integrity margin, the present invention generates suggestions for routing layer adjustment, routing topology reconstruction or stack-up structure optimization to the PCB design end, realizing bidirectional driving of the digital twin on the physical production line and PCB design end, and solving the limitation of the separation between manufacturing compensation and design optimization in the prior art. Attached Figure Description

[0044] Figure 1 This is a system flowchart of the present invention;

[0045] Figure 2 This is a schematic diagram of the coupling mapping of the present invention;

[0046] Figure 3 This is a schematic diagram illustrating the compensation priority determination and decision-making process of the present invention. Detailed Implementation

[0047] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0048] like Figures 1 to 3 This invention proposes a PCB intelligent manufacturing production line control system based on digital twins, comprising: a data acquisition module for acquiring the height value and coordinates of each boss on the PCB board surface; the height value is the measured height value, and the coordinates are two-dimensional spatial coordinates;

[0049] Twin building module: used to parse PCB design files to obtain boss arrays, and extract the layout and height design, stack-up structure and routing topology data of the boss arrays, and signal integrity constraint values. Based on this, a spatial reference grid and digital twin are established, and signal transmission paths are identified and routing main directions are extracted.

[0050] Trend Analysis Module: Used to synchronize height values ​​and coordinates to the digital twin, construct the boss height field based on the spatial reference grid and perform directional trend decomposition, extracting systematic trend components and trend direction components;

[0051] The coupling mapping module is used to determine the electrical performance impact parameters caused by the aforementioned deviations on the transmission path in a digital twin, based on the spatial distribution deviation of the boss height corresponding to the systematic trend component and the individual deviation of each boss relative to the height design, combined with the wiring topology data.

[0052] The decision module assesses the margin of signal integrity constraints based on electrical performance impact parameters, combines the directional correlation analysis of trend direction components and main wiring direction, determines the compensation priority of each grid region in the spatial reference grid, and outputs regional orientation process compensation schemes and design optimization suggestions.

[0053] It should be noted that the 'boob' mentioned in this invention refers to a conductive protrusion structure on the PCB board surface used for chip packaging and substrate interconnection, including but not limited to BGA solder balls, copper pillar bumps, gold bumps and other interconnection protrusion structures. The boss height refers to the vertical distance of the top of the conductive protrusion structure relative to the substrate reference plane.

[0054] The construction method of digital twins is as follows:

[0055] S201. Based on the layout data of the boss array, determine the coverage area of ​​the boss array in the board coordinate system; specifically, extract the two-dimensional design coordinates of the center point of each boss unit from the pad / boss layer of the PCB design file (such as Gerber format or ODB++ format). And determine the smallest bounding rectangle of the boss array in the plate coordinate system as the coverage area;

[0056] S202. Divide the coverage area into regular grids according to the horizontal and vertical spacing of the protrusion array, establish the mapping relationship between the two-dimensional design coordinates of each protrusion unit and the corresponding grid nodes, and obtain the spatial reference grid; wherein the horizontal spacing is used as the basis for the grid. and vertical spacing Using the grid step size, the coverage area is divided into an M×N two-dimensional regular grid, and a one-to-one mapping relationship is established between the two-dimensional design coordinates of the boss element and the nearest neighbor grid node.

[0057] S203. Construct a boss geometric model based on layout and height design data, construct a stacked structure model based on stacked structure data, and construct a wiring topology model based on wiring topology data. Spatially register the boss geometric model, stacked structure model, and wiring topology model through a unified board coordinate system to form a digital twin.

[0058] The geometric model of the boss includes the spatial location and height design value of the boss, and the stacked structure model includes the number and thickness of the dielectric layers. It should be noted that, in the embodiments of the present invention, the dielectric layer refers to the insulating material layer between adjacent conductive copper layers in a PCB multilayer board; the number of layers refers to the total number of insulating material layers, and the thickness refers to the thickness value of each insulating material layer.

[0059] During the coupling mapping process, the dielectric layer thickness is used to calculate the effective dielectric pitch change caused by the boss height deviation, thereby determining the impedance change rate at the connection point; the wiring topology model includes the network node coordinates of the signal transmission path;

[0060] It should be noted that the signal transmission path refers to the complete conductive path connecting the signal transmitter and receiver on the PCB, including trace segments and vias; network node coordinates refer to the two-dimensional coordinates of each feature point on the signal transmission path in the board coordinate system, and the feature points include at least the pad center, via center and trace inflection point.

[0061] During the coupling mapping process, network node coordinates are used to determine the spatial proximity between each boss unit and the signal transmission path, so as to evaluate the physical impact of the boss height deviation on a specific signal transmission path.

[0062] Furthermore, spatial registration involves unifying the three models into a plane coordinate system with one corner of the covered area as the origin, the horizontal axis as the x-axis, and the vertical axis as the y-axis.

[0063] Therefore, by using a unified board coordinate system to spatially register and fuse boss geometric data, stack-up structure data, and wiring topology data, the problem of isolated manufacturing-end geometric inspection data and electrical design data in existing technologies is solved. On this basis, the measured boss height data is synchronously injected into the digital twin, so that the boss height attribute in the digital space is consistent with the physical entity, providing a unified computing carrier for the directional trend decomposition of the boss height field and the correlation analysis between the main wiring direction of the signal transmission path.

[0064] The digital twin identifies the signal transmission path and extracts the main direction of wiring, specifically:

[0065] Based on the level of signal integrity constraint values, target signal transmission paths are selected from the cabling topology data, and the main direction of the target signal transmission path is determined by fitting the main direction of the cabling based on the coordinates of the cabling nodes of the target signal transmission path.

[0066] Specifically, the wiring topology data includes the network connections of all signal transmission paths on the PCB board. However, not all signal transmission paths are equally sensitive to boss height deviations: paths carrying low-speed signals or general data signals are more tolerant of boss coplanarity deviations, while paths carrying high-speed signals, clock signals, reset signals, or high-speed differential pair signals are significantly sensitive to subtle changes in the spatial distribution of boss heights.

[0067] Performing indiscriminate coupling analysis on all paths would result in a large amount of redundant computation and would fail to accurately pinpoint the area where manufacturing deviations pose the most serious threat to signal integrity. Therefore, this invention provides a technical means to filter target transmission paths and extract their main wiring direction based on signal integrity constraint levels:

[0068] Signal integrity constraints refer to the electrical performance boundary conditions set during the PCB design phase to ensure signal transmission quality, including impedance constraints and transmission delay constraints.

[0069] Signal integrity constraint levels are based on the signal rate and signal type of the signals carried in the signal transmission path, and are used to classify the strictness of signal integrity constraint values. Signal types include clock signals, reset signals, high-speed differential pair signals, power signals, and general data signals.

[0070] Signal transmission paths carrying clock signals, reset signals, high-speed differential pair signals, or signal transmission paths with a signal rate not lower than a preset rate threshold, have a strict constraint level for signal integrity; all other signal transmission paths have a general constraint level. The target signal transmission path is the signal transmission path with a strict constraint level.

[0071] The preset rate threshold is determined based on the signal integrity design specifications adopted by the PCB design. For example, for system designs using the Intel PDG specification, the preset rate threshold can be set to 1 Gbps; for high-speed designs using the IPC-2251 standard, the preset rate threshold can be set to 500 Mbps. In practical applications, this threshold is determined by the designer during the PCB design phase based on the sensitivity analysis results of signal rate and boss height tolerance, and is imported into the digital twin along with the routing topology data.

[0072] The main direction fitting method is as follows: obtain the two-dimensional coordinates of each routing node on the target signal transmission path, perform linear regression on the two-dimensional coordinates, and use the direction angle of the straight line obtained by regression as the main routing direction of the target signal transmission path; the routing node includes at least the two-dimensional coordinates of the pad center, via center and trace inflection point on the target signal transmission path; linear regression is a conventional technique in this field and will not be elaborated here.

[0073] Therefore, by classifying and fitting the main direction of the signal transmission path, the priority of subsequent regional orientation process compensation is associated with the critical path with the highest signal integrity requirements. This accurately locates the area where the spatial distribution deviation of the boss height has the most serious impact on signal transmission, significantly improving the accuracy and efficiency of manufacturing deviation detection and compensation.

[0074] The height field of the boss is constructed as follows:

[0075] The height value and coordinates of each boss are mapped to the corresponding grid node of the spatial reference grid. For grid nodes without bosses, interpolation is performed based on the known boss height values ​​in their neighborhood using inverse distance weighting. This ensures that all grid nodes of the spatial reference grid have corresponding height values, and the two-dimensional height distribution formed by each grid node and its corresponding height value is used as the boss height field.

[0076] Specifically, since the boss height value collected by the data acquisition module is discrete sampling data, that is, it only has height information at the boss placement location, it cannot directly reflect the continuous distribution pattern of the boss height along the spatial direction on the physical board surface; moreover, the impact of boss height deviation on signal integrity is not determined by the isolated deviation of a single boss, but is dominated by the macroscopic trend of the boss height continuously changing in a specific spatial direction on the board surface.

[0077] Therefore, in the digital twin, the physical board surface is represented by a spatial reference grid, and a continuous boss height field covering the area of ​​the physical board surface is constructed by interpolation.

[0078] Specifically, the measured height value and two-dimensional spatial coordinates are mapped to the grid node where the corresponding boss unit is located in the spatial reference grid through the plate coordinate system. If a boss has been set at the grid node (m,n), the measured height value of the boss is directly assigned.

[0079] For a grid node (m,n) without a boss, take its K nearest neighbor grid nodes with known boss heights and fill them using inverse distance weighted interpolation: ,in The height value of the known boss mesh node in the k-th neighborhood is given in μm. is the Euclidean distance between the blank grid node (m,n) and the known protrusion grid node in the k-th neighborhood, in μm. The Euclidean distance is calculated from the difference in the two-dimensional coordinates of the two grid nodes; K is the number of known protrusion grid nodes in the neighborhood, preferably K=4 (four neighborhoods) or K=8 (eight neighborhoods).

[0080] This is then used to ensure that all grid nodes of the spatial reference grid have corresponding height values, and that the two-dimensional height distribution formed by each grid node and its corresponding height value is... As the height field of the protrusion.

[0081] Therefore, by mapping the discrete measured height values ​​of the bosses to a continuous two-dimensional height distribution, a continuously differentiable computational object is provided for subsequent directional trend decomposition. This ensures that the extraction of systematic trend components can accurately reflect the macroscopic law of the continuous change of boss height along the board surface space, and avoids the distortion of trend decomposition caused by data discreteness.

[0082] The trend analysis module performs directional trend decomposition on the boss height field, specifically as follows:

[0083] The height field of the boss is smoothed using a two-dimensional polynomial surface. The smoothed surface is used as the systematic trend component, and the gradient direction angle of the systematic trend component is calculated as the trend direction component.

[0084] Furthermore, since the boss height field contains both the systematic trend of continuous change in boss height along a specific spatial direction and random fluctuations caused by local process variations, directly performing directional analysis on the original height field will cause the random fluctuations to mask the true directional characteristics of the systematic trend, leading to biases in subsequent directional correlation analysis.

[0085] Therefore, smoothing is required: using the plate coordinates of each grid node in the boss height field as the independent variable and the corresponding height value as the dependent variable, a two-dimensional quadratic polynomial surface fitting method is used to smooth the boss height field; two-dimensional quadratic polynomial surface fitting is a conventional technique in this field, and the expression for the obtained systematic trend component T(x,y) is as follows:

[0086] ,in , , , , and The coefficients are polynomials, which are determined by least squares fitting. The trend direction component θ is obtained by calculating its gradient direction angle, using the systematic trend component T(x,y) as a smooth surface.

[0087] It should be noted that the systematic trend component is based on the macroscopic height distribution of the boss array on the board surface. It separates the spatial distribution deviation of the boss height from individual random fluctuations, serving as the input basis for the subsequent coupling mapping module to evaluate the physical impact of the boss height spatial distribution deviation on the signal transmission path. Simultaneously, to attribute the spatial direction of the systematic trend component for subsequent directional correlation analysis, this embodiment of the invention calculates the gradient direction angle of the systematic trend component to determine the trend direction component. :

[0088] Where T is the systematic trend component, Let be the partial derivative along the x-direction. Let be the partial derivative along the y-direction. The trend direction component, i.e., the gradient direction angle, is used to indicate the main direction in which the spatial gradient of the boss height changes most drastically; and the role of the trend direction component is to serve as the direction benchmark for direction correlation analysis in the subsequent decision module.

[0089] This design filters out local random fluctuations and extracts systematic trend components through two-dimensional polynomial surface fitting, ensuring that subsequent coupling mapping is based on the macroscopic spatial distribution law of the boss height rather than local noise. At the same time, the trend direction component is quantified by gradient direction angle, providing a clear and calculable direction reference for the decision module, enabling the regional orientation process compensation to accurately point to the signal transmission path most severely affected by the boss height deviation.

[0090] The electrical performance parameters affecting the coupling mapping module include the signal path length difference and the impedance abrupt change rate at the connection point:

[0091] The signal path length difference refers to the deviation of the actual signal transmission path length relative to the preset path length after the mounting device is spatially tilted due to the deviation in the coplanarity of the boss array caused by the deviation in the spatial distribution of boss height.

[0092] The impedance change rate at the connection point refers to the ratio of the change in the actual impedance value at the interface relative to the preset impedance value after the effective dielectric layer thickness changes due to the equivalent height offset caused by the deviation of each individual boss at the interconnect interface; the equivalent height offset is the average absolute value of the individual deviations of each boss covered by the interconnect interface.

[0093] Specifically, based on the systematic trend component and trend direction component extracted by the trend analysis module, in order to determine the true impact of the protrusion manufacturing deviation on the signal transmission quality, this embodiment of the invention further provides a coupling mapping module;

[0094] Moreover, since the trend analysis module has identified the macroscopic spatial distribution pattern of the boss height from a geometric perspective, whether the boss deviation in the manufacturing process ultimately leads to signal integrity degradation depends on the electrical impact of the deviation on the specific signal transmission path.

[0095] Meanwhile, the wiring topology data records the preset path length and network node coordinates of each signal transmission path, providing a spatial basis for orienting the geometric deviation of the boss to a specific signal path. Therefore, in the digital twin, the coupling mapping module, in conjunction with the wiring topology data, maps the geometric deviation of the boss into a parameter affecting the electrical performance of the signal transmission path.

[0096] Furthermore, boss geometric deviations include two categories: the first is the spatial distribution deviation of boss height, which is the macroscopic height fluctuation of the boss array on the board surface space characterized by the system trend component. Its direct consequence is the disruption of the coplanarity of the boss array, thereby causing spatial tilting of the mounted devices. The second is the individual deviation, which is the deviation of the measured height value of each boss from the height design data, forming a local height gradient in space. Since the physical mechanisms of the above two types of deviations are different, their electrical impact on signal transmission is also different, so they need to be mapped separately.

[0097] Specifically, the spatial distribution deviation of the boss height mainly affects the path length of signal transmission by changing the device mounting posture; while the deviation of individual components mainly affects the impedance continuity of the connection point by changing the local geometry at the interconnect interface. Therefore, combined with the wiring topology data, the two types of deviations are mapped to the following electrical performance impact parameters respectively.

[0098] Firstly: the difference in signal path length This is caused by the coplanarity variation resulting from the spatial distribution deviation of the boss height, leading to device spatial tilt and causing the actual signal transmission path length to be relative to the preset path length. This results in a deviation, therefore the coupling mapping module combines the preset path length in the wiring topology data. Determine the difference in signal path length. ,in This represents the coplanarity deviation of the boss array, in μm. The preset path length for signal transmission, in μm; This is the design value for the boss height, in μm; These are dimensionless geometric mapping coefficients related to the device package size.

[0099] The coplanarity deviation of the boss array This refers to using the least-squares fitting plane of the measured height values ​​of all bosses within the area where the boss array is located as the reference plane, and the sum of the maximum positive deviation and the maximum negative deviation of the measured height values ​​of each boss relative to the reference plane as the local coplanarity deviation of the path.

[0100] Geometric mapping coefficients The α value is retrieved from a preset mapping table based on the package type of the mounted device. The preset mapping table includes: α values ​​of 0.8~1.2 for QFN packages, 1.0~1.5 for BGA packages, and 1.2~1.8 for LGA packages.

[0101] Secondly: impedance change rate at connection points It is the actual impedance value at the interface relative to the preset impedance value after the change in the effective dielectric layer thickness caused by the average absolute value of the deviation of each individual boss at the interconnect interface (i.e., the equivalent height offset of the interface). The rate of change; the mean absolute value of the deviation of each boss unit at the interconnect interface. (Unit: μm) is the average of the absolute values ​​of the differences between the measured height values ​​of all bosses covered by the interconnect interface and the designed height values.

[0102] The coupling mapping module combines the preset effective dielectric layer thickness in the stacked structure data. (Unit: μm), determine the impedance change rate at the connection point using the following formula. ; The impedance mapping coefficients associated with the transmission line structure are dimensionless. It is a dimensionless relative change ratio;

[0103] The impedance mapping coefficient β is obtained from a preset mapping table based on the transmission line structure type. The preset mapping table includes: β values ​​of 0.5~0.8 for microstrip lines, β values ​​of 0.3~0.6 for striplines, and β values ​​of 0.4~0.7 for coplanar waveguides.

[0104] Therefore, by distinguishing between the macroscopic distribution characteristics and local gradient characteristics of boss height deviation, and mapping them respectively to signal path length difference and connection point impedance abrupt change rate, the coupling mapping module achieves cross-domain quantitative conversion from the manufacturing geometry domain to the electrical performance domain. This enables the subsequent decision-making module to perform margin assessment and compensation priority determination based on the actual electrical impact on signal integrity.

[0105] The coplanarity deviation of each signal transmission path is then determined by the difference between the maximum and minimum measured heights of all bosses within the grid region traversed by the path in the spatial reference grid; the fluctuation amplitude of the systematic trend component within this grid region reflects the coplanarity deviation.

[0106] The coupling mapping module performs the following mappings in the digital twin: It maps the coplanarity deviation of the boss array to each signal transmission path, and determines the signal path length difference by combining the preset path length in the wiring topology data; simultaneously, it maps the spatial distribution gradient of the individual unit deviation to the boss interconnect interface, and determines the impedance abrupt change rate at the connection point by combining the dielectric layer thickness in the stack-up structure data. The coplanarity deviation is calculated from the spatial distribution deviation of the boss height, and the spatial distribution gradient is obtained by the differential operation of the individual unit deviations on the board surface space.

[0107] The methods for determining the compensation priority for each region are as follows:

[0108] Signal integrity constraints include transmission delay constraints and impedance constraints;

[0109] The signal path length difference of each grid region in the spatial reference grid is combined with the signal propagation speed in the corresponding dielectric layer to convert it into an equivalent transmission delay difference (the propagation speed is determined by the effective dielectric constant in the stacked structure data). Then, the ratio of the equivalent transmission delay difference to the transmission delay constraint value is calculated to obtain the transmission delay dimension margin consumption.

[0110] The impedance dimension margin consumption is calculated by comparing the impedance deviation at the interface reflected by the impedance mutation rate at the connection point with the upper limit of the impedance deviation allowed by the impedance constraint value. Both the transmission delay dimension margin consumption and the impedance dimension margin consumption are dimensionless relative margin consumption ratios. The two are weighted and combined to obtain the comprehensive margin consumption.

[0111] Then, the vector angle between the trend direction component and the main wiring direction is calculated to determine the directional correlation between the boss height trend direction and the signal transmission path direction.

[0112] Finally, by combining the margin consumption degree and the directional correlation degree, the compensation priority of each grid region in the spatial reference grid is determined.

[0113] Specifically, the electrical performance impact parameters output by the above coupling mapping module reflect the degree of electrical impact of the boss deviation on each signal transmission path. However, the threat level of the boss deviation to signal integrity is not the same in different grid areas, and the impact of the boss height trend in the same area on the signal path is significantly different. Therefore, if compensation is uniformly performed based solely on the magnitude of the electrical performance impact parameters, it will be impossible to distinguish the most critical path area under the most serious threat, resulting in improper allocation of compensation resources.

[0114] Therefore, this embodiment of the invention uses both margin consumption degree and directional correlation degree as indicators for comprehensive evaluation;

[0115] Among them, the overall margin consumption ;in and These are the weighting coefficients for the transmission delay dimension and the impedance dimension, respectively, and their sum is 1; For transmission delay dimension margin consumption, This refers to the margin of consumption in the impedance dimension. and Determined based on the signal type of the target signal transmission path: high-speed clock signal is taken =0.7、 =0.3; High-speed data signal acquisition =0.3、 =0.7; generally, high-speed signals take... =0.5、 =0.5.

[0116] Vector angle ,in The trend direction component is expressed in radians or degrees. The main direction of the wiring for signal transmission path, unit and Consistent; The range of values ​​is , The smaller the value, the more closely the direction of the boss height gradient in the grid region matches the direction of the signal transmission path, and the greater the cumulative impact of the spatial distribution deviation of the boss height on the path.

[0117] The directional correlation is This indicates the degree of alignment between the height trend of the boss and the direction of the signal transmission path. exist Within the range, it monotonically increases as the included angle decreases;

[0118] Finally, priority indices are constructed and sorted. , Dimensionless;

[0119] Then, the grid regions are sorted in descending order according to the priority index P. The larger the priority index P value, the greater the cumulative threat of the boss deviation to signal integrity, and the higher the compensation priority.

[0120] Therefore, by weighted synthesis, the overall margin consumption is determined, which quantifies the threat level of the boss deviation to signal integrity; the direction matching degree is quantified by the cosine of the vector angle; the priority index constructed by the product of the two integrates the two indicators into a single ranking criterion, realizing continuous priority ranking without threshold judgment, so that the compensation is accurately directed to the most severely affected and most sensitive key signal path area.

[0121] The method for generating a region-oriented process compensation scheme is as follows:

[0122] Based on the ranking of compensation priorities, differentiated compensation parameters are configured for each grid region. The compensation parameters include compensation accuracy and process margin. The compensation parameters of each grid region are then assembled into a region-oriented process compensation scheme.

[0123] Specifically, based on the ranking results of compensation priorities, in order to match the allocation of compensation resources with the actual threat level of the protrusion deviation, this embodiment of the invention configures differentiated compensation parameters for each grid region, as follows:

[0124] The compensation accuracy refers to the allowable height tolerance zone width during the compensation machining of the boss height; the process allowance is the extra amount of material to be removed or added during the compensation machining, used to cover the repeatability error of the machining equipment and process fluctuations.

[0125] The decision module obtains the corresponding compensation accuracy by querying a pre-established process mapping table based on the ordinal position k of each grid region in the sorting results. and process allowance ;

[0126] The process mapping table defines the quantitative correspondence between the sequence number k and the compensation parameter:

[0127] Process mapping table: ,in, For the sequence mapping function, in the process mapping table, different sequence positions k correspond to different combinations of compensation parameters. The change of sequence position corresponds to the differentiated adjustment of compensation accuracy and process margin.

[0128] Furthermore, the process mapping table defines the quantitative correspondence between the sequence number k and the compensation parameter as follows: the earlier the sequence number, the stricter the compensation accuracy and the larger the process margin; sequence number k=1 corresponds to a compensation accuracy of 2μm and a process margin of 0.5μm, sequence number k=2~3 corresponds to a compensation accuracy of 3μm and a process margin of 0.2~0.3μm, sequence number k=4~5 corresponds to a compensation accuracy of 4~5μm and a process margin of 0~0.2μm, and sequence number k≥6 corresponds to a compensation accuracy of 5μm and a process margin of 0μm.

[0129] The decision module combines the compensation parameters determined for each grid region. Spatial assembly is performed according to the two-dimensional coordinates of the corresponding grid nodes in the spatial reference grid to form a regional orientation process compensation scheme covering the plate area where the boss array is located.

[0130] Specifically, this can be explained using the following example:

[0131] For example, suppose the spatial reference grid is a 3×3 grid, and the coordinates of each grid node are (m,n), where m,n∈{1,2,3}. After sorting and mapping, the ordinal position k=1 of node (1,1), and the compensation parameters are obtained from the table:

[0132] ;

[0133] The ordinal position k of node (2,3) is 5, therefore... The decision module arranges the compensation parameters corresponding to all nodes into a 3×3 compensation parameter matrix according to (m,n), forming a regional orientation process compensation scheme covering each area of ​​the board surface.

[0134] The position of each element in the compensation parameter matrix corresponds one-to-one with the grid node of the spatial reference grid, and the physical production line performs differential compensation based on the two-dimensional coordinate index of the grid node.

[0135] The decision module is also used to: determine the target signal transmission path affected by the boss height deviation based on directional correlation analysis, match and evaluate the margin consumption of the target signal transmission path with the compensation accuracy of the corresponding grid area, generate routing layer adjustment, routing topology reconstruction or stack-up structure optimization suggestions for the target signal transmission path based on the matching evaluation results, and feed them back to the PCB design end.

[0136] Specifically, the area-oriented process compensation scheme corrects the geometric deviation of the boss through process means. However, its compensation capability is limited by the precision of the processing equipment. When there is a significant difference between the margin consumption of some target signal transmission paths and the compensation accuracy, it is difficult to fully restore the signal integrity index to the constraint requirements by relying solely on process compensation. Therefore, this embodiment of the invention triggers design-side optimization feedback through margin matching evaluation:

[0137] The decision module will determine the margin consumption of the grid area where each target signal transmission path is located. Compensation accuracy of the region Perform a matching assessment and calculate the margin compensation difference. ,in:

[0138] margin consumption Design value of boss height The product of these two factors serves as the equivalent height deviation for the grid region. The margin compensation difference ΔG is the sum of the equivalent height deviation and the compensation accuracy. The ratio of ΔG to the gap in process compensation capability is the larger the value of ΔG, indicating that the proportion of deviation that can be eliminated by process compensation with compensation accuracy is smaller.

[0139] For margin compensation difference For grid regions exceeding the process compensation capability, the decision module generates design optimization suggestions for the target signal transmission path carried in that region. These suggestions include:

[0140] Routing layer adjustment: Shift the target signal transmission path to a routing layer that is less affected by boss height deviation;

[0141] Routing topology reconfiguration: Adjusting the main routing direction or network node layout of the target signal transmission path to reduce the correlation between its main routing direction and trend direction components;

[0142] Stack-up optimization: Adjust the thickness of the dielectric layer related to the target signal transmission path to compensate for impedance offset caused by the boss height gradient.

[0143] The decision-making module feeds back the above design optimization suggestions to the PCB design end, and selects one of them to be implemented along with the region-oriented process compensation scheme, so as to realize the bidirectional driving of the digital twin on the physical production line and the PCB design end.

[0144] The present invention is explained by the following embodiments:

[0145] Continuing with the 3×3 grid example, let node (2,2) carry the target signal transmission path. (High-speed clock line), its margin consumption The compensation accuracy of this node after sorting and mapping is 0.85. Design value of boss height If the value is 100μm, then the equivalent height deviation is 85μm, therefore the margin is used to compensate for the difference. :

[0146] Therefore, the margin compensates for the difference. This indicates that the equivalent height deviation caused by the boss deviation in this grid area is 17 times the process compensation accuracy. That is, the process means of the regional orientation process compensation scheme can only correct this deviation by about 1 / 17≈5.9%, and the remaining deviation of about 94.1% cannot be eliminated by process compensation, and there is a substantial gap in the signal integrity margin.

[0147] Therefore, the decision module targets Generate design optimization suggestions: The routing was moved from the top layer to the inner layer where it was less affected by the boss height deviation (routing layer adjustment). At the same time, the main routing direction was adjusted from 0 degrees (X direction) to 90 degrees (Y direction) to reduce the directional correlation with the trend direction component (routing topology reconstruction). The design optimization suggestions were fed back to the PCB design end, and the digital twin was updated after the design end re-draws the drawings.

[0148] Based on the above, the present invention will be further explained according to the following embodiments:

[0149] First, assume that a certain BGA packaged device has a boss array of 2 rows × 3 columns on the PCB board, with a total of six bosses, and the horizontal spacing between them is... 500μm, longitudinal spacing It is 400μm;

[0150] The measured height data are shown in Table 1 below (unit: μm):

[0151] Table 1

[0152]

[0153] As shown in Table 1, the signal transmission path is set as follows: (High-speed clock line): From P11 to P13, the main routing direction is 0 degrees, the preset path length is 12000μm, the transmission delay constraint is 80ps, and the target impedance is 50Ω. The upper limit of impedance deviation is 5. The signal type is a high-speed differential pair signal, with weights... and They are 0.3 and 0.7 respectively;

[0154] Dielectric layer parameters: effective dielectric constant is 4.0, signal propagation speed is 1.5× m / s, dielectric layer thickness d is 100μm, and device package feature length is 1000μm;

[0155] Twin building blocks: Spatial reference grid:

[0156] The coverage area is [0,1000]×[0,400] (unit: μm), and is divided with a grid step size (Δx,Δy)=(500,400) to obtain a spatial reference grid of 2 rows × 3 columns (grid nodes are mapped one-to-one with bosses).

[0157] The mapping relationship between the grid node coordinates (m,n) and the boss is shown in Table 2 below:

[0158] Table 2

[0159]

[0160] As shown in Table 2, in the trend analysis module, the boss height field is constructed as follows: In this example, all grid nodes have already been equipped with bosses, so no interpolation is needed. The boss height field is the set of height values ​​of the above nodes.

[0161] Directional trend decomposition, using a two-dimensional quadratic polynomial: Least square fitting of the height field, trend direction component It is approximately equal to 99°, meaning that the height of the boss systematically increases along the positive direction of the Y-axis (increasing from the lower left to the upper right).

[0162] Signal path length difference ΔL: After passing through the first row (1,1)→(1,3) of the grid region, the coplanarity deviation of this region is... The signal path length difference is 7μm (BGA package, α=1.2). It is 100.8 μm.

[0163] The impedance abrupt change rate at the connection point is used as the average deviation of the individual bosses at each interface as the effective height offset. Simplified approach: The absolute value of the maximum individual boss deviation in each row represents the interface offset for that area.

[0164] The range (row 1) is 0.03.

[0165] Decision-making module: Margin assessment and prioritization:

[0166] Calculation of margin consumption: Region: Equivalent transmission delay difference is 0.672 ps; transmission delay margin consumption is 0.0084; impedance deviation at the interface is 1.5. If the impedance dimension margin consumption is 0.3, then the overall margin consumption is approximately equal to 0.096.

[0167] Both wiring paths have a main direction of 0° (X-direction) and a trend direction component of 99° (approximately Y-direction). It is 81°, which is equivalent to 1.414 radians, and the directional correlation is... It is 0.156;

[0168] Priority index and sorting, if Regional priority index If 0.015 is greater than the priority index of another region, then... The compensation priority for the region is number 1 (k=1).

[0169] Margin matching assessment and design optimization suggestions: Margin compensation difference Since the value is 4.8 > 1, process compensation can only eliminate approximately 21% of the equivalent deviation. Decision module triggered:

[0170] Wiring layer adjustment: The outer microstrip line is transferred to the inner strip line, which is less affected by the deviation in boss height;

[0171] Trace topology reconstruction: The main wiring direction was adjusted from 90° (Y direction) to 0° (X direction), actively severing the parallel relationship with the height trend direction of the boss (99°), reducing the directional correlation from 0.988 to 0.156, and significantly weakening the cumulative impact of the height trend on the clock line;

[0172] Layered structure optimization: fine-tuning The thickness of the dielectric layer is used to compensate for impedance offset.

[0173] In summary, this invention constructs a digital twin that integrates boss geometry, stacked structure, and wiring topology data, and registers and associates manufacturing inspection data with electrical design data within a unified spatial framework, breaking down the data barriers between geometric inspection and electrical analysis that exist in the prior art.

[0174] Based on this, the spatial distribution deviation of the boss height and the individual gradient are mapped to the signal path length difference and the impedance change rate at the connection point, respectively, realizing the quantitative conversion from the manufacturing geometry domain to the electrical performance domain, so that the compensation decision is based on the real electrical impact assessment of signal integrity.

[0175] By introducing directional correlation analysis between the boss height trend direction and the main routing direction of the signal transmission path, the priority of regional compensation is accurately directed to the most severely affected critical path, avoiding resource misallocation caused by sorting only by deviation magnitude. When the process compensation capability is insufficient, suggestions for routing layer adjustment or routing topology reconstruction can be fed back to the PCB design end, forming a collaborative closed loop between manufacturing and design. At the same time, the construction of continuous boss height field and the extraction of systematic trend components provide a continuously differentiable computational basis for directional trend analysis and cross-domain coupling mapping.

[0176] Although embodiments of the invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the appended claims and their equivalents.

Claims

1. A PCB intelligent manufacturing production line control system based on digital twins, characterized in that: include: Data acquisition module: used to acquire the height and coordinates of each boss on the PCB board; Twin building module: used to parse PCB design files to obtain boss arrays, and extract the layout and height design, stack-up structure and routing topology data of the boss arrays, and signal integrity constraint values. Based on this, a spatial reference grid and digital twin are established, and signal transmission paths are identified and routing main directions are extracted. Trend Analysis Module: Used to synchronize height values ​​and coordinates to the digital twin, construct the boss height field based on the spatial reference grid and perform directional trend decomposition, extracting systematic trend components and trend direction components; The coupling mapping module is used to determine the electrical performance impact parameters caused by the aforementioned deviations on the transmission path in a digital twin, based on the spatial distribution deviation of the boss height corresponding to the systematic trend component and the individual deviation of each boss relative to the height design, combined with the wiring topology data. The decision module assesses the margin of signal integrity constraints based on electrical performance impact parameters, combines the directional correlation analysis of trend direction components and main wiring direction, determines the compensation priority of each grid region in the spatial reference grid, and outputs regional orientation process compensation schemes and design optimization suggestions.

2. The PCB intelligent manufacturing production line control system based on digital twin as described in claim 1, characterized in that: The digital twin is constructed in the twin construction module as follows: S201. Based on the layout data of the boss array, determine the coverage area of ​​the boss array in the plate coordinate system; S202. Divide the coverage area into regular grids according to the horizontal and vertical arrangement spacing of the protrusion array, establish the mapping relationship between the two-dimensional design coordinates of each protrusion unit and the corresponding grid nodes, and obtain the spatial reference grid. S203. Construct a boss geometric model based on layout and height design data, construct a stacked structure model based on stacked structure data, and construct a wiring topology model based on wiring topology data. Spatially register the boss geometric model, stacked structure model, and wiring topology model through a unified board coordinate system to form a digital twin.

3. The PCB intelligent manufacturing production line control system based on digital twin as described in claim 1, characterized in that: The digital twin identifies the signal transmission path and extracts the main direction of the wiring, specifically as follows: First, based on the signal rate and signal type of the signal carried by the signal transmission path, the signal integrity constraint level of each signal transmission path is determined, and the signal transmission path with the strict constraint level is selected as the target signal transmission path. The signal types include clock signals, reset signals, high-speed differential pair signals, power signals, and general data signals; Then, the two-dimensional coordinates of the center of each pad and the inflection point of the trace on the target signal transmission path are extracted and least squares linear fitting is performed. The direction angle of the fitted line is taken as the main routing direction of the target signal transmission path.

4. The PCB intelligent manufacturing production line control system based on digital twin as described in claim 3, characterized in that: The trend analysis module constructs the boss height field based on a spatial reference grid, and the specific method is as follows: The height value and coordinates of each boss are mapped to the corresponding grid node of the spatial reference grid. For grid nodes without bosses, interpolation is performed based on the known boss height values ​​in their neighborhood using inverse distance weighting. All grid nodes of the spatial reference grid have corresponding height values, and the two-dimensional height distribution formed by each grid node and its corresponding height value is used as the boss height field.

5. The PCB intelligent manufacturing production line control system based on digital twin according to claim 4, characterized in that: The trend analysis module performs directional trend decomposition on the boss height field, specifically as follows: The boss height field is smoothed using a two-dimensional quadratic polynomial surface containing constant terms, linear terms, quadratic terms, and cross terms; The surface obtained by the smoothing process is used as the systematic trend component, the gradient vector of the systematic trend component is calculated, and the direction angle of the gradient vector is used as the trend direction component.

6. The PCB intelligent manufacturing production line control system based on digital twin as described in claim 5, characterized in that: The electrical performance parameters in the coupling mapping module include the signal path length difference and the impedance change rate at the connection point: The signal path length difference refers to the deviation of the actual signal transmission path length relative to the preset path length after the mounting device is spatially tilted due to the coplanarity deviation of the boss array caused by the spatial distribution deviation of the boss height. The impedance change rate at the connection point refers to the ratio of the change in the actual impedance value at the interface relative to the preset impedance value after the effective dielectric layer thickness changes due to the equivalent height offset caused by the deviation of each individual boss at the interconnect interface; the equivalent height offset is the average absolute value of the individual deviations of each boss covered by the interconnect interface.

7. A PCB intelligent manufacturing production line control system based on digital twins according to claim 6, characterized in that: The coupling mapping module is also used for: For each of the aforementioned signal transmission paths, the coplanarity deviation of the protrusion array in that region is determined based on the measured height of the protrusions within the grid area it passes through, and the signal path length difference is calculated based on the preset path length. Furthermore, for each of the aforementioned boss interconnect interfaces, the spatial distribution gradient is determined based on the individual deviation of each boss at the corresponding position, and the impedance change rate at the connection point is calculated based on the dielectric layer thickness.

8. A PCB intelligent manufacturing production line control system based on digital twins according to claim 7, characterized in that: The decision-making module determines the compensation priority of each grid region in the spatial reference grid, using the following specific method: The signal integrity constraints include transmission delay constraints and impedance constraints. The signal path length difference of each grid region in the spatial reference grid is converted into an equivalent transmission delay difference by combining the signal propagation speed in the corresponding medium layer. Then, the ratio of the equivalent transmission delay difference to the transmission delay constraint value is calculated to obtain the transmission delay dimension margin consumption. The impedance deviation at the interface is calculated by multiplying the impedance mutation rate at the connection point by the preset impedance value of the corresponding transmission line. The impedance deviation at the interface is then compared with the upper limit of the impedance deviation allowed by the impedance constraint value to obtain the impedance dimension margin consumption. The transmission delay dimension margin consumption and the impedance dimension margin consumption are weighted and combined to obtain the comprehensive margin consumption. Then, the vector angle between the trend direction component and the main wiring direction is calculated to determine the directional correlation between the boss height trend direction and the signal transmission path direction; finally, the compensation priority of each grid region in the spatial reference grid is determined by combining the margin consumption degree and the directional correlation degree.

9. A PCB intelligent manufacturing production line control system based on digital twins according to claim 8, characterized in that: The method for generating the region-oriented process compensation scheme in the decision-making module is as follows: Based on the ranking result of the compensation priority, differentiated compensation parameters are configured for each grid region. The compensation parameters include compensation accuracy and process margin. The compensation parameters of each grid region are assembled into the region-oriented process compensation scheme.

10. A PCB intelligent manufacturing production line control system based on digital twins according to claim 8, characterized in that: The decision module is also used for: Based on the directional correlation analysis, the target signal transmission path affected by the boss height deviation is determined, and the margin consumption of the target signal transmission path is matched and evaluated with the compensation accuracy of the corresponding grid area. Based on the matching evaluation results, suggestions for routing layer adjustment, routing topology reconstruction, or layer stack-up optimization for the target signal transmission path are generated and fed back to the PCB design end.

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