An NMOS LDO based on feedforward ripple cancellation

Abstract

This invention belongs to the field of integrated circuit power management chip technology, specifically relating to an NMOS LDO based on feedforward ripple cancellation. This invention designs a feedforward amplifier (FFA) to reduce the source-drain voltage VDS of the power transistor Mpo. Mpo During the replication process, no VREFX needs to be introduced. The replication transistor Mc automatically follows the source-drain voltage VDS of the power transistor Mpo in the LDO main loop through the feedback loop of the feedforward amplifier FFA. Mpo The change ensures the source-drain voltage VDS of the replicator Mc. Mc With the source-drain voltage VDS of the power transistor Mpo Mpo The source-drain voltage VDS of the power transistor Mpo remains constant. Mpo =VIN-VOUT, and ultimately, under the condition of changing VOUT and VIN, the replicating transistor Mc can still dynamically replicate the source-drain voltage of the power transistor Mpo, thus ensuring the accuracy of the replication. Finally, the feedforward amplifier proposed in this invention can adaptively replicate the intrinsic gain of the NMOS power transistor without introducing an external reference voltage VREFX, thereby reducing circuit power consumption and area, and ensuring the effectiveness of the feedforward ripple cancellation technology under various input and output conditions.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuit power management chip technology, specifically relating to an NMOS LDO based on feedforward ripple elimination. Background Technology

[0002] With the continuous evolution of integrated circuit technology, portable electronic devices, high-performance processors, and radio frequency communication modules are placing increasingly stringent demands on power management systems. Low dropout linear regulators (LDOs) are widely used due to their advantages such as simple structure, low noise, and small chip area.

[0003] In LDO design, the Power Supply Rejection Ratio (PSRR) is one of the core performance metrics. It reflects the regulator's ability to suppress input power supply ripple and maintain a stable output voltage. The PSRR of traditional LDOs is typically limited by loop bandwidth and parasitic capacitance of the power transistors. Feedforward Ripple Cancellation (FFRC) technology, with its characteristics of not affecting the LDO dropout voltage and small power consumption and area consumption, has become a commonly used technique to overcome these limitations.

[0004] In the FFRC technology of NMOS LDO, the core circuit includes a feedforward amplifier (FFA), characterized by a power supply ripple vin on the input power supply voltage VIN, and an output value of vin / Av. po Power supply ripple (where Av) po (This refers to the intrinsic gain of the NMOS power transistor). To ensure the accuracy of the feedforward amplifier's ripple output, the FFA needs to accurately replicate the intrinsic gain of the NMOS power transistor. According to the gm / id design method, replicating the intrinsic gain of the power transistor also means replicating the gate length and source-drain voltage VDS of the power transistor. Mpo With the current density I of the power transistor Mpo / W Mpo .

[0005] like Figure 1 The conventional NMOS LDO feedforward amplifier architecture shown obtains the drain-source voltage VDS of the replica transistor Mc through the clamping action of the operational amplifier. Mc for:

[0006]

[0007] To accurately replicate the drain-source voltage VDS of the NMOS power transistor Mpo Mpo To the replication tube Mc, thus realizing VDS Mc =VDS Mpo =VIN-VOUT, the value of the introduced external reference voltage VREFX should be:

[0008]

[0009] The value of VREFX is strongly correlated with the LDO input VIN and LDO output VOUT. Especially in applications where the LDO input VIN and LDO output VOUT are adjustable, the value of VREFX needs to dynamically change with the LDO input voltage VIN and LDO output voltage VOUT. This means that a precisely adjustable voltage source needs to be introduced on-chip or off-chip as VREFX to ensure VDS. Mc =VDS Mpo This ensures the accuracy of the ripple output. However, this increases the power consumption and area of ​​the circuit. Summary of the Invention

[0010] To address the aforementioned problems or shortcomings, this invention provides an NMOS LDO based on feedforward ripple cancellation, the key feature of which is that the internal feedforward amplifier does not require a reference voltage VREFX.

[0011] A type of NMOS LDO based on feedforward ripple cancellation (e.g.) Figure 2 As shown, it includes the LDO main loop, bandgap reference source, output current sensing module and feedforward amplifier (FFA).

[0012] The LDO main loop includes an error amplifier EA, a summing stage SUM, a super source follower SSF, an NMOS power transistor Mpo, feedback resistors RFB1 and RFB2, and a load capacitor CL.

[0013] The negative input of error amplifier EA is connected between feedback resistors RFB1 and RFB2. The output of error amplifier EA is connected to the positive input of summing stage SUM. The negative input of summing stage is connected to the output of feedforward amplifier FFA. The output of summing stage is connected to the input of super source follower SSF. The output of super source follower SSF is connected to the gate of NMOS power transistor Mpo. The drain of NMOS power transistor Mpo is connected to the power supply voltage VIN. The source is connected to feedback resistor RFB1 and one end of load capacitor CL. The source of Mpo serves as the output VOUT of LDO. The other end of load capacitor CL is grounded. The other end of feedback resistor RFB1 is connected to the negative input of error amplifier EA and one end of feedback resistor RFB2. The other end of feedback resistor RFB2 is grounded.

[0014] The bandgap reference source outputs a reference voltage VREF to the positive input terminal of the error amplifier EA in the main loop of the LDO, which is used to provide the reference voltage VREF for the LDO.

[0015] The current detection module mirrors the current Ipo of the power transistor Mpo in the LDO main loop to the feedforward amplifier FFA according to the ratio k, and provides the bias current Isense for the replica transistor Mc in the feedforward amplifier FFA as a bias current source, Isense=k×Ipo.

[0016] The feedforward amplifier includes feedback resistors Rx1, Rx2, Rx3, and Rx4, a replication transistor Mc, an operational amplifier EA2, a buffer BUFFER, and a bias current source Isense.

[0017] Among them, the feedback resistors Rx1, Rx2, Rx3, and Rx4 are of the same type and size; the gate width of the replica transistor Mc is k times the gate width of the power transistor Mpo in the LDO main loop, and the gate length of the replica transistor Mc is the same as the gate length of the power transistor Mpo in the LDO main loop.

[0018] Rx1 is connected at one end to the LDO output VOUT, and at the other end to the positive input of op-amp EA2 and one end of Rx2; the other end of Rx2 is connected to the drain of the replica transistor Mc. Rx3 is connected at one end to the power supply voltage VIN, and at the other end to the negative input of op-amp EA2 and one end of Rx4; the other end of Rx4 is grounded. The output of op-amp EA2 is connected to the gate of the replica transistor Mc and the buffer, and the source of the replica transistor Mc is grounded. The buffer gain is -1, and the output of the buffer serves as the output of the feedforward amplifier, connected to the negative input of the summing stage SUM in the LDO main loop. The bias current source Isense is generated by the output current detection module, with one end connected to the power supply VIN and the other end connected to the drain of the replica transistor Mc.

[0019] Furthermore, k takes a value between 0.0001 and 0.1, and the actual value is determined according to the application scenario.

[0020] Furthermore, the buffer is dynamically biased.

[0021] The feedforward amplifier of this invention operates from the input power supply ripple to the output as follows:

[0022] The gate length of the replica transistor Mc is the same as that of the power transistor Mpo. Isense = k × Ipo is used as the bias current for the replica transistor Mc. The gate width W of the replica transistor Mc is also satisfied. Mc The gate width W of the power transistor Mpo Mpo k times, W Mc =k×W Mpo Then we have:

[0023]

[0024] That is, the current density of the power transistor Mpo is equal to the current density of the replica transistor Mc.

[0025] Through the clamping effect of operational amplifier EA2 in the feedforward amplifier, the minimum drain voltage v of the replicating transistor Mc is reduced. dMc for:

[0026]

[0027] Where vin is the small-signal voltage across the power supply voltage VIN, and vout is the small-signal voltage at the LDO output. For a normally operating LDO, it must have power supply rejection capability, therefore:

[0028]

[0029] Therefore, the minimum signal voltage v at the drain of the replicator Mc is... dMc It can be approximated as:

[0030]

[0031] The drain maximum signal voltage V of the replication transistor Mc DMc for:

[0032]

[0033] Because the source of the replicator Mc is grounded, the source-drain voltage V of the replicator Mc is... DSMc for:

[0034]

[0035] Furthermore, since the source-drain voltage of the power transistor Mpo is:

[0036]

[0037] Therefore, the source-drain voltage of the replica transistor Mc is equal to that of the power transistor Mpo.

[0038] This achieves the simultaneous replication of the large-signal source drain voltage VDS of the power transistor Mpo, while the small-signal power supply ripple vin on the input power supply voltage VIN is fed to the drain of the replicating transistor Mc. Mpo This is applied to the replicator Mc, causing the source-drain voltage VDS of the replicator Mc to... Mc The source-drain voltage VDS of the power transistor Mpo Mpo Maintain consistency.

[0039] At this point, the gate length, current density, and source-drain voltage of the replica transistor Mc and the power transistor Mpo are identical, therefore they have the same intrinsic gain, i.e.:

[0040]

[0041] Ignoring the output impedance of the bias current source Isense, the gain from the gate to the drain of the replicating transistor Mc is approximately:

[0042]

[0043] That is, the small-signal voltage at the gate of the replicator Mc is:

[0044]

[0045] This is how the small-signal gate voltage vg of Mc is obtained. Mc -vin / Av po .

[0046] To ensure that the output signal value of the feedforward amplifier is vin / Av po Furthermore, the small-signal voltage at the gate of the replicator Mc should be inverted. A buffer with a gain of -1 is connected to the gate of the replicator Mc, making the output small-signal value of the buffer vin / Av. po The output of the buffer is the same as the output of the feedforward amplifier.

[0047] In summary, the feedforward amplifier designed in this invention, regarding the source-drain voltage VDS of the power transistor Mpo... Mpo During the replication process, VREFX is not required. The replication transistor Mc automatically follows the source-drain voltage VDS of the power transistor Mpo through the feedback loop of the feedforward amplifier. Mpo The change ensures the source-drain voltage VDS of the replicator Mc. Mc With the source-drain voltage VDS of the power transistor Mpo Mpo The source-drain voltage VDS of the power transistor Mpo remains constant. Mpo =VIN-VOUT, and ultimately, under the condition of changing VOUT and VIN, the replicating transistor Mc can still dynamically replicate the source-drain voltage of the power transistor Mpo, thus ensuring the accuracy of the replication. The feedforward amplifier designed in this invention can adaptively replicate the intrinsic gain of the NMOS power transistor without introducing an external reference voltage VREFX, thereby reducing the power consumption and area of ​​the circuit and ensuring the effectiveness of the feedforward ripple cancellation technology under various input and output conditions. Attached Figure Description

[0048] Figure 1 This is a diagram of a traditional NMOS LDO architecture based on feedforward ripple cancellation technology.

[0049] Figure 2 This is a diagram of the NMOS LDO architecture based on feedforward ripple elimination of the present invention.

[0050] Figure 3 This is a circuit diagram of the output current detection module in the embodiment;

[0051] Figure 4 This is a circuit diagram of the feedforward amplifier in the embodiment;

[0052] Figure 5 This is a circuit diagram of the LDO main loop in the embodiment;

[0053] Figure 6 The following are the PSRR simulation results for the NMOS LDO before and after enabling the feedforward amplifier in the embodiment; Detailed Implementation

[0054] The following detailed description, in conjunction with the accompanying drawings and embodiments, further illustrates the principle and process of feeding power supply ripple into the gate of the power transistor by the feedforward amplifier in this invention.

[0055] An NMOS LDO based on feedforward ripple cancellation includes an LDO main loop, a bandgap reference source, an output current sensing module, and a feedforward amplifier (FFA). The specific architecture is as follows: Figure 2 As shown.

[0056] In this embodiment, the circuit of the output current detection module is as follows: Figure 3 As shown, it includes PMOS transistors: MS1, MS2, and NMOS transistors: MS, Mpo, MS3, MS4.

[0057] Mpo is the power transistor of the NMOS LDO. The gate of Mpo is connected to the gate of MS, the drain of Mpo is connected to the power supply VIN, and the source of Mpo is connected to the LDO output VOUT. The gate of MS is connected to the gate of Mpo, the drain of MS is connected to the power supply voltage VIN, and the source of MS is connected to the source of MS2. The gate of MS1 is connected to the gate of MS2, the source of MS1 is connected to the source of Mpo, and the drain of MS1 is shorted to its gate. The gate of MS2 is connected to the gate of MS1, the drain of MS2 is connected to the drain of MS4, and the source of MS2 is connected to the source of MS. The gate of MS3 is connected to the gate of MS4, the drain of MS3 is connected to the drain of MS1, and the source of MS3 is grounded. The gate and drain of MS4 are shorted and connected to the drain of MS2, and the source of MS4 is grounded. The gate shared by MS3 and MS4 serves as the output of the current sensing module, denoted as I_SENSE.

[0058] The current mirror structure formed by MS3 and MS4 ensures that the currents in both transistors are equal. Since MS1 and MS2 share the same gate, their source voltages are also equal. Therefore, the source voltages of Mpo and MS are equal. Furthermore, Mpo and MS share the same gate and drain, so the current in both transistors is proportional to their width-to-length ratio, i.e.:

[0059]

[0060] MS and MS4 are in the same branch, so the current in the two transistors is equal.

[0061] Furthermore, if we assume that the gate length L of Mpo and MS are equal, then:

[0062]

[0063] The current densities of Mpo and MS are equal.

[0064] In this embodiment, the circuit of the feedforward amplifier is as follows: Figure 4 As shown. Operational amplifier EA2 in the feedforward amplifier is implemented using a conventional folded cascode op-amp. Feedback resistor Rx1 is connected at one end to the LDO output VOUT and at the other end to the positive input of the folded cascode op-amp. Feedback resistor Rx2 is connected at one end to the positive input of the folded cascode op-amp and at the other end to the drain of the replica transistor Mc. Feedback resistor Rx3 is connected at one end to the negative input of the folded cascode op-amp and at the other end to the power supply voltage VIN. Feedback resistor Rx4 is connected at one end to the negative input of the folded cascode op-amp and at the other end to ground.

[0065] PMOS transistors MF5, MF6, MF7, and MF8 form a cascode current mirror, replicating the current on bias transistor MF1 onto transistor Mc as its bias current. PMOS transistors MF9 and MF10, along with NMOS transistors MF11, MF12, MF13, and MF14, form the buffer of the feedforward amplifier. MF9's gate is connected to the gate of MF5, its source to the power supply voltage VIN, and its drain to the drain of MF13. MF10's gate is connected to the bias voltage VBIAS_P, its source to the power supply voltage VIN, and its drain to the drain of MF13. MF11's gate is connected to the drain of MF13, its source to the power supply voltage VIN, and its drain to the drain of MF13. MF12's gate is connected to the gate of the replicating transistor Mc, its source is grounded, and its drain is connected to the source of MF11. MF13's drain is shorted to its gate, and its source is connected to the drain of MF14. MF14's drain is shorted to its gate, and its source is grounded.

[0066] Based on the virtual short characteristic of the operational amplifier and the superposition theorem, the drain maximum signal voltage V of the replica transistor Mc can be obtained. DMc for:

[0067]

[0068] Furthermore, since the source-drain voltage of the power transistor Mpo is:

[0069]

[0070] That is, the source-drain voltage of the replica transistor Mc is equal to that of the power transistor Mpo.

[0071] Through the clamping effect of operational amplifier EA2 in the feedforward amplifier, the minimum drain voltage v of the replicating transistor Mc is reduced. dMc for:

[0072]

[0073] Where vin is the small-signal voltage across the power supply voltage VIN, and vout is the small-signal voltage at the LDO output. For a normally operating LDO, it must have power supply rejection capability, therefore:

[0074]

[0075] Therefore, the minimum signal voltage v at the drain of the replicator Mc is... dMc It can be approximated as:

[0076]

[0077] MF1 tube and Figure 3 In the output current detection module, transistors MS4 and MF1 form a current mirror structure. Assuming transistor MF1 has the same dimensions as MS4, MF1 and MS4 have the same current. The current in MF1 is replicated to the copied transistor Mc through the common-source, common-gate current mirror formed by MF5, MF6, MF7, and MF8. Therefore, the current in Mc is equal to that in MS. Assuming that the gate length and gate width of Mc are both equal to those of MS, then:

[0078]

[0079] The replica transistor Mc and the power transistor Mpo have the same current density and source-drain voltage, and their gate lengths are equal. Therefore, they have the same intrinsic gain.

[0080]

[0081] Ignoring the output impedance of the bias current source Isense, the gain from the gate to the drain of the replicating transistor Mc is approximately:

[0082]

[0083] That is, the small-signal voltage at the gate of the replicator Mc is:

[0084]

[0085] This is how the small-signal gate voltage vg of Mc is obtained. Mc -vin / Av po .

[0086] Among them Av c For the intrinsic gain of the replicator Mc, Av po This represents the intrinsic gain of the power transistor Mpo.

[0087] MF12 and MF11 constitute a buffer. Considering the volume effect of MF11, the voltage gain Av of the buffer is:

[0088]

[0089] To ensure a gain of -1, the aspect ratio of MF12 can be slightly increased compared to MF11 during the design phase, thereby improving the transconductance gm of MF12. F12To compensate for the error caused by the bulk effect of MF11. The transconductance gm of MF12 F12 The following conditions must be met:

[0090]

[0091] This also allows MF11 to be an NMOS using a deep N-well process, thus eliminating the body effect of MF11.

[0092] When the bulk effect of MF11 is canceled or eliminated, the output of the feedforward amplifier is:

[0093]

[0094] The gate of MF11 should be dynamically biased. This is because the gate voltage of Mc, i.e., the gate voltage of MF12, changes dynamically with the LDO load current, causing dynamic changes in the current in the MF11 branch, which in turn affects the gate-source voltage VGS of MF11. MF11 Dynamically changing. The output voltage V of the feedforward amplifier buffer. FFA_OUT The value is:

[0095]

[0096] VG MF11 This is the gate voltage of MF11. The output terminal FFA_OUT of the feedforward amplifier buffer is connected to... Figure 4 In the M3 transistor, without dynamic bias, the gate voltage VG of MF11 is... MF11 It is constant relative to the load current.

[0097] If the LDO load current is large, the gate-source voltage VGS of MF11 will be... MF11 It will also be relatively large, which may cause the output voltage V of the feedforward amplifier buffer to be large. FFA_OUT Below Figure 5 The threshold voltage of the summing stage input transistor M3 in the LDO main loop causes the LDO main loop to open. If the LDO load current is small, the gate-source voltage VGS of MF11 will be low. MF11 It will also be smaller, which may cause the output voltage V of the feedforward amplifier buffer to be lower. FFA_OUT Too high, Figure 5 If the current in M3 is too high, the gate-source voltage of M1 will be too high, which in turn will cause the gate voltage of M1 to be too high, exceeding the swing of the error amplifier EA in the main loop, and the LDO main loop will fail.

[0098] The dynamic bias of the MF11 gate is achieved as follows: a load current is introduced to the bias transistors MF13 and MF14 through a current mirror structure composed of MF6 and MF9. When the load current increases, the voltage drop across MF13 and MF14 also increases, thus increasing the gate voltage of MF11. Simultaneously, the gate-source voltage of MF11 also increases, achieving relative stability of the source voltage of MF11, i.e., the voltage at the FFA_OUT terminal.

[0099] like Figure 5 The diagram shows the circuit of the LDO main loop in the embodiment. The positive input terminal of the error amplifier EA is connected to the reference voltage VREF generated by the bandgap reference source, and the negative input terminal of the error amplifier EA is connected to the feedback voltage VFB. The output terminal of the error amplifier EA is connected to the gate of the summing stage input transistor M1, and the gate of M1 serves as the positive input terminal of the summing stage. M1 and M3 in the LDO main loop constitute the summing stage, where the drain of M1 is connected to the power supply, and the source of M1 is connected to the drain of M3 and the gate of M2, serving as the output of the summing stage. The gate of M3 is connected to the output terminal FFA_OUT of the feedforward amplifier, and the gate of M3 serves as the negative input terminal of the summing stage. The structure of the summing stage is the same as the buffer structure with a gain of -1 formed by MF12 and MF11 in the feedforward amplifier, which also allows the aspect ratio of M3 to be greater than that of M1 to cancel the effect of the body effect of M1. Both M1 and M3 are input transistors, and their small-signal summation result v sum for:

[0100]

[0101] With proper design, such as in this embodiment where an operational amplifier with an NMOS current mirror load is used as the error amplifier EA, the small signal v at the output of the error amplifier EA can be made more stable. EA_OUT If it is approximately 0, then:

[0102]

[0103] The small-signal gain of the PMOS super source follower composed of M2, M4, M5, and M6 is precisely 1. Therefore, the ripple fed into the gate of the power transistor Mpo is:

[0104]

[0105] This refers to the ripple value that needs to be fed to the gate of the power transistor Mpo in the NMOS LDO feedforward ripple elimination technology.

[0106] The simulation results of PSRR before and after enabling the feedforward amplifier in the embodiment are as follows: Figure 6As shown, the PSRR of the NMOS LDO with feedforward amplifier (FFA) is significantly improved at low frequencies, 1kHz, and 100kHz. However, after 100kHz, the loop of the feedforward amplifier (FFA) gradually fails, and the effect of the feedforward amplifier (FFA) on the PSR of the LDO weakens. The frequency range of PSRR improvement can be widened by increasing the bandwidth of the feedforward amplifier (FFA).

[0107] As can be seen from the above embodiments, the feedforward amplifier proposed in this invention achieves accurate feeding of power supply ripple to the gate of the power transistor without the need for an external reference voltage by adaptively following the source-drain voltage of the power transistor, thus ensuring the effectiveness of the feedforward ripple elimination technology.

Claims

1. An NMOS LDO based on feedforward ripple cancellation, comprising an LDO main loop, a bandgap reference source, an output current detection module, and a feedforward amplifier (FFA), characterized in that: The LDO main loop includes an error amplifier EA, a summing stage SUM, a super source follower SSF, an NMOS power transistor Mpo, feedback resistors RFB1 and RFB2, and a load capacitor CL. The negative input terminal of the error amplifier EA is connected between the feedback resistors RFB1 and RFB2. The output terminal of the error amplifier EA is connected to the positive input terminal of the summing stage SUM. The negative input terminal of the summing stage is connected to the output terminal of the feedforward amplifier FFA. The output of the summing stage is connected to the input of the super source follower SSF, and the output of the super source follower SSF is connected to the gate of the NMOS power transistor Mpo. The drain of the NMOS power transistor Mpo is connected to the power supply voltage VIN, and the source is connected to the feedback resistor RFB1 and one end of the load capacitor CL. The source of Mpo serves as the output of the LDO. The other end of the load capacitor CL is grounded. The other end of the feedback resistor RFB1 is connected to the negative input terminal of the error amplifier EA and one end of the feedback resistor RFB2, and the other end of the feedback resistor RFB2 is grounded. The bandgap reference source outputs a reference voltage VREF to the positive input terminal of the error amplifier EA in the main loop of the LDO; The current detection module mirrors the current Ipo of the power transistor Mpo in the LDO main loop to the feedforward amplifier FFA according to the ratio k, and provides the bias current Isense for the replica transistor Mc in the feedforward amplifier FFA as a bias current source, Isense=k×Ipo. The feedforward amplifier (FFA) includes feedback resistors Rx1, Rx2, Rx3, and Rx4, a replication transistor Mc, an operational amplifier EA2, a buffer BUFFER, and a bias current source Isense. Among them, the feedback resistors Rx1, Rx2, Rx3, and Rx4 are of the same type and size; the gate width of the replica transistor Mc is k times the gate width of the power transistor Mpo in the LDO main loop, and the gate length of the replica transistor Mc is the same as the gate length of the power transistor Mpo in the LDO main loop. One end of Rx1 is connected to the output terminal VOUT of LDO, and the other end is connected to the positive input terminal of op-amp EA2 and one end of Rx2; the other end of Rx2 is connected to the drain of the replica transistor Mc; one end of Rx3 is connected to the power supply voltage VIN, and the other end is connected to the negative input terminal of op-amp EA2 and one end of Rx4; the other end of Rx4 is grounded. The output of op-amp EA2 is connected to the gate of the replica transistor Mc and the buffer, and the source of the replica transistor Mc is grounded; the buffer gain is -1, and the output of the buffer is used as the output of the feedforward amplifier FFA, which is connected to the negative input of the summing stage SUM in the main loop of the LDO; the bias current source Isense is generated by the output current detection module, one end of which is connected to the power supply VIN, and the other end is connected to the drain of the replica transistor Mc.

2. The NMOS LDO based on feedforward ripple cancellation as described in claim 1, characterized in that: The value of k is between 0.0001 and 0.

1.

3. The NMOS LDO based on feedforward ripple cancellation as described in claim 1, characterized in that: The operational amplifier EA2 in the feedforward amplifier is a folded common-source cascode operational amplifier.

4. The NMOS LDO based on feedforward ripple cancellation as described in claim 1, characterized in that: The buffer in the feedforward amplifier is dynamically biased.

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