A pre-stabilized bandgap reference source with high and low temperature curvature compensation

Abstract

This invention discloses a pre-regulated bandgap reference source with high and low temperature curvature compensation, belonging to the field of power management chips. The main circuit includes an initial bias current source, a pre-regulated circuit, a positive temperature coefficient current generation circuit, a negative temperature coefficient current generation circuit, a high and low temperature curvature compensation circuit, and a reference voltage generation circuit. The positive and negative temperature coefficient current generation circuits utilize the special relationship between the base-emitter voltage and temperature of a bipolar transistor to form positive and negative temperature coefficient currents that are approximately linearly related to temperature. These currents, along with the compensation current generated by the high and low temperature curvature compensation circuit, are summed in the reference voltage generation circuit. The summed current, after flowing through a resistor, forms a reference voltage that is almost independent of temperature, and is then buffered for voltage regulation. ref Voltage Output. The pre-regulator circuit improves the power supply rejection ratio by providing a stable supply voltage to the core circuit. This invention uses a 0.18μm BCD process, with a minimum operating voltage of 2.2V and a maximum operating voltage of 3V. It has advantages such as low temperature drift and high power supply rejection ratio, simple structure, and high integration, and can meet the needs of the power management chip field for high-precision reference voltage sources.

Description

Technical Field

[0001] This invention belongs to the field of power management chip technology, specifically a pre-regulated bandgap reference source with high and low temperature curvature compensation. Background Technology

[0002] The bandgap reference (BGR) is one of the most critical reference circuits in analog and mixed-signal integrated circuits. It utilizes the inherent temperature coefficient of semiconductor materials and employs various circuit design techniques to offset the temperature drift of the reference voltage. It is a key basic circuit unit for chips to maintain stable operation at different temperatures and is widely used in power management chips, digital-to-analog converters, and analog front-end circuits for sensors.

[0003] Traditional bandgap reference sources rely on the base-emitter voltage (V) of a bipolar transistor. BE The negative temperature coefficient of transistors and the transistor voltage difference (ΔV) BE By using first-order linear compensation of the positive temperature coefficient of V, a near-zero temperature drift reference voltage output can be achieved within a temperature range of -40-125℃, meeting the reference voltage requirements of various chip systems. However, in actual operating conditions, V BE The relationship between reference voltage and temperature is not an ideal linear one, but rather involves non-negligible high-order nonlinear factors. The curve of the relationship between reference voltage and temperature usually exhibits a "U-shape" or "inverted U-shape," with a significant increase in curvature under high and low temperature conditions. This means that traditional first-order compensation structures can only achieve a temperature coefficient of around 30 ppm / ℃. Temperature drift directly leads to system errors in the chip, causing problems such as output voltage deviation of the power management chip, decreased accuracy of digital-to-analog converter conversion, and distortion of sensor measurement data.

[0004] On the other hand, existing conventional bandgap reference sources generally lack dedicated pre-regulation structures, with the core reference circuit directly powered by the system power supply, resulting in insufficient power supply rejection capability. In actual operating conditions, the system power supply is susceptible to load switching, external electromagnetic interference, and other factors, leading to non-ideal factors such as low-frequency voltage deviation and high-frequency ripple noise. Due to the lack of isolation measures, traditional bandgap reference sources have poor power supply rejection ratio performance and cannot effectively isolate power supply disturbances, causing power supply fluctuations to be directly coupled to the output of the bandgap reference source, resulting in reference voltage fluctuations and distortion.

[0005] In summary, traditional bandgap reference sources generally suffer from drawbacks such as a relatively large temperature coefficient and weak power supply anti-interference performance, making it difficult to simultaneously meet the requirements of high-end chip applications that demand low temperature drift, high precision, and high anti-interference capabilities. Therefore, this invention proposes a pre-regulated bandgap reference source with high and low temperature curvature compensation to address the numerous shortcomings of traditional bandgap reference sources. Summary of the Invention

[0006] This invention proposes a pre-regulated bandgap reference source with high and low temperature curvature compensation, aiming to solve the problems of large temperature coefficient and weak power supply interference resistance of traditional bandgap reference sources. In this scheme, the positive temperature coefficient current generation circuit and the negative temperature coefficient current generation circuit utilize the special relationship between the base-emitter voltage and temperature of a bipolar transistor to form positive and negative temperature coefficient currents that are approximately linearly related to temperature. These currents, along with the compensation current generated by the high and low temperature curvature compensation circuit, are summed in the reference voltage generation circuit. The summed current, after flowing through a resistor, forms a reference voltage that is nearly independent of temperature, and is then buffered for voltage regulation. ref Voltage output. The pre-regulator circuit improves the power supply rejection ratio by providing a stable supply voltage to the core circuit.

[0007] To achieve the above objectives, the present invention provides the following technical solution:

[0008] A pre-regulated bandgap reference source with high and low temperature curvature compensation includes: an initial bias current source, a pre-regulated circuit, a positive temperature coefficient current generation circuit, a negative temperature coefficient current generation circuit, a high and low temperature curvature compensation circuit, and a reference voltage generation circuit. The initial bias current source provides a bias current source for other circuits after power-on. The pre-regulated circuit provides a fixed supply voltage for the core circuit of the bandgap reference source, which is unaffected by the power supply voltage. The positive and negative temperature coefficient current generation circuits generate currents that are positively and negatively correlated with temperature, respectively. The high and low temperature curvature compensation circuit generates currents that can compensate for the high and low temperature portions of the temperature curve. The reference voltage generation circuit sums the currents from each circuit and generates a temperature-independent reference voltage, which is then output to external circuits through a buffer.

[0009] The input port of the initial bias current source is the power supply VDD, and the output port is I. Nbias with I Pbias , where I Nbias Includes I Nbias1 To I Nbias11 There are 11 ports in total, I Pbias Includes I Pbias1 and I Pbias2 Two ports: the input port VDD is connected to an external power supply, and the output port I... Nbias1 Input port I connected to the positive temperature coefficient current generating circuit Nbias1 Output port I Nbias2 Input port I connected to the positive temperature coefficient current generating circuit Nbias2 Output port I Nbias3 Input port I connected to the positive temperature coefficient current generating circuit Nbias3 Output port I Nbias4Input port I connected to the negative temperature coefficient current generating circuit Nbias4 Output port I Nbias5 Input port I connected to the negative temperature coefficient current generating circuit Nbias5 Output port I Nbias6 Input port I connected to the negative temperature coefficient current generating circuit Nbias6 Output port I Nbias7 Input port I connected to the reference voltage generation circuit Nbias7 Output port I Nbias8 Input port I connected to the reference voltage generation circuit Nbias8 Output port I Nbias9 Input port I connected to the pre-regulator circuit Nbias9 Output port I Nbias10 Input port I connected to the pre-regulator circuit Nbias10 Output port I Nbias11 Input port I connected to the pre-regulator circuit Nbias11 Output port I Pbias1 Input port I connected to the high and low temperature curvature compensation circuit Pbias1 Output port I Pbias2 Input port I connected to the pre-regulator circuit Pbias2 The input ports of the pre-regulator circuit are VDD and V... ref I Pbias2 I Nbias9 I Nbias10 with I Nbias11 The output port is LVDD, the input port VDD is connected to the external power supply, and the input port V... ref The output port V of the reference voltage generation circuit ref Connected, input port I Pbias2 Output port I of the initial bias current source Pbias2 Connected, input port I Nbias9 Output port I of the initial bias current source Nbias9 Connected, input port I Nbias10 Output port I of the initial bias current source Nbias10 Connected, input port I Nbias11 Output port I of the initial bias current source Nbias11 The output port LVDD is connected to the input port LVDD of the positive temperature coefficient current generating circuit, the negative temperature coefficient current generating circuit, the high and low temperature curvature compensation circuit, and the reference voltage generating circuit, respectively; the input port of the positive temperature coefficient current generating circuit is LVDD, I Nbias1 I Nbias2 and I Nbias3 The output port is I PTAT1 and I PTAT2The input port LVDD is connected to the output port LVDD of the pre-regulator circuit, and the input port I... Nbias1 Output port I of the initial bias current source Nbias1 Connected, input port I Nbias2 Output port I of the initial bias current source Nbias2 Connected, input port I Nbias3 Output port I of the initial bias current source Nbias3 Connected, output port I PTAT1 Input port I of the reference voltage generation circuit PTAT1 Connected, output port I PTAT2 Input port I of the high and low temperature curvature compensation circuit PTAT2 Connected; the input ports of the negative temperature coefficient current generating circuit are LVDD and I. Nbias4 I Nbias5 with I Nbias6 The output port is I CTAT The input port LVDD is connected to the output port LVDD of the pre-regulator circuit, and the input port I... Nbias4 Output port I of the initial bias current source Nbias4 Connected, input port I Nbias5 Output port I of the initial bias current source Nbias5 Connected, input port I Nbias6 Output port I of the initial bias current source Nbias6 Connected, output port I CTAT Input port I of the reference voltage generation circuit CTAT The ports are connected; the input ports of the high and low temperature curvature compensation circuit are LVDD and I. PTAT2 with I Pbias1 The output port is the low-temperature compensation current port I. LC and high temperature compensation current port I HC The input port LVDD is connected to the output port LVDD of the pre-regulator circuit, and the input port I... PTAT2 Output port I of the positive temperature coefficient current generating circuit PTAT2 Connected, input port I Pbias1 Output port I of the initial bias current source Pbias1 Connected, output port I LC Input port I of the reference voltage generation circuit LC Connected, output port I HC Input port I of the reference voltage generation circuit HC Connected; the input ports of the reference voltage generation circuit are LVDD and I. PTAT1 I CTAT I LC with I HC The output port is Vref The input port LVDD is connected to the output port LVDD of the pre-regulator circuit, and the input port I... PTAT1 Output port I of the positive temperature coefficient current generating circuit PTAT1 Connected, input port I CTAT Output port I of the negative temperature coefficient current generating circuit CTAT Connected, input port I LC Output port I of the high and low temperature curvature compensation circuit LC Connected, input port I HC Output port I of the high and low temperature curvature compensation circuit HC Connected, output port V ref With the input port V of the pre-regulator circuit ref Connected, and V ref The port outputs a reference voltage to external circuits. The overall bandgap reference source circuit places the core circuit module under the voltage generated by the pre-regulated circuit, which greatly enhances the power supply rejection capability of the reference voltage compared to existing technologies. Furthermore, by compensating for the temperature curvature of the reference voltage at high and low temperatures respectively, it can better accommodate the voltage output requirements at high and low temperatures and avoid over-compensation for intermediate temperature curvature.

[0010] Furthermore, the initial bias current source includes 5 PMOS transistors, 15 NMOS transistors, and a resistor; the 5 PMOS transistors are designated PM1-PM5, and the 15 NMOS transistors are designated NM1-NM5. 15 One resistor is R1; the source of PM1 is connected to the power supply VDD, and its gate and drain are shorted. The gate of PM1 is connected to the gates of PM2-PM5 respectively; the source of PM2 is connected to the power supply VDD, and its drain is connected to the drain and gate of NM3; the source of PM3 is connected to the power supply VDD, and its drain is connected to the drain and gate of NM4; the source of PM4 is connected to the power supply VDD, and its drain serves as the output port I. Pbias1 The source of PM5 is connected to the power supply VDD, and the drain is used as the output port I. Pbias2 The drain and gate of NM1 are shorted, and simultaneously connected to the gate of PM2; the source is connected to the gate of NM2. The gate of NM2 is connected to the gate of NM3, and the source is connected to R1. One end of R1 is connected to the source of NM2, and the other end is connected to GND. The source of NM3 is connected to GND. The source of NM4 is connected to GND, and its gate and drain are shorted. The gate of NM4 is connected to NM5-NM1 respectively. 15 The gates of the two terminals are connected together; the source of the NM5 is connected to GND, and the drain is used as the output port I. Nbias1 The source of the NM6 is connected to GND, and the drain is used as the output port I. Nbias2 The source of the NM7 is connected to GND, and the drain is used as the output port I. Nbias3The source of the NM8 is connected to GND, and the drain is used as the output port I. Nbias4 The source of the NM9 is connected to GND, and the drain is used as the output port I. Nbias5 NM 10 The source is connected to GND, and the drain is used as the output port I. Nbias6 NM 11 The source is connected to GND, and the drain is used as the output port I. Nbias7 NM 12 The source is connected to GND, and the drain is used as the output port I. Nbias8 NM 13 The source is connected to GND, and the drain is used as the output port I. Nbias9 NM 14 The source is connected to GND, and the drain is used as the output port I. Nbias10 NM 15 The source is connected to GND, and the drain is used as the output port I. Nbias11 .

[0011] The pre-regulator circuit includes one operational amplifier, six PMOS transistors, two NMOS transistors, four resistors, and one capacitor; the operational amplifier is denoted as op-amp 1, and the six PMOS transistors are PM6-PM6. 11 The two NMOS transistors are NM 16 and NM 17 The four resistors are R2-R5, and the capacitor is C1. The input port VDD of op-amp 1 is connected to the power supply VDD, the GND port is connected to GND, and the inverting input port is connected to the output port V of the reference voltage generation circuit. ref The non-inverting input port is connected to the center voltage divider point of resistors R2 and R3 connected in series. Input port I Nbias9 and I Nbias10 Connect to the output port I of the initial bias current source Nbias9 and I Nbias10 The output port OUT of operational amplifier 1 is connected to the gate of PM6; the source of PM6 is connected to the power supply VDD, and its drain is connected to R2, serving as the output port LVDD of the pre-regulator circuit; the source of PM7 is connected to the power supply VDD, and its gate is connected to PM6. 11 The drains of PM8 are connected together, and the drain is connected to the output port LVDD; the source of PM8 is connected to the input port I. Pbias2 Connected, gate and PM 10 The drain of PM9 is connected to R4, and the drain is connected to the center voltage divider point of R4 and R5 connected in series. The source of PM9 is connected to R5, and the gate is connected to the center voltage divider point of R2 and R3 connected in series. The drain is connected to NM. 16 The drain and gate are connected; PM 10 The source and input port I Pbias2 Connected, gate and input port V ref Connected, drain and NM17 The drains are connected; PM 11 The source is connected to the power supply VDD, and the gate is connected to PM. 10 The drain is connected to the input port I. Nbias11 Connected; NM 16 The source is connected to GND, and the gate and drain are shorted; NM 17 The source of the capacitor is connected to GND; resistors R2 and R3 are connected in series, with the other end of R2 being the output port LVDD and the other end of R3 being connected to GND; capacitor C1 is connected between the gate and drain of the PM6 capacitor. The pre-regulator circuit replaces the traditional startup circuit by adding a logic judgment circuit, solving the startup problem. Compared with existing technologies, it simplifies the circuit structure while ensuring good startup timing.

[0012] The positive temperature coefficient current generating circuit includes one operational amplifier, nine PMOS transistors, two PNP bipolar transistors, and one resistor; the operational amplifier is denoted as op-amp 2, and the nine PMOS transistors are denoted as PM 1, P2, P3, P4, P5, P6, P7, P8, P9, P1, P2 ...2, P3, P4, P5, P6, P1, P 12 -PM 20 The two PNP transistors are PNP1 and PNP2, and the resistor is R6. The input port LVDD of op-amp 2 is connected to the power supply LVDD, the GND port is connected to GND, the inverting input port is connected to the emitter of PNP2, the non-inverting input port is connected to the upper end of R6, and the input port I... Nbias2 and I Nbias3 Connect to the output port I of the initial bias current source Nbias2 and I Nbias3 The output port OUT of op-amp 2 is connected to PM 13 PM 15 PM 17 and PM 19 The gates are connected; PM 12 The source is connected to LVDD, and the gate and drain are shorted to the input port I. Nbias1 Connected, and with PM 14 PM 16 PM 18 and PM 20 The gates are connected; PM 13 The source is connected to LVDD, and the drain is connected to PM. 14 The source and the pole are connected; PM 14 The drain of PM is connected to the upper end of R6; 15 The source is connected to LVDD, and the drain is connected to PM. 16 The source and the pole are connected; PM 16 The drain of PM is connected to the emitter of the PNP2; 17 The source is connected to LVDD, and the drain is connected to PM. 18 The source and the pole are connected; PM 18 The drain is the output port I PTAT1 PM19 The source is connected to LVDD, and the drain is connected to PM. 20 The source of PM; 20 The drain is the output port I PTAT2 The base and collector of PNP1 are shorted and then connected to GND; the base and collector of PNP2 are shorted and then connected to GND; R6 is connected to PM. 14 Between the drain of PNP1 and the emitter of PNP1.

[0013] The negative temperature coefficient current generating circuit includes one operational amplifier, seven PMOS transistors, one NMOS transistor, one PNP transistor, and one resistor; let the operational amplifier be designated as op-amp 3, and the seven PMOS transistors be designated as PM3. 21 -PM 27 One NMOS transistor is an NM 18 One PNP transistor is a PNP3, and one resistor is R7. The input port LVDD of op-amp 3 is connected to LVDD, the GND port is connected to GND, and the inverting input port is connected to NM. 18 The source of the PNP3 is connected to the emitter of the PNP3, and the input port I is connected to the emitter of the PNP3. Nbias5 and I Nbias6 Output port I of the initial bias current source Nbias5 and I Nbias6 Connect the output port OUT to NM 18 The gates are connected; PM 21 The source is connected to LVDD, and the gate and drain are shorted to the input port I. Nbias4 Connected, and respectively with PM 23 PM 25 and PM 27 The gates are connected; PM 22 The source is connected to LVDD, and the gate is connected to PM respectively. 24 and PM 26 The gate is connected to the drain and the PM. 23 The source and the pole are connected; PM 23 The drain of the PNP3 is connected to the emitter of the PNP3; PM 24 The source is connected to LVDD, and the drain is connected to PM. 25 The source of PM; 25 Drain connection to PM 24 gate and NM 18 Drain; PM 26 The source is connected to LVDD, and the drain is connected to PM. 27 The source of PM; 27 The drain is the output port I CTAT NM 18 The source of the PNP3 is connected to the upper end of R7; the base and collector of the PNP3 are shorted and connected to GND, and the emitter is connected to the non-inverting input port of the operational amplifier 3; R7 is connected across NM18 Between the source and GND.

[0014] The high and low temperature curvature compensation circuit includes two PMOS transistors, seven NMOS transistors, one resistor, and one NPN transistor; the two PMOS transistors are denoted as PM10, PM20, PM30, PM40, PM5, PM60, PM7, PM8, PM10 ... 28 and PM 29 The seven NMOS transistors are NM 19 -NM 25 One resistor is R8, and one NPN transistor is NPN1; PM 28 The source is connected to LVDD, and the gate is connected to NM. 22 The drain of R8 and the lower end of R8 form the output port I. HC PM 29 The source is connected to LVDD, and the gate is connected to the emitter of NPN1 and NM. 24 The drain is the output port I. LC NM 19 After the drain and gate are shorted, they are connected to the input port I. Pbias1 Connected, and respectively connected to NM 20 NM 22 and NM 24 The gates are connected; NM 20 The drain and input port I PTAT2 and NM 21 The gate is connected to the source and the source is connected to the NM. 21 The drains are connected; NM 21 The source is connected to GND, and the gate is connected to NM. 20 While the drain is connected, it is respectively connected to NM 23 and NM 25 The gates are connected; NM 22 The source and NM 23 The drains are connected; NM 23 The source is connected to GND; NM 24 The source terminal of NM 25 Drain; NM 25 The source is connected to GND; R8 is connected across PM. 28 Between the source and gate; the collector and base of NPN1 are shorted and then connected to LVDD, and the emitter is connected to PM. 29 The gate of the reference voltage generation circuit utilizes the temperature characteristics of resistor R8 and the voltage across transistor NPN1 to construct a compensation current I that is generated only in the high-temperature and low-temperature ranges, respectively. HC and I LC Compared to existing technologies, this technology greatly simplifies the circuit structure while ensuring the temperature curvature compensation effect.

[0015] The reference voltage generation circuit includes one operational amplifier and two resistors; let the operational amplifier be designated as op-amp 4, and the two resistors be R9 and R... 10 The LVDD input port of op-amp 4 is connected to LVDD, the GND port is connected to GND, the inverting input port is shorted to the output port, and it is used as the output port V. ref Output reference voltage to the outside, input port I Nbias7 and I Nbias8 The output ports I of the initial bias current source are respectively connected to the output ports of the bias current source. Nbias7 and I Nbias8 Connected; the upper end of R9 is connected to input port I respectively. PTAT1 and I CTAT Connected, R9 and R 10 The center voltage divider point after series connection is respectively connected to the input port I LC and I HC Connected; R 10 The lower end is connected to GND. The reference voltage passes through an additional buffer, making V... ref It has a stronger current drive capability and can provide a reference voltage for more circuit modules with load attributes.

[0016] The above circuit module uses an operational amplifier circuit module. The operational amplifier used in this invention includes 13 PMOS transistors and 5 NMOS transistors; let the 13 PMOS transistors be labeled PM13, PM2.5, PM3.5, PM4.5, PM5.5, PM6.5, PM13, PM14.5, PM15, PM16. ... 30 -PM 42 The five NMOS transistors are NM 26 -NM 30 PM 30 The source is connected to the power supply VCC, and the gate and drain are shorted and then connected to the input port I. NbiasA And respectively with PM 32 PM 34 PM 36 PM 40 and PM 42 The gates are connected; PM 31 The source is connected to VCC, and the drain is connected to PM. 32 The source and gate are respectively connected to PM 33 PM 35 PM 39 and PM 41 The gates are connected; PM 32 The drain is connected to the input port I. NbiasB PM 33 The source is connected to VCC, and the drain is connected to PM. 34 The source of PM; 34 The drain is connected to NM 26 Gate and drain; PM 35 The source is connected to VCC, and the drain is connected to PM. 36The source of PM; 36 Drain connection to PM 37 and PM 38 The source of PM; 37 The gate is connected to the non-inverting input port INP, and the drain is connected to NM. 28 Drain; PM 38 The gate is connected to the inverting input port INN, and the drain is connected to NM. 30 Drain; PM 39 The source is connected to VCC, and the drain is connected to PM. 40 The source of PM; 40 The drain is connected to NM 27 The drain and NM 28 The gate of PM; 41 The source is connected to VCC, and the drain is connected to PM. 42 The source of PM; 42 The drain and NM 29 The drains are connected together and form the output port OUT of the operational amplifier; NM 26 The gate and drain are shorted and then connected to NM. 27 and NM 29 The gate and source are connected to GND; NM 27 The drain is connected to NM 28 The gate and source are connected to NM 28 Drain; NM 28 The gate and NM 30 The gate is connected to the source, and the source is connected to GND; NM 29 The source terminal of NM 30 Drain; NM 30 The source is connected to GND.

[0017] Compared with existing traditional technologies, this invention effectively solves the defects of traditional bandgap reference sources, such as large temperature coefficient, weak power supply anti-interference capability, and susceptibility to interference in the accuracy of output reference voltage, through structural optimization and innovative compensation circuits. It has significant advantages such as small temperature coefficient, strong anti-interference capability, and high output accuracy. The specific beneficial effects are as follows:

[0018] 1. This invention achieves high and low temperature curvature compensation, significantly reducing the temperature coefficient of the reference voltage. Traditional bandgap reference sources often employ a single linear temperature compensation method, which can only correct the first-order temperature drift of the reference voltage and cannot offset the nonlinear drift of the voltage curve under high and low temperature conditions. The temperature coefficient is typically 30 ppm / ℃. This invention innovatively corrects the curvature drift error in the low and high temperature ranges, improving the compensation blind zone of traditional compensation methods, effectively suppressing the nonlinear fluctuations of the reference voltage in the low and high temperature ranges, and significantly reducing the overall temperature coefficient to below 10 ppm / ℃.

[0019] 2. By adding a pre-regulator circuit module, the anti-interference capability of the bandgap reference source is significantly improved. Traditional bandgap reference sources often have their core circuits directly powered by the system power supply, causing the reference output voltage to easily deviate with changes in the power supply voltage, resulting in poor power supply rejection ratio (PSRR). This invention, by adding an independent pre-regulator circuit module, can perform pre-regulation and filtering of the input power supply voltage, providing the core circuit of the bandgap reference source with a relatively stable power supply voltage that isolates it from power supply disturbances. This suppresses the influence of the power supply voltage on the core circuit and the output reference voltage, thereby improving the power supply anti-interference capability and PSRR performance of the bandgap reference source. Attached Figure Description

[0020] Figure 1 This is a block diagram of the overall structure of the circuit of the present invention.

[0021] Figure 2 This is a schematic diagram of the initial bias current source.

[0022] Figure 3 This is the schematic diagram of the pre-regulator circuit.

[0023] Figure 4 This is a schematic diagram of a positive temperature coefficient current generating circuit.

[0024] Figure 5 This is a schematic diagram of a circuit that generates current with a negative temperature coefficient.

[0025] Figure 6 This is a schematic diagram of a high and low temperature curvature compensation circuit.

[0026] Figure 7 This is a schematic diagram of a reference voltage generation circuit.

[0027] Figure 8 This is the schematic diagram of an operational amplifier.

[0028] Figure 9 Transient simulation diagram of the output reference voltage of the bandgap reference source.

[0029] Figure 10 The temperature curve simulation diagram of the output reference voltage of the bandgap reference source.

[0030] Figure 11 The power supply rejection ratio (PSRR) is a simulation diagram of the output reference voltage of the bandgap reference source. Detailed Implementation

[0031] The present invention will now be described in detail with reference to the accompanying drawings and embodiments. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without inventive effort are within the scope of protection of the present invention.

[0032] Example: Refer to Figure 1 A pre-regulated bandgap reference source with high and low temperature curvature compensation includes an initial bias current source, a pre-regulation circuit, a positive temperature coefficient current generation circuit, a negative temperature coefficient current generation circuit, a high and low temperature curvature compensation circuit, and a reference voltage generation circuit. The basic architecture is as follows: the initial bias current source provides the bias current source for other circuit modules after power-on; the pre-regulation circuit provides a fixed supply voltage to the core circuit of the bandgap reference source, unaffected by the power supply voltage; the positive and negative temperature coefficient current generation circuits generate currents positively and negatively correlated with temperature, respectively; the high and low temperature curvature compensation circuit generates currents that compensate for the high and low temperature portions of the temperature curve; and the reference voltage generation circuit sums the currents from each circuit and generates a temperature-independent reference voltage, which is then output to external circuits through a buffer. The input port of the initial bias current source is the power supply VDD, and the output port is I... Nbias with I Pbias , where I Nbias Includes I Nbias1 To I Nbias11 There are 11 ports in total, I Pbias Includes I Pbias1 and I Pbias2 Two ports: the input port VDD is connected to an external power supply, and the output port I... Nbias1 Input port I connected to the positive temperature coefficient current generating circuit Nbias1 Output port I Nbias2 Input port I connected to the positive temperature coefficient current generating circuit Nbias2 Output port I Nbias3 Input port I connected to the positive temperature coefficient current generating circuit Nbias3 Output port I Nbias4 Input port I connected to the negative temperature coefficient current generating circuit Nbias4 Output port I Nbias5 Input port I connected to the negative temperature coefficient current generating circuit Nbias5 Output port I Nbias6 Input port I connected to the negative temperature coefficient current generating circuit Nbias6 Output port I Nbias7 Input port I connected to the reference voltage generation circuit Nbias7 Output port I Nbias8 Input port I connected to the reference voltage generation circuit Nbias8 Output port I Nbias9 Input port I connected to the pre-regulator circuit Nbias9 Output port I Nbias10 Input port I connected to the pre-regulator circuit Nbias10 Output port I Nbias11Input port I connected to the pre-regulator circuit Nbias11 Output port I Pbias1 Input port I connected to the high and low temperature curvature compensation circuit Pbias1 Output port I Pbias2 Input port I connected to the pre-regulator circuit Pbias2 The input ports of the pre-regulator circuit are VDD and V... ref I Pbias2 I Nbias9 I Nbias10 with I Nbias11 The output port is LVDD, the input port VDD is connected to the external power supply, and the input port V... ref The output port V of the reference voltage generation circuit ref Connected, input port I Pbias2 Output port I of the initial bias current source Pbias2 Connected, input port I Nbias9 Output port I of the initial bias current source Nbias9 Connected, input port I Nbias10 Output port I of the initial bias current source Nbias10 Connected, input port I Nbias11 Output port I of the initial bias current source Nbias11 The output port LVDD is connected to the input port LVDD of the positive temperature coefficient current generating circuit, the negative temperature coefficient current generating circuit, the high and low temperature curvature compensation circuit, and the reference voltage generating circuit, respectively; the input port of the positive temperature coefficient current generating circuit is LVDD, I Nbias1 I Nbias2 and I Nbias3 The output port is I PTAT1 and I PTAT2 The input port LVDD is connected to the output port LVDD of the pre-regulator circuit, and the input port I... Nbias1 Output port I of the initial bias current source Nbias1 Connected, input port I Nbias2 Output port I of the initial bias current source Nbias2 Connected, input port I Nbias3 Output port I of the initial bias current source Nbias3 Connected, output port I PTAT1 Input port I of the reference voltage generation circuit PTAT1 Connected, output port I PTAT2 Input port I of the high and low temperature curvature compensation circuit PTAT2 Connected; the input ports of the negative temperature coefficient current generating circuit are LVDD and I. Nbias4 I Nbias5 with I Nbias6 The output port is ICTAT The input port LVDD is connected to the output port LVDD of the pre-regulator circuit, and the input port I... Nbias4 Output port I of the initial bias current source Nbias4 Connected, input port I Nbias5 Output port I of the initial bias current source Nbias5 Connected, input port I Nbias6 Output port I of the initial bias current source Nbias6 Connected, output port I CTAT Input port I of the reference voltage generation circuit CTAT The ports are connected; the input ports of the high and low temperature curvature compensation circuit are LVDD and I. PTAT2 with I Pbias1 The output port is the low-temperature compensation current port I. LC and high temperature compensation current port I HC The input port LVDD is connected to the output port LVDD of the pre-regulator circuit, and the input port I... PTAT2 Output port I of the positive temperature coefficient current generating circuit PTAT2 Connected, input port I Pbias1 Output port I of the initial bias current source Pbias1 Connected, output port I LC Input port I of the reference voltage generation circuit LC Connected, output port I HC Input port I of the reference voltage generation circuit HC Connected; the input ports of the reference voltage generation circuit are LVDD and I. PTAT1 I CTAT I LC with I HC The output port is V ref The input port LVDD is connected to the output port LVDD of the pre-regulator circuit, and the input port I... PTAT1 Output port I of the positive temperature coefficient current generating circuit PTAT1 Connected, input port I CTAT Output port I of the negative temperature coefficient current generating circuit CTAT Connected, input port I LC Output port I of the high and low temperature curvature compensation circuit LC Connected, input port I HC Output port I of the high and low temperature curvature compensation circuit HC Connected, output port V ref With the input port V of the pre-regulator circuit ref Connected, and V ref The port outputs a reference voltage to external circuits.

[0033] The schematic diagram of the initial bias current source is as follows: Figure 2 As shown, this circuit structure controls the drain currents of NM2 and NM3 to be equal through a current mirror formed by PM1 and PM2. Then, by setting the size ratio of NM2 and NM3 to 4:1, a bias current is formed on R1 using the gate-source voltage difference between NM2 and NM3, and this bias current is transmitted through PM3-PM5 and NM4-NM3. 15 A series of current mirrors provide bias current to other circuit modules. NM1 is the startup circuit for the initial bias current source. During the circuit startup phase, when the supply voltage exceeds the sum of the threshold voltages of PM1, NM1, and NM3, it can generate current to help the circuit overcome the dead zone. After the circuit startup is complete, when the supply voltage is less than the sum of the source-gate voltages of PM1 and NM1 and the threshold voltage of NM1, NM1 is turned off, and the startup circuit shuts down. (Refer to...) Figure 2 The source of the initial bias current source PM1 is connected to the power supply VDD, and its gate and drain are shorted. The gate of PM1 is connected to the gates of PM2-PM5 respectively. The source of PM2 is connected to the power supply VDD, and its drain is connected to the drain and gate of NM3. The source of PM3 is connected to the power supply VDD, and its drain is connected to the drain and gate of NM4. The source of PM4 is connected to the power supply VDD, and its drain serves as the output port I. Pbias1 The source of PM5 is connected to the power supply VDD, and the drain is used as the output port I. Pbias2 The drain and gate of NM1 are shorted, and simultaneously connected to the gate of PM2; the source is connected to the gate of NM2. The gate of NM2 is connected to the gate of NM3, and the source is connected to R1. One end of R1 is connected to the source of NM2, and the other end is connected to GND. The source of NM3 is connected to GND. The source of NM4 is connected to GND, and its gate and drain are shorted. The gate of NM4 is connected to NM5-NM1 respectively. 15 The gates of the two terminals are connected together; the source of the NM5 is connected to GND, and the drain is used as the output port I. Nbias1 The source of the NM6 is connected to GND, and the drain is used as the output port I. Nbias2 The source of the NM7 is connected to GND, and the drain is used as the output port I. Nbias3 The source of the NM8 is connected to GND, and the drain is used as the output port I. Nbias4 The source of the NM9 is connected to GND, and the drain is used as the output port I. Nbias5 NM 10 The source is connected to GND, and the drain is used as the output port I. Nbias6 NM 11 The source is connected to GND, and the drain is used as the output port I. Nbias7 NM 12 The source is connected to GND, and the drain is used as the output port I. Nbias8 NM 13 The source is connected to GND, and the drain is used as the output port I. Nbias9 NM14 The source is connected to GND, and the drain is used as the output port I. Nbias10 NM 15 The source is connected to GND, and the drain is used as the output port I. Nbias11 .

[0034] The schematic diagram of the pre-regulator circuit is as follows: Figure 3 As shown, this circuit structure uses V ref Using the operational amplifier, PM6, and feedback resistors R2 and R3 as the reference voltage, a negative feedback network is formed to generate the output voltage LVDD. To ensure loop stability, capacitor C1 connected between the gate and drain of PM6 provides Miller compensation for the loop. Since the LVDD voltage is determined by the reference voltage V... ref The feedback voltage is generated after feedback, and since the core circuit of the bandgap reference source is powered by the LVDD voltage, a judgment circuit is needed to prevent the circuit from entering the dead zone. This is achieved by judging whether the feedback voltage formed by the center point of the voltage divider between R2 and R3 is close to V. ref To determine whether LVDD has completed startup, resistors R4, R5, and PM8 create a hysteresis. Before LVDD startup is complete, PM7 is turned on, making LVDD equal to VDD, and VDD provides power to the core circuitry of the bandgap reference source. After LVDD startup is complete, PM7 is turned off, and LVDD provides power to the core circuitry of the bandgap reference source. (Refer to...) Figure 3 The input port VDD of operational amplifier 1 in the pre-regulator circuit is connected to the power supply VDD, the GND port is connected to GND, and the inverting input port is connected to the output port V of the reference voltage generation circuit. ref The non-inverting input port is connected to the center voltage divider point of resistors R2 and R3 connected in series. Input port I Nbias9 and I Nbias10 Connect to the output port I of the initial bias current source Nbias9 and I Nbias10 The output port OUT of operational amplifier 1 is connected to the gate of PM6; the source of PM6 is connected to the power supply VDD, and its drain is connected to R2, serving as the output port LVDD of the pre-regulator circuit; the source of PM7 is connected to the power supply VDD, and its gate is connected to PM6. 11 The drains of PM8 are connected together, and the drain is connected to the output port LVDD; the source of PM8 is connected to the input port I. Pbias2 Connected, gate and PM 10 The drain of PM9 is connected to R4, and the drain is connected to the center voltage divider point of R4 and R5 connected in series. The source of PM9 is connected to R5, and the gate is connected to the center voltage divider point of R2 and R3 connected in series. The drain is connected to NM. 16 The drain and gate are connected; PM 10 The source and input port I Pbias2 Connected, gate and input port V ref Connected, drain and NM 17The drains are connected; PM 11 The source is connected to the power supply VDD, and the gate is connected to PM. 10 The drain is connected to the input port I. Nbias11 Connected; NM 16 The source is connected to GND, and the gate and drain are shorted; NM 17 The source of PM6 is connected to GND; resistors R2 and R3 are connected in series, with the other end of R2 being the output port LVDD and the other end of R3 being connected to GND; C1 is connected between the gate and drain of PM6.

[0035] The schematic diagram of the positive temperature coefficient current generating circuit is as follows: Figure 4 As shown, this circuit structure is achieved through PM 13 PM 14 and PM 15 PM 16 The formed current mirror controls the emitter-collector currents of PNP1 and PNP2 to be equal, while setting the size ratio of PNP1 and PNP2 to 8:1. Subsequently, through the negative feedback loop formed by the operational amplifier, the voltage at the upper end of R6 is made to achieve a virtual short between the voltage at the emitter of PNP2, ultimately forming a temperature-proportional ΔV on R6. EB Voltage and current with a positive temperature coefficient, and I formed through a current mirror. PTAT1 and I PTAT2 Two positive temperature coefficient current output ports. PM 12 It can generate a bias voltage after receiving current from an initial bias current source, constructing a cascode layer for a series of current mirrors, suppressing channel length modulation effects, and further improving the current mirror replication accuracy. (Refer to...) Figure 4 In the positive temperature coefficient current generating circuit, the input port LVDD of operational amplifier 2 is connected to the power supply LVDD, the GND port is connected to GND, the inverting input port is connected to the emitter of PNP2, the non-inverting input port is connected to the upper end of R6, and the input port I... Nbias2 and I Nbias3 Connect to the output port I of the initial bias current source Nbias2 and I Nbias3 The output port OUT of op-amp 2 is connected to PM 13 PM 15 PM 17 and PM 19 The gates are connected; PM 12 The source is connected to LVDD, and the gate and drain are shorted to the input port I. Nbias1 Connected, and with PM 14 PM 16 PM 18 and PM 20 The gates are connected; PM 13 The source is connected to LVDD, and the drain is connected to PM. 14The source and the pole are connected; PM 14 The drain of PM is connected to the upper end of R6; 15 The source is connected to LVDD, and the drain is connected to PM. 16 The source and the pole are connected; PM 16 The drain of PM is connected to the emitter of the PNP2; 17 The source is connected to LVDD, and the drain is connected to PM. 18 The source and the pole are connected; PM 18 The drain is the output port I PTAT1 PM 19 The source is connected to LVDD, and the drain is connected to PM. 20 The source of PM; 20 The drain is the output port I PTAT2 The base and collector of PNP1 are shorted and then connected to GND; the base and collector of PNP2 are shorted and then connected to GND; R6 is connected to PM. 14 Between the drain of PNP1 and the emitter of PNP1.

[0036] The schematic diagram of the negative temperature coefficient current generating circuit is as follows: Figure 5 As shown, this circuit structure utilizes the negative temperature coefficient current across resistor R7 by leveraging the emitter-base voltage of the PNP3 amplifier. Op-amp 3 and NM... 18 It can provide a certain driving capability for the emitter-base voltage of the PNP3. The negative temperature coefficient current on R7 passes through PM 24 PM 25 and PM 26 PM 27 The current mirror formed forms the output current port I. CTAT PM 21 It can generate a bias voltage after receiving current from an initial bias current source, constructing a cascode layer for a series of current mirrors, suppressing channel length modulation effects, and further improving the current mirror replication accuracy. (Refer to...) Figure 5 In the negative temperature coefficient current generating circuit, the input port LVDD of operational amplifier 3 is connected to LVDD, the GND port is connected to GND, and the inverting input port is connected to NM. 18 The source of the PNP3 is connected to the emitter of the PNP3, and the input port I is connected to the emitter of the PNP3. Nbias5 and I Nbias6 Output port I of the initial bias current source Nbias5 and I Nbias6 Connect the output port OUT to NM 18 The gates are connected; PM 21 The source is connected to LVDD, and the gate and drain are shorted to the input port I. Nbias4 Connected, and respectively with PM 23 PM 25 and PM 27The gates are connected; PM 22 The source is connected to LVDD, and the gate is connected to PM respectively. 24 and PM 26 The gate is connected to the drain and the PM. 23 The source and the pole are connected; PM 23 The drain of the PNP3 is connected to the emitter of the PNP3; PM 24 The source is connected to LVDD, and the drain is connected to PM. 25 The source of PM; 25 Drain connection to PM 24 gate and NM 18 Drain; PM 26 The source is connected to LVDD, and the drain is connected to PM. 27 The source of PM; 27 The drain is the output port I CTAT NM 18 The source of the PNP3 is connected to the upper end of R7; the base and collector of the PNP3 are shorted and connected to GND, and the emitter is connected to the non-inverting input port of the operational amplifier 3; R7 is connected across NM 18 Between the source and GND.

[0037] The schematic diagram of the high and low temperature curvature compensation circuit is as follows: Figure 6 As shown, this circuit structure utilizes the different voltage and temperature characteristics of R8 and NPN1 to achieve different performance at PM. 28 and PM 29 The drain provides high-temperature and low-temperature current compensation. Because R8 receives a positive temperature coefficient current from the current mirror, the voltage across its lower terminal decreases as temperature rises, while PM... 28 The source-gate voltage is smaller at low temperatures and larger at high temperatures. PM 28 The leakage current is smaller or shut off at low temperatures, and larger at high temperatures; the base-emitter voltage of NPN1 decreases as temperature increases, while PM... 29 The source-gate voltage is larger at low temperatures and smaller at high temperatures. PM 29 The leakage current is larger at low temperatures and smaller or shut off at high temperatures. (Through I) HC and I LC Current compensation at both high and low temperatures allows for a smaller temperature coefficient in the reference voltage. (Refer to...) Figure 6 PM of high and low temperature curvature compensation circuit 28 Source connected to LVDD, gate connected to NM 22 The drain of R8 and the lower end of R8 form the output port I. HC PM 29 The source is connected to LVDD, and the gate is connected to the emitter of NPN1 and NM. 24 The drain is the output port I. LC NM 19After the drain and gate are shorted, they are connected to the input port I. Pbias1 Connected, and respectively connected to NM 20 NM 22 and NM 24 The gates are connected; NM 20 The drain and input port I PTAT2 and NM 21 The gate is connected to the source and the source is connected to the NM. 21 The drains are connected; NM 21 The source is connected to GND, and the gate is connected to NM. 20 While the drain is connected, it is respectively connected to NM 23 and NM 25 The gates are connected; NM 22 The source and NM 23 The drains are connected; NM 23 The source is connected to GND; NM 24 The source terminal of NM 25 Drain; NM 25 The source is connected to GND; R8 is connected across PM. 28 Between the source and gate; the collector and base of NPN1 are shorted and then connected to LVDD, and the emitter is connected to PM. 29 The gate.

[0038] The schematic diagram of the reference voltage generation circuit is as follows: Figure 7 As shown, this circuit structure will I LC I HC I PTAT1 and I CTAT The four currents are summed, and then R is calculated. 10 A reference voltage is formed on top, and V is simultaneously realized through a buffer composed of operational amplifiers. ref The buffer can provide a reference voltage output and a voltage of V. ref Provides a certain current drive capability. (Refer to...) Figure 7 In the reference voltage generation circuit, the LVDD input port of operational amplifier 4 is connected to LVDD, the GND port is connected to GND, the inverting input port is shorted to the output port, and serves as the output port V. ref Output reference voltage to the outside, input port I Nbias7 and I Nbias8 The output ports I of the initial bias current source are respectively connected to the output ports of the bias current source. Nbias7 and I Nbias8 Connected; the upper end of R9 is connected to input port I respectively. PTAT1 and I CTAT Connected, R9 and R 10 The center voltage divider point after series connection is respectively connected to the input port I LC and I HC Connected; R 10 The lower end is connected to GND.

[0039] The schematic diagram of the operational amplifier is as follows: Figure 8 As shown, the circuit structure uses PM 37 and PM 38 For input transistors, a folded cascode structure is adopted, PM 30 and NM 26 Bias voltages are provided for the common-source, common-gate layers of the PMOS and NMOS current mirrors, respectively. (Refer to...) Figure 8 The PM of the operational amplifier 30 The source is connected to the power supply VCC, and the gate and drain are shorted and then connected to the input port I. NbiasA And respectively with PM 32 PM 34 PM 36 PM 40 and PM 42 The gates are connected; PM 31 The source is connected to VCC, and the drain is connected to PM. 32 The source and gate are respectively connected to PM 33 PM 35 PM 39 and PM 41 The gates are connected; PM 32 The drain is connected to the input port I. NbiasB PM 33 The source is connected to VCC, and the drain is connected to PM. 34 The source of PM; 34 The drain is connected to NM 26 Gate and drain; PM 35 The source is connected to VCC, and the drain is connected to PM. 36 The source of PM; 36 Drain connection to PM 37 and PM 38 The source of PM; 37 The gate is connected to the non-inverting input port INP, and the drain is connected to NM. 28 Drain; PM 38 The gate is connected to the inverting input port INN, and the drain is connected to NM. 30 Drain; PM 39 The source is connected to VCC, and the drain is connected to PM. 40 The source of PM; 40 The drain is connected to NM 27 The drain and NM 28 The gate of PM; 41 The source is connected to VCC, and the drain is connected to PM. 42 The source of PM; 42 The drain and NM 29 The drains are connected together and form the output port OUT of the operational amplifier; NM 26The gate and drain are shorted and then connected to NM. 27 and NM 29 The gate and source are connected to GND; NM 27 The drain is connected to NM 28 The gate and source are connected to NM 28 Drain; NM 28 The gate and NM 30 The gate is connected to the source, and the source is connected to GND; NM 29 The source terminal of NM 30 Drain; NM 30 The source is connected to GND.

[0040] Example 1:

[0041] Reference Figure 1 This invention only requires a 2.2-3V power supply to the VDD terminal of the circuit to achieve output V... ref A reference voltage of 500mV is obtained at the location.

[0042] refer to Figure 7 Schematic diagram of the reference voltage generation circuit, V ref It can be represented as:

[0043]

[0044] Where R 10 for Figure 7 The resistance I in the reference voltage generation circuit LC and I HC for Figure 6 The low-temperature and high-temperature compensation currents generated by the high and low temperature curvature compensation circuit, I PTAT1 for Figure 4 The output current I of the positive temperature coefficient current generating circuit PTAT1 ,I CTAT for Figure 5 The output current I of the negative temperature coefficient current generating circuit CTAT .

[0045] refer to Figure 4 Schematic diagram of a positive temperature coefficient current generating circuit, I PTAT1 It can be represented as:

[0046]

[0047] Where V EB1 and V EB2 They are respectively Figure 4 The emitter-base voltages of PNP1 and PNP2 are given by R6. Figure 4 The resistance in (W / L) P13 and (W / L) P17 Divided into PM13 and PM 17 The aspect ratio.

[0048] refer to Figure 5 Schematic diagram of a negative temperature coefficient current generating circuit, I CTAT It can be represented as:

[0049]

[0050] Where V EB3 for Figure 5 The emitter-base voltage of the PNP3 is given by R7. Figure 5 The resistance in it.

[0051] refer to Figure 6 Schematic diagram of high and low temperature curvature compensation circuit, I LC and I HC It can be represented as:

[0052]

[0053]

[0054] Where V BE1 for Figure 6 The emitter-base voltage of NPN1, |V TH29 |For PM 29 The threshold voltage, I PTAT2 The positive temperature coefficient current (W / L) of the positive temperature coefficient generating circuit. N21 (W / L) N23 (W / L) P28 (W / L) P29 NM respectively 21 NM 23 PM 28 and PM 29 The aspect ratio, R8 is Figure 6 The resistance in |V TH28 |For PM 28 Threshold voltage.

[0055] Based on the above formula and the specific parameters of the process used, V can be calculated. ref The value is approximately 500mV.

[0056] Based on the analysis of the circuit structure and principle, in order to further describe the actual effect of the invention, the circuit of the invention was built and simulated based on the 0.18μm BCD process. Figure 9 Reference voltage V ref The transient simulation diagram at startup shows that a stable voltage of approximately 500mV is formed after startup, which is consistent with the calculation results. Figure 10Reference voltage V ref The temperature curve simulation graph shows that the difference between the maximum and minimum values ​​is less than 0.65mV, and the temperature coefficient is approximately 8.13ppm / ℃. Figure 11 The simulation graph shows the power supply rejection ratio (PSRR) of the bandgap reference voltage. At low frequencies, the PSRR can reach -76dB.

[0057] It should be noted that the above embodiments are not intended to limit the scope of protection of the present invention. Equivalent transformations or substitutions made based on the above technical solutions all fall within the scope of protection of the claims of the present invention.

Claims

1. A pre-stabilized bandgap reference source with high and low temperature curvature compensation, characterized in that, It includes an initial bias current source, a pre-regulator circuit, a positive temperature coefficient current generation circuit, a negative temperature coefficient current generation circuit, a high and low temperature curvature compensation circuit, and a reference voltage generation circuit. The initial bias current source is connected to the pre-regulator circuit, the positive temperature coefficient current generation circuit, the negative temperature coefficient current generation circuit, the high and low temperature curvature compensation circuit, and the reference voltage generation circuit, respectively, and provides the bias current source for these circuits after they are powered on. The pre-regulator circuit is connected to the positive temperature coefficient current generation circuit, the negative temperature coefficient current generation circuit, the high and low temperature curvature compensation circuit, and the reference voltage generation circuit, respectively, and provides a fixed supply voltage for the core circuit of the bandgap reference source that is unaffected by the power supply voltage. The positive temperature coefficient current generating circuit is connected to the negative temperature coefficient current generating circuit and the reference voltage generating circuit respectively, providing them with a current that is positively correlated with temperature; A negative temperature coefficient current generating circuit is connected to a reference voltage generating circuit, providing it with a current that is negatively correlated with temperature; a high and low temperature curvature compensation circuit is connected to the reference voltage generating circuit, providing it with curvature compensation current for high and low temperatures; the reference voltage generating circuit ultimately generates a reference voltage V. ref It is provided to external circuits.

2. The pre-stabilized bandgap reference source with high and low temperature curvature compensation according to claim 1, characterized in that, The input port of the initial bias current source is the power supply VDD, and the output port is I. Nbias with I Pbias , where I Nbias Includes I Nbias1 To I Nbias11 There are 11 ports in total, I Pbias Includes I Pbias1 and I Pbias2 Two ports: the input port VDD is connected to an external power supply, and the output port I... Nbias1 Input port I connected to the positive temperature coefficient current generating circuit Nbias1 Output port I Nbias2 Input port I connected to the positive temperature coefficient current generating circuit Nbias2 Output port I Nbias3 Input port I connected to the positive temperature coefficient current generating circuit Nbias3 Output port I Nbias4 Input port I connected to the negative temperature coefficient current generating circuit Nbias4 Output port I Nbias5 Input port I connected to the negative temperature coefficient current generating circuit Nbias5 Output port I Nbias6 Input port I connected to the negative temperature coefficient current generating circuit Nbias6 Output port I Nbias7 Input port I connected to the reference voltage generation circuit Nbias7 Output port I Nbias8 Input port I connected to the reference voltage generation circuit Nbias8 Output port I Nbias9 Input port I connected to the pre-regulator circuit Nbias9 Output port I Nbias10 Input port I connected to the pre-regulator circuit Nbias10 Output port I Nbias11 Input port I connected to the pre-regulator circuit Nbias11 Output port I Pbias1 Input port I connected to the high and low temperature curvature compensation circuit Pbias1 Output port I Pbias2 Input port I connected to the pre-regulator circuit Pbias2 The input ports of the pre-regulator circuit are VDD and V... ref I Pbias2 I Nbias9 I Nbias10 with I Nbias11 The output port is LVDD, the input port VDD is connected to the external power supply, and the input port V... ref The output port V of the reference voltage generation circuit ref Connected, input port I Pbias2 Output port I of the initial bias current source Pbias2 Connected, input port I Nbias9 Output port I of the initial bias current source Nbias9 Connected, input port I Nbias10 Output port I of the initial bias current source Nbias10 Connected, input port I Nbias11 Output port I of the initial bias current source Nbias11 The output port LVDD is connected to the input port LVDD of the positive temperature coefficient current generating circuit, the negative temperature coefficient current generating circuit, the high and low temperature curvature compensation circuit, and the reference voltage generating circuit, respectively; the input port of the positive temperature coefficient current generating circuit is LVDD, I Nbias1 I Nbias2 and I Nbias3 The output port is I PTAT1 and I PTAT2 The input port LVDD is connected to the output port LVDD of the pre-regulator circuit, and the input port I... Nbias1 Output port I of the initial bias current source Nbias1 Connected, input port I Nbias2 Output port I of the initial bias current source Nbias2 Connected, input port I Nbias3 Output port I of the initial bias current source Nbias3 Connected, output port I PTAT1 Input port I of the reference voltage generation circuit PTAT1 Connected, output port I PTAT2 Input port I of the high and low temperature curvature compensation circuit PTAT2 Connected; the input ports of the negative temperature coefficient current generating circuit are LVDD and I. Nbias4 I Nbias5 with I Nbias6 The output port is I CTAT The input port LVDD is connected to the output port LVDD of the pre-regulator circuit, and the input port I... Nbias4 Output port I of the initial bias current source Nbias4 Connected, input port I Nbias5 Output port I of the initial bias current source Nbias5 Connected, input port I Nbias6 Output port I of the initial bias current source Nbias6 Connected, output port I CTAT Input port I of the reference voltage generation circuit CTAT The ports are connected; the input ports of the high and low temperature curvature compensation circuit are LVDD and I. PTAT2 with I Pbias1 The output port is the low-temperature compensation current port I. LC and high temperature compensation current port I HC The input port LVDD is connected to the output port LVDD of the pre-regulator circuit, and the input port I... PTAT2 Output port I of the positive temperature coefficient current generating circuit PTAT2 Connected, input port I Pbias1 Output port I of the initial bias current source Pbias1 Connected, output port I LC Input port I of the reference voltage generation circuit LC Connected, output port I HC Input port I of the reference voltage generation circuit HC Connected; the input ports of the reference voltage generation circuit are LVDD and I. PTAT1 I CTAT I LC with I HC The output port is V ref The input port LVDD is connected to the output port LVDD of the pre-regulator circuit, and the input port I... PTAT1 Output port I of the positive temperature coefficient current generating circuit PTAT1 Connected, input port I CTAT Output port I of the negative temperature coefficient current generating circuit CTAT Connected, input port I LC Output port I of the high and low temperature curvature compensation circuit LC Connected, input port I HC Output port I of the high and low temperature curvature compensation circuit HC Connected, output port V ref With the input port V of the pre-regulator circuit ref Connected, and V ref The port outputs a reference voltage to external circuits.

3. A pre-stabilized bandgap reference source with high and low temperature curvature compensation according to claim 1, characterized in that, The initial bias current source includes 5 PMOS transistors, 15 NMOS transistors, and a resistor; the 5 PMOS transistors are designated PM1-PM5, and the 15 NMOS transistors are designated NM1-NM5. 15 One resistor is R1; the source of PM1 is connected to the power supply VDD, and its gate and drain are shorted. The gate of PM1 is connected to the gates of PM2-PM5 respectively; the source of PM2 is connected to the power supply VDD, and its drain is connected to the drain and gate of NM3; the source of PM3 is connected to the power supply VDD, and its drain is connected to the drain and gate of NM4; the source of PM4 is connected to the power supply VDD, and its drain serves as the output port I. Pbias1 The source of PM5 is connected to the power supply VDD, and the drain is used as the output port I. Pbias2 The drain and gate of NM1 are shorted, and simultaneously connected to the gate of PM2; the source is connected to the gate of NM2. The gate of NM2 is connected to the gate of NM3, and the source is connected to R1. One end of R1 is connected to the source of NM2, and the other end is connected to GND. The source of NM3 is connected to GND. The source of NM4 is connected to GND, and its gate and drain are shorted. The gate of NM4 is connected to NM5-NM1 respectively. 15 The gates of the two terminals are connected together; the source of the NM5 is connected to GND, and the drain is used as the output port I. Nbias1 The source of the NM6 is connected to GND, and the drain is used as the output port I. Nbias2 The source of the NM7 is connected to GND, and the drain is used as the output port I. Nbias3 The source of the NM8 is connected to GND, and the drain is used as the output port I. Nbias4 The source of the NM9 is connected to GND, and the drain is used as the output port I. Nbias5 NM 10 The source is connected to GND, and the drain is used as the output port I. Nbias6 NM 11 The source is connected to GND, and the drain is used as the output port I. Nbias7 NM 12 The source is connected to GND, and the drain is used as the output port I. Nbias8 NM 13 The source is connected to GND, and the drain is used as the output port I. Nbias9 NM 14 The source is connected to GND, and the drain is used as the output port I. Nbias10 NM 15 The source is connected to GND, and the drain is used as the output port I. Nbias11 .

4. A pre-stabilized bandgap reference source with high and low temperature curvature compensation according to claim 1, characterized in that, The pre-regulator circuit includes one operational amplifier, six PMOS transistors, two NMOS transistors, four resistors, and one capacitor; the operational amplifier is denoted as op-amp 1, and the six PMOS transistors are PM6-PM6. 11 The two NMOS transistors are NM 16 and NM 17 The four resistors are R2-R5, and the capacitor is C1. The input port VDD of op-amp 1 is connected to the power supply VDD, the GND port is connected to GND, and the inverting input port is connected to the output port V of the reference voltage generation circuit. ref The non-inverting input port is connected to the center voltage divider point of resistors R2 and R3 connected in series. Input port I Nbias9 and I Nbias10 Connect to the output port I of the initial bias current source Nbias9 and I Nbias10 The output port OUT of operational amplifier 1 is connected to the gate of PM6; the source of PM6 is connected to the power supply VDD, and its drain is connected to R2, serving as the output port LVDD of the pre-regulator circuit; the source of PM7 is connected to the power supply VDD, and its gate is connected to PM6. 11 The drains of PM8 are connected together, and the drain is connected to the output port LVDD; the source of PM8 is connected to the input port I. Pbias2 Connected, gate and PM 10 The drain of PM9 is connected to R4, and the drain is connected to the center voltage divider point of R4 and R5 connected in series. The source of PM9 is connected to R5, and the gate is connected to the center voltage divider point of R2 and R3 connected in series. The drain is connected to NM. 16 The drain and gate are connected; PM 10 The source and input port I Pbias2 Connected, gate and input port V ref Connected, drain and NM 17 The drains are connected; PM 11 The source is connected to the power supply VDD, and the gate is connected to PM. 10 The drain is connected to the input port I. Nbias11 Connected; NM 16 The source is connected to GND, and the gate and drain are shorted; NM 17 The source of PM6 is connected to GND; resistors R2 and R3 are connected in series, with the other end of R2 being the output port LVDD and the other end of R3 being connected to GND; C1 is connected between the gate and drain of PM6.

5. A pre-stabilized bandgap reference source with high and low temperature curvature compensation according to claim 1, characterized in that, The positive temperature coefficient current generating circuit includes one operational amplifier, nine PMOS transistors, two PNP bipolar transistors, and one resistor; the operational amplifier is denoted as op-amp 2, and the nine PMOS transistors are denoted as PM 1, P2, P3, P4, P5, P6, P7, P8, P9, P1, P2 ...2, P3, P4, P5, P6, P1, P 12 -PM 20 The two PNP transistors are PNP1 and PNP2, and the resistor is R6. The input port LVDD of op-amp 2 is connected to the power supply LVDD, the GND port is connected to GND, the inverting input port is connected to the emitter of PNP2, the non-inverting input port is connected to the upper end of R6, and the input port I... Nbias2 and I Nbias3 Connect to the output port I of the initial bias current source Nbias2 and I Nbias3 The output port OUT of op-amp 2 is connected to PM 13 PM 15 PM 17 and PM 19 The gates are connected; PM 12 The source is connected to LVDD, and the gate and drain are shorted to the input port I. Nbias1 Connected, and with PM 14 PM 16 PM 18 and PM 20 The gates are connected; PM 13 The source is connected to LVDD, and the drain is connected to PM. 14 The source and the pole are connected; PM 14 The drain of PM is connected to the upper end of R6; 15 The source is connected to LVDD, and the drain is connected to PM. 16 The source and the pole are connected; PM 16 The drain of PM is connected to the emitter of the PNP2; 17 The source is connected to LVDD, and the drain is connected to PM. 18 The source and the pole are connected; PM 18 The drain is the output port I PTAT1 PM 19 The source is connected to LVDD, and the drain is connected to PM. 20 The source of PM; 20 The drain is the output port I PTAT2 The base and collector of PNP1 are shorted and then connected to GND; the base and collector of PNP2 are shorted and then connected to GND; R6 is connected to PM. 14 Between the drain of PNP1 and the emitter of PNP1.

6. A pre-stabilized bandgap reference source with high and low temperature curvature compensation according to claim 1, characterized in that, The negative temperature coefficient current generating circuit includes one operational amplifier, seven PMOS transistors, one NMOS transistor, one PNP transistor, and one resistor; let the operational amplifier be designated as op-amp 3, and the seven PMOS transistors be designated as PM3. 21 -PM 27 One NMOS transistor is an NM 18 One PNP transistor is a PNP3, and one resistor is R7. The input port LVDD of op-amp 3 is connected to LVDD, the GND port is connected to GND, and the inverting input port is connected to NM. 18 The source of the PNP3 is connected to the emitter of the PNP3, and the input port I is connected to the emitter of the PNP3. Nbias5 and I Nbias6 Output port I of the initial bias current source Nbias5 and I Nbias6 Connect the output port OUT to NM 18 The gates are connected; PM 21 The source is connected to LVDD, and the gate and drain are shorted to the input port I. Nbias4 Connected, and respectively with PM 23 PM 25 and PM 27 The gates are connected; PM 22 The source is connected to LVDD, and the gate is connected to PM respectively. 24 and PM 26 The gate is connected to the drain and the PM. 23 The source and the pole are connected; PM 23 The drain of the PNP3 is connected to the emitter of the PNP3; PM 24 The source is connected to LVDD, and the drain is connected to PM. 25 The source of PM; 25 Drain connection to PM 24 gate and NM 18 Drain; PM 26 The source is connected to LVDD, and the drain is connected to PM. 27 The source of PM; 27 The drain is the output port I CTAT NM 18 The source of the PNP3 is connected to the upper end of R7; the base and collector of the PNP3 are shorted and connected to GND, and the emitter is connected to the non-inverting input port of the operational amplifier 3; R7 is connected across NM 18 Between the source and GND.

7. A pre-stabilized bandgap reference source with high and low temperature curvature compensation according to claim 1, characterized in that, The high and low temperature curvature compensation circuit includes 2 PMOS transistors, 7 NMOS transistors, 1 resistor, and 1 NPN transistor; the 2 PMOS transistors are denoted as PM10, PM20, PM30, PM40, PM50, PM60, PM70, PM1 ... 28 and PM 29 The seven NMOS transistors are NM 19 -NM 25 One resistor is R8, and one NPN transistor is NPN1; PM 28 The source is connected to LVDD, and the gate is connected to NM. 22 The drain of R8 and the lower end of R8 form the output port I. HC PM 29 The source is connected to LVDD, and the gate is connected to the emitter of NPN1 and NM. 24 The drain is the output port I. LC NM 19 After the drain and gate are shorted, they are connected to the input port I. Pbias1 Connected, and respectively connected to NM 20 NM 22 and NM 24 The gates are connected; NM 20 The drain and input port I PTAT2 and NM 21 The gate is connected to the source and the source is connected to the NM. 21 The drains are connected; NM 21 The source is connected to GND, and the gate is connected to NM. 20 While the drain is connected, it is respectively connected to NM 23 and NM 25 The gates are connected; NM 22 The source and NM 23 The drains are connected; NM 23 The source is connected to GND; NM 24 The source terminal of NM 25 Drain; NM 25 The source is connected to GND; R8 is connected across PM. 28 Between the source and gate; the collector and base of NPN1 are shorted and then connected to LVDD, and the emitter is connected to PM. 29 The gate.

8. A pre-stabilized bandgap reference source with high and low temperature curvature compensation according to claim 1, characterized in that, The reference voltage generation circuit includes one operational amplifier and two resistors. The operational amplifier is designated as op-amp 4, and the two resistors are R9 and R10. The LVDD input port of op-amp 4 is connected to LVDD, the GND port is connected to GND, the inverting input port is shorted to the output port, and serves as the output port Vref to output a reference voltage. Input ports INbias7 and INbias8 are connected to the output ports INbias7 and INbias8 of the initial bias current source, respectively. The upper end of R9 is connected to input ports IPTAT1 and ICTAT, respectively. The center voltage divider point of the series connection of R9 and R10 is connected to input ports ILC and IHC, respectively. The lower end of R10 is connected to GND.

9. A pre-stabilized bandgap reference source with high and low temperature curvature compensation according to claim 1, characterized in that, The operational amplifiers used in each module include 13 PMOS transistors and 5 NMOS transistors; let the 13 PMOS transistors be designated PM13, PM23, PM33, PM43, PM53, PM63, PM73, PM8 ... 30 -PM 42 The five NMOS transistors are NM 26 -NM 30 PM 30 The source is connected to the power supply VCC, and the gate and drain are shorted and then connected to the input port I. NbiasA And respectively with PM 32 PM 34 PM 36 PM 40 and PM 42 The gates are connected; PM 31 The source is connected to VCC, and the drain is connected to PM. 32 The source and gate are respectively connected to PM 33 PM 35 PM 39 and PM 41 The gates are connected; PM 32 The drain is connected to the input port I. NbiasB PM 33 The source is connected to VCC, and the drain is connected to PM. 34 The source of PM; 34 The drain is connected to NM 26 Gate and drain; PM 35 The source is connected to VCC, and the drain is connected to PM. 36 The source of PM; 36 Drain connection to PM 37 and PM 38 The source of PM; 37 The gate is connected to the non-inverting input port INP, and the drain is connected to NM. 28 Drain; PM 38 The gate is connected to the inverting input port INN, and the drain is connected to NM. 30 Drain; PM 39 The source is connected to VCC, and the drain is connected to PM. 40 The source of PM; 40 The drain is connected to NM 27 The drain and NM 28 The gate of PM; 41 The source is connected to VCC, and the drain is connected to PM. 42 The source of PM; 42 The drain and NM 29 The drains are connected together and form the output port OUT of the operational amplifier; NM 26 The gate and drain are shorted and then connected to NM. 27 and NM 29 The gate and source are connected to GND; NM 27 The drain is connected to NM 28 The gate and source are connected to NM 28 Drain; NM 28 The gate and NM 30 The gate is connected to the source, and the source is connected to GND; NM 29 The source terminal of NM 30 Drain; NM 30 The source is connected to GND.

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