A voltage regulation method, device and storage medium

Abstract

This application provides a voltage regulation method, device, and storage medium. The method includes: acquiring frequency data of each core of a multi-core central processing unit (CPU) within a preset time window; determining the global weighted variance and multi-core synergy index of the CPU based on the frequency data of each core; evaluating the frequency stability of the CPU based on the global weighted variance and the multi-core synergy index to obtain an evaluation result; and adjusting the voltage of the CPU in response to the evaluation result indicating that the CPU frequency is stable. This application achieves safe and effective dynamic voltage regulation by adjusting the voltage only when the frequency is stable, avoiding calculation errors, operational abnormalities, or hardware damage caused by voltage adjustment in an unstable state.

Description

Technical Field

[0001] This application relates to the field of data processing, and more particularly to a voltage regulation method, apparatus, and storage medium. Background Technology

[0002] Reducing the voltage appropriately while ensuring the multi-core CPU meets performance requirements can significantly reduce power consumption and improve energy efficiency. However, if the multi-core CPU is in an unstable state (such as sudden load or core frequency fluctuations), abruptly reducing the voltage can easily lead to calculation errors, operational abnormalities, or hardware damage. Therefore, knowing how to safely and effectively regulate voltage is crucial. Summary of the Invention

[0003] This application provides a voltage regulation method, device, and storage medium to at least solve the above-mentioned technical problems existing in the prior art.

[0004] A first aspect of this application provides a voltage regulation method, the method comprising:

[0005] Obtain frequency data of each core of a multi-core CPU within a preset time window; Based on the frequency data of each core, determine the global weighted variance and multi-core synergy index of the multi-core central processing unit; The frequency stability of the multi-core central processing unit is evaluated based on the global weighted variance and the multi-core synergy index, and the evaluation result is obtained. In response to the evaluation result indicating that the frequency of the multi-core CPU is stable, the voltage of the multi-core CPU is adjusted.

[0006] In one possible implementation, determining the global weighted variance and multi-core synergy index of the multi-core CPU based on the frequency data of each core includes: Based on the frequency data for each core, determine the exponentially smoothed weighted variance for each core; The global weighted variance of the multi-core CPU is determined based on the exponentially smoothed weighted variance of all cores. Based on the frequency data of all cores, the multi-core synergy index of the multi-core central processing unit is determined.

[0007] In one possible implementation, determining the exponentially smoothed weighted variance of each core based on the frequency data of each core includes: Based on a preset smoothing coefficient, time decay weights are assigned to different time points of each core within the preset time window; wherein, the value of the time decay weight decreases exponentially from the nearest to the furthest time point. Based on the time decay weights at each time point and the frequency data of each core, the exponentially smoothed weighted variance of each core is determined.

[0008] In one possible implementation, the frequency data includes the frequency corresponding to each time point within the preset time window; determining the exponentially smoothed weighted variance of each core based on the time decay weight of each time point and the frequency data of each core includes: Based on the frequency of each core at each time point and the corresponding time decay weight, determine the frequency-weighted average of each core; Based on the time decay weights at each time point, the core exponentially smoothed weighted variance is obtained by taking the weighted average of the squared differences between the frequency and the frequency-weighted mean at each time point.

[0009] In one possible implementation, determining the multi-core synergy index of the multi-core CPU based on the frequency data of all cores includes: Determine the direction of frequency change for each core at the current time point relative to the previous time point; Determine the direction of change of the main frequency based on the direction of frequency change of all cores; Calculate the number of cores whose frequency change direction is consistent with the main frequency change direction; The multi-core synergy index is determined based on the number of cores and the total number of cores.

[0010] In one possible implementation, the evaluation result is used to characterize whether the frequency of the multi-core CPU is stable; the evaluation of the frequency stability of the multi-core CPU based on the global weighted variance and the multi-core synergy index to obtain the evaluation result includes: The global weighted variance is compared with a preset first threshold. The multi-core synergy index is compared with a preset second threshold. In response to the global weighted variance being lower than the first threshold and the multi-core synergy index being lower than the second threshold, an evaluation result of the frequency stability of the multi-core central processing unit is obtained; In response to the global weighted variance being higher than the first threshold and / or the multi-core synergy index being higher than the second threshold, an evaluation result of the frequency instability of the multi-core central processing unit is obtained.

[0011] In one possible implementation, adjusting the voltage of the multi-core CPU in response to the evaluation result indicating that the multi-core CPU frequency is stable includes: In response to the evaluation result that the frequency of the multi-core central processing unit is stable, a target frequency is determined based on the current frequency of each core; Based on the target frequency and voltage frequency relationship table, determine the minimum voltage required to maintain stable operation at the target frequency; Determine the minimum voltage offset based on the minimum voltage and the current voltage; The voltage of the multi-core central processing unit is adjusted according to the minimum voltage offset.

[0012] In one possible implementation, the method further includes: In response to the evaluation result that the frequency of the multi-core CPU is unstable, the voltage of the multi-core CPU is adjusted to a safe voltage.

[0013] A second aspect of this application provides a voltage regulating device, the device comprising: The acquisition module is used to acquire frequency data of each core of a multi-core central processing unit within a preset time window; The determination module is used to determine the global weighted variance and multi-core synergy index of the multi-core central processing unit based on the frequency data of each core. The evaluation module is used to evaluate the frequency stability of the multi-core central processing unit based on the global weighted variance and the multi-core synergy index, and obtain the evaluation result. An adjustment module is used to adjust the voltage of the multi-core CPU in response to the evaluation result indicating that the frequency of the multi-core CPU is stable.

[0014] This application provides an electronic device, comprising: At least one processor; and A memory communicatively connected to the at least one processor; wherein, The memory stores instructions that can be executed by the at least one processor to enable the at least one processor to perform the method described in this application.

[0015] According to a fourth aspect of this application, a non-transitory computer-readable storage medium is provided storing computer instructions for causing the computer to perform the methods described in this application.

[0016] This application discloses a voltage regulation method, device, and storage medium that acquires frequency data of each core of a multi-core CPU within a preset time window; determines the global weighted variance and multi-core synergy index of the multi-core CPU based on the frequency data of each core; evaluates the frequency stability of the multi-core CPU based on the global weighted variance and the multi-core synergy index, obtaining an evaluation result; and adjusts the voltage of the multi-core CPU in response to the evaluation result indicating that the frequency of the multi-core CPU is stable. This application achieves safe and effective dynamic voltage regulation by adjusting the voltage only when the frequency is stable, avoiding calculation errors, operational abnormalities, or hardware damage caused by voltage adjustment in an unstable state.

[0017] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of this application, nor is it intended to limit the scope of this application. Other features of this application will become readily apparent from the following description. Attached Figure Description

[0018] The above and other objects, features, and advantages of exemplary embodiments of this application will become readily apparent upon reading the following detailed description with reference to the accompanying drawings. Several embodiments of this application are illustrated in the drawings by way of example and not limitation, in which: In the accompanying drawings, the same or corresponding reference numerals indicate the same or corresponding parts.

[0019] Figure 1 A schematic diagram illustrating the implementation flow of the voltage regulation method provided in an embodiment of this application is shown; Figure 2 This paper illustrates a schematic diagram of the implementation process of the exponential smoothing weighted variance calculation operation of the voltage regulation method provided in the embodiments of this application; Figure 3 A schematic diagram illustrating the implementation flow of the multi-core cooperative index calculation operation of the voltage regulation method provided in this application embodiment is shown; Figure 4 A schematic diagram illustrating the implementation flow of the evaluation operation of the voltage regulation method provided in the embodiments of this application is shown; Figure 5 A schematic diagram illustrating the implementation flow of a specific application example of the voltage regulation method provided in this application embodiment is shown. Figure 6 A comparison diagram showing the application effects of the voltage regulation method of this application embodiment and related technical solutions is provided. Figure 7 A schematic diagram of the composition structure of the voltage regulation system provided in an embodiment of this application is shown; Figure 8 A schematic diagram of the composition structure of the voltage regulation device provided in the embodiments of this application is shown; Figure 9 A schematic diagram of the composition structure of an electronic device according to an embodiment of this application is shown. Detailed Implementation

[0020] To make the objectives, features, and advantages of this application more apparent and understandable, the technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0021] Figure 1 A schematic diagram illustrating the implementation flow of the voltage regulation method provided in the embodiments of this application is shown.

[0022] refer to Figure 1 This application provides a voltage regulation method applicable to the hardware and software systems of various electronic devices, such as an intelligent dynamic voltage regulation system (iDVSS), for monitoring and evaluating the frequency stability of multi-core central processing units. These electronic devices include, but are not limited to, servers, personal computers, laptops, smartphones, tablets, and embedded devices. The method includes: Operation 101: Obtain the frequency data of each core of the multi-core CPU within a preset time window.

[0023] Here, "multi-core CPU" refers to a CPU chip containing two or more independent processing cores. Frequency data refers to the frequency value of each core at discrete sampling points, measured in Hz. The preset time window represents a configurable continuous time period; its length determines the amount of historical data used for a single analysis and can be configured according to the actual application scenario's requirements for real-time performance and historical dependency, for example, it can be set to tens of milliseconds to several seconds.

[0024] In one embodiment of this application, frequency data for each core is obtained by accessing specific registers within the multi-core CPU. Specifically, the multi-core CPU typically has an independent performance monitoring register or model-specific register (MSR) for each core, used to store or reflect the core's real-time operating multiplier. These registers are read using privileged instructions to obtain the current multiplier value for each core. This multiplier value is then multiplied by the CPU's external clock frequency (i.e., the base frequency, typically a fixed value of 100MHz) to calculate the frequency value for each core. In this way, frequency data for each core can be continuously collected at multiple time points, providing a basis for subsequent stability evaluation.

[0025] Operation 102 determines the global weighted variance and multi-core synergy index of the multi-core CPU based on the frequency data of each core.

[0026] In one embodiment of this application, determining the global weighted variance and multi-core synergy index of a multi-core CPU based on the frequency data of each core includes: determining the exponentially smoothed weighted variance of each core based on the frequency data of each core; determining the global weighted variance of the multi-core CPU based on the exponentially smoothed weighted variance of all cores; and determining the multi-core synergy index of the multi-core CPU based on the frequency data of all cores.

[0027] Specifically, the exponentially smoothed weighted variance characterizes the degree of fluctuation in the frequency decay of each core over time. The larger the value, the more significant the core frequency fluctuation; conversely, the smaller the value, the more stable the frequency. The exponentially smoothed weighted variance can be obtained by weighting the frequency values ​​of the cores at each time point within a preset time window.

[0028] However, exponentially smoothed weighted variance reflects the frequency fluctuation of a single core. To understand the overall frequency fluctuation level of a multi-core CPU, a comprehensive analysis based on the exponentially smoothed weighted variance of all cores is needed to obtain an index that characterizes the overall frequency fluctuation of the multi-core CPU, namely, the global weighted variance. The global weighted variance can be generated by integrating the exponentially smoothed weighted variances of all cores. For example, this can be achieved by performing comprehensive statistical analysis on the exponentially smoothed weighted variances of all cores (such as weighted averaging, summation, etc.).

[0029] Furthermore, to evaluate the correlation of frequency changes among the cores of a multi-core CPU under varying loads, this application also introduces a multi-core coordination index. This index can be obtained by analyzing the coordination relationship of frequency changes across all cores. The multi-core coordination index can be a quantifiable value; a higher value indicates more synchronized behavior and better coordination among the cores. For example, the index can be obtained by statistically analyzing the proportion of cores exhibiting consistent frequency change directions at adjacent time points.

[0030] Operation 103 evaluates the frequency stability of the multi-core CPU based on the global weighted variance and the multi-core synergy index, and obtains the evaluation results.

[0031] To make a comprehensive judgment on the frequency stability of multi-core CPUs, the global weighted variance, which reflects the overall fluctuation level, can be combined with the multi-core synergy index, which reflects the synergy of behavior, to obtain the frequency stability assessment results of multi-core CPUs.

[0032] In one embodiment of this application, the global weighted variance and multi-core synergy index can be input into a preset decision model to output an evaluation result characterizing the stability of the multi-core CPU frequency. The decision model can be constructed based on rule-based logic, statistical classification, or machine learning algorithms.

[0033] Operation 104, in response to the evaluation result that the multi-core CPU frequency is stable, adjusts the voltage of the multi-core CPU.

[0034] If the evaluation results show that the multi-core CPU frequency is stable, dynamic voltage adjustment can be performed based on the data obtained from this evaluation to further optimize the energy efficiency of the multi-core CPU.

[0035] Thus, this embodiment of the application collects multi-core timing frequency data and calculates the global weighted variance and multi-core synergy index respectively, comprehensively evaluating the frequency stability of multi-core central processing units from two dimensions: overall fluctuation and multi-core behavioral synergy. This achieves accurate, comprehensive, and real-time evaluation. It avoids the problems of related technologies that rely on single-core average frequency or static thresholds, resulting in a single evaluation dimension and insensitivity to sudden loads and multi-core synergy changes. This provides a more reliable and timely stability judgment basis for power management strategies such as Dynamic Voltage Frequency Scaling (DVFS). By adjusting the voltage only when the evaluation results indicate frequency stability, safe and effective dynamic voltage regulation is achieved, avoiding the risks of operational anomalies, calculation errors, or hardware damage caused by rashly adjusting the voltage in a frequency unstable state.

[0036] Figure 2 This diagram illustrates the implementation flow of the exponential smoothing weighted variance calculation operation of the voltage regulation method provided in this application embodiment.

[0037] refer to Figure 2 In one embodiment of this application, the above-described operation 102, which determines the exponentially smoothed weighted variance of each core based on the frequency data of each core, includes: Operation 201 assigns time decay weights to different time points of each core within a preset time window based on a preset smoothing coefficient; the value of the time decay weight decreases exponentially from the nearest to the furthest time point.

[0038] Specifically, to give higher analytical weight to recent frequency fluctuations than distant fluctuations in stability assessments, thereby more sensitively reflecting the latest state changes of the system, this application embodiment also sets a time decay weight. The value of the time decay weight decreases exponentially from the most recent to the furthest point in time. "From most recent to furthest" means looking back from the current assessment moment to historical time points; exponential decay can be understood as the weight value decreasing exponentially as the time point moves further away from the current moment. This setting ensures that recent data has a significantly higher influence in subsequent calculations than distant data.

[0039] Operation 202 determines the exponentially smoothed weighted variance of each core based on the time decay weights at each time point and the frequency data of each core.

[0040] In one embodiment of this application, the frequency data includes the frequency corresponding to each time point within a preset time window; based on the time decay weight of each time point and the frequency data of each core, the exponentially smoothed weighted variance of each core is determined, including: based on the frequency of each core at each time point and the corresponding time decay weight, the frequency-weighted mean of each core is determined; based on the time decay weight of each time point, the squares of the differences between the frequency and the frequency-weighted mean at each time point are weighted and averaged to obtain the exponentially smoothed weighted variance of the core.

[0041] To obtain a quantitative value that effectively characterizes the severity of core frequency fluctuations and incorporates the concept of time decay, an exponentially smoothed weighted variance is calculated by combining time decay weights with frequency data. Specifically, firstly, the frequency value at each time point is multiplied by its corresponding time decay weight, summed, and then divided by the total weights to obtain the frequency-weighted mean. Next, the square of the difference between the frequency at each time point and the frequency-weighted mean is calculated to quantify the deviation of the frequency from the central trend at each moment and to eliminate the effect of positive and negative deviations canceling each other out. Finally, the squares of the differences between the frequency and the frequency-weighted mean at each time point are weighted and averaged to obtain the exponentially smoothed weighted variance.

[0042] In one embodiment of this application, the global weighted variance can be obtained based on a global weighted variance calculation model, which can be specifically represented by the following algorithm:

[0043] in, This represents the global weighted variance. This indicates the total number of cores in a multi-core central processing unit. Indicates the first The core exponentially smoothed weighted variance, This can be expressed as:

[0044] Indicates the time decay weight. T is the preset time window length, t=1 represents the oldest time point, and α represents the smoothing coefficient, which is used to control the weight decay rate. It is usually taken as 0≤α≤1. Indicates the first The core is the point in time. The frequency value, Indicates the first The frequency-weighted average of the cores within a preset time window. Indicates a point in time The corresponding time decay weight.

[0045] Specifically, after collecting frequency data of each core of a multi-core CPU within a preset time window, this data is input into a global weighted variance calculation model, which then outputs the global weighted variance. The global weighted variance calculation model is flexible in its physical implementation. It can be integrated as a software module, firmware program, or hardware logic unit within the electronic device executing the voltage regulation method of this application. Alternatively, the global weighted variance calculation model may not be part of the electronic device executing the method of this application; for example, it can be deployed on an edge computing node, cloud server, or dedicated coprocessor connected to the electronic device, with external computing resources performing the model calculation and returning the result. This application does not limit the specific deployment location or implementation form of the global weighted variance calculation model.

[0046] Figure 3 This paper illustrates a schematic diagram of the implementation process of the multi-core cooperative index calculation operation of the voltage regulation method provided in the embodiments of this application.

[0047] refer to Figure 3 In one embodiment of this application, the above-described operation 104, determining the multi-core synergy index of the multi-core CPU based on the frequency data of all cores, includes: Operation 301: Determine the direction of frequency change for each core at the current time point relative to the previous time point; Operation 302: Determine the main frequency change direction based on the frequency change direction of all cores; Operation 303: Calculate the number of cores whose frequency change direction is consistent with the main frequency change direction; Operation 304: Determine the multi-core synergy index based on the number of cores and the total number of cores.

[0048] Specifically, by comparing the frequency value of each core at the current sampling time point with the frequency value at the immediately preceding sampling time point, it is determined whether the frequency change of each core is increasing, decreasing, or remaining stable, thus obtaining the independent frequency change direction of each core. Then, the individual change directions of all cores are statistically summarized to identify the common trend followed by most cores at the current moment, obtaining the dominant frequency change direction, i.e., the mainstream frequency change direction. Finally, based on the determined mainstream frequency change direction, the individual frequency change directions of all cores are retrospectively checked, and the number of cores consistent with the mainstream frequency change direction is counted. The multi-core synergy index is calculated by the ratio of the number of cores to the total number of cores.

[0049] In one embodiment of this application, the execution process of operations 301-304 described above can be implemented by the following multi-core collaborative index calculation model, which can be represented by the following algorithm:

[0050] in, This represents the multi-core synergy index, with a value range of [0,1]; N represents the total number of CPU cores. This represents the frequency value of core i at time t; Indicates core At the immediately preceding sampling time point The frequency value; This is a symbolic function used to determine the core. The direction of frequency change; δ(x) is an indicator function for the same direction of change, defined as:

[0051] This represents the mainstream frequency change direction determined statistically based on the frequency change directions of all cores at the current sampling time. δ(x) determines whether the frequency change direction of each core aligns with the mainstream frequency change direction; if they do, the function δ(x) outputs 1; otherwise, it outputs 0.

[0052] Specifically, by inputting all core frequency data into the multi-core synergy index calculation model, the multi-core synergy index output by the model can be obtained. The multi-core synergy index calculation model can be deployed on an electronic device executing the method of this application, or on other electronic devices; this application does not impose any specific limitations.

[0053] Figure 4 A schematic diagram illustrating the implementation flow of the evaluation operation of the voltage regulation method provided in the embodiments of this application is shown.

[0054] In one embodiment of this application, the evaluation result is used to characterize whether the frequency of the multi-core central processing unit is stable. Operation 105, based on the global weighted variance and the multi-core synergy index, evaluates the frequency stability of the multi-core central processing unit to obtain the evaluation result, including: Operation 401 compares the global weighted variance with a preset first threshold; Operation 402 compares the multi-core synergy index with a preset second threshold; Operation 403 responds to the global weighted variance being lower than the first threshold and the multi-core synergy index being lower than the second threshold, thus obtaining an evaluation result of the stability of the multi-core central processing unit frequency. Operation 404, in response to the global weighted variance being higher than the first threshold and / or the multi-core synergy index being higher than the second threshold, yields an assessment result of multi-core CPU frequency instability.

[0055] Specifically, after obtaining the global weighted variance and the multi-core synergy index, the global weighted variance is compared with a first threshold to determine whether the overall frequency fluctuation is within the allowable range; simultaneously, the multi-core synergy index is compared with a second threshold to determine whether the synergy of each core's behavior reaches the expected level. If the global weighted variance is lower than the first threshold and the multi-core synergy index is lower than the second threshold, the multi-core CPU frequency is determined to be stable; if at least one of the following conditions is met—the global weighted variance being higher than the first threshold and the multi-core synergy index being higher than the second threshold—the multi-core CPU frequency is determined to be unstable. The first and second thresholds can be determined comprehensively based on the multi-core CPU's specifications, statistical analysis of historical operating data, experimental calibration results, or stability requirements under specific application scenarios.

[0056] In one embodiment of this application, the above operation 104, in response to the evaluation result showing that the multi-core CPU frequency is stable, adjusts the voltage of the multi-core CPU, including: in response to the evaluation result showing that the multi-core CPU frequency is stable, determining a target frequency based on the current frequency of each core; determining the minimum voltage required to maintain stable operation of the target frequency according to a voltage-frequency relationship table; determining a minimum voltage offset based on the minimum voltage and the current voltage; and adjusting the voltage of the multi-core CPU according to the minimum voltage offset.

[0057] Specifically, the target frequency is first selected from the median, average, or expected frequency value determined based on load planning of all core frequencies. Then, the minimum voltage is determined by consulting a voltage-frequency relationship table based on the target frequency. This table, established beforehand through testing or according to multi-core CPU specifications, describes the minimum operating voltage required to maintain stable operation at a specific frequency. Next, the difference between the minimum voltage and the current voltage is calculated to obtain the minimum voltage offset. Finally, voltage adjustment is performed based on the minimum voltage offset; that is, the operating voltage of the multi-core CPU is adjusted downwards by the corresponding amount according to the calculated minimum voltage offset.

[0058] In one embodiment of this application, in response to the evaluation result that the frequency of the multi-core CPU is unstable, the voltage of the multi-core CPU is adjusted to a safe voltage.

[0059] Specifically, if the frequency of a multi-core CPU is unstable, its operating voltage needs to be set to a safe voltage to quickly exit the unstable state. The safe voltage is a pre-set voltage value to ensure the multi-core CPU maintains basic stable operation under various load conditions. It is typically higher than the minimum operating voltage of the multi-core CPU to provide sufficient voltage margin to cope with sudden loads or process fluctuations. This safe voltage can be set based on the recommended voltage specified in the multi-core CPU's datasheet, a long-term stable voltage determined through system-level verification, or a safety boundary value obtained from historical stable operating data.

[0060] In one embodiment of this application, the voltage regulation process can be implemented by introducing a state machine. Specifically, multiple states can be configured, such as a monitoring state, a stability evaluation state, a fine voltage regulation state, a protection voltage regulation state, and an idle state. The state machine is configured to perform state transitions and process control based on the evaluation results and events during the voltage regulation process. The operating logic of the state machine can be set as follows: initially or by default, it is in the monitoring state, in which the system continuously collects frequency data and performs a stability evaluation; if the evaluation result is stable, the state machine transitions from the monitoring state to the fine voltage regulation state, in which fine voltage regulation based on the minimum voltage offset is performed; if the evaluation result is unstable, the state machine transitions from the monitoring state to the protection voltage regulation state, in which the voltage is adjusted to a safe voltage. After the fine voltage regulation state or the protection voltage regulation state is completed, the state machine returns to the monitoring state, thus forming a closed-loop control. Furthermore, if an error occurs during the regulation process (such as triggering a WHEA warning error), the state machine can transition to the idle state, waiting for error handling or system recovery before re-entering the monitoring state.

[0061] Figure 5 The diagram illustrates a specific application example of the voltage regulation method provided in this application.

[0062] To further understand the technical solution of this application, a specific application example is given below.

[0063] refer to Figure 5 The voltage regulation method in this specific application example is also known as a voltage regulation method based on multi-dimensional timing analysis of CPU frequency stability. This specific application example includes: S1, Begin.

[0064] Start performing a frequency stability assessment of the multi-core CPU.

[0065] S2 collects core multiplication data at each moment.

[0066] Record the frequency multiplication data of all cores at each sampling time.

[0067] S3, Has the two-dimensional time-core frequency window been successfully constructed?

[0068] The two-dimensional time-core frequency window refers to the harmonic data within a preset time window, which includes harmonic values ​​at multiple consecutive sampling time points. S3 aims to determine whether the acquisition of each core harmonic data within the preset time window has been completed. If so, S4 is executed; otherwise, S3 is returned to continue the acquisition.

[0069] S4, update the core data at time T, and delete the core data at time T-(N-1).

[0070] To maintain a fixed-length sliding time window, i.e. a preset time window, while incorporating the latest core frequency multiplication data (time T), historical data from the earliest time (time T-(N-1)) is removed, thereby achieving rolling updates of the data.

[0071] S5 iterates through the multiplication data of each core at time T.

[0072] The frequency multiplication data of each core within the preset duration window at the current moment are traversed one by one.

[0073] S6 calculates the weighted average per core.

[0074] Based on the product of the multiplication factor of each core and the external frequency, the frequency data of each core is calculated, and based on the frequency data of each core and the corresponding time decay weight, the weighted mean (i.e., frequency-weighted mean) of each core is calculated.

[0075] S7, the number of cores changing at time T-1.

[0076] By comparing the frequency values ​​of each core at adjacent time points (time T and time T-1), cores whose frequencies change can be identified.

[0077] S8, Calculate the weighted variance per core.

[0078] Based on the weighted mean of each core, calculate the weighted variance of the frequency sequence of each core to quantify the fluctuations of a single core.

[0079] S9, Calculate the synergy index C.

[0080] Based on the change core statistics result of S7, calculate the synergy quantification value C of the frequency change behavior of all cores.

[0081] S10, Calculate the global weighted variance σ².

[0082] Aggregate (such as averaging) the weighted variances of all cores to obtain the global index σ² representing the overall fluctuation level.

[0083] S11, Does it satisfy the thresholds σ² < A and synergy C < B?

[0084] Compare the calculated global weighted variance σ² with the preset threshold A (the first threshold), and compare the synergy index C with the preset threshold B (the second threshold) to determine whether the frequency is stable. If it is judged unstable, execute S12, otherwise execute S13.

[0085] S12, Retreat to the safe voltage margin.

[0086] If S11 judges that the frequency is unstable, then execute the protective operation to adjust the working voltage of the multi-core central processing unit to a pre-determined safe voltage that can ensure stable operation.

[0087] S13, Calculate the minimum voltage offset at the current stable frequency.

[0088] If S11 judges that the frequency is stable, then in this stable state, further calculate the difference between the minimum working voltage required to maintain the current performance and the current voltage, and adjust the voltage of the multi-core central processing unit based on this difference.

[0089] S14, End.

[0090] End the evaluation and adjustment process.

[0091] Thus, this specific application example, by constructing data analysis windows along the time and core dimensions and combining multi-dimensional analysis methods such as exponentially smoothed weighted variance and synergy index, achieves high-precision, real-time evaluation of the frequency stability of multi-core CPUs. At the data level, it simultaneously collects frequency sequences from multiple time points and multiple cores, overcoming the limitations of a single average frequency. At the algorithm level, exponentially smoothed weighted variance strengthens the weight of recent fluctuations, making the evaluation more sensitive, while the synergy index effectively identifies global load mutations. At the implementation level, through direct hardware register control and algorithm optimization, it achieves millisecond-level detection response and extremely low computational overhead. This improves evaluation accuracy while ensuring the real-time performance and practicality of the method. Furthermore, voltage reduction is only performed when the frequency is stable, achieving safe and effective voltage regulation and avoiding the risks of operational anomalies, calculation errors, or hardware damage caused by rashly adjusting voltage in an unstable frequency state.

[0092] To visually verify the technical advantages of the method in this application, the embodiments of this application compare the voltage regulation method with related technical solutions in terms of actual effects. The specific comparison results are as follows: Figure 6 As shown, Figure 6 A comparison diagram showing the application effects of the voltage regulation method according to the embodiments of this application and related technical solutions is provided. (Reference) Figure 6 It can be seen that, under the same average frame rate, when applying the voltage regulation method of this application embodiment, the power consumption (unit: watts W) is significantly lower than that under the traditional default voltage setting or static regulation method. This verifies that the method of this application has excellent energy efficiency optimization effect while ensuring stable performance.

[0093] Figure 7 A schematic diagram of the composition structure of the voltage regulation system provided in the embodiment of this application is shown.

[0094] refer to Figure 7 Based on the aforementioned voltage regulation method, this application also provides a voltage regulation system for executing the voltage regulation method of this application. This system is also known as an Intelligent Dynamic Voltage Regulation System (iDVSS). The architecture of the voltage regulation system is divided into a kernel layer and a user layer. The kernel layer mainly includes the MSR register, which is used to directly interact with the CPU hardware. By accessing registers at specific addresses (such as 0x198 for frequency and 0x150 for voltage), all core frequencies at the current time T can be read. The user layer mainly includes a CPU monitoring module, a voltage regulation decision analysis module, and an execution state machine.

[0095] The CPU monitoring module is used to monitor the frequency data collected by the kernel layer and initiate a two-dimensional time-core frequency window analysis process to stabilize the CPU.

[0096] The voltage regulation decision analysis module incorporates stability assessment algorithms, including Algorithm 1 and Algorithm 2. Algorithm 1 calculates the exponentially smoothed weighted variance and the global weighted variance; Algorithm 2 calculates the multi-core synergy index. This module executes these algorithms to assess the stability of the multi-core CPU.

[0097] The execution state machine controls the system workflow based on the stability judgment results of the voltage regulation decision analysis module. If the system is determined to be stable, it drives the system into a fine voltage regulation process: reading all core frequencies at time T, querying the frequency-offset voltage table, confirming the minimum offset voltage at time T, and implementing fine voltage regulation through the Apply control path. If the system is determined to be unstable, it drives the system into a protection process: the control state transitions to idle (safe state), and may trigger a WHEA warning (Windows Hardware Error Architecture Warning) error handling path to implement protective operations.

[0098] It should be noted that the description of the system in this application embodiment is similar to that of the method embodiment described above, and has similar beneficial effects as the method embodiment; therefore, it will not be repeated. For any technical details not covered in the voltage regulation system provided in this application embodiment, please refer to... Figures 1 to 6 The meaning is understood in accordance with the description of any of the accompanying drawings.

[0099] Figure 8 A schematic diagram of the composition structure of the voltage regulation device provided in the embodiments of this application is shown.

[0100] refer to Figure 8 This application also provides a voltage regulation device, which may, but is not limited to, be integrated into the aforementioned voltage regulation system as a functional module combination for implementing the core voltage regulation function of the system. The device includes: The acquisition module 501 is used to acquire frequency data of each core of a multi-core central processing unit within a preset time window; The determination module 502 is used to determine the global weighted variance and multi-core synergy index of the multi-core CPU based on the frequency data of each core. Evaluation module 503 is used to evaluate the frequency stability of a multi-core CPU based on global weighted variance and multi-core synergy index, and obtain evaluation results. The adjustment module 504 is used to adjust the voltage of the multi-core CPU in response to the evaluation result that the multi-core CPU frequency is stable.

[0101] According to embodiments of this application, this application also provides an electronic device and a readable storage medium.

[0102] Figure 9 A schematic block diagram of an example electronic device 600 that can be used to implement embodiments of this application is shown. The electronic device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device may also represent various forms of mobile devices, such as personal digital processors, cellular phones, smartphones, wearable devices, and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely illustrative and are not intended to limit the implementation of the application described and / or claimed herein.

[0103] like Figure 9 As shown, the electronic device 600 includes a computing unit 601, which can perform various appropriate actions and processes based on a computer program stored in a read-only memory (ROM) 602 or a computer program loaded from a storage unit 608 into a random access memory (RAM) 603. The RAM 603 may also store various programs and data required for the operation of the electronic device 600. The computing unit 601, ROM 602, and RAM 603 are interconnected via a bus 604. An input / output (I / O) interface 605 is also connected to the bus 604.

[0104] Multiple components in electronic device 600 are connected to I / O interface 605, including: input unit 606, such as keyboard, mouse, etc.; output unit 607, such as various types of displays, speakers, etc.; storage unit 608, such as disk, optical disk, etc.; and communication unit 609, such as network card, modem, wireless transceiver, etc. Communication unit 609 allows electronic device 600 to exchange information / data with other devices through computer networks such as the Internet and / or various telecommunications networks.

[0105] The computing unit 601 can be a variety of general-purpose and / or special-purpose processing components with processing and computing capabilities. Some examples of the computing unit 601 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various special-purpose artificial intelligence (AI) computing chips, various computing units running machine learning model algorithms, a digital signal processor (DSP), and any suitable processor, controller, microcontroller, etc. The computing unit 601 performs the various methods and processes described above, such as voltage regulation methods. For example, in some embodiments, the voltage regulation method may be implemented as a computer software program tangibly contained in a machine-readable medium, such as storage unit 608. In some embodiments, part or all of the computer program may be loaded and / or installed on the electronic device 600 via ROM 602 and / or communication unit 609. When the computer program is loaded into RAM 603 and executed by the computing unit 601, one or more steps of the voltage regulation method described above may be performed. Alternatively, in other embodiments, the computing unit 601 may be configured to perform voltage regulation methods by any other suitable means (e.g., by means of firmware).

[0106] Various embodiments of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), application-specific standard products (ASSPs), system-on-a-chip (SoCs), complex programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various embodiments may include implementations in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which may be a dedicated or general-purpose programmable processor, capable of receiving data and instructions from a storage system, at least one input device, and at least one output device, and transferring data and instructions to the storage system, the at least one input device, and the at least one output device.

[0107] The program code used to implement the methods of this application may be written in any combination of one or more programming languages. This program code may be provided to a processor or controller of a general-purpose computer, special-purpose computer, or other programmable data processing device, such that when executed by the processor or controller, the functions / operations specified in the flowcharts and / or block diagrams are implemented. The program code may be executed entirely on a machine, partially on a machine, as a standalone software package partially on a machine and partially on a remote machine, or entirely on a remote machine or server.

[0108] In the context of this application, a machine-readable medium can be a tangible medium that may contain or store a program for use by or in conjunction with an instruction execution system, apparatus, or device. A machine-readable medium can be a machine-readable signal medium or a machine-readable storage medium. Machine-readable media can be, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination of the foregoing. More specific examples of machine-readable storage media include electrical connections based on one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fibers, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination of the foregoing.

[0109] To provide interaction with a user, the systems and techniques described herein can be implemented on a computer having: a display device for displaying information to the user (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor); and a keyboard and pointing device (e.g., a mouse or trackball) through which the user provides input to the computer. Other types of devices can also be used to provide interaction with the user; for example, feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including sound input, voice input, or tactile input).

[0110] The systems and technologies described herein can be implemented in computing systems that include backend components (e.g., as a data server), or computing systems that include middleware components (e.g., an application server), or computing systems that include frontend components (e.g., a user computer with a graphical user interface or web browser through which a user can interact with implementations of the systems and technologies described herein), or any combination of such backend, middleware, or frontend components. The components of the system can be interconnected via digital data communication of any form or medium (e.g., a communication network). Examples of communication networks include local area networks (LANs), wide area networks (WANs), and the Internet.

[0111] Computer systems can include clients and servers. Clients and servers are generally located far apart and typically interact via communication networks. Client-server relationships are created by computer programs running on the respective computers and having a client-server relationship with each other. Servers can be cloud servers, servers in distributed systems, or servers incorporating blockchain technology.

[0112] It should be understood that the various forms of processes shown above can be used to rearrange, add, or delete steps. For example, the steps described in this application can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution disclosed in this application can be achieved, and this is not limited herein.

[0113] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this application, "a plurality of" means two or more, unless otherwise explicitly specified.

[0114] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A voltage regulation method, characterized in that, The method includes: Obtain frequency data of each core of a multi-core CPU within a preset time window; Based on the frequency data of each core, determine the global weighted variance and multi-core synergy index of the multi-core central processing unit; The frequency stability of the multi-core central processing unit is evaluated based on the global weighted variance and the multi-core synergy index, and the evaluation result is obtained. In response to the evaluation result indicating that the frequency of the multi-core CPU is stable, the voltage of the multi-core CPU is adjusted.

2. The voltage regulation method according to claim 1, characterized in that, The step of determining the global weighted variance and multi-core synergy index of the multi-core central processing unit based on the frequency data of each core includes: Based on the frequency data for each core, determine the exponentially smoothed weighted variance for each core; The global weighted variance of the multi-core CPU is determined based on the exponentially smoothed weighted variance of all cores. Based on the frequency data of all cores, the multi-core synergy index of the multi-core central processing unit is determined.

3. The voltage regulation method according to claim 2, characterized in that, The determination of the exponentially smoothed weighted variance of each core based on its frequency data includes: Based on a preset smoothing coefficient, time decay weights are assigned to different time points of each core within the preset time window; wherein, the value of the time decay weight decreases exponentially from the nearest to the furthest time point. Based on the time decay weights at each time point and the frequency data of each core, the exponentially smoothed weighted variance of each core is determined.

4. The voltage regulation method according to claim 3, characterized in that, The frequency data includes the frequency corresponding to each time point within the preset time window; the determination of the exponentially smoothed weighted variance of each core based on the time decay weight of each time point and the frequency data of each core includes: Based on the frequency of each core at each time point and the corresponding time decay weight, determine the frequency-weighted average of each core; Based on the time decay weights at each time point, the core exponentially smoothed weighted variance is obtained by taking the weighted average of the squared differences between the frequency and the frequency-weighted mean at each time point.

5. The voltage regulation method according to claim 2, characterized in that, The step of determining the multi-core synergy index of the multi-core central processing unit based on the frequency data of all cores includes: Determine the direction of frequency change for each core at the current time point relative to the previous time point; Determine the direction of change of the main frequency based on the direction of frequency change of all cores; Calculate the number of cores whose frequency change direction is consistent with the main frequency change direction; The multi-core synergy index is determined based on the number of cores and the total number of cores.

6. The voltage regulation method according to claim 1, characterized in that, The evaluation results are used to characterize whether the frequency of the multi-core CPU is stable; the evaluation of the frequency stability of the multi-core CPU based on the global weighted variance and the multi-core synergy index, to obtain the evaluation results, includes: The global weighted variance is compared with a preset first threshold. The multi-core synergy index is compared with a preset second threshold. In response to the global weighted variance being lower than the first threshold and the multi-core synergy index being lower than the second threshold, an evaluation result of the frequency stability of the multi-core central processing unit is obtained; In response to the global weighted variance being higher than the first threshold and / or the multi-core synergy index being higher than the second threshold, an evaluation result of the frequency instability of the multi-core central processing unit is obtained.

7. The voltage regulation method according to claim 1, characterized in that, In response to the evaluation result indicating that the multi-core CPU frequency is stable, the voltage of the multi-core CPU is adjusted, including: In response to the evaluation result that the frequency of the multi-core central processing unit is stable, a target frequency is determined based on the current frequency of each core; Based on the target frequency and voltage frequency relationship table, determine the minimum voltage required to maintain stable operation at the target frequency; Determine the minimum voltage offset based on the minimum voltage and the current voltage; The voltage of the multi-core central processing unit is adjusted according to the minimum voltage offset.

8. The voltage regulation method according to claim 1, characterized in that, The method further includes: In response to the evaluation result that the frequency of the multi-core CPU is unstable, the voltage of the multi-core CPU is adjusted to a safe voltage.

9. An electronic device, characterized in that, include: At least one processor; as well as A memory communicatively connected to the at least one processor; wherein, The memory stores instructions that can be executed by the at least one processor to enable the at least one processor to perform the method of any one of claims 1-8.

10. A non-transitory computer-readable storage medium storing computer instructions, characterized in that, The computer instructions are used to cause the computer to perform the method according to any one of claims 1-8.

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