A hardware energy-saving control device

Abstract

This invention discloses a hardware energy-saving management device, belonging to the field of hardware energy-saving control technology. The device includes core energy-saving hardware and supporting collaborative hardware. The core energy-saving hardware consists of a bidirectional leakage current latch-up circuit, a targeted power-off control circuit, a low-power standby circuit, and a wake-up and reset circuit. The supporting hardware is adaptable to single-directory or parallel multi-directory storage architectures. Through hardware-level precise power-off, leakage current latch-up, on-demand wake-up, redundancy-free addressing, and multi-level security verification, it achieves closed-loop energy management throughout the entire process. This invention eliminates reliance on traditional software energy-saving solutions and is adaptable to various scenarios such as smart homes, embedded large-scale terminal devices, and smart mobile devices. It significantly reduces device operating and standby power consumption while forming a complete and protectable hardware architecture, possessing outstanding energy-saving effects and industrial application value.

Description

Technical Field

[0001] This invention relates to the field of hardware energy-saving control technology, specifically to a pure hardware energy-saving management and control device with energy saving as its core objective, which can be adapted to single-directory or parallel multi-directory storage architectures. Background Technology

[0002] Energy-saving solutions for existing electronic devices, embedded large-scale terminal devices, and smart mobile devices generally rely on software scheduling, which has three major drawbacks: First, the energy-saving effect is greatly affected by the software's operating status, and it is impossible to achieve precise power-off and leakage current blocking at the hardware level. The energy loss caused by standby leakage current and redundant hardware running under no-load cannot be completely eliminated, and the standby power consumption of the equipment remains high. Second, regardless of whether it is a single-directory or multi-directory storage architecture, there is a problem of redundant addressing process. In the single-directory scenario, the entire storage array is continuously powered on without load, while in the multi-directory scenario, the power is ineffective for directories that are not called, resulting in a lot of unnecessary energy consumption. At the same time, the addressing process relies on software traversal scanning, and the hardware runs for a long time, which increases the energy consumption. Third, output security verification is mostly done through interactive software, which adds extra hardware load and energy consumption. Furthermore, software energy-saving solutions cannot provide stable patent protection for hardware combinations, and hardware innovations cannot be effectively recognized.

[0003] To address the aforementioned shortcomings, there is currently no complete, purely hardware-based management solution centered on energy conservation that can simultaneously achieve closed-loop energy management at the hardware level throughout the entire process, adapt to storage architectures across all scenarios, and form a complete and protectable hardware combination. Summary of the Invention

[0004] Technical problems to be solved This invention overcomes the shortcomings of existing software energy-saving solutions and provides a hardware energy-saving management device. Through core energy-saving hardware, it achieves precise power-off, leakage current locking, low-power standby, and on-demand wake-up. It is equipped with hardware addressing circuits adaptable to single-directory / parallel multi-directory scenarios, multi-level hardware security verification circuits, and full-process anomaly protection circuits, forming a complete hardware collaborative system. All hardware modules are designed around energy-saving goals, starting on demand and shutting down immediately after use, with no redundant operation and no idle loss. It can achieve complete closed-loop energy saving in single-directory scenarios and seamlessly expand and adapt in parallel multi-directory scenarios. Simultaneously, the entire hardware assembly forms a fixed, patentable architecture, solving the problems of poor energy-saving effects, reliance on software, weak adaptability, and inability to form effective hardware protection in existing technologies. Technical solution

[0005] To achieve the above objectives, the present invention provides the following technical solution: a hardware energy-saving control device, comprising 25 sets of hardware circuits, divided into core energy-saving hardware circuits and supporting energy-saving collaborative hardware circuits. All circuits are fixedly connected to the power supply link through signal links and work collaboratively around the energy-saving goal.

[0006] The core energy-saving hardware circuits include: a bidirectional leakage current latch-up circuit, a targeted power-off control circuit, a low-power standby circuit, and a wake-up and reset circuit. The supporting energy-saving and collaborative hardware circuits include: hardware synchronization timing circuit, link cleaning and sleep control circuit, physical isolation processing circuit adaptable to single / multi-domain, anomaly detection and status latching circuit, highest priority power supply latching circuit, independent hardware watchdog circuit, register power-on latching circuit, anomaly counting and glitch filtering circuit, hardware boundary firewall circuit, voice or text command acquisition circuit, hardware storage array adaptable to single directory or parallel multi-directory, hardware bus physical isolation switch adaptable to single / multi-channel, hardware multimodal instruction parsing circuit, hardware access control authentication unit adaptable to single / multi-track, hardware access control latch, hardware global atomic addressing jump unit, two-level hardware isolation archive storage array, hardware national cryptographic SM4 encryption engine, large model external hardware interface unit, hardware result collection and compliance review circuit, and hardware anomaly forced hard reset circuit.

[0007] The specific connection relationships and functions of each hardware circuit are as follows: 1. Leakage current bidirectional locking circuit: The core energy-saving hardware is connected to the targeted power-off control circuit and the low-power standby circuit respectively. It is used to bidirectionally lock the static leakage current of the entire circuit of the device, blocking the hidden leakage current loss after power failure and in standby mode, and eliminating static ineffective energy consumption from the root.

[0008] 2. Targeted power-off control circuit: The core energy-saving hardware is connected to the power supply terminals of the hardware synchronization timing circuit, the low-power standby circuit, and all supporting hardware circuits. It is used to perform point-to-point precise power-off on idle and non-essential hardware modules in the device, keeping only the hardware necessary for the current process powered on, thus avoiding energy waste caused by powering on all modules.

[0009] 3. Low-power standby circuit: The core energy-saving hardware is connected to the wake-up reset circuit, the targeted power-off control circuit, and the leakage current bidirectional latch-up circuit. It is used to provide a micro-current to the core control unit when the device is not executing any tasks, maintain the device in a minimum standby state, and significantly reduce standby power consumption.

[0010] 4. Wake-up and Reset Circuit: The core energy-saving hardware is connected to the low-power standby circuit, the voice or text command acquisition circuit, and the hardware synchronization timing circuit. After receiving the trigger signal, it wakes up only the hardware modules necessary for the current process without powering on the entire device, thus achieving on-demand wake-up and energy-saving startup.

[0011] 5. Hardware Synchronization Timing Circuit: Equipped with energy-saving collaborative hardware, it connects to the signals of all hardware circuits to coordinate the working timing of all hardware circuits, control each module to start up in sequence according to the process, and immediately cut off power after the task is completed, avoiding ineffective energy consumption caused by premature power-on and delayed power-off of hardware.

[0012] 6. Link Cleanup and Sleep Control Circuit: Equipped with energy-saving collaborative hardware, it is connected to the targeted power-off control circuit and all functional hardware circuits. It is used to clean up idle signal links and drive the hardware modules to enter a deep sleep state after the task is completed, further reducing the device's idle power consumption.

[0013] 7. Adaptable to single / multi-domain physical isolation processing circuit: Equipped with energy-saving collaborative hardware, connected to low-power standby circuit and hardware bus physical isolation switch adaptable to single / multi-channel. In single-directory scenarios, it is used to divide the device into working domain and standby domain. In parallel multi-directory scenarios, it is used to divide the device into independent physical working domains corresponding to each directory, physically isolating the power supply and signal links of each domain to prevent cross-domain invalid power supply and energy leakage.

[0014] 8. Anomaly detection and status latching circuit: Equipped with energy-saving collaborative hardware, it is connected to the power supply terminal and targeted power-off control circuit of all hardware circuits. It is used to monitor the operating status of all hardware circuits in real time. When hardware is found to be unloaded, redundantly running, abnormally powered, or addressing abnormally, the power supply of the corresponding hardware is immediately latched to reduce abnormal energy consumption.

[0015] 9. Highest priority power supply interruption circuit: Equipped with energy-saving collaborative hardware, it is connected to the power supply links of the targeted power-off control circuit and all hardware circuits. It is used to lock the highest execution authority of energy-saving control commands, prioritize the execution of power-off and power-locking operations, prevent the execution of unnecessary power supply commands, and firmly control the power supply control of the device.

[0016] 10. Independent hardware watchdog circuit: It is equipped with energy-saving collaborative hardware and is connected to the hardware synchronization timing circuit and wake-up reset circuit. It is used to independently monitor the operating status of the device, avoid continuous energy waste caused by device jamming and hardware idle operation, and quickly trigger reset and power-off operations in case of abnormality.

[0017] 11. Register power-on lockout circuit: It is equipped with energy-saving collaborative hardware and is connected to the register terminals of all hardware circuits. It is used to immediately fix the energy-saving operation parameters, addressing parameters, and permission parameters after the device is powered on, so as to prevent the hardware from running at full load and idling due to abnormal parameters and stabilize the energy-saving effect of the device.

[0018] 12. Anomaly Counting and Glitching Filtering Circuit: Equipped with energy-saving collaborative hardware, it is connected to all signal input links and hardware synchronization timing circuits to count the number of hardware anomalies, while filtering out glitches and invalid interference signals in signal transmission, avoiding frequent hardware start-ups and shutdowns and additional power consumption caused by false triggering, false jumps, and false addressing.

[0019] 13. Hardware Boundary Firewall Circuit: Equipped with energy-saving collaborative hardware, it connects to the voice or text command acquisition circuit, the hardware multimodal command parsing circuit, the large-model external hardware interface unit, and the hardware result collection and compliance review circuit. This enables three-level hardware security verification, proactively intercepting invalid commands, malicious data, and redundant content, avoiding hardware load and additional energy consumption caused by invalid data processing. The first level is pre-input verification, intercepting invalid and malicious commands; the second level is address content filtering verification, eliminating redundant and illegal data; the third level is silent hardware verification of output results, with compliance verification performed seamlessly in the background, without additional interaction or interruption of the output process. Normal content is allowed to pass directly, and only abnormal content triggers interception, with no additional power consumption throughout the process.

[0020] 14. Voice or text command acquisition circuit: It is equipped with energy-saving collaborative hardware and connected to the wake-up reset circuit and hardware boundary firewall circuit. It is used to acquire external voice and text trigger commands. When there is no task, it is in a low-current, low-power sleep state and is only woken up when a valid command is detected, thereby reducing the standby power consumption of the acquisition module.

[0021] 15. Hardware storage array adaptable to single directory or parallel multi-directory architecture: Equipped with energy-saving collaborative hardware, connected to a hardware bus physical isolation switch and a hardware global atomic addressing jump unit adaptable to single / multi-channel architecture, it can seamlessly adapt to single directory architecture, or two or more physically independent, non-nested, parallel multi-directory architectures, with dual directories being the preferred embodiment; each storage unit corresponds to an independent power supply link and bus channel, and power supply to the corresponding storage area is activated as needed, without the need for the entire array to be powered on simultaneously, reducing the energy consumption of the storage module.

[0022] 16. Hardware bus physical isolation switch adaptable to single / multi-channel: With matching energy-saving collaborative hardware, it connects with hardware storage arrays that can adapt to single directories or parallel multi-directory arrays and physical isolation processing circuits that can adapt to single / multi-domain arrays. In single-directory scenarios, it is used to isolate bus links of idle storage partitions. In parallel multi-directory scenarios, an independent switch is set for each directory to physically isolate bus links of unused directories. Unused storage areas are completely powered off through the corresponding switch to eliminate bus power loss under no-load conditions.

[0023] 17. Hardware Multimodal Instruction Parsing Circuit: Equipped with energy-saving collaborative hardware, connected to the hardware boundary firewall circuit and the hardware global atomic addressing jump unit, it is used to perform hardware-level parsing of voice and text instructions, extract target content features, and only start power supply after the instruction passes the first-level firewall verification. After the parsing is completed, it immediately shuts down and goes into sleep mode to reduce the ineffective power consumption of the parsing module.

[0024] 18. Hardware permission authentication unit adaptable to single / multi-track systems: It is equipped with energy-saving collaborative hardware and connects to hardware permission latches and hardware boundary firewall circuits. In single-directory scenarios, it is used to implement single-path hardware-level permission verification. In parallel multi-directory scenarios, it is used to implement hardware-level permission verification of multiple independent paths corresponding to each directory. It can quickly complete the verification and immediately cut off the power, without the need for continuous power supply, thus reducing the energy consumption of the permission verification process.

[0025] 19. Hardware permission latch: Equipped with energy-saving collaborative hardware, it connects with single / multi-track hardware permission authentication units and register power-on latching circuits to solidify permission parameters in the hardware-level storage area. This eliminates the need to repeatedly power on the verification circuit, reducing energy consumption caused by repeated verification.

[0026] 20. Hardware Global Atomic Addressing Jump Unit: Equipped with energy-saving collaborative hardware, it connects to the hardware multimodal instruction parsing circuit and the hardware storage array that can adapt to single directories or parallel multi-directory scenarios. In single-directory scenarios, it is used to perform normal addressing and intelligent addressing within the same directory. In parallel multi-directory scenarios, it additionally supports cross-directory hardware-level atomic jumps, eliminating redundant traversal scanning processes, significantly shortening the runtime of addressing hardware, and reducing energy consumption in the addressing process.

[0027] 21. Two-level hardware isolated archiving storage array: Equipped with energy-saving collaborative hardware, connected to hardware result collection and compliance review circuits and hardware national cryptographic SM4 encryption engine, it is used for automatic archiving and storage of interactive data, instruction content, addressing process, jump record, and output results. When there is no archiving task, it is in a power-off hibernation state and can automatically create archive folders without manual intervention, and operates with low power consumption throughout.

[0028] 22. Hardware-based SM4 encryption engine: Equipped with energy-saving collaborative hardware, connected to a two-level hardware-isolated archiving storage array, it provides hardware-level encryption and tamper-proof protection for archived data. It only starts powering on during archiving and immediately shuts down and goes into hibernation after encryption is complete, avoiding continuous power consumption.

[0029] 23. Large Model External Hardware Interface Unit: Equipped with energy-saving collaborative hardware, connected to the hardware boundary firewall circuit and the hardware result collection and compliance verification circuit, used for hardware connection and data transmission with the external large model. Power is only activated after the data passes through the secondary firewall verification, and power is immediately cut off after the data transmission is completed to cut off the interface's idle power consumption.

[0030] 24. Hardware result collection and compliance verification circuit: Equipped with energy-saving collaborative hardware, it connects to the external hardware interface unit of the large model, the hardware boundary firewall circuit, and the two-level hardware isolation archive storage array. It is used for unified collection and compliance verification of interactive results. After quickly completing the verification, it immediately shuts down and goes into hibernation, with no redundant operating energy consumption.

[0031] 25. Hardware Anomaly Forced Hard Reset Circuit: Equipped with energy-saving collaborative hardware, connected to the anomaly detection and status latching circuit, the highest priority power supply interruption circuit, and the low-power standby circuit, it is used to forcibly cut off the power supply to all non-core hardware when the device experiences serious anomalies, unauthorized operations, or addressing deadlocks, allowing the device to quickly return to a low-power standby state and avoid energy waste caused by continuous operation due to faults. Beneficial effects

[0032] Compared with the prior art, the present invention has the following advantages: 1. Ultimate hardware-level energy saving effect: Through the synergy of four core energy-saving hardware components, precise targeted power-off, bidirectional leakage current lockout, low-current low-power standby, and on-demand wake-up are achieved. This eliminates energy loss caused by hidden leakage, redundant no-load, and ineffective power supply from the root. Compared with traditional software energy-saving solutions, the device's standby power consumption can be reduced by more than 85%, and the overall operating power consumption can be reduced by more than 60%, resulting in outstanding energy-saving effect.

[0033] 2. Strong adaptability to all scenarios: The entire device can seamlessly adapt to single-directory, dual-directory and any number of parallel multi-directory storage architectures. The dual-directory is only a preferred embodiment and does not limit the scope of protection. It can be widely used in various scenarios such as smart home control terminals, embedded large model hardware, smart mobile devices, and industrial control terminals, with a wide range of industrial applications.

[0034] 3. Completely free from software dependence, stable and reliable operation: All energy-saving control, addressing, and security verification functions are implemented through pure hardware circuits, unaffected by software running status or system freezes. At the same time, anomaly detection, watchdog timer, and forced hard reset circuits provide full-process anomaly protection, making the operation stability far higher than software energy-saving solutions.

[0035] 4. Complete and Protectable Hardware Architecture: The entire device consists of 25 sets of hardware circuits forming a fixed collaborative architecture. The core innovation points are clearly defined, and the claims and specification are completely consistent, forming a complete patent protection barrier that can effectively protect hardware innovation achievements.

[0036] 5. Energy saving and security synergistic optimization: Full-process security verification is achieved through a three-level hardware firewall, especially silent verification at the output end, which achieves security protection without increasing additional energy consumption. At the same time, by intercepting invalid commands and redundant data in advance, invalid hardware operation is avoided, further enhancing the energy saving effect and achieving a two-way improvement in security and energy saving. Detailed Implementation

[0037] The technical solution of the present invention will be clearly and completely described below with reference to the embodiments of the present invention. The described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0038] Example 1: Single-Catalog Basic Scenario Example (Smart Home Control Terminal) This embodiment is a basic single-directory application scenario, applied to a smart home central control terminal. All 25 hardware circuits of the device are integrated into the terminal main control board, and the storage architecture adopts a single-directory hardware storage array to store smart home device control commands and scene configuration data.

[0039] When there is no control task, the device only operates with low power standby circuit. The leakage current bidirectional lockout circuit synchronously locks the static leakage current of the entire board. The targeted power-off control circuit cuts off all power supply to the storage array, communication interface, and peripheral modules. The register power-on lockout circuit has pre-fixed energy-saving parameters, addressing parameters, and permission parameters. The device is in the lowest power standby state, and the terminal standby power consumption is reduced to less than 12% of the industry's conventional solution.

[0040] When the voice or text command acquisition circuit detects the user's voice control command, the wake-up reset circuit only wakes up the acquisition circuit and the core control unit, without starting the other hardware; the abnormal counting and glitch filtering circuit simultaneously filters signal glitch and interference to avoid false wake-up and energy consumption; after the command acquisition is completed, the acquisition circuit immediately returns to a low-power sleep state.

[0041] The collected instructions are transmitted to the hardware boundary firewall circuit to complete the first hardware-level security check, intercepting invalid instructions, malicious instructions and redundant content in advance; invalid instructions are directly intercepted, and the firewall circuit immediately returns to a low-power state to avoid unnecessary power consumption caused by subsequent meaningless hardware startup.

[0042] The compliant instruction is transmitted to the hardware multimodal instruction parsing circuit. The hardware synchronous timing circuit only powers the parsing module, while other unrelated hardware remains powered off. After the parsing circuit completes instruction parsing and extracts the features of the target control instruction, it immediately powers off and goes into sleep mode.

[0043] The parsed target features are transmitted to the hardware global atomic addressing jump unit. The targeted power-off control circuit only activates the power supply to the target storage partition in the single-directory hardware storage array, while all other idle storage partitions are completely powered off through the physical isolation switch of the single-channel hardware bus. The single-domain physical isolation processing circuit ensures physical isolation between the working domain and the standby domain throughout the process. The addressing unit performs normal addressing within the single directory, accurately matching the target control command. The anomaly detection and status latching circuit monitors addressing anomalies throughout the process to avoid energy consumption from invalid searches.

[0044] If the target content is not found through normal addressing, the addressing unit immediately initiates intelligent addressing within the same directory to perform a full-range supplementary search and matching; if the target content has been found through normal addressing, the intelligent addressing step is skipped directly to minimize the runtime of the addressing hardware; during the addressing process, the highest priority power supply interruption circuit ensures that only the addressing-related hardware is powered on, eliminating unnecessary power supply.

[0045] After a single directory full-range addressing is completed, the retrieved target control commands are summarized, the addressing unit is immediately powered off and put into hibernation, the link cleaning and hibernation control circuits simultaneously clean up all idle storage links, drive unused storage partitions into deep hibernation, and the targeted power-off control circuits cut off unnecessary power to the storage array.

[0046] All the information from the addressing summary is transmitted to the hardware boundary firewall circuit to complete the second hardware-level security check, filtering redundant data, illegal data, and invalid content; invalid data is directly removed and does not enter the subsequent large model processing stage, avoiding the high hardware load and energy consumption caused by invalid computing power.

[0047] Once the verified compliant content is transmitted to the external large model via the external hardware interface unit, corresponding control commands are generated. The targeted power-off control circuit only powers on the interface module, while other unrelated hardware remains powered off and in sleep mode. After data transmission and model calculation are completed, the interface unit is immediately powered off to cut off the interface's idle power consumption.

[0048] The computation results output by the large model flow back to the hardware boundary firewall circuit to complete the third silent hardware-level security check. The entire process is executed in the background without any noticeable impact, without any additional interaction or interruption of the output process. It only triggers interception for illegal or abnormal content, while allowing compliant content to pass directly without generating additional processing power. After the check is completed, the firewall circuit immediately enters a low-power sleep state.

[0049] After the compliance results are collected by the hardware results and finalized by the compliance review circuit, they are sent to the corresponding smart home devices for execution. Once the review is complete, the circuit is immediately powered off and put into sleep mode. Simultaneously, all interactive data, instruction content, addressing process, and calculation results of this entire process are synchronously transmitted to a two-level hardware-isolated archiving storage array. Data with existing archiving directories is directly stored, while data without corresponding archiving directories is automatically stored in a new folder to complete the full archiving. Throughout the archiving process, only the storage array and the hardware national cryptographic SM4 encryption engine are powered. Once the encrypted archiving is completed, all related circuits are immediately powered off and put into sleep mode.

[0050] Throughout the entire process, an independent hardware watchdog circuit monitors the device's operating status in real time. If the system freezes or addressing freezes, it immediately triggers a reset to prevent the hardware from consuming power under no-load conditions. In the event of serious privilege escalation, hardware failure, or abnormal power supply, the hardware abnormality forced hard reset circuit is immediately triggered to forcibly cut off the power supply to all non-core hardware, allowing the device to quickly return to a low-power standby state.

[0051] After the entire process is completed, the targeted power-off control circuit cuts off all power supply to all functional modules, the leakage current bidirectional locking circuit locks the static leakage current of the entire circuit again, and the device returns to the lowest power consumption standby state, completing the closed-loop energy saving of the entire process in the single-directory scenario.

[0052] Example 2: Preferred Implementation of Dual-Directory Parallel Architecture (Embedded Large Model Multi-GPU Module) This embodiment is a preferred example of a parallel multi-directory architecture, applied to an embedded large-model multi-graphics card hardware terminal. All 25 hardware circuits of the device are integrated on the main control board of the terminal. The core energy-saving circuit is directly connected to the power supply link of the multi-graphics card module. The storage architecture adopts two physically independent parallel directories, namely a public business storage array and a user-dedicated storage array.

[0053] When there are no interactive tasks, the device only powers on the low-power standby circuit. The leakage current bidirectional locking circuit locks the leakage current of the entire board, and the targeted power-off control circuit cuts off the power supply to all idle graphics card cores, storage modules, and interface circuits. The terminal standby power consumption is reduced to less than 15% of the industry's conventional solutions.

[0054] Upon receiving a voice command, the device wakes up the corresponding hardware module as needed. Invalid commands are intercepted in advance by the first firewall to prevent the graphics card module from running idle. The process involves normal addressing of the first directory → intelligent addressing → atomic jump to the second directory → normal addressing of the second directory → intelligent addressing. Throughout the process, only the corresponding directory storage and addressing hardware is activated, while the idle graphics card and storage module remain powered off. After addressing is completed, the content is verified by the second firewall and sent to the corresponding graphics card core for large-scale model calculation. After the calculation is completed, the interface and graphics card core are immediately powered off. The output result is output after being silently verified in the background by the third firewall. The entire process involves automatic low-power data archiving and no redundant hardware operation. Compared with traditional software energy-saving solutions, the overall power consumption of the terminal is reduced by more than 65%.

[0055] Example 3: Extended Example of Three-Directory Parallel Architecture (Industry Smart Terminal) This embodiment is an extension scheme of the parallel multi-directory architecture, applied to smart terminals in the industrial / financial sectors. The device's 25 sets of hardware circuits are adapted to three physically independent parallel storage directories, namely a public business directory, a user-specific directory, and an industry compliance directory. Each directory corresponds to an independent physical isolation domain and a bus isolation switch.

[0056] In standby mode, only the core low-power circuit is powered on, the targeted power-off control circuit cuts off the power supply to all three storage directories, and the leakage current bidirectional latching circuit blocks static leakage current. Upon receiving a business instruction, the device follows the core process to complete the current directory addressing → intelligent addressing → atomic jump to the next directory, looping through all three directories to complete the full range of addressing. Throughout the process, only the currently searched directory is powered on, while the other directories are completely powered off. After addressing is completed, the content is verified by a two-level firewall and sent to the industry's large model for processing. The output results are verified by a silent firewall before being output. All business data is automatically encrypted and archived. Compared to the traditional multi-directory synchronous power-on solution, the energy consumption of the storage stage is reduced by more than 70%.

[0057] The above description is merely a preferred embodiment of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A hardware energy-saving control device, characterized in that, It includes a bidirectional leakage current latch-up circuit, a targeted power-off control circuit, a low-power standby circuit, and a wake-up and reset circuit. The targeted power-off control circuit is used to perform precise power-off on idle, non-core hardware modules of the device to reduce ineffective power consumption. The leakage current bidirectional locking circuit is used to bidirectionally lock the static leakage current of the entire circuit of the device, thereby blocking the hidden leakage loss. The low-power standby circuit is used to provide a micro-current to the core unit only when the device is not performing any tasks, so as to maintain a minimum power consumption standby state. The wake-up reset circuit is used to receive command trigger signals and wake up the necessary hardware modules of the device as needed, avoiding full power-on and energy consumption.

2. The hardware energy-saving control device according to claim 1, characterized in that, It also includes hardware synchronization timing circuits, link cleaning and sleep control circuits, physical isolation processing circuits that can adapt to single / multi-domain applications, and anomaly detection and state latching circuits. The hardware synchronization timing circuit is connected to all the circuit signals described in claim 1, and is used to coordinate the running sequence of each hardware component to avoid energy waste caused by premature power-on and delayed power-off of the hardware. The link clearing and hibernation control circuit is connected to the targeted power-off control circuit, which is used to clear idle signal links and drive non-running hardware into deep hibernation. The adaptable single / multi-domain physical isolation processing circuit is connected to the low-power standby circuit to divide the working domain and standby domain in a single-directory scenario, or to divide the independent physical working domain corresponding to each directory in a parallel multi-directory scenario, so as to realize physical isolation power supply and prevent cross-domain invalid energy consumption. The anomaly detection and status latching circuit is connected to the targeted power-off control circuit to monitor the hardware operating status and immediately lock the power supply to the corresponding hardware when redundant no-load is detected.

3. The hardware energy-saving control device according to claim 1, characterized in that, It also includes a highest priority power supply lockout circuit, an independent hardware watchdog circuit, a register power-on lockout circuit, and an anomaly counting and glitch filtering circuit. The highest priority power supply interruption circuit is connected to the targeted power-off control circuit to ensure that the energy-saving power-off command is executed with the highest priority and to eliminate unnecessary power supply. The independent hardware watchdog circuit is connected to the hardware synchronization timing circuit to monitor the operating status of the device and prevent continuous energy consumption caused by system freeze and no load. The register power-on lockout circuit is connected to the register terminals of all hardware circuits and is used to solidify the energy-saving operation parameters and addressing parameters of the device after power-on, preventing abnormal parameters from causing hardware to consume energy under no-load conditions. The abnormal counting and glitch filtering circuit is connected to the hardware synchronization timing circuit to filter out invalid signal interference and avoid frequent hardware start-stop and power consumption caused by false triggering.

4. The hardware energy-saving control device according to claim 1, characterized in that, It also includes hardware boundary firewall circuits and voice or text command acquisition circuits; The hardware boundary firewall circuit is used to implement three levels of hardware security verification, the first level is pre-verification of instruction input, the second level is address content filtering verification, and the third level is silent background verification of output results, which intercepts invalid instructions and redundant data in advance and reduces energy consumption in subsequent processes. The voice or text command acquisition circuit is connected to the wake-up reset circuit and the hardware boundary firewall circuit, respectively. When there is no task, it is in a low-power sleep state and is only woken up when a command is detected, thereby reducing the standby power consumption of the acquisition module.

5. The hardware energy-saving control device according to claim 1, characterized in that, It also includes hardware storage arrays that can adapt to single directories or parallel multi-directory arrays, and hardware bus physical isolation switches that can adapt to single / multi-channel arrays. The hardware storage array that can adapt to a single directory or parallel multiple directories can support a single directory architecture or two or more physically independent, non-nested parallel multiple directory architectures. Dual directories are a preferred embodiment. Power is supplied to the corresponding storage area as needed, without the need for the entire array to be powered on and running at the same time. The adaptable single / multi-channel hardware bus physical isolation switch is used to isolate the bus and power supply of the unused storage area, so as to achieve complete power-off and energy saving of the unused area.

6. The hardware energy-saving control device according to claim 1, characterized in that, It also includes a hardware multimodal instruction parsing circuit, a hardware authorization authentication unit that can be adapted to single / multi-track systems, and a hardware authorization latch; The hardware multimodal instruction parsing circuit is connected to the hardware boundary firewall circuit and the hardware global atomic addressing jump unit, respectively. It is started only after the instruction verification is passed and is powered off immediately after parsing is completed. The adaptable single / multi-track hardware permission authentication unit is connected to the hardware boundary firewall circuit and is used for independent hardware-level permission verification in single directory or parallel multi-directory scenarios without continuous power-on operation. The hardware permission latch is connected to a hardware permission authentication unit that can be adapted to single / multi-track systems and a register power-on latch circuit, respectively, to solidify the permission parameters of the storage area and reduce the energy consumption of repeated verification.

7. The hardware energy-saving control device according to claim 1, characterized in that, It also includes a hardware global atomic addressing jump unit, which is connected to a hardware multimodal instruction parsing circuit and a hardware storage array that can adapt to a single directory or parallel multiple directories. In a single-directory scenario, it is used to perform normal and intelligent addressing of the current directory without redundant traversal scanning; In parallel multi-directory scenarios, it is used to perform normal and intelligent addressing of the current directory. Regardless of whether the current directory is successfully addressed, it performs cross-directory hardware-level atomic jumps to other parallel directories, and completes the addressing of all directories in sequence, shortening the addressing runtime and reducing addressing energy consumption.

8. The hardware energy-saving control device according to claim 1, characterized in that, It also includes a two-level hardware-isolated archive storage array and a hardware-based SM4 encryption engine; The two-level hardware-isolated archiving storage array is connected to the hardware result collection and compliance review circuit, which is used for automatic archiving of interactive data and addressing process. It can automatically create archive folders and go into hibernation when there are no archiving tasks. The hardware-based SM4 encryption engine is connected to a two-level hardware-isolated archive storage array for hardware-level encryption of archived data. Power is cut off immediately after encryption to avoid continuous energy consumption.

9. The hardware energy-saving control device according to claim 1, characterized in that, It also includes external hardware interface units for large models, hardware result collection and compliance review circuits; The external hardware interface unit of the large model is connected to the hardware boundary firewall circuit and the hardware result collection and compliance review circuit, respectively. It is powered on only after the data is compliant and powered off immediately after processing is completed. The hardware result collection and compliance review circuit is connected to the hardware boundary firewall circuit for interactive result collection and compliance verification. After the review is completed, it is powered off and put into sleep mode.

10. The hardware energy-saving control device according to claim 1, characterized in that, It also includes a hardware fault forced hard reset circuit, which is connected to the fault detection and status latch circuit, the highest priority power supply interruption circuit, and the low power standby circuit, respectively. It is used to forcibly cut off the power supply to non-core hardware when the device malfunctions and quickly return to the energy-saving standby state.