Processing chips, power consumption control methods, semiconductor packaging structures and electronic devices

Abstract

This application discloses a processing chip, a power consumption control method, a semiconductor packaging structure, and an electronic device, relating to the field of semiconductor technology. The processing chip is provided with a physical core group, and the multiple physical cores in the physical core group are divided into a first physical core and a second physical core. The first physical core has a first power consumption management circuit, and the second physical core has a second power consumption management circuit. The first power consumption management circuit and the second power consumption management circuit have different strategies when there is a sudden change in instantaneous power consumption, which can improve the power consumption change of the first physical core and the second physical core, compensate for the power consumption change of the first physical core, make the instantaneous power consumption of the physical core group as a whole tend to be stable, improve the voltage drop or overshoot of the chip power supply network, avoid excessive throttling, improve the working stability of the chip, reduce the power supply margin, and reduce the chip power consumption.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to processing chips, power consumption control methods, semiconductor packaging structures, and electronic devices. Background Technology

[0002] With the evolution of semiconductor technology, the power supply voltage of processing chips has further decreased due to the constraint of heat density per unit chip area. Typically, processing chips integrate a large number of physical cores. During operation, transient changes in the load of these physical cores cause sudden changes in their power consumption, resulting in sudden changes in their load current. Because of the distributed inductance in the path supplying the power voltage to the processing chip, when the load current of a physical core changes abruptly, it can cause a voltage drop or overshoot in the chip's power supply network connected to the physical core. This can lead to malfunctions in the physical core, reduce the chip's operational stability, and increase power margin and chip power consumption. Summary of the Invention

[0003] This application provides a processing chip, a power consumption control method, a semiconductor packaging structure, and an electronic device to improve the problem of voltage overshoot or voltage drop in the chip power supply network, improve the chip's operating stability, reduce power supply margin, and reduce chip power consumption.

[0004] In a first aspect, this application provides a processing chip, which includes one or more physical core groups, the physical core groups including multiple physical cores; the multiple physical cores include a first physical core and a second physical core, wherein the first physical core includes a first power management circuit and the second physical core includes a second power management circuit.

[0005] The first power management circuit detects the power consumption of the first physical core in each sampling period. When the first target power consumption increases relative to the second target power consumption, it decreases the operating parameters of the first physical core to reduce or even suppress the rate of increase in the instantaneous power consumption of the first physical core, thereby reducing the degree of increase in the instantaneous power consumption of the first physical core. Conversely, when the first target power consumption decreases relative to the second target power consumption, it increases the operating parameters of the first physical core to compensate for the decrease in the instantaneous power consumption of the first physical core, thereby reducing the degree of decrease in the instantaneous power consumption of the first physical core. The first target power consumption indicates the power consumption detected by the first power management circuit in the current sampling period, and the second target power consumption indicates the power consumption detected by the first power management circuit in the previous sampling period. Thus, the first power management circuit can obtain the first target power consumption and the second target power consumption based on the detected power consumption, and adjust the operating parameters of the first physical core based on the increase and decrease of the first target power consumption relative to the second target power consumption to control the instantaneous power consumption of the first physical core, thereby improving the power consumption fluctuations of the first physical core.

[0006] Furthermore, since the first power management circuit is connected to the second power management circuit, the first power management circuit is also used to output at least a portion of the power consumption detected in each sampling period to the second power management circuit, and the second power management circuit is used to detect the power consumption of the second physical core in each sampling period. Based on this, the second power management circuit not only detects the power consumption of the second physical core in each sampling period, but also receives the power consumption output by the first power management circuit in each sampling period. Based on this, when the third target power consumption increases relative to the fourth target power consumption, the second power management circuit reduces the operating parameters of the second physical core, reducing or even suppressing the rate of increase of the instantaneous power consumption of the second physical core, thereby reducing the degree of increase in the instantaneous power consumption of the second physical core. When the third target power consumption decreases relative to the fourth target power consumption, the operating parameters of the second physical core are increased to compensate for the decrease in the instantaneous power consumption of the second physical core, thereby reducing the degree of decrease in the instantaneous power consumption of the second physical core. Wherein, the third target power consumption is used to indicate the sum of the power consumption detected and received by the second power management circuit in the current sampling period, and the fourth target power consumption is used to indicate the sum of the power consumption detected and received by the second power management circuit in the previous sampling period. Therefore, the second power management circuit can adjust the operating parameters of the second physical core based on the increase and decrease of the third target power consumption relative to the fourth target power consumption, so as to control the instantaneous power consumption of the second physical core. This not only improves the power consumption fluctuation of the second physical core, but also compensates for the power consumption fluctuation of the first physical core.

[0007] In addition, the operating parameters include one or more of the following: operating frequency, number of gated clocks, and number of pipelines, which makes it relatively simple to adjust the power consumption of the physical core, reducing design difficulty and production costs.

[0008] Therefore, in this embodiment, by setting up a physical core group, the multiple physical cores in the physical core group are divided into a first physical core and a second physical core. The first physical core integrates a first power management circuit, and the second physical core integrates a second power management circuit. The first power management circuit and the second power management circuit have different strategies when the instantaneous power consumption of the first physical core and the second physical core change. This not only improves the power consumption change of the second physical core, but also compensates for the power consumption change of the first physical core, so that the instantaneous power consumption and load current of the physical core group as a whole can tend to be stable. This can improve the problem of voltage drop or overshoot in the chip power supply network, thereby avoiding excessive throttling, improving the chip's operating stability, reducing power supply margin, and reducing chip power consumption. Furthermore, since there is only unidirectional communication of power output from the first physical core to the second physical core, and no communication process of power output from the second physical core to the first physical core, the first physical core is equivalent to the master physical core, and the second physical core is equivalent to the slave physical core. This can reduce the impact of communication delay, thereby timely improving the problem of voltage drop or overshoot in the chip power supply network, and further improving the chip's operating stability.

[0009] In one possible implementation of this application, when the first target power consumption is unchanged or changes only slightly relative to the second target power consumption, the first power management circuit controls the operating parameters of the first physical core to remain unchanged.

[0010] In one possible implementation of this application, when the third target power consumption is unchanged or changes only slightly relative to the fourth target power consumption, the second power management circuit controls the operating parameters of the second physical core to remain unchanged.

[0011] In one possible implementation of this application, the process of determining that the first target power consumption is higher than the second target power consumption may include: the difference between the first target power consumption and the second target power consumption is greater than a first power consumption threshold. This makes the determination process relatively simpler to implement.

[0012] In one possible implementation of this application, the process of determining that the first target power consumption is lower than the second target power consumption may include: the difference between the first target power consumption and the second target power consumption is less than a second power consumption threshold. This makes the determination process relatively simpler to implement.

[0013] Wherein, the first target power consumption is the product of the first weight and the power consumption detected by the first power management circuit in the current sampling period, the second target power consumption is the product of the first weight and the power consumption detected by the first power management circuit in the previous sampling period, and the second power consumption threshold is less than the first power consumption threshold.

[0014] In one possible implementation of this application, the process of determining that the first target power consumption is unchanged or changes only slightly relative to the second target power consumption may include: the difference between the first target power consumption and the second target power consumption is greater than or equal to a second power consumption threshold, and less than or equal to a first power consumption threshold. This makes the determination process relatively simpler to implement.

[0015] In one possible embodiment of this application, the first power management circuit includes: a first power estimation circuit, a first power control circuit, and a first weighting circuit. The first power estimation circuit is connected to the first weighting circuit and is used to detect the power consumption of a first physical core in each sampling period and output the detected power consumption to the first weighting circuit. Furthermore, the first weighting circuit is connected to the first power control circuit and is used to receive the power consumption output by the first power estimation circuit, and output a first target power consumption to the first power control circuit in the current sampling period, and output a second target power consumption to the first power control circuit in the previous sampling period. The first power control circuit is used to decrease the operating parameters of the first physical core when the difference between the first target power consumption and the second target power consumption is greater than a first power consumption threshold, and increase the operating parameters of the first physical core when the difference between the first target power consumption and the second target power consumption is less than the second power consumption threshold. In addition, the first power estimation circuit is also connected to a second power management circuit and is used to output at least a portion of the power consumption detected in each sampling period to the second power management circuit. Therefore, the function of the first power management circuit can be realized through the first power estimation circuit, the first power control circuit, and the first weighting circuit, which makes the implementation of the first power management circuit relatively simple, reduces the design difficulty, and reduces the production cost.

[0016] In one possible implementation of this application, the first weight is less than 1 and greater than 0. Therefore, the power consumption detected by the first power management circuit can be compressed using the first weight to improve the power consumption fluctuations of the first physical core. For example, the value of the first weight ranges from 0.5 to 0.9 to avoid the power consumption detected by the first power management circuit being compressed too low, thus affecting the performance of the first physical core.

[0017] In one possible implementation of this application, the process of determining that the third target power consumption is higher than the fourth target power consumption may include: the difference between the third target power consumption and the fourth target power consumption is greater than a third power consumption threshold. This makes the determination process relatively simpler to implement.

[0018] In one possible implementation of this application, the process of determining that the third target power consumption is lower than the fourth target power consumption may include: the difference between the third target power consumption and the fourth target power consumption is less than the fourth power consumption threshold. This makes the determination process relatively simpler to implement.

[0019] In one possible implementation of this application, the process of determining that the third target power consumption is unchanged or changes only slightly relative to the fourth target power consumption may include: the difference between the third target power consumption and the fourth target power consumption is greater than or equal to the fourth power consumption threshold, and less than or equal to the third power consumption threshold. This makes the determination process relatively simpler to implement.

[0020] The third target power consumption is the sum of the first weight power consumption and the second weight power consumption. The first weight power consumption is the product of the second weight and the power consumption detected by the second power management circuit in the current sampling period. The second weight power consumption is the product of the third weight and the power consumption received by the second power management circuit in the current sampling period.

[0021] The fourth target power consumption is the sum of the third weight power consumption and the fourth weight power consumption. The third weight power consumption is the product of the second weight and the power consumption detected by the second power management circuit in the previous sampling period. The fourth weight power consumption is the product of the third weight and the power consumption received by the second power management circuit in the previous sampling period.

[0022] The fourth power consumption threshold is less than the third power consumption threshold.

[0023] In one possible embodiment of this application, the second power management circuit includes: a second power estimation circuit, a second power control circuit, a second weighting circuit, a third weighting circuit, and a power combination circuit. The second power estimation circuit is connected to the second weighting circuit and is used to detect the power consumption of the second physical core in each sampling period and output the detected power consumption to the second weighting circuit. The second weighting circuit is connected to the power combination circuit and is used to receive the power consumption output by the second power estimation circuit, and output a first weighted power consumption to the power combination circuit in the current sampling period, and a third weighted power consumption to the power combination circuit in the previous sampling period. The third weighting circuit is connected to both the first power management circuit and the power combination circuit, and is used to receive the power consumption output by the first power management circuit, and output a second weighted power consumption to the power combination circuit in the current sampling period, and a fourth weighted power consumption to the power combination circuit in the previous sampling period. The power combination circuit is connected to the second power control circuit and is used to receive the first weighted power consumption and the second weighted power consumption in the current sampling period, and output a third target power consumption in the current sampling period; and to receive the third weighted power consumption and the fourth weighted power consumption in the previous sampling period, and output a fourth target power consumption in the previous sampling period. Furthermore, the second power consumption control circuit is used to reduce the operating parameters of the second physical core when the difference between the third and fourth target power consumption is greater than the third power consumption threshold, and to increase the operating parameters of the second physical core when the difference between the third and fourth target power consumption is less than the fourth power consumption threshold. Thus, the function of the second power consumption management circuit can be realized through the second power consumption estimation circuit, the second power consumption control circuit, the second weighting circuit, the third weighting circuit, and the power consumption combination circuit, making the implementation of the second power consumption management circuit relatively simple, reducing design difficulty, and lowering production costs.

[0024] In one possible implementation of this application, the second weight is less than or equal to 1, and the second weight is greater than 0. Therefore, by assigning appropriate weights, the power consumption detected by the second power management circuit can be processed through the second weights to improve the power consumption fluctuations of the second physical core. For example, the value range of the second weight is 0.5 to 1, to avoid the power consumption detected by the second power management circuit being compressed too low, thus affecting the performance of the second physical core.

[0025] In one possible implementation of this application, the third weight is less than or equal to 1 and greater than 0. Therefore, by assigning appropriate weights, the power consumption of the first power management circuit output to the second power management circuit can be processed by the third weight, thereby improving the power consumption fluctuations of the second physical core.

[0026] In one possible implementation of this application, the sum of the third weight and the first weight is 1. Therefore, the first power management circuit can improve the power consumption fluctuations of the first physical core based on a portion of the detected power consumption. Furthermore, the second power management circuit, based on another portion of the power consumption detected by the first power management circuit, combined with its own power consumption, improves the power consumption fluctuations of the second physical core and compensates for the power consumption fluctuations of the first physical core.

[0027] In one possible implementation of this application, the plurality of physical cores includes a first physical core and a second physical core, and in any sampling period, the power consumption received by the second power management circuit is the power consumption detected by the first power management circuit.

[0028] In one possible implementation of this application, the multiple physical cores in any physical core group include multiple first physical cores and a second physical core. In any sampling period, the power consumption received by the second power management circuit is the sum of the power consumption detected by the first power management circuits in the multiple first physical cores.

[0029] In one possible implementation of this application, the multiple physical cores in any physical core group include a first physical core and multiple second physical cores. In any sampling period, the power consumption received by the second power management circuit in any second physical core is a portion of the power consumption detected by the first power management circuit.

[0030] In one possible implementation of this application, the multiple physical cores in any physical core group include multiple first physical cores and multiple second physical cores. In any sampling period, the power consumption received by the second power management circuit in any second physical core is a portion of the accumulated power consumption, and the accumulated power consumption is the sum of the power consumption detected by the first power management circuits in the multiple first physical cores.

[0031] In one possible implementation of this application, multiple physical cores in any group of physical cores operate in alternating first and second time periods. During the first time period, a subset of the physical cores are designated as first physical cores, and another subset as second physical cores. Furthermore, during the second time period, a subset of the physical cores are designated as second physical cores, and another subset as first physical cores. This improves the performance symmetry between the first and second physical cores.

[0032] In one possible implementation of this application, the processing chip further includes a global arbitrator connected to each physical core. In response to the control of the global arbitrator, multiple physical cores in any group of physical cores operate in alternating first and second time periods. This simplifies the implementation of controlling the switching process between the first and second physical cores, reducing design complexity and production costs.

[0033] In one possible implementation of this application, the processing chip further includes a central arbiter connected to each physical core. In response to the control of the central arbiter, multiple physical cores in any group of physical cores operate in alternating first and second time periods. This simplifies the implementation of controlling the switching process between the first and second physical cores, reducing design complexity and production costs.

[0034] Secondly, this application provides a power consumption control method for a processing chip. The processing chip includes one or more physical core groups, and the physical core groups include multiple physical cores. The multiple physical cores include a first physical core and a second physical core. The first physical core includes a first power management circuit, and the second physical core includes a second power management circuit.

[0035] The method includes:

[0036] The first power management circuit detects the power consumption of the first physical core in each sampling period and outputs at least a portion of the power consumption detected in each sampling period to the second power management circuit; the second power management circuit detects the power consumption of the second physical core in each sampling period.

[0037] When the first target power consumption increases relative to the second target power consumption, and the third target power consumption increases relative to the fourth target power consumption, the first power management circuit reduces the operating parameters of the first physical core, and the second power management circuit reduces the operating parameters of the second physical core.

[0038] When the first target power consumption decreases relative to the second target power consumption, and the third target power consumption decreases relative to the fourth target power consumption, the first power management circuit increases the operating parameters of the first physical core, and the second power management circuit increases the operating parameters of the second physical core.

[0039] When the first target power consumption increases relative to the second target power consumption and the third target power consumption decreases relative to the fourth target power consumption, the first power management circuit reduces the operating parameters of the first physical core, and the second power management circuit increases the operating parameters of the second physical core.

[0040] When the first target power consumption decreases relative to the second target power consumption and the third target power consumption increases relative to the fourth target power consumption, the first power management circuit increases the operating parameters of the first physical core, and the second power management circuit decreases the operating parameters of the second physical core.

[0041] The first target power consumption is used to indicate the power consumption detected by the first power management circuit in the current sampling period, the second target power consumption is used to indicate the power consumption detected by the first power management circuit in the previous sampling period, the third target power consumption is used to indicate the sum of the power consumption detected by the second power management circuit in the current sampling period and the power consumption received, and the fourth target power consumption is used to indicate the sum of the power consumption detected by the second power management circuit in the previous sampling period and the power consumption received.

[0042] Therefore, in this embodiment, the first power management circuit and the second power management circuit employ different strategies when the instantaneous power consumption of the first and second physical cores changes abruptly. This not only improves the power consumption fluctuations of the first and second physical cores but also compensates for the power consumption fluctuations of the first physical core, allowing the instantaneous power consumption and load current of the entire physical core group to stabilize. This improves the voltage drop or overshoot problem in the chip's power supply network, thereby avoiding excessive throttling and improving the performance of the processing chip. Furthermore, since there is only unidirectional communication between the first and second physical cores, and no communication between the second and first physical cores, the first physical core acts as the master physical core, and the second physical core acts as the slave physical core. This reduces the impact of communication latency, thereby promptly improving the voltage drop or overshoot problem in the chip's power supply network and further enhancing the performance of the processing chip.

[0043] In one possible implementation of this application, the process of determining that the first target power consumption is higher than the second target power consumption may include: the difference between the first target power consumption and the second target power consumption is greater than a first power consumption threshold. This makes the determination process relatively simpler to implement.

[0044] In one possible implementation of this application, the process of determining that the first target power consumption is lower than the second target power consumption may include: the difference between the first target power consumption and the second target power consumption is less than a second power consumption threshold. This makes the determination process relatively simpler to implement.

[0045] Wherein, the first target power consumption is the product of the first weight and the power consumption detected by the first power management circuit in the current sampling period, the second target power consumption is the product of the first weight and the power consumption detected by the first power management circuit in the previous sampling period, and the second power consumption threshold is less than the first power consumption threshold.

[0046] In one possible implementation of this application, the first weight is less than 1 and the first weight is greater than 0.

[0047] In one possible implementation of this application, the third target power consumption is higher than the fourth target power consumption, and is determined based on the difference between the third target power consumption and the fourth target power consumption being greater than a third power consumption threshold. This simplifies the determination process.

[0048] In one possible implementation of this application, the third target power consumption is lower than the fourth target power consumption, and is determined based on the fact that the difference between the third target power consumption and the fourth target power consumption is less than the fourth power consumption threshold. This simplifies the determination process.

[0049] The third target power consumption is the sum of the first weight power consumption and the second weight power consumption. The first weight power consumption is the product of the second weight and the power consumption detected by the second power management circuit in the current sampling period. The second weight power consumption is the product of the third weight and the power consumption received by the second power management circuit in the current sampling period.

[0050] The fourth target power consumption is the sum of the third weight power consumption and the fourth weight power consumption. The third weight power consumption is the product of the second weight and the power consumption detected by the second power management circuit in the previous sampling period. The fourth weight power consumption is the product of the third weight and the power consumption received by the second power management circuit in the previous sampling period.

[0051] The fourth power consumption threshold is less than the third power consumption threshold.

[0052] In one possible implementation of this application, the second weight is less than or equal to 1, and the second weight is greater than 0.

[0053] In one possible implementation of this application, the third weight is less than or equal to 1, and the third weight is greater than 0.

[0054] Thirdly, this application provides a semiconductor packaging structure including a packaging substrate and a processing chip, wherein the processing chip is packaged on the packaging substrate. The processing chip is as described in the first aspect or the embodiments of the first aspect. Because the processing chip in the embodiments of this application has better performance, the semiconductor packaging structure including the processing chip also has better performance.

[0055] Fourthly, this application provides an electronic device comprising: a circuit board and a semiconductor package structure, wherein the semiconductor package structure is disposed on the circuit board. The semiconductor package structure is as described in the third aspect or the embodiments thereof. Because the semiconductor package structure in the embodiments of this application has better performance, the electronic device incorporating this semiconductor package structure also has better performance.

[0056] Furthermore, the technical effects of the corresponding solutions in the second to fourth aspects can be referred to the technical effects that can be obtained by the corresponding solutions in the first aspect, and the repetitions will not be detailed. Attached Figure Description

[0057] Figure 1 This is a schematic diagram of the structure of an electronic device in an embodiment of this application;

[0058] Figure 2 This is a schematic diagram of the semiconductor packaging structure in the embodiments of this application;

[0059] Figure 3 This is a schematic diagram of the structure of the processing chip in an embodiment of this application;

[0060] Figure 4 This is a schematic diagram of a physical core assembly in an embodiment of this application;

[0061] Figure 5 This is a schematic diagram of the first and second physical cores in a physical core group in an embodiment of this application;

[0062] Figure 6 This is yet another schematic diagram of the first and second physical cores in a physical core group in an embodiment of this application;

[0063] Figure 7 This is a flowchart of the power consumption control method in the embodiments of this application;

[0064] Figure 8 Another schematic diagram of the first and second physical cores in a physical core group in an embodiment of this application;

[0065] Figure 9 Another schematic diagram of the first and second physical cores in a physical core group in an embodiment of this application;

[0066] Figure 10A This is yet another schematic diagram illustrating the time-division conversion of the physical core into the first physical core and the second physical core in the embodiments of this application;

[0067] Figure 10B This is yet another illustration of the time-division conversion of the physical core into the first physical core and the second physical core in the embodiments of this application;

[0068] Figure 11 This is yet another schematic diagram illustrating the time-division conversion of the physical core into the first physical core and the second physical core in the embodiments of this application;

[0069] Figure 12 This is yet another schematic diagram of the first and second physical cores in a physical core group in an embodiment of this application;

[0070] Figure 13 This is yet another schematic diagram of the first and second physical cores in a physical core group in an embodiment of this application;

[0071] Figure 14 This is yet another schematic diagram of the first and second physical cores in a physical core group in an embodiment of this application.

[0072] Figure label:

[0073] 100 - Housing; 200 - Circuit board; 210 - Semiconductor package structure; 211 - Package substrate; 212 - Processing chip; 213 - First conductive connection structure; 214 - In-package decoupling capacitor; 215 - Molding layer; 216 - Second conductive connection structure; 220 - Power supply module; 230 - On-board decoupling capacitor; 300a / 300a_1 / 300a_2 - First physical core; 300b / 300b_1 / 300b_2 - Second physical core; 310_1~310_16 - Physical core; 311a - First power management circuit; 3 111a - First power consumption estimation circuit; 3112a - First power consumption control circuit; 3113a - First weighting circuit; 311b - Second power consumption management circuit; 3111b - Second power consumption estimation circuit; 3112b - Second power consumption control circuit; 3113b - Second weighting circuit; 3114a / 3114b - Third weighting circuit; 3115a / 3115b - Power consumption combination circuit; 320 - Chip power supply network; 410_1~410_8 - Physical core group; 510 - Global arbitrator; 511 - Global counter; 520 - Central arbitrator. Detailed Implementation

[0074] To make the objectives, technical solutions, and advantages of this application clearer, the application will be further described in detail below with reference to the accompanying drawings. The specific operational methods in the method embodiments can also be applied to the device embodiments or system embodiments. It should be noted that in the description of this application, "multiple" can be understood as "at least two". Furthermore, it should be understood that in the description of this application, terms such as "first" and "second" are used only for distinguishing purposes and should not be construed as indicating or implying relative importance, nor as indicating or implying order.

[0075] It should be noted that the same reference numerals in the accompanying drawings of this application denote the same or similar structures, and therefore repeated descriptions of them will be omitted. Terms expressing position and direction described in this application are illustrative based on the accompanying drawings, but may be modified as needed, and all modifications are included within the scope of protection of this application. The accompanying drawings of this application are for illustrating relative positional relationships only and do not represent actual scale.

[0076] To facilitate understanding of the processing chip, power consumption control method, semiconductor packaging structure, and electronic device provided in the embodiments of this application, their application scenarios will be introduced first below.

[0077] The processing chip provided in this application embodiment can be applied to various electronic devices, such as electronic devices with semiconductor packaging structures. Exemplarily, electronic devices include, but are not limited to, terminal devices and communication devices. For example, terminal devices include, but are not limited to, mobile phones, computers, televisions, set-top boxes, watches, personal computers (PCs), wearable devices, workstations, etc. Communication devices include, but are not limited to, wireless network devices, fixed network devices, servers, smart broadband devices, etc. It is understood that the specific implementation of the electronic device can be determined according to the actual application scenario and is not limited herein.

[0078] The processing chip, power consumption control method, semiconductor packaging structure, and electronic device provided in the embodiments of this application are described below with reference to the accompanying drawings.

[0079] Figure 1 This is a schematic diagram of the structure of an electronic device according to an embodiment of this application. (Refer to...) Figure 1 The electronic device includes a circuit board 200, a power supply module 220, and a semiconductor package structure 210, with the power supply module 220 and semiconductor package structure 210 respectively disposed on the circuit board 200. The power supply module 220 and semiconductor package structure 210 are connected, and the power supply module 220 is used to provide power voltage to the processing chip in the semiconductor package structure 210. In addition, the electronic device also includes a housing 100, which has a receiving space, and the circuit board 200 is disposed in the receiving space and fixed on the housing 100.

[0080] For example, the semiconductor package structure 210 and the circuit board 200 can be connected by bonding, soldering or other methods to achieve electrical connection between them, thereby enabling signal transmission between the semiconductor package structure 210 and the circuit board 200.

[0081] For example, the power supply module 220 includes, but is not limited to, a voltage regulator module (VRM). The power supply module 220 and the circuit board 200 can also be connected by bonding, soldering or other methods to achieve an electrical connection between the power supply module 220 and the semiconductor package structure 210 through the circuit board 200, thereby enabling the power supply module 220 to provide power voltage to the processing chip 212 in the semiconductor package structure.

[0082] For example, an on-board decoupling capacitor 230 may also be integrated on the circuit board 200 to stabilize the power supply voltage and reduce signal interference.

[0083] For example, circuit board 200 includes, but is not limited to, a printed circuit board (PCB).

[0084] For example, the semiconductor package structure 210 can be a packaged device. For instance, the semiconductor package structure 210 includes, but is not limited to, logic circuits and system-on-chips (SOCs) that integrate logic and memory circuits, etc., which will not be listed here. For example, refer to... Figure 2 , Figure 2 This is a schematic diagram of the semiconductor packaging structure in an embodiment of this application. The semiconductor packaging structure 210 may include a packaging substrate 211 and a processing chip 212, with the processing chip 212 packaged on the packaging substrate 211. Exemplarily, the processing chip 212 is electrically connected to the packaging substrate 211 via a first conductive connection structure 213 to achieve signal transmission. Furthermore, the semiconductor packaging structure 210 may include a molding compound layer 215 to encapsulate the processing chip 212 on the packaging substrate 211. In addition, the semiconductor packaging structure 210 may also include an in-package decoupling capacitor 214, which is electrically connected to the packaging substrate 211 to stabilize the power supply voltage and reduce signal interference. Furthermore, the semiconductor packaging structure 210 may also include a second conductive connection structure 216 to be electrically connected to the circuit board 200. Exemplarily, the first conductive connection structure 213 and the second conductive connection structure 216 include, but are not limited to, solder balls, bumps, and microbumps.

[0085] For example, the processing chip 212 includes, but is not limited to, a central processing unit (CPU), a graphics processing unit (GPU), an artificial intelligence (AI) processor, a digital signal processor (DSP), and a neural network processor. For instance, the processing chip 212 is a die.

[0086] Figure 3 This is a schematic diagram of the processing chip in one embodiment of this application, with reference to... Figure 3The processing chip 212 may include multiple physical cores 310_1 to 310_16. Each physical core 310_1 to 310_16 is connected to the chip power supply network 320. The chip power supply network 320 is connected to the power supply module 220 through the circuit board 200. The power supply voltage output by the power supply module 220 is transmitted to each physical core 310_1 to 310_16 through the chip power supply network 320 to power each physical core 310_1 to 310_16.

[0087] Exemplarily, the physical core is the core component of the processing chip 212, responsible for executing all computations, receiving / storing commands, and data processing tasks. Exemplarily, the physical core may include structures such as an arithmetic unit, a control unit, registers, and a cache. The arithmetic unit (e.g., an arithmetic and logic unit (ALU)) is responsible for performing arithmetic and logical operations. The control unit is responsible for reading instructions from memory, decoding these instructions to determine the operation to be performed, and also for controlling the data transmission and timing relationships between various components within the physical core. Registers are high-speed storage units within the physical core, used for temporarily storing data and instructions. A cache is a high-speed memory used to store recently used or frequently accessed data and instructions. The above are merely illustrative examples of some internal structures of the physical core in this embodiment. In specific implementations, the structure of the physical core is not limited to the structures described in this embodiment, and may also be other structures known to those skilled in the art.

[0088] In some embodiments of this application, the chip power supply network 320 and the plurality of physical cores 310_1 to 310_16 can be integrated on a semiconductor substrate (e.g., a silicon substrate) using semiconductor processes. It is understood that, in order to clearly illustrate the structure of the processing chip 212 in the embodiments of this application, Figure 3 The following is an example of a processing chip 212 having 16 physical cores. In other embodiments of this application, the processing chip 212 may also have 2, 4, 6, 8 or 12 physical cores. Alternatively, the number of physical cores in the processing chip 212 may be flexibly designed according to the actual application scenario. Furthermore, the grouping method of these physical cores is based on the structure of the physical core group in the embodiments of this application, and will not be elaborated here.

[0089] Because there is distributed inductance in the path providing power to the processing chip 212, and the processing chip 212 integrates a large number of physical cores, sudden power consumption changes in multiple physical cores can cause voltage drops or overshoots on the chip power supply network 320, leading to malfunctions in physical cores 310_1 to 310_16, reducing the operational stability of the chip 212, and increasing power supply margin and chip power consumption. To address this issue, in this embodiment, the processing chip 212 may include multiple physical core groups, each group comprising multiple physical cores. Different physical core groups contain different physical cores, and each physical core group includes a first physical core 300a and a second physical core 300b. The strategies for power consumption changes in the first physical core 300a and the second physical core 300b are different, allowing for a smooth transition in the overall power consumption of the physical core group. This, in turn, allows for a smooth transition in the voltage of the chip power supply network of the processing chip 212, thereby improving the problem of voltage overshoot or drops in the chip power supply network, enhancing the operational stability of the chip 212, reducing power supply margin, and decreasing chip power consumption.

[0090] For example, refer to Figure 4 , Figure 4 This is a schematic diagram of a physical core group in an embodiment of this application. The processing chip 212 may include physical core groups 410_1 to 410_8, and each physical core group 410_1 to 410_8 includes multiple physical cores, and the physical cores in different physical core groups 410_1 to 410_8 are different. For example, physical core group 410_1 contains physical cores 310_1 and 310_2, physical core group 410_2 contains physical cores 310_3 and 310_4, physical core group 410_3 contains physical cores 310_5 and 310_6, physical core group 410_4 contains physical cores 310_7 and 310_8, physical core group 410_5 contains physical cores 310_9 and 310_10, physical core group 410_6 contains physical cores 310_11 and 310_12, physical core group 410_7 contains physical cores 310_13 and 310_14, and physical core group 410_8 contains physical cores 310_15 and 310_16.

[0091] Furthermore, referring to Figure 5 , Figure 5This is a schematic diagram of the first and second physical cores in a physical core group according to an embodiment of this application. Taking physical core group 410_1 as an example, physical core 310_1 is the first physical core 300a, and physical core 310_2 is the second physical core 300b. The first physical core 300a has a first power management circuit 311a. The first power management circuit 311a is used to detect the power consumption of the first physical core 300a in each sampling period. The first power management circuit 311a can obtain a first target power consumption and a second target power consumption based on the detected power consumption. Therefore, based on the increase and decrease of the first target power consumption relative to the second target power consumption, the operating parameters of the first physical core 300a are adjusted to control the instantaneous power consumption of the first physical core 300a, thereby improving the power consumption fluctuation of the first physical core 300a. Exemplarily, the first target power consumption is used to indicate the power consumption detected by the first power management circuit 311a in the current sampling period t, and the second target power consumption is used to indicate the power consumption detected by the first power management circuit 311a in the previous sampling period t-1. Furthermore, when the first target power consumption increases relative to the second target power consumption, the first power management circuit 311a reduces the operating parameters of the first physical core 300a, thereby reducing or even suppressing the rate of increase of the instantaneous power consumption of the first physical core 300a, and thus reducing the degree of increase in the instantaneous power consumption of the first physical core 300a. Conversely, when the first target power consumption decreases relative to the second target power consumption, the operating parameters of the first physical core 300a are increased to compensate for the decrease in the instantaneous power consumption of the first physical core 300a, thereby reducing the degree of decrease in the instantaneous power consumption of the first physical core 300a.

[0092] The second physical core 300b includes a second power management circuit 311b, which detects the power consumption of the second physical core 300b in each sampling period. Furthermore, the second power management circuit 311b is connected to a first power management circuit 311a, which also outputs at least a portion of the power consumption detected in each sampling period to the second power management circuit 311b. Therefore, the second power management circuit 311b not only detects the power consumption of the second physical core 300b in each sampling period but can also receive the power consumption output by the first power management circuit 311a in each sampling period. Based on this, a third target power consumption and a fourth target power consumption can be obtained. The third target power consumption indicates the sum of the power consumption PS1(t) detected and the power consumption PS2(t) received by the second power management circuit 311b in the current sampling period t. The fourth target power consumption indicates the sum of the power consumption PS1(t-1) detected and the power consumption PS2(t-1) received by the second power management circuit 311b in the previous sampling period t-1. Therefore, based on the increase and decrease of the third target power consumption relative to the fourth target power consumption, the operating parameters of the second physical core 300b are adjusted to control the instantaneous power consumption of the second physical core 300b. This not only improves the power consumption fluctuations of the second physical core 300b but also compensates for the power consumption fluctuations of the first physical core 300a. For example, when the third target power consumption increases relative to the fourth target power consumption, the second power management circuit 311b reduces the operating parameters of the second physical core 300b, reducing or even suppressing the rate of increase of the instantaneous power consumption of the second physical core 300b, thereby reducing the degree of increase in the instantaneous power consumption of the second physical core 300b. Conversely, when the power consumption of the third target decreases relative to the power consumption of the fourth target, the second power management circuit 311b is used to increase the operating parameters of the second physical core 300b to compensate for the decrease in the instantaneous power consumption of the second physical core 300b, so as to reduce the degree of decrease in the instantaneous power consumption of the second physical core 300b.

[0093] In other words, when the first target power consumption increases relative to the second target power consumption, and the third target power consumption increases relative to the fourth target power consumption, it indicates that the instantaneous power consumption of the physical core group 410_1 as a whole will increase sharply. This will cause the current of the processing chip 212 to increase sharply, resulting in a voltage drop in the chip power supply network. To address this, the first power management circuit 311a controls the operating parameters of the first physical core 300a to reduce the degree of increase in the instantaneous power consumption of the first physical core 300a, and the second power management circuit 311b controls the operating parameters of the second physical core 300b to reduce the degree of increase in the instantaneous power consumption of the second physical core 300b. This allows the instantaneous power consumption of the physical core group 410_1 as a whole to transition smoothly, thereby improving the problem of voltage drop in the chip power supply network.

[0094] When the first target power consumption decreases relative to the second target power consumption, and the third target power consumption decreases relative to the fourth target power consumption, it indicates that the instantaneous power consumption of the physical core group 410_1 as a whole will drop sharply. This will cause a sharp drop in the current of the processing chip 212, resulting in a voltage overshoot problem in the chip power supply network. To address this, the first power management circuit 311a controls the operating parameters of the first physical core 300a to increase, thereby reducing the degree of decrease in the instantaneous power consumption of the first physical core 300a. The second power management circuit 311b controls the operating parameters of the second physical core 300b to increase, thereby reducing the degree of decrease in the instantaneous power consumption of the second physical core 300b. This allows the instantaneous power consumption of the physical core group 410_1 as a whole to transition smoothly, thus improving the voltage overshoot problem in the chip power supply network.

[0095] When the first target power consumption increases relative to the second target power consumption, and the third target power consumption decreases relative to the fourth target power consumption, it indicates that the instantaneous power consumption of the first physical core 300a will increase, and the instantaneous power consumption of the second physical core 300b will decrease. This may cause voltage overshoot or voltage drop in the chip power supply network. To address this, the first power management circuit 311a controls the operating parameters of the first physical core 300a to decrease the degree of increase in the instantaneous power consumption of the first physical core 300a, and the second power management circuit 311b controls the operating parameters of the second physical core 300b to increase the degree of decrease in the instantaneous power consumption of the second physical core 300b. This allows the instantaneous power consumption of the physical core group 410_1 as a whole to transition smoothly, thereby improving the problem of voltage overshoot or voltage drop in the chip power supply network.

[0096] When the first target power consumption decreases relative to the second target power consumption and the third target power consumption increases relative to the fourth target power consumption, it indicates that the instantaneous power consumption of the first physical core 300a will decrease and the instantaneous power consumption of the second physical core 300b will increase. This may cause voltage overshoot or voltage drop in the chip power supply network. To address this, the first power management circuit 311a controls the operating parameters of the first physical core 300a to increase, thereby reducing the degree of decrease in the instantaneous power consumption of the first physical core 300a. The second power management circuit 311b controls the operating parameters of the second physical core 300b to decrease, thereby reducing the degree of increase in the instantaneous power consumption of the second physical core 300b. This allows the instantaneous power consumption of the physical core group 410_1 as a whole to transition smoothly, thus improving the problem of voltage overshoot or voltage drop in the chip power supply network.

[0097] Furthermore, one method in existing technologies to improve the voltage drop or overshoot problem in the chip power supply network is to allow each physical core to independently adjust its power consumption. However, since the chip power supply network 320 of the physical cores is interconnected, the existing technology of independently managing power consumption fluctuations for each physical core is mainly to prevent the worst-case scenario of simultaneous power consumption fluctuations (power consumption increasing or decreasing simultaneously) across all physical cores. In real-world scenarios, the probability of such a worst-case scenario is small; therefore, this method is an over-design. Another method is for each physical core to communicate with a central arbiter 520, reporting its own transient power consumption. The central arbiter 520 then allocates a permissible power consumption fluctuation limit for each physical core, suppressing the total power consumption fluctuation within an acceptable range. However, this method requires round-trip communication between the physical cores and the central arbiter 520. Since the communication process usually involves a delay, this delay affects the real-time performance of power consumption fluctuation suppression. This necessitates a margin to mask possible transient power consumption changes during the communication delay, increasing performance loss and weakening the suppression effect.

[0098] In view of the above-mentioned prior art, in the embodiments of this application, a physical core group is set up, in which multiple physical cores are divided into a first physical core 300a and a second physical core 300b. The first physical core 300a integrates a first power management circuit 311a, and the second physical core 300b integrates a second power management circuit 311b. The first power management circuit 311a and the second power management circuit 311b have different strategies when the instantaneous power consumption of the first physical core 300a and the second physical core 300b changes, so that not only can the power consumption changes of the first physical core 300a and the second physical core 300b be improved, but also the power consumption changes of the first physical core 300a can be compensated. This makes the instantaneous power consumption and load current of the physical core group as a whole tend to be stable, thereby improving the problem of voltage drop or overshoot in the chip power supply network, thus avoiding excessive throttling, improving the working stability of the chip 212, reducing power supply margin, and reducing chip power consumption. Furthermore, since there is only one-way communication between the first physical core 300a and the second physical core 300b, and no communication between the second physical core 300b and the first physical core 300a, the first physical core 300a is equivalent to the main physical core and the second physical core 300b is equivalent to the slave physical core. This reduces the impact of communication latency, thereby promptly improving the voltage drop or overshoot problem of the chip power supply network, further improving the working stability of the chip 212, reducing power supply margin, and reducing chip power consumption.

[0099] In one embodiment of this application, the operating parameters include one or more of the following: operating frequency, number of gated clocks, and number of pipelines. This makes it relatively simple to adjust the power consumption of the physical core, reducing design difficulty and production costs.

[0100] As an example, the operating parameter can be the operating frequency. Based on this, the power consumption of the physical core can be adjusted by controlling the operating frequency of the physical core. This makes adjusting the power consumption of the physical core relatively simple to implement, reduces design difficulty, and lowers production costs.

[0101] As another example, the operating parameter can also be the number of gated clocks. Based on this, the power consumption of the physical core can be adjusted by controlling the number of gated clocks of the physical core. This makes adjusting the power consumption of the physical core relatively simple to implement, reduces design difficulty, and lowers production costs.

[0102] As another example, the running parameter can also be the number of pipelines. Based on this, the power consumption of physical cores can be adjusted by controlling the number of pipelines of physical cores. This makes adjusting the power consumption of physical cores relatively simple to implement, reduces design difficulty, and lowers production costs.

[0103] As another example, the operating parameters can also be any two or all of the following: operating frequency, number of gated clocks, and number of pipelines. This allows for timely adjustment of the power consumption of the physical cores, timely improvement of voltage drops or overshoots in the chip's power supply network, and further enhancement of the performance of the 212 processing chip.

[0104] For example, in any physical core group, a communication connection is established between the first physical core 300a and the second physical core 300b. This simplifies the one-way communication between the first physical core 300a and the second physical core 300b, reducing design complexity and production costs. In other embodiments of this application, a communication connection can be established between any two physical cores.

[0105] It is understood that the power consumption of the first physical core 300a detected by the first power management circuit 311a in each sampling period can be the instantaneous power consumption of the first physical core 300a, and the power consumption of the second physical core 300b detected by the second power management circuit 311b in each sampling period can be the instantaneous power consumption of the second physical core 300b. Furthermore, to clearly illustrate the relationship between the first physical core 300a and the second physical core 300b in the embodiments of this application, Figure 5 The following is an illustration using physical cores 310_1 and 310_2 in physical core group 410_1 as examples. The implementation methods of the other physical core groups 410_2 to 410_8 are the same as those of physical core group 410_1, and will not be described in detail here.

[0106] It is worth mentioning that when the first target power consumption remains unchanged or changes only slightly compared to the second target power consumption, the first power management circuit 311a controls the operating parameters of the first physical core 300a to remain unchanged. Similarly, when the third target power consumption remains unchanged or changes only slightly compared to the fourth target power consumption, the second power management circuit 311b controls the operating parameters of the second physical core 300b to remain unchanged. This reduces the overall instantaneous power consumption of the physical core group 410_1.

[0107] In one embodiment of this application, reference is made to... Figure 5 Taking physical core group 410_1 as an example, the multiple physical cores in physical core group 410_1 include a first physical core 300a and a second physical core 300b. For example, physical core 310_1 is the first physical core 300a, and physical core 310_2 is the second physical core 300b. Furthermore, in any sampling period, the power consumption received by the second power management circuit 311b is the power consumption detected by the first power management circuit 311a. For example, the power consumption PS2(t) received by the second power management circuit 311b in the current sampling period t is the power consumption PM(t) detected by the first power management circuit 311a in the current sampling period t, and the power consumption PS2(t-1) received by the second power management circuit 311b in the previous sampling period t-1 is the power consumption PM(t-1) detected by the first power management circuit 311a in the previous sampling period t-1. Therefore, the first power management circuit 311a can directly output the power consumption detected in each sampling period to the second power management circuit 311b, without requiring the first power management circuit 311a to perform additional processing on the detected power consumption, which can further reduce communication latency. In other embodiments of this application, the power consumption received by the second power management circuit 311b in any sampling period can also be a portion of the power consumption detected by the first power management circuit 311a.

[0108] For example, the process of determining that the first target power consumption is higher than the second target power consumption may include: the difference between the first target power consumption PA(t) and the second target power consumption PA(t-1) (i.e., PA(t)-PA(t-1)) is greater than the first power consumption threshold ThA0. In other words, the increase in the first target power consumption relative to the second target power consumption can be determined according to the formula PA(t)-PA(t-1)>ThA0 or the formula PA(t)>PA(t-1)+ThA0. This makes the determination process relatively simpler to implement.

[0109] Exemplarily, for the process of determining that the first target power consumption is reduced relative to the second target power consumption, it may include: the difference between the first target power consumption PA(t) and the second target power consumption PA(t - 1) (i.e., PA(t) - PA(t - 1)) is less than the second power consumption threshold ThA1. That is, it can be determined that the first target power consumption is reduced relative to the second target power consumption according to the formula PA(t) - PA(t - 1) < ThA1 or the formula PA(t) < PA(t - 1) + ThA1. Thus, this determination process can be made diverse.

[0110] Exemplarily, for the process of determining that the first target power consumption has not changed or has a small change amount relative to the second target power consumption, it may include: the difference between the first target power consumption PA(t) and the second target power consumption PA(t - 1) (i.e., PA(t) - PA(t - 1)) is greater than or equal to the second power consumption threshold ThA1 and less than or equal to the first power consumption threshold ThA0. That is, it can be determined that the first target power consumption has not changed or has a small change amount relative to the second target power consumption according to the formula ThA1 ≤ PA(t) - PA(t - 1) ≤ ThA0 or the formula PA(t - 1) + ThA1 ≤ PA(t) ≤ PA(t - 1) + ThA0. Thus, this determination process can be relatively simple to implement.

[0111] The first target power consumption PA(t) is the product of the first weight KM and the power consumption PM(t) detected by the first power management circuit 311a in the current sampling period t, that is, PA(t) = PM(t) * KM. The second target power consumption PA(t - 1) is the product of the first weight KM and the power consumption PM(t - 1) detected by the first power management circuit 311a in the previous sampling period t - 1, that is, PA(t - 1) = PM(t - 1) * KM. Thus, by setting the first weight KM, the first target power consumption PA(t) and the second target power consumption PA(t - 1) can be relatively simple to implement, reducing the design difficulty and production cost.

[0112] Exemplarily, the second power consumption threshold ThA1 is less than the first power consumption threshold ThA0. And, the second power consumption threshold ThA1 is less than zero, the first power consumption threshold ThA0 is greater than zero, and the specific values of the second power consumption threshold ThA1 and the first power consumption threshold ThA0 can be flexibly designed according to the requirements of the actual application scenario and are not limited herein. Also, the first power consumption threshold ThA0 and the second power consumption threshold ThA1 can be stored in the first power management circuit 311a, or the first power consumption threshold ThA0 and the second power consumption threshold ThA1 can also be obtained through a hardware circuit. In addition, the first power consumption threshold ThA0 and the second power consumption threshold ThA1 can be fixed values or flexibly configurable values and are not limited herein.

[0113] Exemplarily, the first weight KM is less than 1 and greater than 0. Thus, the power consumption PM(t) and PM(t - 1) can be compressed by the first weight KM to improve the power consumption mutation of the first physical core 300a. Exemplarily, 0.5 ≤ KM ≤ 0.9 to avoid the power consumption PM(t) and PM(t - 1) being compressed too low and affecting the performance of the first physical core 300a. For example, the first weight KM can be 0.9, 0.8, 0.7, 0.6, 0.5, etc. Of course, the specific value of the first weight KM can also be flexibly designed according to the requirements of the actual application scenario and is not limited herein. In other embodiments of the present application, the first weight KM can also be equal to 1. In addition, the first weight KM can be stored in the first power management circuit 311a, or the first weight KM can also be stored in other hardware circuits of the first physical core 300a.

[0114] Exemplarily, for the process of determining that the third target power consumption increases relative to the fourth target power consumption, it may include: the difference between the third target power consumption PB(t) and the fourth target power consumption PB(t - 1) (i.e., PB(t) - PB(t - 1)) is greater than the third power consumption threshold ThB0. That is, it can be determined that the third target power consumption increases relative to the fourth target power consumption according to the formula PB(t) - PB(t - 1) > ThB0 or the formula PB(t) > PB(t - 1) + ThB0. Thus, this determination process can be relatively simple to implement.

[0115] Exemplarily, for the process of determining that the third target power consumption decreases relative to the fourth target power consumption, it may include: the difference between the third target power consumption PB(t) and the fourth target power consumption PB(t - 1) (i.e., PB(t) - PB(t - 1)) is less than the fourth power consumption threshold ThB1. That is, it can be determined that the third target power consumption decreases relative to the fourth target power consumption according to the formula PB(t) - PB(t - 1) < ThB1 or the formula PB(t) < PB(t - 1) + ThB1. Thus, this determination process can be relatively simple to implement.

[0116] Exemplarily, for the process of determining that the third target power consumption does not change or the change amount is small relative to the fourth target power consumption, it may include: the difference between the third target power consumption PB(t) and the fourth target power consumption PB(t - 1) (i.e., PB(t) - PB(t - 1)) is greater than or equal to the fourth power consumption threshold ThB1 and less than or equal to the third power consumption threshold ThB0. That is, it can be determined that the third target power consumption does not change or the change amount is small relative to the fourth target power consumption according to the formula ThB1 ≤ PB(t) - PB(t - 1) ≤ ThB0 or the formula PB(t - 1) + ThB1 ≤ PA(t) ≤ PB(t - 1) + ThB0. Thus, this determination process can be relatively simple to implement.

[0117] Wherein, the third target power consumption PB(t) is the sum of the first weighted power consumption PBa(t) and the second weighted power consumption PBb(t), i.e., PB(t) = PBa(t) + PBb(t). Furthermore, the first weighted power consumption PBa(t) is the product of the second weight KS and the power consumption PS1(t) detected by the second power management circuit 311b in the current sampling period t, i.e., PBa(t) = PS1(t) * KS. The second weighted power consumption PBb(t) is the product of the third weight KT and the power consumption PS2(t) received by the second power management circuit 311b in the current sampling period t, i.e., PBb(t) = PS2(t) * KT. Therefore, PB(t) = PS1(t) * KS + PS2(t) * KT. Therefore, by setting the second weight KS and the third weight KT, the power consumption PS2(t) and PS1(t) are combined with weights to obtain the third target power consumption PB(t). This makes the third target power consumption PB(t) relatively simple to implement, reduces the design difficulty, and reduces the production cost.

[0118] The fourth target power consumption PB(t-1) is the sum of the third weight power consumption PBa(t-1) and the fourth weight power consumption PBb(t-1), i.e., PB(t-1) = PBa(t-1) + PBb(t-1). Furthermore, the third weight power consumption PBa(t-1) is the product of the second weight KS and the power consumption PS1(t-1) detected by the second power management circuit 311b in the previous sampling period t-1, i.e., PBa(t-1) = PS1(t-1) * KS. The fourth weight power consumption PBb(t-1) is the product of the third weight KT and the power consumption PS2(t-1) received by the second power management circuit 311b in the previous sampling period t-1, i.e., PBb(t-1) = PS2(t-1) * KT. Therefore, PB(t-1) = PS1(t-1) * KS + PS2(t-1) * KT. Therefore, by setting the second weight KS and the third weight KT, the power consumption PS2(t-1) and PS1(t-1) are combined with weights to obtain the fourth target power consumption PB(t-1). This makes the fourth target power consumption PB(t-1) relatively simple to implement, reduces the design difficulty, and reduces the production cost.

[0119] Exemplarily, the fourth power consumption threshold ThB1 is less than the third power consumption threshold ThB0. Also, the fourth power consumption threshold ThB1 is less than zero, the third power consumption threshold ThB0 is greater than zero, and the specific values of the fourth power consumption threshold ThB1 and the third power consumption threshold ThB0 can be flexibly designed according to the requirements of the actual application scenario and are not limited herein. Moreover, the fourth power consumption threshold ThB1 and the third power consumption threshold ThB0 can be stored in the power consumption management circuit, or the fourth power consumption threshold ThB1 and the third power consumption threshold ThB0 can also be obtained through a hardware circuit. In addition, the fourth power consumption threshold ThB1 and the third power consumption threshold ThB0 can be fixed values or flexibly configurable values and are not limited herein.

[0120] Exemplarily, the second weight KS is less than or equal to 1 and greater than 0. Thus, by allocating corresponding weights, the power consumptions PS1(t) and PS1(t - 1) can be processed by the second weight KS to improve the power consumption mutation of the second physical core 300b. Exemplarily, 0.5 ≤ KS ≤ 1 to avoid the power consumptions PS1(t) and PS1(t - 1) from being compressed too low, which affects the performance of the second physical core 300b. For example, the second weight KS can be 1, 0.9, 0.8, 0.7, 0.6, 0.5, etc. Of course, the specific value of the second weight KS can also be flexibly designed according to the requirements of the actual application scenario and is not limited herein. Moreover, the second weight KS can be stored in the second power consumption management circuit 311b, or the second weight KS can also be stored in other hardware circuits of the second physical core 300b.

[0121] Exemplarily, the third weight KT is less than or equal to 1 and greater than 0. Thus, by allocating corresponding weights, the power consumptions PS2(t) and PS2(t - 1) can be processed by the third weight KT to improve the power consumption mutation of the second physical core 300b. Exemplarily, 0 < KT ≤ 0.5 to avoid the power consumptions PS2(t) and PS2(t - 1) from being compressed too low, which affects the performance of the second physical core 300b. For example, the third weight KT can be 0.5, 0.4, 0.3, 0.2, 0.1, etc. Of course, the specific value of the third weight KT can also be flexibly designed according to the requirements of the actual application scenario and is not limited herein. Moreover, the third weight KT can be stored in the second power consumption management circuit 311b, or the third weight KT can also be stored in other hardware circuits of the second physical core 300b.

[0122] Understandably, the sum of the third weight KT and the first weight KM can be 1, i.e., KT + KM = 1. Therefore, the first power management circuit 311a can improve the power consumption fluctuations of the first physical core 300a based on a portion of the power consumption PM(t-1) and a portion of the power consumption PM(t). Furthermore, the second power management circuit 311b, based on another portion of the power consumption PM(t-1) and another portion of the power consumption PM(t), combined with its own power consumption, can improve the power consumption fluctuations of the second physical core 300b and compensate for the power consumption fluctuations of the first physical core 300a. In other embodiments of this application, the sum of the third weight KT and the first weight KM can also be non-equal to 1, i.e., KT + KM > 1 or KT + KM < 1, thus allowing for flexible design of the relationship between the third weight KT and the first weight KM.

[0123] For example, refer to Figure 6 , Figure 6 This is another schematic diagram of the first and second physical cores in a physical core group according to an embodiment of this application. Taking physical core group 410_1 as an example, the first power management circuit 311a may include: a first power estimation circuit 3111a, a first power control circuit 3112a, and a first weighting circuit 3113a. The first power estimation circuit 3111a is connected to the first weighting circuit 3113a, and the first weighting circuit 3113a is connected to the first power control circuit 3112a. Therefore, the function of the first power management circuit 311a can be realized through the first power estimation circuit 3111a, the first power control circuit 3112a, and the first weighting circuit 3113a, making the implementation of the first power management circuit 311a relatively simple, reducing design difficulty, and lowering production costs.

[0124] The first power consumption estimation circuit 3111a is used to detect the power consumption of the first physical core 300a in each sampling period and output the detected power consumption to the first weighting circuit 3113a. For example, the first power consumption estimation circuit 3111a detects the power consumption PM(t) of the first physical core 300a in the current sampling period t and outputs the power consumption PM(t) to the first weighting circuit 3113a, and detects the power consumption PM(t-1) of the first physical core 300a in the previous sampling period t-1 and outputs the power consumption PM(t-1) to the first weighting circuit 3113a. Exemplarily, the first power consumption estimation circuit 3111a can obtain the instantaneous power consumption of the physical core using analog or digital circuits. For example, the first power consumption estimation circuit 3111a can calculate the instantaneous power consumption of the physical core based on the power consumption activity events in the physical core it belongs to. The power consumption activity events include some data information or services processed by the physical core. For example, the power consumption activity event can be all the data or services processed by the physical core, or it can be the data or services with higher power consumption among all the data or services processed by the physical core. Furthermore, the first power consumption estimation circuit 3111a is also connected to the second power consumption management circuit 311b, and is used to output at least a portion of the power consumption detected in each sampling period to the second power consumption management circuit 311b. For example, the first power consumption estimation circuit 3111a outputs the power consumption detected in each sampling period to the second power consumption management circuit 311b.

[0125] The first weighting circuit 3113a receives the power consumption output by the first power consumption estimation circuit 3111a, and outputs a first target power consumption PA(t) to the first power consumption control circuit 3112a in the current sampling period t, and outputs a second target power consumption PA(t-1) to the first power consumption control circuit 3112a in the previous sampling period t-1. For example, the first weighting circuit 3113a can multiply the power consumption PM(t) and PM(t-1) by the first weight KM respectively to calculate the first target power consumption PA(t) and the second target power consumption PA(t-1). The first weight can be stored in the first weighting circuit 3113a, or it can be stored in other hardware circuits of the first physical core 300a, and the first weighting circuit 3113a can directly call it when needed.

[0126] The first power consumption control circuit 3112a can acquire a first target power consumption PA(t) and a second target power consumption PA(t-1), and compare PA(t)-PA(t-1) with ThA0 and ThA1. When the difference between the first target power consumption PA(t) and the second target power consumption PA(t-1) (i.e., PA(t)-PA(t-1)) is greater than the first power consumption threshold ThA0, the operating parameters of the first physical core 300a are reduced, thereby reducing the instantaneous power consumption of the first physical core 300a. When the difference between the first target power consumption PA(t) and the second target power consumption PA(t-1) (i.e., PA(t)-PA(t-1)) is less than the second power consumption threshold ThA1, the operating parameters of the first physical core 300a are increased, thereby increasing the instantaneous power consumption of the first physical core 300a. For example, the first power consumption control circuit 3112a can store the target power consumption output by the first weighting circuit 3113a in one or more sampling periods prior to the current sampling period t. For example, the first power consumption control circuit 3112a can store the second target power consumption PA(t-1) from the previous sampling period t-1 in the current sampling period t. In addition, the first power consumption control circuit 3112a is also used to control the operating parameters of the first physical core 300a to remain unchanged when the difference between the first target power consumption PA(t) and the second target power consumption PA(t-1) (i.e., PA(t)-PA(t-1)) is greater than or equal to the second power consumption threshold ThA1 and less than or equal to the first power consumption threshold ThA0.

[0127] For example, refer to Figure 6 The second power management circuit 311b may include: a second power estimation circuit 3111b, a second power control circuit 3112b, a second weighting circuit 3113b, a third weighting circuit 3114b, and a power combination circuit 3115b. The second power estimation circuit 3111b is connected to the second weighting circuit 3113b, the second weighting circuit 3113b is connected to the power combination circuit 3115b, the third weighting circuit 3114b is connected to both the first power management circuit 311a and the power combination circuit 3115b, and the power combination circuit 3115b is connected to the second power control circuit 3112b. Therefore, the functions of the second power management circuit 311b can be achieved through the second power estimation circuit 3111b, the second power control circuit 3112b, the second weighting circuit 3113b, the third weighting circuit 3114b, and the power combination circuit 3115b, making the implementation of the second power management circuit relatively simple, reducing design difficulty, and lowering production costs.

[0128] The second power consumption estimation circuit 3111b is used to detect the power consumption of the second physical core 300b in each sampling period and output the detected power consumption to the second weighting circuit 3113b. For example, the second power consumption estimation circuit 3111b detects the power consumption PS1(t) of the second physical core 300b in the current sampling period t and outputs the power consumption PS1(t) to the second weighting circuit 3113b; in the previous sampling period t-1, it detects the power consumption PS1(t-1) of the second physical core 300b and outputs the power consumption PS1(t-1) to the second weighting circuit 3113b. Exemplarily, the second power consumption estimation circuit 3111b can obtain the instantaneous power consumption of the physical core using analog or digital circuits. For example, the second power consumption estimation circuit 3111b can calculate the instantaneous power consumption of the physical core based on power consumption activity events in the physical core it belongs to. These power consumption activity events include some data information or services processed by the physical core. For example, the power consumption activity event can be all the data or services processed by the physical core, or it can be the data or services with higher power consumption among all the data or services processed by the physical core. Furthermore, the structures of the first power consumption estimation circuit 3111a and the second power consumption estimation circuit 3111b can be the same or different.

[0129] The second weighting circuit 3113b receives the power consumption output by the second power consumption estimation circuit 3111b and outputs the first weighted power consumption PBa(t) to the power consumption combination circuit 3115b in the current sampling period t, and outputs the third weighted power consumption PBa(t-1) to the power consumption combination circuit 3115b in the previous sampling period t-1. For example, the second weighting circuit 3113b can multiply the power consumption PS1(t) and PS1(t-1) with the second weight KS respectively to calculate the first weighted power consumption PBa(t) and the third weighted power consumption PBa(t-1). The second weight can be stored in the second weighting circuit 3113b, or it can be stored in other hardware circuits of the second physical core 300b, and the second weighting circuit 3113b can directly call it when needed.

[0130] The third weighting circuit 3114b receives the power consumption output by the first power management circuit 311a and outputs the second weighted power consumption PBb(t) to the power combination circuit 3115b in the current sampling period t, and outputs the fourth weighted power consumption PBb(t-1) to the power combination circuit 3115b in the previous sampling period t-1. For example, the third weighting circuit 3114b can multiply the power consumption PS2(t) and PS2(t-1) with the third weight KT respectively to calculate the second weighted power consumption PBb(t) and the fourth weighted power consumption PBb(t-1). The third weight can be stored in the third weighting circuit 3114b, or it can be stored in other hardware circuits of the second physical core 300b, and the third weighting circuit 3114b can directly call it when needed.

[0131] The power consumption combination circuit 3115b is used to receive the first weighted power consumption PBa(t) and the second weighted power consumption PBb(t) in the current sampling period t, add PBa(t) and PBb(t) together, and output the third target power consumption PB(t) in the current sampling period t. In the previous sampling period t-1, it receives the third weighted power consumption PBa(t-1) and the fourth weighted power consumption PBb(t-1), adds PBa(t-1) and PBb(t-1) together, and outputs the fourth target power consumption PB(t-1) in the previous sampling period t-1.

[0132] The second power consumption control circuit 3112b can acquire the third target power consumption PB(t) and the fourth target power consumption PB(t-1), and compare PB(t)-PB(t-1) with ThB0 and ThB1. When the difference between the third target power consumption PB(t) and the fourth target power consumption PB(t-1) (i.e., PB(t)-PB(t-1)) is greater than the third power consumption threshold ThB0, the operating parameters of the second physical core 300b are reduced, resulting in a decrease in the instantaneous power consumption of the second physical core 300b. When the difference between the third target power consumption PB(t) and the fourth target power consumption PB(t-1) (i.e., PB(t)-PB(t-1)) is less than the fourth power consumption threshold ThB1, the operating parameters of the second physical core 300b are increased, resulting in an increase in the instantaneous power consumption of the second physical core 300b. For example, the second power consumption control circuit 3112b can store the target power consumption output by the power consumption combination circuit 3115b in one or more sampling periods prior to the current sampling period t. For example, the second power consumption control circuit 3112b can store the fourth target power consumption PB(t-1) from the previous sampling period t-1 in the current sampling period t. In addition, the second power consumption control circuit 3112b is also used to control the operating parameters of the second physical core 300b to remain unchanged when the difference between the third target power consumption PB(t) and the fourth target power consumption PB(t-1) (i.e., PB(t)-PB(t-1)) is greater than or equal to the fourth power consumption threshold ThB1 and less than or equal to the third power consumption threshold ThB0.

[0133] For example, the second weighting circuit 3113b and the third weighting circuit 3114b can be integrated together, or the second weighting circuit 3113b and the third weighting circuit 3114b can be independent weighting circuits.

[0134] For example, any one of the first weighting circuit 3113a, the second weighting circuit 3113b, and the third weighting circuit 3114b may be, but is not limited to, a register capable of performing storage functions.

[0135] The following is based on Figure 6 Taking the structure of the physical core group shown as an example, combined with Figure 7 The working process of the first physical core 300a and the second physical core 300b in the embodiments of this application is described.

[0136] S11. The first power consumption estimation circuit 3111a acquires the power consumption activity event of the first physical core 300a in the current sampling period t, and detects the power consumption PM(t) of the first physical core 300a based on the power consumption activity event. Then, the first power consumption estimation circuit 3111a outputs the power consumption PM(t) to the first weighting circuit 3113a and the third weighting circuit 3114b in the current sampling period t.

[0137] S12. The first weighting circuit 3113a receives the power consumption PM(t), multiplies the power consumption PM(t) by the first weight KM, calculates PM(t)*KM, and outputs the first target power consumption PA(t) to the first power consumption control circuit 3112a.

[0138] S13. The first power consumption control circuit 3112a acquires the first target power consumption PA(t) and the second target power consumption PA(t-1). When the difference between the first target power consumption PA(t) and the second target power consumption PA(t-1) (i.e., PA(t)-PA(t-1)) is greater than the first power consumption threshold ThA0, the operating parameters of the first physical core 300a are reduced, thereby reducing the instantaneous power consumption of the first physical core 300a. When the difference between the first target power consumption PA(t) and the second target power consumption PA(t-1) (i.e., PA(t)-PA(t-1)) is less than the second power consumption threshold ThA1, the operating parameters of the first physical core 300a are increased, thereby increasing the instantaneous power consumption of the first physical core 300a. The second target power consumption PA(t-1) is stored by the first power consumption control circuit 3112a.

[0139] S21. The second power consumption estimation circuit 3111b acquires the power consumption activity event of the second physical core 300b in the current sampling period t, and detects the power consumption PS1(t) of the second physical core 300b based on the power consumption activity event. Then, the second power consumption estimation circuit 3111b outputs the power consumption PS1(t) to the second weighting circuit 3113b in the current sampling period t.

[0140] S22. The second weighting circuit 3113b receives the power consumption PS1(t), multiplies the power consumption PS1(t) by the second weight KS, calculates PS1(t)*KS, and outputs the first weight power consumption PBa(t) to the power consumption combination circuit 3115b.

[0141] S23. The third weighting circuit 3114b receives the power consumption PS2(t), multiplies the power consumption PS2(t) by the third weight KT, calculates PS2(t)*KT, and outputs the second weight power consumption PBb(t) to the power consumption combination circuit 3115b.

[0142] S24. The power consumption combination circuit 3115b receives the first weighted power consumption PBa(t) and the second weighted power consumption PBb(t) in the current sampling period t, calculates PBa(t) + PBb(t), and outputs the third target power consumption PB(t) to the second power consumption control circuit 3112b.

[0143] S25. The second power consumption control circuit 3112b acquires the third target power consumption PB(t) and the fourth target power consumption PB(t-1). When the difference between the third target power consumption PB(t) and the fourth target power consumption PB(t-1) (i.e., PB(t)-PB(t-1)) is greater than the third power consumption threshold ThB0, the operating parameters of the second physical core 300b are reduced, thereby reducing the instantaneous power consumption of the second physical core 300b. When the difference between the third target power consumption PB(t) and the fourth target power consumption PB(t-1) (i.e., PB(t)-PB(t-1)) is less than the fourth power consumption threshold ThB1, the operating parameters of the second physical core 300b are increased, thereby increasing the instantaneous power consumption of the second physical core 300b. The fourth target power consumption PB(t-1) is stored by the second power consumption control circuit 3112b.

[0144] It is understandable that steps S11 to S13 and steps S21 to S22 can be performed in any order and can be done simultaneously.

[0145] It is worth mentioning that in the above embodiments of this application, some physical cores in the physical core group are first physical cores 300a, and the other part are second physical cores 300b. A potential problem introduced by this is that it leads to an asymmetry in the performance of the first physical core 300a and the second physical core 300b. This is a disadvantage for the symmetric multi-physical core processing chip 212 system. Since the second physical core 300b may need to bear the throttling losses caused by the simultaneous surge in power consumption of the first physical core 300a and the second physical core 300b, the performance of the second physical core 300b will be slightly lower than that of the first physical core 300a. To improve the performance symmetry between the first physical core 300a and the second physical core 300b, this application provides further embodiments in which the physical cores in the physical core group are time-divisionally swapped to the first physical core 300a and the second physical core 300b. That is, the same physical core is time-divisionally used as the first physical core 300a and the second physical core 300b, so that the performance loss is distributed across different physical cores in a time-division manner, thereby improving the performance symmetry between the first physical core 300a and the second physical core 300b. The following describes this embodiment in detail with reference to the embodiments and accompanying drawings. The similarities between the following embodiments and the above embodiments will not be repeated here; only the differences will be described.

[0146] In yet another embodiment of this application, reference is made to... Figure 8 , Figure 8This application provides another schematic diagram of the first and second physical cores in a physical core group according to an embodiment. Taking physical core group 410_1 as an example, physical cores 310_1 and 310_2 operate in alternating first and second time periods. In the first time period, physical core 310_1 is the first physical core 300a, and physical core 310_2 is the second physical core 300b. In the second time period, physical core 310_1 is the second physical core 300b, and physical core 310_2 is the first physical core 300a. For example, refer to... Figure 8 When physical core 310_1 is the first physical core 300a and physical core 310_2 is the second physical core 300b, the implementation methods of physical cores 310_1 and 310_2 can refer to the above embodiments, and will not be repeated here. Furthermore, when physical core 310_2 is the first physical core 300a and physical core 310_1 is the second physical core 300b, the implementation of physical core 310_2 can refer to the implementation of physical core 310_1 in the above embodiments, and the implementation of physical core 310_1 can refer to the implementation of physical core 310_2 in the above embodiments. That is, when physical core 310_2 is the first physical core 300a, physical core 310_2 may include a first power consumption estimation circuit 3111a, a first power consumption control circuit 3112a, and a first weighting circuit 3113a. And when physical core 310_1 is the second physical core 300b, physical core 310_1 may include a second power consumption estimation circuit 3111b, a second power consumption control circuit 3112b, a second weighting circuit 3113b, a third weighting circuit 3114b, and a power consumption combination circuit 3115b. The specific working process will not be described in detail here.

[0147] As an example, to reduce the area of ​​the physical core and increase integration density, the first power management circuit 311a and the second power management circuit 311b can have partially identical structures. For example, refer to... Figure 8When physical core 310_1 is the first physical core 300a, it includes a first power consumption estimation circuit 3111a, a first power consumption control circuit 3112a, and a first weighting circuit 3113a. When physical core 310_1 is the second physical core 300b, it includes a second power consumption estimation circuit 3111b, a second power consumption control circuit 3112b, and a second weighting circuit 3113b. The first power consumption estimation circuit 3111a and the second power consumption estimation circuit 3111b are the same circuit, meaning they are reused when physical core 310_1 is either the first physical core 300a or the second physical core 300b. The first power consumption control circuit 3112a and the second power consumption control circuit 3112b are the same, meaning they are reused when physical core 310_1 is configured as either physical core 300a or physical core 300b. Similarly, the first weighting circuit 3113a and the second weighting circuit 3113b are the same, meaning they are reused when physical core 310_1 is configured as either physical core 300a or physical core 300b. Therefore, not only can the corresponding functions be achieved when physical core 310_1 is time-division converted to either physical core 300a or physical core 300b, but the area of ​​the physical core can also be reduced, increasing integration density.

[0148] As another example, to reduce the area of ​​the physical core and increase integration density, the entire structure of the first power management circuit 311a and the second power management circuit 311b can be identical. For example, refer to... Figure 9 , Figure 9This application embodiment shows another schematic diagram of the first and second physical cores in a physical core group. When physical core 310_1 is the first physical core 300a, in addition to the first power consumption estimation circuit 3111a, the first power consumption control circuit 3112a, and the first weighting circuit 3113a, physical core 310_1 may also have a power consumption combination circuit 3115a and a third weighting circuit 3114a. The power consumption combination circuit 3115a is connected between the first weighting circuit 3113a and the first power consumption control circuit 3112a. Then, the first target power consumption PA(t) and the second target power consumption PA(t-1) output by the first weighting circuit 3113a are respectively output to the first power consumption control circuit 3112a through the power consumption combination circuit 3115a. When physical core 310_1 is the first physical core 300a, the power consumption combination circuit 3115a does not work. Furthermore, when physical core 310_1 is the second physical core 300b, physical core 310_1 includes a second power consumption estimation circuit 3111b, a second power consumption control circuit 3112b, a second weighting circuit 3113b, a third weighting circuit 3114b, and a power consumption combination circuit 3115b. The first power consumption estimation circuit 3111a and the second power consumption estimation circuit 3111b are the same, meaning they are reused when physical core 310_1 is either the first physical core 300a or the second physical core 300b. Similarly, the first power consumption control circuit 3112a and the second power consumption control circuit 3112b are the same, meaning they are reused when physical core 310_1 is either the first physical core 300a or the second physical core 300b. The first weighting circuit 3113a and the second weighting circuit 3113b are the same, meaning they are reused when physical core 310_1 is either the first physical core 300a or the second physical core 300b. The third weighting circuit 3114a and the third weighting circuit 3114b are the same, meaning they are reused when physical core 310_1 is either the first physical core 300a or the second physical core 300b. The power consumption combination circuit 3115a and the power consumption combination circuit 3115b are the same, meaning they are reused when physical core 310_1 is either the first physical core 300a or the second physical core 300b. Therefore, not only can the physical core 310_1 be converted into the first physical core 300a and the second physical core 300b in a time-division manner, but the area of ​​the physical core can also be reduced and the integration density improved.

[0149] Understandably, in order to clearly illustrate the relationship between the first physical core 300a and the second physical core 300b in the embodiments of this application, Figure 8The following is an illustration using physical cores 310_1 and 310_2 in physical core group 410_1 as examples. The implementation methods of the other physical core groups 410_2 to 410_8 are the same as those of physical core group 410_1, and will not be described in detail here.

[0150] In one embodiment of this application, reference is made to... Figure 10A , Figure 10A This is another schematic diagram illustrating the time-division multiplexing of physical cores into first and second physical cores in this embodiment. The processing chip 212 also includes a global arbitrator 510, which is connected to each physical core. In response to the control of the global arbitrator 510, multiple physical cores in any physical core group operate in alternating first and second time periods. This simplifies the implementation of controlling the switching process between the first and second physical cores, reducing design complexity and production costs. For example, taking physical core group 410_1 as an example, when the arbitration result of the global arbitrator 510 is "1", the first time period begins, with physical core 310_1 becoming the first physical core 300a and physical core 310_2 becoming the second physical core 300b. When the arbitration result of the global arbitrator 510 is "0", the second time period begins, with physical core 310_1 becoming the second physical core 300b and physical core 310_2 becoming the first physical core 300a.

[0151] For example, refer to Figure 10B , Figure 10B This is another schematic diagram illustrating the time-sharing conversion of physical cores to the first and second physical cores in this embodiment. The global arbitrator 510 can be a global counter 511, which simplifies its implementation, reduces design complexity, and lowers production costs. For example, when the flag bit of the global counter 511 is "1", it indicates an arbitration result of "1", thus entering the first time period. Physical core 310_1 becomes the first physical core 300a, and physical core 310_2 becomes the second physical core 300b. When the flag bit of the global counter 511 is "0", it indicates an arbitration result of "0", thus entering the second time period. Physical core 310_1 becomes the second physical core 300b, and physical core 310_2 becomes the first physical core 300a. It is understood that the flag bit is a specific bit of the global counter 511, and the configuration register can select which bit to use as the switching flag bit. In this way, the switching period between the first and second time periods can be controlled. In other embodiments of this application, the global arbitrator 510 may be implemented in other ways, which are not limited here.

[0152] In yet another embodiment of this application, reference is made to... Figure 11 , Figure 11This is another schematic diagram illustrating the time-division multiplexing of physical cores into first and second physical cores in this embodiment. The processing chip 212 also includes a central arbitrator 520, which is connected to each physical core. In response to the control of the central arbitrator 520, multiple physical cores in any physical core group operate in alternating first and second time periods. This simplifies the implementation of controlling the switching process between the first and second physical cores, reducing design complexity and production costs. For example, taking physical core group 410_1 as an example, when the arbitration result of the central arbitrator 520 is "1", the first time period begins, with physical core 310_1 becoming the first physical core 300a and physical core 310_2 becoming the second physical core 300b. When the arbitration result of the central arbitrator 520 is "0", the second time period begins, with physical core 310_1 becoming the second physical core 300b and physical core 310_2 becoming the first physical core 300a. Understandably, the central arbiter 520 can control the time ratio of the first time period and the second time period by controlling the ratio of outputs 1 and 0, thereby achieving symmetrical control and improving the performance symmetry between the first physical core 300a and the second physical core 300b. In other embodiments of this application, the central arbiter 520 can also control the time ratio of the first time period and the second time period by controlling the ratio of outputs 1 and 0, thereby achieving asymmetric control, making the performance of one physical core higher than that of the other physical core, and realizing Quality of Service (QoS) control.

[0153] Understandably, the global arbitrator 510 and the central arbitrator 520 are only used to control the switching of physical cores between the first physical core 300a and the second physical core 300b, and will not participate in the power consumption control strategy of the first physical core 300a and the second physical core 300b. Therefore, the arbitration delay of the global arbitrator 510 and the central arbitrator 520 will not affect the power consumption control effect.

[0154] Figure 12 This is another schematic diagram of the first and second physical cores in a physical core group in an embodiment of this application, referring to... Figure 12This embodiment modifies the implementation methods described in the above embodiments. The similarities are not repeated here. The difference between this embodiment and the above embodiments is that: the multiple physical cores in any physical core group include multiple first physical cores and one second physical core; and, in any sampling period, the power consumption received by the second power management circuit is the sum of the power consumption detected by the first power management circuits in the multiple first physical cores. For example, taking a physical core group including physical cores 310_1 to 310_3, where physical core 310_1 is the first physical core 300a_1, physical core 310_2 is the first physical core 300a_2, and physical core 310_3 is the second physical core 300b, then in any sampling period t, the power consumption received by the second power management circuit in the second physical core 300b can be the sum of the power consumption detected by the first power management circuit in the first physical core 300a_1 and the power consumption detected by the first power management circuit in the first physical core 300a_2. Furthermore, the working process of the first and second physical cores in this physical core group can refer to the above implementation methods, and will not be repeated here.

[0155] In other embodiments of this application, the power consumption received by the second power management circuit is a portion of the sum of the power consumption detected by the first power management circuit in the plurality of first physical cores.

[0156] It is understood that, in order to clearly illustrate the relationship between any physical core group in the embodiments of this application, which includes multiple first physical cores and one second physical core, Figure 12 The following is an example of a physical core group consisting of two first physical cores. A physical core group may also include other numbers of first physical cores, which will not be elaborated here.

[0157] Figure 13 This is another schematic diagram of the first and second physical cores in a physical core group in an embodiment of this application, referring to... Figure 13This embodiment modifies the implementation methods described in the above embodiments, and the similarities are not repeated here. The difference between this embodiment and the above embodiments is that: the multiple physical cores in any physical core group include one first physical core and multiple second physical cores, and in any sampling period, the power consumption received by the second power management circuit in any second physical core is a portion of the power consumption detected by the first power management circuit. For example, taking a physical core group including physical cores 310_1 to 310_3 as an example, physical core 310_1 is the first physical core 300a, physical core 310_2 is the second physical core 300b_1, and physical core 310_3 is the second physical core 300b_2, then in any sampling period, the power consumption received by the second power management circuit in the second physical core 300b_1 can be a portion of the power consumption detected by the first power management circuit in the first physical core 300a, and the power consumption received by the second power management circuit in the second physical core 300b_2 can be another portion of the power consumption detected by the first power management circuit in the first physical core 300a. Furthermore, the working process of the first and second physical cores in this physical core group can refer to the above implementation method, and will not be elaborated here.

[0158] In one embodiment of this application, the power consumption detected by the first power management circuit in the first physical core 300a can be sent to different second physical cores 300b_1 to 300b_2 according to a certain ratio, so that the different second physical cores 300b_1 to 300b_2 can compensate for the power consumption fluctuations of the first physical core 300a according to the ratio. Exemplarily, this ratio can be flexibly determined according to the needs of the actual application scenario, and is not limited here.

[0159] It is understood that, in order to clearly illustrate the relationship between any physical core group in the embodiments of this application, which includes one first physical core and multiple second physical cores, Figure 13 The following is an example of a physical core group including two second physical cores. A physical core group may also include other numbers of second physical cores, which will not be elaborated here.

[0160] Figure 14 This is another schematic diagram of the first and second physical cores in a physical core group in an embodiment of this application, referring to... Figure 14This embodiment modifies the implementation method described in the above embodiments. The similarities are not repeated here. The difference between this embodiment and the above embodiments is that: the multiple physical cores in any physical core group include multiple first physical cores and multiple second physical cores, and in any sampling period, the power consumption received by the second power management circuit in any second physical core is a portion of the accumulated power consumption, which is the sum of the power consumption detected by the first power management circuit in the multiple first physical cores. For example, taking a physical core group including physical cores 310_1 to 310_4 as an example, physical core 310_1 is the first physical core 300a_1, physical core 310_2 is the first physical core 300a_2, physical core 310_3 is the second physical core 300b_1, and physical core 310_4 is the second physical core 300b_2. Then, in any sampling period, the sum of the power consumption detected by the first physical cores 300a_1 and 300a_2 is the accumulated power consumption. The power consumption received by the second power management circuit in the second physical core 300b_1 is a part of the accumulated power consumption, and the power consumption received by the second power management circuit in the second physical core 300b_2 is the other part of the accumulated power consumption. In addition, the working process of the first physical core and the second physical core in this physical core group can refer to the above implementation method, and the specific details will not be repeated here.

[0161] In one embodiment of this application, the accumulated power consumption can be sent to different second physical cores 300b_1 to 300b_2 according to a certain ratio, so that the different second physical cores 300b_1 to 300b_2 can compensate for the power consumption fluctuations of the first physical cores 300a_1 to 300a_2 as a whole. Exemplarily, this ratio can be flexibly determined according to the needs of the actual application scenario, and is not limited here.

[0162] It is understood that, in order to clearly illustrate the relationship between any physical core group in the embodiments of this application, it is included that it comprises multiple first physical cores and multiple second physical cores. Figure 14 The following is an example of a physical core group consisting of two first physical cores and two second physical cores. A physical core group may also include other numbers of first physical cores and other numbers of second physical cores, which will not be elaborated here.

[0163] Based on the same inventive concept, this application also provides a power consumption control method for a processing chip. The processing chip includes one or more physical core groups, and the physical core groups include multiple physical cores. The multiple physical cores include a first physical core and a second physical core. The first physical core includes a first power management circuit, and the second physical core includes a second power management circuit.

[0164] The method includes:

[0165] The first power management circuit detects the power consumption of the first physical core in each sampling period and outputs at least a portion of the power consumption detected in each sampling period to the second power management circuit; the second power management circuit detects the power consumption of the second physical core in each sampling period.

[0166] When the first target power consumption increases relative to the second target power consumption, and the third target power consumption increases relative to the fourth target power consumption, the first power management circuit reduces the operating parameters of the first physical core, and the second power management circuit reduces the operating parameters of the second physical core.

[0167] When the first target power consumption decreases relative to the second target power consumption, and the third target power consumption decreases relative to the fourth target power consumption, the first power management circuit increases the operating parameters of the first physical core, and the second power management circuit increases the operating parameters of the second physical core.

[0168] When the first target power consumption increases relative to the second target power consumption and the third target power consumption decreases relative to the fourth target power consumption, the first power management circuit reduces the operating parameters of the first physical core, and the second power management circuit increases the operating parameters of the second physical core.

[0169] When the first target power consumption decreases relative to the second target power consumption and the third target power consumption increases relative to the fourth target power consumption, the first power management circuit increases the operating parameters of the first physical core, and the second power management circuit decreases the operating parameters of the second physical core.

[0170] The first target power consumption is used to indicate the power consumption detected by the first power management circuit in the current sampling period, the second target power consumption is used to indicate the power consumption detected by the first power management circuit in the previous sampling period, the third target power consumption is used to indicate the sum of the power consumption detected by the second power management circuit in the current sampling period and the power consumption received, and the fourth target power consumption is used to indicate the sum of the power consumption detected by the second power management circuit in the previous sampling period and the power consumption received.

[0171] In one embodiment of this application, determining that the first target power consumption is higher than the second target power consumption includes: the difference between the first target power consumption and the second target power consumption is greater than a first power consumption threshold.

[0172] In one embodiment of this application, determining that the first target power consumption is lower than the second target power consumption includes: the difference between the first target power consumption and the second target power consumption is less than the second power consumption threshold.

[0173] Wherein, the first target power consumption is the product of the first weight and the power consumption detected by the first power management circuit in the current sampling period, the second target power consumption is the product of the first weight and the power consumption detected by the first power management circuit in the previous sampling period, and the second power consumption threshold is less than the first power consumption threshold.

[0174] In one embodiment of this application, the first weight is less than 1 and the first weight is greater than 0.

[0175] In one embodiment of this application, determining that the third target power consumption is higher than the fourth target power consumption includes: the difference between the third target power consumption and the fourth target power consumption is greater than the third power consumption threshold.

[0176] In one embodiment of this application, determining that the third target power consumption is lower than the fourth target power consumption includes: the difference between the third target power consumption and the fourth target power consumption is less than the fourth power consumption threshold.

[0177] The third target power consumption is the sum of the first weight power consumption and the second weight power consumption. The first weight power consumption is the product of the second weight and the power consumption detected by the second power management circuit in the current sampling period. The second weight power consumption is the product of the third weight and the power consumption received by the second power management circuit in the current sampling period.

[0178] The fourth target power consumption is the sum of the third weight power consumption and the fourth weight power consumption. The third weight power consumption is the product of the second weight and the power consumption detected by the second power management circuit in the previous sampling period. The fourth weight power consumption is the product of the third weight and the power consumption received by the second power management circuit in the previous sampling period.

[0179] The fourth power consumption threshold is less than the third power consumption threshold.

[0180] In one embodiment of this application, the second weight is less than or equal to 1, and the second weight is greater than 0.

[0181] In one embodiment of this application, the third weight is less than or equal to 1, and the third weight is greater than 0.

[0182] The above description is only a specific implementation of this application, but the protection scope of this application is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the protection scope of this application.

Claims

1. A processing chip, characterized in that, It includes one or more physical core groups, the physical core groups including multiple physical cores; the multiple physical cores include a first physical core and a second physical core, the first physical core including a first power management circuit, and the second physical core including a second power management circuit; The first power management circuit is configured to: detect the power consumption of the first physical core in each sampling period; decrease the operating parameters of the first physical core when the first target power consumption increases relative to the second target power consumption; and increase the operating parameters of the first physical core when the first target power consumption decreases relative to the second target power consumption. The first target power consumption is used to indicate the power consumption detected by the first power management circuit in the current sampling period, and the second target power consumption is used to indicate the power consumption detected by the first power management circuit in the previous sampling period. The first power management circuit is connected to the second power management circuit and is further configured to: output at least a portion of the power consumption detected in each sampling period to the second power management circuit; The second power management circuit is configured to: detect the power consumption of the second physical core in each sampling period, and, when the third target power consumption increases relative to the fourth target power consumption, decrease the operating parameters of the second physical core, and when the third target power consumption decreases relative to the fourth target power consumption, increase the operating parameters of the second physical core, wherein the third target power consumption is used to indicate the sum of the power consumption detected and received by the second power management circuit in the current sampling period, and the fourth target power consumption is used to indicate the sum of the power consumption detected and received by the second power management circuit in the previous sampling period; The operating parameters include one or more of the following: operating frequency, number of gated clocks, and number of pipelines.

2. The processing chip according to claim 1, characterized in that, Determining that the first target power consumption is higher than the second target power consumption includes: the difference between the first target power consumption and the second target power consumption is greater than a first power consumption threshold; or, Determining that the first target power consumption is lower than the second target power consumption includes: the difference between the first target power consumption and the second target power consumption is less than a second power consumption threshold; Wherein, the first target power consumption is the product of the first weight and the power consumption detected by the first power management circuit in the current sampling period, the second target power consumption is the product of the first weight and the power consumption detected by the first power management circuit in the previous sampling period, and the second power consumption threshold is less than the first power consumption threshold.

3. The processing chip according to claim 2, characterized in that, The first power management circuit includes: a first power estimation circuit, a first power control circuit, and a first weighting circuit; The first power consumption estimation circuit is connected to the first weighting circuit and is used to detect the power consumption of the first physical core in each sampling period and output the detected power consumption to the first weighting circuit. The first weighting circuit is connected to the first power consumption control circuit, and is used to receive the power consumption output by the first power consumption estimation circuit, and output the first target power consumption to the first power consumption control circuit in the current sampling period, and output the second target power consumption to the first power consumption control circuit in the previous sampling period; The first power consumption control circuit is used to reduce the operating parameters of the first physical core when the difference between the first target power consumption and the second target power consumption is greater than the first power consumption threshold, and to increase the operating parameters of the first physical core when the difference between the first target power consumption and the second target power consumption is less than the second power consumption threshold. The first power consumption estimation circuit is also connected to the second power consumption management circuit, and is used to output at least a portion of the power consumption detected in each sampling period to the second power consumption management circuit.

4. The processing chip according to claim 2 or 3, characterized in that, The first weight is less than 1, and the first weight is greater than 0.

5. The processing chip according to any one of claims 1-4, characterized in that, Determining that the third target power consumption is higher than the fourth target power consumption includes: the difference between the third target power consumption and the fourth target power consumption is greater than a third power consumption threshold; or, Determining that the third target power consumption is lower than the fourth target power consumption includes: the difference between the third target power consumption and the fourth target power consumption is less than the fourth power consumption threshold; Wherein, the third target power consumption is the sum of the first weighted power consumption and the second weighted power consumption, the first weighted power consumption is the product of the second weight and the power consumption detected by the second power management circuit in the current sampling period, and the second weighted power consumption is the product of the third weight and the power consumption received by the second power management circuit in the current sampling period. The fourth target power consumption is the sum of the third weight power consumption and the fourth weight power consumption. The third weight power consumption is the product of the second weight and the power consumption detected by the second power management circuit in the previous sampling period. The fourth weight power consumption is the product of the third weight and the power consumption received by the second power management circuit in the previous sampling period. The fourth power consumption threshold is less than the third power consumption threshold.

6. The processing chip according to claim 5, characterized in that, The second power management circuit includes: a second power estimation circuit, a second power control circuit, a second weighting circuit, a third weighting circuit, and a power combination circuit; The second power consumption estimation circuit is connected to the second weighting circuit and is used to detect the power consumption of the second physical core in each sampling period and output the detected power consumption to the second weighting circuit. The second weighting circuit is connected to the power consumption combination circuit, and is used to receive the power consumption output by the second power consumption estimation circuit, and output the first weighted power consumption to the power consumption combination circuit in the current sampling period, and output the third weighted power consumption to the power consumption combination circuit in the previous sampling period. The third weighting circuit is connected to the first power management circuit and the power combination circuit respectively, and is used to receive the power output by the first power management circuit, output the second weighted power consumption to the power combination circuit in the current sampling period, and output the fourth weighted power consumption to the power combination circuit in the previous sampling period. The power consumption combination circuit is connected to the second power consumption control circuit and is used to receive the first weighted power consumption and the second weighted power consumption in the current sampling period and output the third target power consumption in the current sampling period, and to receive the third weighted power consumption and the fourth weighted power consumption in the previous sampling period and output the fourth target power consumption in the previous sampling period. The second power consumption control circuit is used to reduce the operating parameters of the second physical core when the difference between the third target power consumption and the fourth target power consumption is greater than the third power consumption threshold, and to increase the operating parameters of the second physical core when the difference between the third target power consumption and the fourth target power consumption is less than the fourth power consumption threshold.

7. The processing chip according to claim 5 or 6, characterized in that, The second weight is less than or equal to 1, and the second weight is greater than 0; Alternatively, the third weight is less than or equal to 1, and the third weight is greater than 0.

8. The processing chip according to any one of claims 1-7, characterized in that, The plurality of physical cores in any of the physical core groups includes one first physical core and one second physical core, and in any of the sampling periods, the power consumption received by the second power management circuit is the power consumption detected by the first power management circuit; or, The plurality of physical cores in any of the physical core groups include a plurality of first physical cores and a second physical core. In any of the sampling periods, the power consumption received by the second power management circuit is the sum of the power consumption detected by the first power management circuit in the plurality of first physical cores.

9. The processing chip according to any one of claims 1-7, characterized in that, The plurality of physical cores in any of the physical core groups includes one first physical core and a plurality of second physical cores. In any of the sampling periods, the power consumption received by the second power management circuit in any second physical core is a portion of the power consumption detected by the first power management circuit; or... The plurality of physical cores in any physical core group include a plurality of first physical cores and a plurality of second physical cores. In any sampling period, the power consumption received by the second power management circuit in any second physical core is a portion of the accumulated power consumption, wherein the accumulated power consumption is the sum of the power consumption detected by the first power management circuit in the plurality of first physical cores.

10. The processing chip according to any one of claims 1-9, characterized in that, The multiple physical cores operate in alternating first and second time periods; During the first time period, a portion of the multiple physical cores are the first physical cores, and another portion of the physical cores are the second physical cores; During the second time period, one part of the physical core is the second physical core, and the other part of the physical core is the first physical core.

11. The processing chip according to claim 10, characterized in that, The processing chip further includes a global arbiter connected to each of the physical cores. In response to the control of the global arbiter, the plurality of physical cores in any group of physical cores are configured to operate during alternating first and second time periods; or... The processing chip also includes a central arbiter connected to each of the physical cores, which, in response to the control of the central arbiter, causes the plurality of physical cores in any group of physical cores to operate in alternating first and second time periods.

12. A power consumption control method for a processing chip, characterized in that, The processing chip includes one or more physical core groups, and the physical core group includes multiple physical cores; the multiple physical cores include a first physical core and a second physical core, the first physical core includes a first power management circuit, and the second physical core includes a second power management circuit. The method includes: The first power management circuit detects the power consumption of the first physical core in each sampling period and outputs at least a portion of the power consumption detected in each sampling period to the second power management circuit; the second power management circuit detects the power consumption of the second physical core in each sampling period. When the first target power consumption increases relative to the second target power consumption, and the third target power consumption increases relative to the fourth target power consumption, the first power management circuit reduces the operating parameters of the first physical core, and the second power management circuit reduces the operating parameters of the second physical core. When the first target power consumption decreases relative to the second target power consumption, and the third target power consumption decreases relative to the fourth target power consumption, the first power management circuit increases the operating parameters of the first physical core, and the second power management circuit increases the operating parameters of the second physical core. When the first target power consumption increases relative to the second target power consumption, and the third target power consumption decreases relative to the fourth target power consumption, the first power management circuit reduces the operating parameters of the first physical core, and the second power management circuit increases the operating parameters of the second physical core. When the first target power consumption decreases relative to the second target power consumption and the third target power consumption increases relative to the fourth target power consumption, the first power management circuit increases the operating parameters of the first physical core, and the second power management circuit decreases the operating parameters of the second physical core. Wherein, the first target power consumption is used to indicate the power consumption detected by the first power management circuit in the current sampling period, the second target power consumption is used to indicate the power consumption detected by the first power management circuit in the previous sampling period, the third target power consumption is used to indicate the sum of the power consumption detected by the second power management circuit and the power consumption received in the current sampling period, and the fourth target power consumption is used to indicate the sum of the power consumption detected by the second power management circuit and the power consumption received in the previous sampling period.

13. The method according to claim 12, characterized in that, Determining that the first target power consumption is higher than the second target power consumption includes: the difference between the first target power consumption and the second target power consumption is greater than a first power consumption threshold; or, Determining that the first target power consumption is lower than the second target power consumption includes: the difference between the first target power consumption and the second target power consumption is less than a second power consumption threshold; Wherein, the first target power consumption is the product of the first weight and the power consumption detected by the first power management circuit in the current sampling period, the second target power consumption is the product of the first weight and the power consumption detected by the first power management circuit in the previous sampling period, and the second power consumption threshold is less than the first power consumption threshold.

14. The method according to claim 13, characterized in that, The first weight is less than 1, and the first weight is greater than 0.

15. The method according to any one of claims 12-14, characterized in that, Determining that the third target power consumption is higher than the fourth target power consumption includes: the difference between the third target power consumption and the fourth target power consumption is greater than a third power consumption threshold; or, Determining that the third target power consumption is lower than the fourth target power consumption includes: the difference between the third target power consumption and the fourth target power consumption is less than the fourth power consumption threshold; Wherein, the third target power consumption is the sum of the first weighted power consumption and the second weighted power consumption, the first weighted power consumption is the product of the second weight and the power consumption detected by the second power management circuit in the current sampling period, and the second weighted power consumption is the product of the third weight and the power consumption received by the second power management circuit in the current sampling period. The fourth target power consumption is the sum of the third weight power consumption and the fourth weight power consumption. The third weight power consumption is the product of the second weight and the power consumption detected by the second power management circuit in the previous sampling period. The fourth weight power consumption is the product of the third weight and the power consumption received by the second power management circuit in the previous sampling period. The fourth power consumption threshold is less than the third power consumption threshold.

16. The method according to claim 15, characterized in that, The second weight is less than or equal to 1, and the second weight is greater than 0; Alternatively, the third weight is less than or equal to 1, and the third weight is greater than 0.

17. A semiconductor packaging structure, characterized in that, It includes a packaging substrate and a processing chip as described in any one of claims 1-11, wherein the processing chip is packaged on the packaging substrate.

18. An electronic device, characterized in that, include: The circuit board, the power supply module, and the semiconductor package structure as described in claim 17 are respectively disposed on the circuit board, the power supply module and the semiconductor package structure are connected, and the power supply module is used to provide power voltage to the processing chip in the semiconductor package structure.

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