A hardware energy-saving control method and circuit

Abstract

This invention discloses a hardware energy-saving control method and circuit, belonging to the field of hardware power consumption control technology. This invention performs power management through a hardware energy-saving control circuit whose physical topology, logic operations, timing control, and clock source are all independent of the system's main CPU. The circuit is implemented only by non-programmable fixed hardware combinational logic and timing logic, containing no firmware, microcode, or programmable configuration data. It does not interact with the main CPU, system software, or other hardware modules in any data or signal manner, and does not sample external hardware status or level signals. It independently performs power on / off, sleep, and wake-up control of the target hardware module solely through its own preset fixed timing logic, without requiring adaptation or coordination from existing systems, drivers, or software. This invention does not occupy main system resources, has no firmware security risks, and achieves highly efficient and reliable hardware-level energy-saving control.

Description

Technical Field

[0001] This invention relates to the field of hardware power consumption control technology, and in particular to a hardware energy-saving control method and circuit. Background Technology

[0002] With the widespread application of electronic devices, computer systems, and edge computing terminals, hardware power consumption control has become one of the core technologies for improving device battery life, reducing operating costs, and extending hardware lifespan. Existing hardware energy-saving solutions mainly fall into the following categories, all of which have insurmountable technical defects: The first type is software-driven energy-saving solutions, which use the operating system, drivers, or main CPU to run energy-saving algorithms, monitor hardware operating status, and perform power consumption regulation. These solutions rely on the main CPU and system software, consuming significant main system resources and easily causing system lag; they also have high response latency, making real-time and precise power consumption control impossible; and they are highly susceptible to system operating conditions, failing to function properly when the system crashes or is under excessive load, resulting in insufficient reliability.

[0003] The second type is a hardware-based energy-saving solution with firmware / microcontroller unit (MCU). This solution uses a power management chip with an integrated MCU to perform energy-saving control, requiring firmware to be programmed to implement the control logic. This type of solution requires compatible drivers and system software. Different hardware platforms require separate adaptation packages, resulting in high adaptation costs and long development cycles. It also carries security risks such as firmware vulnerabilities and malicious tampering. Furthermore, it still needs to interact with the main CPU and system bus during operation, making completely independent operation impossible and exhibiting poor anti-interference capabilities.

[0004] The third category is conventional hardware energy-saving circuits. Although these circuits are implemented using hardware logic, they must sample signals such as the status pins, operating levels, and bus transmission status of external hardware in order to determine the hardware operating status and execute energy-saving control. The control logic is complex and easily affected by external signals. They still require the main CPU to provide control instructions or status feedback and cannot operate independently of the main system. Some solutions require modification of the original hardware signal paths and operating logic, resulting in extremely poor compatibility and making them unsuitable for large-scale application.

[0005] In summary, there is currently no hardware energy-saving solution that can be completely independent of the main CPU and system software, implemented with pure fixed hardware logic, without sampling any external status signals, and without any software adaptation or system coordination. It cannot simultaneously solve the core problems of resource consumption, adaptation costs, security risks, and poor reliability of existing solutions. Summary of the Invention

[0006] (a) Technical problems to be solved The purpose of this invention is to overcome the above-mentioned defects of the prior art and provide a hardware energy-saving control method and circuit, which completely solves the core problems of existing energy-saving solutions that rely on the main CPU / software / firmware, occupy system resources, have high adaptation costs, have security vulnerabilities, require sampling external signals, and cannot operate completely independently, so as to achieve hardware-level energy-saving control that requires no system collaboration, is plug-and-play, highly reliable, and highly secure.

[0007] (II) Technical Solution To achieve the above objectives, the present invention adopts the following technical solution: A hardware energy-saving control method is disclosed, which performs power consumption management on target hardware modules within a system through a hardware energy-saving control circuit. The physical topology, logic operations, timing control, and clock source of the hardware energy-saving control circuit are independent of the system's main CPU. It is implemented solely by non-programmable fixed hardware combinational logic and sequential logic circuits, containing no executable firmware, microcode, software instructions, or programmable logic configuration data, and lacks one-time or multiple programmability. The hardware energy-saving control circuit does not participate in the instruction execution flow of the system's main CPU, does not read or write to the main CPU's internal registers, does not sample the main CPU's operating status parameters, does not receive control instructions and status feedback signals from the main CPU, and does not... It does not interact with the main CPU and upper-level system software in any data or instruction manner, does not listen to any transmission content or status of the system bus, does not sample the status pins, enable pins, operating levels and control signals of any hardware modules other than its own circuits, and does not modify or interfere with the internal signal paths and native working logic of the original hardware modules. The hardware energy-saving control circuit independently completes the switching of operating states, sleep triggering and wake-up triggering through its own internally preset fixed timing logic, and autonomously performs power supply on / off control, sleep control and wake-up control on the target hardware module. Its entire operation does not require any adaptation configuration, operation coordination or intervention from the original system, hardware driver or software program.

[0008] Furthermore, when the hardware energy-saving control circuit determines that the target hardware module is in an idle state, it performs a hardware-level targeted power-off operation on the module to cut off its power supply circuit and reduce ineffective power consumption.

[0009] Furthermore, the hardware energy-saving control circuit uses an independent dedicated clock source, and its timing control logic is completely isolated from the clock system of the main CPU and has no synchronization relationship.

[0010] Furthermore, the hardware energy-saving control circuit performs a hardware-level leakage current lockout operation on the target hardware module in a power-off sleep state, cutting off the leakage current path of the module through a hardware switch to reduce standby power consumption.

[0011] Furthermore, the hardware energy-saving control circuit monitors the wake-up trigger conditions solely through its internally preset fixed timing logic, and completes the wake-up operation of the target hardware module without any signal interaction with any other modules in the system.

[0012] This invention also provides a hardware energy-saving control circuit, which is a dedicated circuit for executing the aforementioned hardware energy-saving control method. The physical topology, logic operations, timing control, and clock source of this circuit are all independent of the system's main CPU. It is implemented solely by non-programmable fixed hardware combinational logic and timing logic circuits, containing no executable firmware, microcode, software instructions, or programmable logic configuration data, and lacks one-time or multiple programmability. This circuit does not participate in the instruction execution flow of the system's main CPU, does not read or write the main CPU's internal registers, does not sample the main CPU's operating status parameters, does not receive control instructions and status feedback signals from the main CPU, and does not interact with the main CPU. The CPU and upper-level system software do not interact with each other in any way, do not listen to any transmission content or status of the system bus, do not sample the status pins, enable pins, operating levels and control signals of any hardware modules other than its own circuits, and do not modify or interfere with the internal signal paths and native working logic of the original hardware modules. The circuit independently completes the switching of operating states, sleep triggering and wake-up triggering through its own internally preset fixed timing logic, and autonomously performs power supply on / off control, sleep control and wake-up control on the target hardware module. Its entire operation does not require any adaptation configuration, operation coordination or intervention from the original system, hardware driver or software program.

[0013] (III) Beneficial Effects Compared with the prior art, the present invention has the following significant advantages: 1. Completely independent operation with no system resource occupation: The control circuit of this invention is completely independent of the main CPU in four dimensions: physical, logical, timing, and clock. It does not participate in the execution of main CPU instructions, does not interact with the main CPU or system software, does not occupy any main system resources, and does not affect the normal operation of the main system. Even if the main system crashes or the load is too high, it can still stably perform energy-saving control, and the reliability reaches industrial-grade standards.

[0014] 2. Purely fixed hardware logic, eliminating security risks at the source: This invention is implemented using only non-programmable fixed hardware combination logic and timing logic, without any firmware, microcode, or software instructions, and has no programmability. This eliminates the security risks of firmware vulnerabilities and malicious tampering at the source. The control logic is fixed at the factory, with extremely high operational stability and a service life consistent with the hardware itself.

[0015] 3. No external signal dependence and strong anti-interference capability: This invention does not monitor the system bus or sample the status pins, enable pins, working levels and control signals of any external hardware. It completes all control operations only through its own internally preset fixed timing logic. It is completely unaffected by external signal interference, the control logic is extremely simple, the failure rate is extremely low, and it can be applied to complex industrial environments such as strong electromagnetic interference and high dust.

[0016] 4. Plug and play, no additional adaptation development required: This invention does not require modification of the original hardware signal path and native working logic, and does not require any adaptation configuration or operation coordination from the original system, driver or software. It can be directly connected in series in the power supply circuit of the target hardware module. No additional development is required. It is compatible with all mainstream hardware platforms and has low cost for large-scale application.

[0017] 5. Precise hardware-level control and excellent energy efficiency: This invention cuts off the power supply circuit of idle modules by targeting power off at the hardware level and cuts off the leakage current path of hibernation modules by locking off leakage current at the hardware level. This can significantly reduce the standby power consumption of idle hardware and achieve energy efficiency that is superior to existing software energy-saving solutions and conventional hardware energy-saving solutions. Attached Figure Description

[0018] Figure 1 This is a schematic diagram of the system architecture of the hardware energy-saving control circuit described in an embodiment of the present invention; Figure 2 This is a schematic flowchart of the hardware energy-saving control method described in an embodiment of the present invention. Detailed Implementation

[0019] The present invention will now be described in further detail and in complete detail with reference to the accompanying drawings and specific embodiments. The specific embodiments described herein are for illustrative purposes only and are not intended to limit the scope of protection of the present invention. Example

[0020] This embodiment provides a hardware energy-saving control circuit, the system architecture of which is as follows: Figure 1 As shown, this is applied to an X86 / ARM architecture computer system. The system includes a main CPU, a system bus, and multiple target hardware modules (in this embodiment, a hard disk module, a USB peripheral module, and a PCIe expansion module). The hardware energy-saving control circuit is connected in series in the power supply circuit of each target hardware module and has no electrical connection with the signal pins of the main CPU, the system bus, or the target hardware modules.

[0021] The hardware energy-saving control circuit specifically includes: an independent clock module, a fixed timing logic core module, a power supply switch array, and a leakage current lockout module. All modules are implemented using non-programmable fixed hardware circuits, without any programmable devices.

[0022] The independent clock module uses an independent 32.768kHz passive crystal oscillator as a dedicated clock source to provide a stable clock signal for the fixed timing logic core module. Its timing output is completely isolated from the clock system of the main CPU and has no synchronization relationship, ensuring that the circuit timing control is completely independent of the main system.

[0023] The fixed timing logic core module is implemented only by fixed hardware combinational logic and timing logic circuits consisting of gate circuits, D flip-flops, and hardware timers. It does not contain any executable firmware, microcode, software instructions, or programmable logic configuration data, and does not have the ability to be programmed once or multiple times. The module has preset fixed timing control logic, including idle determination timing, sleep trigger timing, and wake-up trigger timing. All logic is fixed at the factory and cannot be modified in any way.

[0024] The power supply switch array is a hardware switch array composed of N-channel MOSFETs. Each switch corresponds to a power supply circuit of a target hardware module. The control terminal of the switch is only connected to the output pin of the fixed timing logic core module and is independently controlled by the fixed timing logic core module without any other control signal input.

[0025] The leakage current blocking module uses a hardware blocking switch connected in series in the power supply circuit of the target hardware module. It is linked with the power supply switch array. When the power supply switch cuts off the power supply circuit, it simultaneously blocks the power supply circuit, completely cutting off the leakage current path of the target hardware module.

[0026] In this embodiment, the hardware energy-saving control circuit meets all of the following conditions throughout its operation: - It does not participate in the instruction execution process of the main CPU, does not read or write the internal registers of the main CPU, does not sample the operating status parameters of the main CPU, does not receive control instructions and status feedback signals from the main CPU, and does not interact with the main CPU or the upper-level software of the system in any way. - It does not listen to any transmission content or status of the system bus, nor does it sample the status pins, enable pins, operating levels, and control signals of any hardware modules in the system other than its own circuitry; - Without modifying or interfering with the internal signal paths and native working logic of the original hardware module, the native working logic of the target hardware module is completely unaffected, with only the power supply circuit being controlled by the circuit. - The entire process requires no adaptation, configuration, coordination or intervention from the original system, hardware drivers or software programs. It runs automatically according to the preset fixed timing logic after power-on. Example

[0027] This embodiment provides a hardware energy-saving control method, implemented based on the hardware energy-saving control circuit described in Embodiment 1, the process of which is as follows: Figure 2As shown, the specific steps include: S1. Power-on initialization: After the hardware energy-saving control circuit is powered on, the fixed timing logic core module completes initialization through the clock signal provided by the independent clock module, all power supply switch arrays are closed, all target hardware modules are powered normally, and the circuit enters normal operation state; S2. Idle State Determination: The fixed-sequence logic core module executes cumulative timing through a hardware timer according to the internally preset fixed sequence. When the time reaches the preset idle threshold, the target hardware module is determined to be in an idle state, triggering a sleep operation. In this step, the idle threshold is a preset fixed duration, and no external signal input is required for determination. S3. Hardware-level targeted power-off: The fixed-timing logic core module outputs a control signal to control the power supply switch array of the corresponding target hardware module to disconnect, cut off the power supply circuit of the module, stop the power supply to the idle module, and reduce ineffective power consumption; S4. Hardware-level leakage current lockout: When the power supply switch array is disconnected, the leakage current lockout module simultaneously locks out the power supply circuit, cuts off the leakage current path of the target hardware module, and significantly reduces the standby power consumption of the module. S5. Wake-up condition monitoring: The fixed timing logic core module monitors the wake-up trigger condition through a hardware timer according to the internally preset fixed timing. The wake-up trigger condition is a preset fixed sleep duration, which does not require any external signal input. S6. Hardware wake-up control: When the preset wake-up trigger conditions are met, the fixed timing logic core module outputs a control signal, first controlling the leakage current lockout module to unlock, then controlling the power supply switch array to close, restoring the power supply to the target hardware module, completing the hardware wake-up, and the circuit returns to normal operation.

[0028] In this embodiment, all steps are completed independently by the fixed timing logic of the hardware energy-saving control circuit itself, without any signal interaction with the system's main CPU, system software, or other hardware modules, and without any external control or coordination.

[0029] Example 3: Modular Intelligent Computing Center Data Center Scenario Application This embodiment provides a hardware energy-saving control circuit adapted to prefabricated modular intelligent computing rooms. It is applied to standard modular data center rack units. Each rack unit is an independent prefabricated module, which integrates multiple AI training GPU servers, a rack-top switch, a distributed storage module, and a matching heat dissipation unit. The hardware energy-saving control circuit is a rack-level modular design, which is fully compatible with the modular architecture of the rack unit. It can be directly prefabricated and integrated into the rack power supply bus, without the need to modify the original architecture of the data center.

[0030] The core modules of the hardware energy-saving control circuit are completely identical to those in Embodiment 1, including an independent clock module, a fixed timing logic core module, an expandable branch power supply switch array, and a leakage current lockout module. All modules are implemented using non-programmable fixed hardware combination logic and timing logic circuits, without any executable firmware, microcode, software instructions, or programmable logic configuration data, and do not have the capability for one-time or multiple programmability. The expandable branch power supply switch array can flexibly expand the number of channels according to the number of devices in the rack, matching the flexible deployment requirements of modular data centers.

[0031] The hardware energy-saving control circuit is connected in series at the front end of the single-card power supply circuit of each GPU server, the power supply circuit of the idle port of the switch, and the power supply circuit of the hard disk of the storage module in the rack. It has no electrical connection with any signal links of the GPU server main CPU, BMC management chip, rack top switch control system, and data center environmental monitoring system. It only controls the power supply circuit of the target hardware module and does not modify or interfere with the original hardware signal path and native working logic.

[0032] In this embodiment, the hardware energy-saving control circuit adopts an independent industrial-grade dedicated clock source. Its timing control logic is completely isolated from the clock system of the server's main CPU and the computer room's environmental control system, and has no synchronization association. The circuit has a fixed preset timing control logic, including multi-level idle time thresholds adapted to intelligent computing scenarios, hierarchical sleep timing, and periodic wake-up timing. All logic is fixed at the factory and cannot be modified in any way.

[0033] In this embodiment, the circuit operates under all of the following conditions throughout its entire operation: - It does not participate in the instruction execution process of the server's main CPU, does not read or write the internal registers of the main CPU and BMC chip, does not sample server operating status parameters, does not receive any control instructions or status feedback signals from the main CPU, BMC, and environmental system, and does not interact with any management system or upper-level software in any way. - It does not listen to any transmission content or status of the system bus, PCIe bus, or management bus, and does not sample any status pins, enable pins, operating levels, or control signals of the GPU card, switch, or storage module; - The entire process requires no server system, data center environmental system, or hardware driver to provide any adaptation configuration, operation coordination, or intervention. After the rack is powered on, the circuit automatically runs independently according to the preset fixed timing logic. Even if the server crashes, the BMC fails, or the environmental system is disconnected from the network, it can still stably perform energy-saving control.

[0034] This embodiment enables precise power consumption control of idle hardware in intelligent computing rooms without the need to modify existing hardware and management systems. It is plug-and-play and compatible with modular data center and server equipment from all brands, significantly reducing idle standby power consumption and operating electricity costs of intelligent computing centers.

[0035] Example 4: Application of dual-path scenarios in smartphones This embodiment provides a miniaturized hardware energy-saving control circuit adapted to the dual-path architecture of smartphones, applied to 5G / 6G smartphones. The smartphone hardware is divided into a main path (application processor AP, baseband RF module, memory, flash memory) and a secondary path (peripheral sensor module, secondary RF module, USB interface module, camera auxiliary module, secondary screen display module). The hardware energy-saving control circuit adopts a miniaturized semiconductor integrated design and can be directly integrated on the phone's power management PCB board, occupying a very small area and not affecting the phone's internal stacking architecture.

[0036] The core modules of the hardware energy-saving control circuit include an independent low-power clock module, a fixed timing logic core module, a dual-path shunt power supply switch array, and a leakage current latch-up module. All modules are implemented using non-programmable fixed hardware gate circuits, D flip-flops, and low-power hardware timers. They do not contain any executable firmware, microcode, software instructions, or programmable logic configuration data, and do not have the capability to be programmed once or multiple times.

[0037] The hardware energy-saving control circuit is connected in series on the independent power supply circuit of each module in the secondary channel of the mobile phone. It has no electrical connection with any signal links of the main AP, baseband chip, and operating system kernel of the mobile phone. It only controls the power supply circuit of the target hardware module in the secondary channel. It does not modify or interfere with the signal path and original working logic of the main channel of the mobile phone, and does not affect the normal operation of core functions such as mobile phone calls and emergency calls.

[0038] In this embodiment, the hardware energy-saving control circuit uses an independent 32kHz low-power passive crystal oscillator as a dedicated clock source. Its timing control logic is completely isolated from the clock system of the mobile phone's main AP and has no synchronization relationship. The circuit has a fixed preset timing control logic, including standby idle threshold, hierarchical sleep timing, and periodic wake-up timing adapted to mobile phone scenarios. All logic is fixed at the factory and cannot be modified in any way.

[0039] In this embodiment, the circuit operates under all of the following conditions throughout its entire operation: - It does not participate in the instruction execution process of the main AP, does not read or write the internal registers of the main AP, does not sample the operating status parameters of the main AP, does not receive any control instructions or status feedback signals from the main AP, and does not interact with the mobile operating system or drivers in any way. - It does not listen to any transmission content or transmission status of the mobile phone system bus, nor does it sample any status pins, enable pins, operating levels and control signals of each module in the secondary path; - The entire process requires no adaptation, configuration, coordination or intervention from the mobile phone operating system or hardware drivers. After the mobile phone is powered on, the circuit automatically runs independently according to the preset fixed timing logic. Even if the mobile phone operating system crashes or freezes, it can still stably perform energy-saving control without affecting the core functions of the mobile phone.

[0040] This embodiment can significantly reduce the ineffective power consumption of the secondary path module in the standby state of the mobile phone, extend the battery life of the mobile phone, and does not need to be adapted to different brands and versions of mobile phone operating systems. It has extremely strong compatibility and can be adapted to all mainstream smartphone architectures.

[0041] It should be noted that the above embodiments are merely preferred embodiments of the present invention and are not intended to limit the scope of protection of the present invention. Any equivalent substitutions, modifications, or simplifications made within the core technical concept and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A hardware energy-saving control method, characterized in that, The system employs a hardware energy-saving control circuit to manage the power consumption of target hardware modules. The physical topology, logic operations, timing control, and clock source of this hardware energy-saving control circuit are independent of the system's main CPU. It is implemented solely by non-programmable fixed hardware combinational logic and sequential logic circuits, containing no executable firmware, microcode, software instructions, or programmable logic configuration data, and lacks one-time or multiple programmability. This hardware energy-saving control circuit does not participate in the main CPU's instruction execution flow, does not read or write to the main CPU's internal registers, does not sample the main CPU's operating status parameters, does not receive control instructions or status feedback signals from the main CPU, and does not interact with the main CPU. The upper-layer software of the system does not engage in any data or instruction interaction, does not listen to any transmission content or status of the system bus, does not sample the status pins, enable pins, operating levels and control signals of any hardware modules other than its own circuits, and does not modify or interfere with the internal signal paths and native working logic of the original hardware modules; the hardware energy-saving control circuit independently completes the switching of operating states, sleep triggering and wake-up triggering only through its own internally preset fixed timing logic, and autonomously performs power supply on / off control, sleep control and wake-up control on the target hardware module. Its entire operation does not require any adaptation configuration, operation coordination or intervention from the original system, hardware driver or software program.

2. The hardware energy-saving control method according to claim 1, characterized in that, When the hardware energy-saving control circuit determines that the target hardware module is in an idle state, it performs a hardware-level targeted power-off operation on the module, cutting off its power supply circuit to reduce ineffective power consumption.

3. The hardware energy-saving control method according to claim 1, characterized in that, The hardware energy-saving control circuit uses an independent dedicated clock source, and its timing control logic is completely isolated from the clock system of the main CPU and has no synchronization relationship.

4. The hardware energy-saving control method according to claim 1, characterized in that, The hardware energy-saving control circuit performs a hardware-level leakage current lockout operation on the target hardware module in a power-off sleep state, cutting off the leakage current path of the module through a hardware switch to reduce standby power consumption.

5. The hardware energy-saving control method according to claim 1, characterized in that, The hardware energy-saving control circuit monitors the wake-up trigger conditions solely through its internally preset fixed timing logic, and completes the wake-up operation of the target hardware module without any signal interaction with any other modules in the system.

6. A hardware energy-saving control circuit, characterized in that, The circuit described is a dedicated circuit for executing the hardware energy-saving control method according to any one of claims 1 to 5; the physical topology, logic operations, timing control, and clock source of the circuit are all independent of the system's main CPU, and are implemented only by non-programmable fixed hardware combinational logic and timing logic circuits, without any executable firmware, microcode, software instructions, or programmable logic configuration data, and do not have the capability of one-time or multiple programmability; the circuit does not participate in the instruction execution flow of the system's main CPU, does not read or write the main CPU's internal registers, does not sample the main CPU's operating status parameters, does not receive the main CPU's control instructions and status feedback signals, and does not interact with the main CPU and The upper-layer software of the system does not engage in any data or instruction interaction, does not listen to any transmission content or status of the system bus, does not sample the status pins, enable pins, operating levels and control signals of any hardware modules other than its own circuits, and does not modify or interfere with the internal signal paths and native working logic of the original hardware modules. The circuit independently completes the switching of operating states, sleep triggering and wake-up triggering only through its own internally preset fixed timing logic, and autonomously performs power supply on / off control, sleep control and wake-up control on the target hardware module. Its entire operation does not require any adaptation configuration, operation coordination or intervention from the original system, hardware driver or software program.

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