A processor clock gating control system and electronic device

Abstract

This invention proposes a processor clock gating control system and electronic device. After detecting a first type of low-power state indication signal from the processor, if the control module does not detect a second type of low-power state indication signal within a buffer time window, and if the processor does not receive a valid interrupt request within the buffer time window, it sends a clock shutdown signal to the clock gating unit. The first type of low-power state indication signal indicates that the processor has entered a low-power state, and the second type of low-power state indication signal indicates that the processor has exited a low-power state. Upon receiving the clock shutdown signal, the clock gating unit shuts down the processor clock. By not immediately shutting down the processor clock after detecting the first type of low-power state indication signal, a buffer time is provided for potentially imminent interrupts, avoiding interrupt response delays caused by immediate gating and the additional power consumption caused by frequent gating toggles.

Description

Technical Field

[0001] This invention relates to the field of chips, and more specifically, to a processor clock gating control system and electronic device. Background Technology

[0002] As an open instruction set architecture, RISC-V has been widely adopted in low-power applications such as the Internet of Things (IoT) and edge computing due to its simple and modular design. To reduce power consumption, RISC-V processors typically support the WFI (Wait for Interrupt) instruction. When the processor executes WFI, it enters a low-power mode, suspends the instruction pipeline, and waits for an interrupt to wake it up. In low-power mode, gating the processor clock is an effective way to reduce dynamic power consumption.

[0003] In existing technologies, a common clock gating strategy is to immediately shut down the processor clock after detecting that the processor has executed a WFI instruction. While immediately shutting down the clock can quickly reduce power consumption, it can lead to increased interrupt response delays if an interrupt is about to arrive before the clock is shut down. Furthermore, frequent gating operations themselves also incur additional power consumption overhead. Summary of the Invention

[0004] The purpose of this invention is to provide a processor clock gating control system and electronic device to improve the above-mentioned problems.

[0005] To achieve the above objectives, the technical solutions adopted in the embodiments of the present invention are as follows: In a first aspect, embodiments of the present invention provide a processor clock gating control system, the processor clock gating control system including a control module and a clock gating unit deployed on the clock input path of the processor, the control module being connected to the processor and the clock gating unit; The control module is used to send a clock shutdown signal to the clock gating unit after detecting that the processor outputs a first type of low power state indication signal. If the processor does not output a second type of low power state indication signal within the buffer time window, and the processor does not obtain a valid interrupt request within the buffer time window, the control module is used to send a clock shutdown signal to the clock gating unit. The first type of low-power state indication signal is used to indicate that the processor enters a low-power state, and the second type of low-power state indication signal is used to indicate that the processor exits a low-power state; The clock gating unit is used to turn off the processor clock after receiving a clock off signal.

[0006] Optionally, the control module includes a control unit, a monitoring unit, and a counter unit. The control unit is connected to the clock gating unit, the monitoring unit, and the counter unit, respectively. The monitoring unit is connected to the processor. The monitoring unit is used to forward a first type of low-power state indication signal to the control unit when it detects that the processor is outputting a low-power state indication signal. The control unit is used to send a start signal to the counter unit after receiving the first type of low power state indication signal; The counter unit is used to start counting after receiving a start signal, and to output a counter full indication signal to the control unit when the count value reaches a set threshold. The control unit is used to determine the end of the buffer time window upon receiving the counter full indication signal.

[0007] Alternatively, the monitoring unit may also be connected to the counter unit; The monitoring unit is used to send a start signal to the counter unit when it detects that the processor outputs a first type of low power state indication signal; The counter unit is used to start counting after receiving a start signal, and to output a counter full indication signal to the control unit when the count value reaches a set threshold. The control unit is used to determine the end of the buffer time window upon receiving the counter full indication signal.

[0008] Optionally, the monitoring unit is configured to forward a second type of low-power state indication signal to the control unit when it detects that the processor is outputting such a signal. The control unit is used to send a reset signal to the counter unit after receiving the second type of low power state indication signal.

[0009] Optionally, the control module further includes an interrupt monitoring unit, which is connected to the counter unit; The interrupt monitoring unit is used to send a reset trigger signal to the counter unit when it detects that the processor has obtained a valid interrupt request; The control unit is used to send a clock off signal to the clock gating unit when it receives the counter full indication signal.

[0010] Optionally, the processor is provided with one or more interrupt register groups, the interrupt register groups including interrupt pending registers and corresponding interrupt enable registers; The interrupt monitoring unit is connected to each interrupt register group; The interrupt monitoring unit is used to determine that the processor has obtained a valid interrupt request when both the interrupt pending register and the interrupt enable register in any interrupt register group are in a high state.

[0011] Optionally, the processor is provided with one or more of the following: machine mode interrupt register group, privileged mode interrupt register group, and user mode interrupt register group.

[0012] Optionally, the machine mode interrupt register group includes a machine mode interrupt enable register and a machine mode interrupt pending register; The privileged mode interrupt register group includes a privileged mode interrupt enable register and a privileged mode interrupt pending register; The user-mode interrupt register group includes a user-mode interrupt enable register and a user-mode interrupt suspend register.

[0013] Optionally, the count value in the counter unit increases with the processor clock, and when the counter value reaches a set threshold, a counter full indication signal is output to the control unit.

[0014] Secondly, embodiments of the present invention provide an electronic device including the processor clock gating control system described above.

[0015] Compared to existing technologies, the processor clock gating control system and electronic device provided in this invention, after the control module detects that the processor outputs a first type of low-power state indication signal, if it does not detect the processor outputting a second type of low-power state indication signal within a buffer time window, and detects that the processor has not acquired a valid interrupt request within the buffer time window, then it sends a clock shutdown signal to the clock gating unit. The first type of low-power state indication signal is used to indicate that the processor enters a low-power state, and the second type of low-power state indication signal is used to indicate that the processor exits a low-power state. After receiving the clock shutdown signal, the clock gating unit shuts down the processor clock. By not immediately shutting down the processor clock after detecting the first type of low-power state indication signal, a buffer time is provided for potentially imminent interrupts, avoiding interrupt response delays caused by immediate gating and the additional power consumption caused by frequent gating toggles.

[0016] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, preferred embodiments are described below in detail with reference to the accompanying drawings. Attached Figure Description

[0017] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the present invention and should not be regarded as a limitation on the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1This is one of the structural schematic diagrams of a processor clock gating control system provided in an embodiment of the invention.

[0019] Figure 2 The second schematic diagram of the processor clock gating control system provided for the embodiments of the invention.

[0020] Figure 3 The third schematic diagram of the processor clock gating control system provided for the embodiments of the invention. Detailed Implementation

[0021] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. The components of the embodiments of the present invention described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0022] Therefore, the following detailed description of the embodiments of the invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the invention without inventive effort are within the scope of protection of the invention.

[0023] It should be noted that similar reference numerals and letters in the following figures indicate similar items; therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures. Furthermore, in the description of this invention, terms such as "first," "second," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0024] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0025] In the description of this invention, it should be noted that the terms "upper," "lower," "inner," "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship in which the product of this invention is usually placed when in use. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limiting this invention.

[0026] In the description of this invention, it should also be noted that, unless otherwise explicitly specified and limited, the terms "set" and "connection" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances.

[0027] The following detailed description of some embodiments of the present invention is provided in conjunction with the accompanying drawings. Unless otherwise specified, the following embodiments and features can be combined with each other.

[0028] The current interrupt wake-up mechanism is imperfect: traditional solutions often only monitor external interrupt pins or simple interrupt flags, failing to combine the interrupt enable status (such as the mie and sie registers) and interrupt pending status (such as the mip and sip registers) inside the RISC-V processor for comprehensive judgment, which may lead to false wake-ups or interrupt loss.

[0029] This invention provides a processor clock gating control system, please refer to... Figure 1 , Figure 1 This is one of the structural schematic diagrams of a processor clock gating control system provided in an embodiment of the present invention. The processor clock gating control system includes a control module and a clock gating unit deployed on the clock input path of the processor. The control module is connected to the processor and the clock gating unit.

[0030] When the clock gating unit is turned on, it can transmit the clock signal to the processor. When the clock gating unit is turned off, it stops transmitting the clock signal to the processor. In this embodiment of the invention, the processor may be, but is not limited to, a RISC-V processor, and may be, but is not limited to, a central processing unit (CPU).

[0031] The control module, upon detecting that the processor outputs a first-type low-power state indication signal, and if it does not detect the processor output a second-type low-power state indication signal within the buffer time window, and detects that the processor has not acquired a valid interrupt request within the buffer time window, sends a clock shutdown signal to the clock gating unit. When the clock shutdown signal is high, the clock enable signal is low; when the clock shutdown signal is low, the clock enable signal is high.

[0032] It should be understood that once the processor enters a low-power state, any sudden interrupt request will usually occur within the buffer time window. After the buffer time window, the likelihood of a valid interrupt request occurring again is relatively low.

[0033] The first type of low-power state indicator signal is used to indicate that the processor enters a low-power state, and the second type of low-power state indicator signal is used to indicate that the processor exits a low-power state; when the first type of low-power state indicator signal is high, the second type of low-power state indicator signal is low; when the first type of low-power state indicator signal is low, the second type of low-power state indicator signal is high.

[0034] The clock gating unit is used to turn off the processor clock upon receiving a clock off signal and to turn on the processor clock upon receiving a clock on signal.

[0035] In the processor clock gating control system provided in this embodiment of the invention, the processor clock is not immediately shut down after detecting a first type of low-power state indication signal. This provides a buffer time for potentially imminent interrupts, avoiding interrupt response delays caused by immediate gating and additional power consumption due to frequent gating toggles. The length of the buffer time window is configurable to adapt to different application scenarios.

[0036] Please refer to Figure 2 , Figure 2 This is a second schematic diagram of the processor clock gating control system provided in an embodiment of the present invention. The control module includes a control unit, a monitoring unit, and a counter unit. The control unit is connected to the clock gating unit, the monitoring unit, and the counter unit, respectively. The monitoring unit is connected to the processor.

[0037] The monitoring unit is used to forward a Type I low-power state indication signal to the control unit when it detects that the processor is outputting such a signal.

[0038] The control unit sends a start signal to the counter unit after receiving a first type of low-power state indication signal.

[0039] The counter unit is used to start counting after receiving a start signal, and outputs a counter full indication signal to the control unit when the count value reaches a set threshold. At this time, the count value of the counter unit may not change.

[0040] In one alternative implementation, the threshold setting of the counter unit can be configured as a static threshold, such as 10 or other numbers. This threshold setting is related to the duration of the buffer time window and can be set as needed.

[0041] In another alternative implementation, the set threshold of the counter unit supports dynamic threshold adjustment to achieve adaptive interrupt gating based on interrupt arrival time prediction.

[0042] Specifically, the control module also includes a gating control mode selection register, which can be configured to switch between static and dynamic thresholds.

[0043] When the gating control mode selection register is configured to dynamic threshold mode, the set threshold corresponding to different dynamic adjustment counter units is adjusted when a start signal is sent to the counter unit.

[0044] The specific process of the control unit adjusting the set threshold corresponding to the counter unit includes: obtaining the arrival time of the most recent N historical interrupt requests (the time when the interrupt suspension signal goes high), obtaining the interval between any two adjacent historical interrupt requests (the interval between the arrival time), obtaining the average value of all intervals, and adjusting the set threshold corresponding to the counter unit based on the average value.

[0045] A larger N will store more interrupt interval times, meaning it will occupy more storage space, but the prediction results will be more accurate. N can be set to 6, meaning the arrival time of the 7th interrupt is the average of the time intervals of the previous 6 interrupts. If the number of interrupts is less than N, the set threshold corresponding to the counter unit will be the static threshold. If a converted threshold t is obtained based on this average, and the converted threshold t is greater than or equal to the static threshold, then the set threshold corresponding to the counter unit will be adjusted to the static threshold. If the calculated converted threshold t is less than the static threshold, then the set threshold corresponding to the counter unit will be adjusted to be equal to t, thus avoiding an excessively long buffer time window.

[0046] Dynamic threshold control for sampling can avoid frequent wake-ups caused by turning on clock gating too early, or wasting power by turning off clock gating too late.

[0047] The control unit is used to determine the end of the buffer time window upon receiving a counter full indication signal.

[0048] Please continue to refer to this. Figure 2 Alternatively, the monitoring unit can also be connected to the counter unit, reducing the interface requirements for the control unit and lowering costs.

[0049] The monitoring unit is used to send a start signal to the counter unit when it detects that the processor outputs a first type of low power state indication signal.

[0050] The counter unit is used to start counting after receiving a start signal, and to output a counter full indication signal to the control unit when the count value reaches a set threshold. The control unit is used to determine the end of the buffer time window upon receiving a counter full indication signal.

[0051] Optionally, the monitoring unit is used to forward a Type II low-power state indication signal to the control unit when it detects that the processor is outputting such a signal.

[0052] The control unit sends a reset signal to the counter unit after receiving a Type II low-power state indication signal. The counter unit is then reset, and no full counter indication signal is output at this time.

[0053] In one alternative implementation, the monitoring unit is used to send a clear signal directly to the counter unit when it detects that the processor outputs a second type of low power state indication signal. At this time, it does not send a clock off signal to the clock gating unit, and the clock gating unit remains in the open state.

[0054] Please refer to Figure 3 , Figure 3 This is the third schematic diagram of the processor clock gating control system provided in an embodiment of the present invention. The control module also includes an interrupt monitoring unit, which is connected to the counter unit and the processor.

[0055] The interrupt monitoring unit is used to send a reset trigger signal to the counter unit when it detects that the processor has acquired a valid interrupt request.

[0056] The control unit sends a clock off signal to the clock gating unit when it receives a counter full indication signal.

[0057] The control unit receives a counter full indication signal, indicating that no second type low power state indication signal was detected from the processor within the buffer time window, and that the processor did not obtain a valid interrupt request within the buffer time window.

[0058] In one alternative implementation, the processor is provided with one or more interrupt register groups, which include interrupt pending registers and corresponding interrupt enable registers.

[0059] The interrupt monitoring unit is connected to each interrupt register group.

[0060] The interrupt monitoring unit is used to determine that the processor has acquired a valid interrupt request when both the interrupt pending register and the interrupt enable register in any interrupt register group are in the high state.

[0061] By combining interrupt suspension and enable registers (in the RISC-V privileged architecture), the CPU is ensured to be woken up only by interrupts that truly require CPU processing. This avoids unnecessary wake-ups caused by false interrupts (such as disabled interrupt suspensions), further reducing power consumption.

[0062] Optionally, the processor may be provided with one or more of the following: machine mode interrupt register group, privileged mode interrupt register group, and user mode interrupt register group.

[0063] Optionally, the machine mode interrupt register set includes a machine mode interrupt enable (MIE) register and a machine mode interrupt pending (MIP) register; The privileged mode interrupt register group includes the privileged mode interrupt enable (SIE) register and the privileged mode interrupt pending (SIE) register; The user-mode interrupt register group includes the User Interrupt Enable (UIE) register and the User Interrupt Suspend (UIE) register.

[0064] In one optional implementation, the interrupt monitoring unit is connected to the meip, msip, seip, ssip, ueip, and usip signals (meip in machine mode, msip in software interrupt suspension; seip in privileged mode, ssip in software interrupt suspension; ueip in user mode, usip in software interrupt suspension) output from the platform level interrupt controller (PLIC) to the processor. The interrupt monitoring unit is also connected to the interrupt enable register within the processor.

[0065] This connection method enables predictive wake-up of the interrupt controller. Firstly, regarding interrupts, in the RISC-V architecture, all external interrupts sent to the processor will first enter the interrupt controller module for integration and filtering. If the user has enabled the corresponding interrupt number and the priority meets the threshold, the interrupt controller will raise the corresponding interrupt suspension signal and send the interrupt number to the processor. After receiving the information from the interrupt controller, the processor will combine the status of its internal MIE (external interrupt enable register in machine mode), MSIE (software interrupt enable register in machine mode), SEIE (external interrupt enable register in privileged mode), SIE (software interrupt enable register in privileged mode), UEIE (external interrupt enable register in user mode), and USIE (software interrupt enable register in user mode) to determine whether to accept the interrupt and enter the interrupt function. MIE, MSIE, SEIE, SIE, UEIE, and USIE all belong to the processor's internal interrupt enable registers (MIE).

[0066] A valid interrupt request is determined when both the interrupt suspend signal and the corresponding interrupt enable register are high. For example, in machine mode, a valid interrupt request is determined when both the external interrupt suspend signal meip and the external interrupt enable register meie (in the processor in machine mode) are high.

[0067] If the processor accepts the interrupt, then the processor's internal interrupt pending register will be enabled. In other words, if the interrupt controller sends an interrupt pending signal to the processor, and the corresponding internal interrupt enabling register is enabled, it means the interrupt will be received by the processor, which implies the processor will be woken up (if the processor is in a low-power state at this time). The difference between monitoring the interrupt pending signal output by the interrupt controller and monitoring the processor's internal interrupt pending register is that the interrupt pending signal output by the interrupt controller must be activated earlier than the processor's internal interrupt pending register. This means this module can predict whether the processor needs to be woken up earlier, de-gated the clock earlier, and prepare to enter the interrupt function earlier.

[0068] It should be noted that this is a predictive wake-up. For example, after receiving the MEIP from the interrupt controller, the processor checks its own MEIE. If the MEIE is 1, the interrupt is considered valid. In this embodiment of the invention, the interrupt monitoring unit preemptively determines whether the interrupt is valid, without waiting for the processor to make the judgment. The interrupt monitoring unit completes the determination of the interrupt's validity before the interrupt controller's MEIP is even sent to the processor. This allows the processor to de-gated the clock earlier, preparing to enter the interrupt function.

[0069] Optionally, the count value in the counter unit increments with the processor clock, and when the counter value reaches a set threshold (e.g., 10 cycles), a counter full indication signal is output to the control unit.

[0070] This invention also provides a system-on-a-chip (SoC) including the processor clock gating control system described above.

[0071] This invention also provides an electronic device, including the above-described system-on-a-chip or processor clock gating control system.

[0072] In summary, the processor clock gating control system and electronic device provided by this invention, after the control module detects that the processor outputs a first type of low-power state indication signal, if it does not detect the processor outputting a second type of low-power state indication signal within a buffer time window, and detects that the processor has not acquired a valid interrupt request within the buffer time window, then it sends a clock shutdown signal to the clock gating unit. The first type of low-power state indication signal is used to indicate that the processor enters a low-power state, and the second type of low-power state indication signal is used to indicate that the processor exits a low-power state. After receiving the clock shutdown signal, the clock gating unit shuts down the processor clock. By not immediately shutting down the processor clock after detecting the first type of low-power state indication signal, a buffer time is provided for potentially imminent interrupts, avoiding interrupt response delays caused by immediate gating and the additional power consumption caused by frequent gating toggles.

[0073] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

[0074] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above, and that the invention can be implemented in other specific forms without departing from its spirit or essential characteristics. Therefore, the embodiments should be considered in all respects as exemplary and non-limiting, and the scope of the invention is defined by the appended claims rather than the foregoing description. Thus, all variations falling within the meaning and scope of equivalents of the claims are intended to be included within the present invention. No reference numerals in the claims should be construed as limiting the scope of the claims.

Claims

1. A processor clock gating control system, characterized in that, The processor clock gating control system includes a control module and a clock gating unit deployed on the clock input path of the processor. The control module is connected to the processor and the clock gating unit. The control module is used to send a clock shutdown signal to the clock gating unit after detecting that the processor outputs a first type of low power state indication signal. If the processor does not output a second type of low power state indication signal within the buffer time window, and the processor does not obtain a valid interrupt request within the buffer time window, the control module is used to send a clock shutdown signal to the clock gating unit. The first type of low-power state indication signal is used to indicate that the processor enters a low-power state, and the second type of low-power state indication signal is used to indicate that the processor exits a low-power state; The clock gating unit is used to turn off the processor clock after receiving a clock off signal.

2. The processor clock gating control system as described in claim 1, characterized in that, The control module includes a control unit, a monitoring unit, and a counter unit. The control unit is connected to the clock gating unit, the monitoring unit, and the counter unit, respectively. The monitoring unit is connected to the processor. The monitoring unit is used to forward a first type of low-power state indication signal to the control unit when it detects that the processor is outputting a first type of low-power state indication signal. The control unit is used to send a start signal to the counter unit after receiving the first type of low power state indication signal; The counter unit is used to start counting after receiving a start signal, and to output a counter full indication signal to the control unit when the count value reaches a set threshold. The control unit is used to determine the end of the buffer time window upon receiving the counter full indication signal.

3. The processor clock gating control system as described in claim 2, characterized in that, Alternatively, the monitoring unit may also be connected to the counter unit; The monitoring unit is used to send a start signal to the counter unit when it detects that the processor outputs a first type of low power state indication signal; The counter unit is used to start counting after receiving a start signal, and to output a counter full indication signal to the control unit when the count value reaches a set threshold. The control unit is used to determine the end of the buffer time window upon receiving the counter full indication signal.

4. The processor clock gating control system as described in claim 2 or 3, characterized in that, The monitoring unit is used to forward a second type of low-power state indication signal to the control unit when it detects that the processor is outputting a second type of low-power state indication signal. The control unit is used to send a reset signal to the counter unit after receiving the second type of low power state indication signal.

5. The processor clock gating control system as described in claim 4, characterized in that, The control module further includes an interrupt monitoring unit, which is connected to the counter unit; The interrupt monitoring unit is used to send a reset trigger signal to the counter unit when it detects that the processor has obtained a valid interrupt request; The control unit is used to send a clock off signal to the clock gating unit when it receives the counter full indication signal.

6. The processor clock gating control system as described in claim 5, characterized in that, The processor is provided with one or more interrupt register groups, the interrupt register groups including interrupt pending registers and corresponding interrupt enable registers; The interrupt monitoring unit is connected to each interrupt register group; The interrupt monitoring unit is used to determine that the processor has obtained a valid interrupt request when both the interrupt pending register and the interrupt enable register in any interrupt register group are in a high state.

7. The processor clock gating control system as described in claim 6, characterized in that, The processor is provided with one or more of the following: machine mode interrupt register group, privileged mode interrupt register group, and user mode interrupt register group.

8. The processor clock gating control system as described in claim 7, characterized in that, The machine mode interrupt register group includes a machine mode interrupt enable register and a machine mode interrupt pending register. The privileged mode interrupt register group includes a privileged mode interrupt enable register and a privileged mode interrupt pending register; The user-mode interrupt register group includes a user-mode interrupt enable register and a user-mode interrupt pending register.

9. The processor clock gating control system as described in claim 2 or 3, characterized in that, The counter value in the counter unit increases as the processor clock flips. When the counter value reaches a set threshold, it outputs a counter full indication signal to the control unit.

10. An electronic device, characterized in that, The processor clock gating control system includes any one of claims 1-9.

Images