A power consumption control method for a low-power multimedia visual processing integrated circuit

Abstract

This invention relates to the field of industrial real-time control software technology, and more particularly to a power consumption control method for a low-power multimedia vision processing integrated circuit. The method includes: extracting visual request features and assigning priorities through a task parsing unit; using sensors to collect real-time load and thermal status data of heterogeneous computing units; inputting the features and status data into a deep reinforcement learning model to predict and output voltage step commands and frequency adjustment ratios for each unit; driving a power management unit and a clock generation unit to perform multi-level gated collaborative control; and establishing a feedback mechanism between visual processing accuracy and power consumption. This invention achieves fine-grained resource scheduling, significantly reducing integrated circuit power consumption while effectively ensuring industrial-grade stability for critical control tasks.

Description

Technical Field

[0001] This invention relates to the field of industrial real-time control software technology, and in particular to a power consumption control method for a low-power multimedia vision processing integrated circuit. Background Technology

[0002] With the rapid development of industrial automation and intelligent manufacturing technologies, multimedia vision processing integrated circuits are increasingly widely used in the field of industrial real-time control. As a core component of industrial vision systems, these integrated circuits are responsible for real-time acquisition, preprocessing, and feature extraction of high-resolution image streams, thereby providing accurate decision support for automated production lines. Low-power control technology is the core guarantee for the continuous operation of multimedia vision processing integrated circuits in industrial environments.

[0003] Traditional power management methods typically employ fixed frequency regulation or simple voltage shutdown strategies, which are ill-suited to the highly dynamic vision processing demands of industrial environments. Furthermore, existing technologies, when processing high-concurrency, non-linear vision data streams, often suffer from unnecessary energy consumption due to a lack of deep understanding of task priorities, and may even lead to chip overheating and performance throttling.

[0004] In addition, traditional control logic cannot achieve fine-grained power consumption allocation under multi-core heterogeneous architecture, which can easily lead to delays in the execution of critical control instructions and fail to meet the extreme pursuit of low latency in industrial real-time control software. Summary of the Invention

[0005] The purpose of this invention is to provide a power consumption control method for a low-power multimedia visual processing integrated circuit, so as to effectively solve the technical problems in the background art.

[0006] This invention provides a power consumption control method for a low-power multimedia visual processing integrated circuit, comprising: S1. Through the task parsing unit inside the integrated circuit, the sequence of vision processing requests issued by the industrial real-time control software is obtained in real time, and feature parameters including image resolution, color depth, target detection accuracy requirements and task deadline are extracted. Priority coefficients are assigned to each task according to the urgency of the control instructions. S2. Utilize multiple hardware monitoring sensors distributed inside the chip to collect in real time the utilization rate, current operating frequency, operating voltage, and core temperature of the central processing unit, graphics processing unit, neural network processing unit, and digital signal processing unit, and summarize them to generate a multi-dimensional feature vector reflecting the current hardware load and thermal state. S3. Input the feature parameters and the feature vector into the deep reinforcement learning model in the low-power management core of the system-on-a-chip, perform nonlinear mapping through the multi-layer fully connected neural network inside the model, calculate and output the voltage step command and frequency adjustment ratio for different heterogeneous computing units; S4. Based on the voltage step command and frequency adjustment ratio, drive the power management unit to perform voltage adjustment or shutdown operations on multiple independent power domains, and synchronously control the clock generation unit to adjust the clock enable signals of each functional module. S5. Monitor the execution time and output accuracy of the vision algorithm in real time to determine whether it meets the real-time threshold preset by the industrial real-time control software. If the current power consumption state causes the processing delay to exceed the threshold, trigger an emergency frequency boost response, readjust the power allocation strategy, and establish a closed-loop feedback mechanism.

[0007] In some embodiments, in S1, the extraction of feature parameters and allocation of priority coefficients through the task parsing unit inside the integrated circuit includes: The command stream sniffing module in the task parsing unit is used to intercept the sequence of vision processing requests issued by the industrial real-time control software. The visual processing request sequence is stored in a first-in-first-out circular buffer of a preset capacity, wherein each request includes a task descriptor; the task descriptor is parsed to extract image resolutions covering various industrial camera output specifications, color depths of various preset bit depths, target detection accuracy requirements, and task deadlines within a preset response time range. The task type-based priority weighting algorithm sets control commands involving safe shutdown and emergency obstacle avoidance as the first priority, tasks involving product surface defect detection as the second priority, and tasks involving logistics statistics and counting as the third priority. Priority coefficients within a preset value range are assigned to tasks of different priorities.

[0008] In some embodiments, in S2, the core temperature monitoring point of the central processing unit is located between the arithmetic logic unit and the floating-point operation unit; the operating voltage of the graphics processing unit is adjusted in preset voltage steps within a preset operating voltage range; the neural network processing unit consists of multiple independent computing clusters, each computing cluster integrating multiple multiply-accumulate units, and dynamically activating an appropriate number of computing clusters according to the complexity of the image; the digital signal processing unit integrates a high-speed static random access memory of a predetermined capacity as a data buffer, reducing the total power consumption of the system by reducing the number of accesses to off-chip memory; the collected data is aggregated to generate a multi-dimensional feature vector reflecting the current hardware load and thermal state, the multi-dimensional feature vector including the instantaneous power consumption estimate, cache hit rate, and bus occupancy rate of each computing unit.

[0009] In some embodiments, in S3, feature parameters and feature vectors are concatenated to form a global state vector, which is then input into a deep reinforcement learning model in the low-power management core. The deep reinforcement learning model adopts an actor-critic architecture, with its hidden layers having a multi-layer structure and each layer containing a preset number of neurons. A linear rectified function is used as the activation function, and the output layer generates an action probability distribution for each computing unit through a flexible maximum function. The reward function of the deep reinforcement learning model is composed of a weighted average of the power consumption reduction rate, the task timeliness rate, and the algorithm accuracy loss, and power consumption control is optimized by maximizing the cumulative reward value.

[0010] In some embodiments, in S4, a power management unit employing a high-frequency switching regulator architecture is used to perform voltage regulation, shutdown, or buck operations on multiple independent power domains according to voltage step instructions. By inserting automatic clock gating units at the root and branches of the clock tree in the register transfer stage, when a specific functional module is detected to have no valid data input for a consecutive preset number of clock cycles, the clock supply to that module is automatically cut off to eliminate invalid switching power consumption. According to the real-time requirements of data exchange bandwidth, the on-chip bus frequency is dynamically adjusted and switched between multiple preset frequency points to match the data throughput rate between different computing units. The power management unit supports multiple independent controlled outputs and ensures that the voltage ripple of each output is within a preset ripple threshold, and that the time delay from receiving the instruction to completing voltage stabilization is within a predetermined switching time range.

[0011] In some embodiments, in S5, the execution time of the vision algorithm is measured by a high-precision timer inside the integrated circuit, and the output accuracy is calculated by the confidence evaluation module of the neural network processing unit. The execution time is compared with the real-time threshold of the corresponding industrial bus protocol cycle. When the processing delay is detected to exceed the real-time threshold, the low-power management core sends the highest level of frequency boosting command to the power management unit and the clock generation unit to switch the relevant computing units to performance mode.

[0012] In some embodiments, a precision compensation step is also included. When the neural network inference precision is detected to drop below a preset precision threshold, the supply voltage of the neural network processing unit is increased, and the precision loss is compensated by increasing the number of iterations or switching to an operator library with a preset bit width. The real-time threshold is dynamically synchronized according to the period of the Ethernet control automation technology protocol to ensure that the vision processing results are delivered to the industrial real-time control software before the start of the next control cycle.

[0013] Compared with the prior art, the present invention has the following beneficial effects: 1. By employing a deep reinforcement learning model for fine-grained resource scheduling, this invention achieves deep suppression of both dynamic and static power consumption during multimedia visual processing. When performing complex industrial visual inspection tasks, this invention can significantly reduce the total power consumption of integrated circuits and substantially increase the number of operations that can be performed per unit of power consumption. 2. This invention addresses the needs of industrial real-time control software by establishing a task priority system and feedback mechanism. By linking visual processing accuracy with execution time, it ensures that critical control commands are completed within preset thresholds under any load fluctuations. The application of an emergency frequency upsampling response mechanism and a high-frequency switching regulator enables the system to respond rapidly to sudden computational demands, effectively preventing industrial production line downtime caused by computational delays. 3. In industrial environments characterized by high temperature, high humidity, and strong electromagnetic interference, this invention can maintain uninterrupted and stable system operation by dynamically adjusting power consumption budget and instruction error correction. 4. Power consumption control based on deep reinforcement learning can automatically optimize the voltage-frequency adjustment curve according to the visual processing characteristics of different industries and production processes. This adaptive capability allows the present invention to achieve the optimal energy efficiency balance point in various multimedia visual scenarios without the need for tedious manual tuning of specific algorithms. Attached Figure Description

[0014] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0015] Figure 1 This is a flowchart of the power consumption control method for the low-power multimedia visual processing integrated circuit of the present invention; Figure 2 This is a schematic diagram of the power consumption prediction based on deep reinforcement learning in this invention. Detailed Implementation

[0016] The following will be based on embodiments of the present invention. Figures 1-2 The technical solutions in the embodiments of the present invention will be clearly and completely described together. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments.

[0017] Application Overview Driven by industrial real-time control software, integrated circuits need to dynamically schedule resources for varying task loads to balance computing performance and energy consumption. Effective power consumption control should be able to adjust the working state of each functional module inside the chip in real time according to the urgency and computational complexity of the vision processing task, so as to minimize system thermal stress while meeting real-time requirements.

[0018] Example 1 This embodiment provides a power consumption control method for a low-power multimedia vision processing integrated circuit. First, in step S1, the task parsing unit inside the integrated circuit acquires the sequence of vision processing requests issued by the industrial real-time control software in real time, extracts feature parameters including image resolution, color depth, target detection accuracy requirements, and task deadlines, and assigns priority coefficients to each task based on the urgency of the control commands; thus, a multi-dimensional perception model of the industrial real-time control task is constructed.

[0019] Specifically, the task parsing unit within the integrated circuit establishes a real-time communication link with the industrial real-time control software through a hardware abstraction layer interface. The task parsing unit includes an instruction stream sniffing module, which intercepts and parses the visual processing request sequence issued by the industrial real-time control software in real time. The visual processing request sequence is stored in a first-in-first-out circular buffer with a preset capacity, and each request contains a task descriptor. The task parsing unit performs deep parsing on the task descriptors, extracting core feature parameters including image resolution, color depth, target detection accuracy requirements, and task deadline.

[0020] Image resolutions cover a variety of mainstream industrial camera output specifications, including 640×480, 1280×720, 1920×1080, and 3840×2160; color depths include multiple preset bit depths such as 8-bit, 10-bit, 12-bit, and 16-bit, used to characterize the quantization accuracy of the raw image data. The task deadline is set within a preset response time range of 10 milliseconds to 500 milliseconds based on the cycle time of the industrial automated production line. This parameter determines the real-time boundary of the vision processing task in the industrial control cycle, ensuring the synchronization of visual feedback and mechanical motion control.

[0021] The task analysis unit further assigns a priority coefficient to each task within a preset range of 0 to 1.0 based on the urgency of the control instructions. The calculation method for the priority coefficient is strictly based on the task type: control instructions involving safe shutdown and emergency obstacle avoidance are set to the first priority, with a priority coefficient set to 0.9 to 1.0; tasks involving product surface defect detection are set to the second priority, with a priority coefficient set to 0.6 to 0.89; and tasks involving logistics statistics and counting are set to the third priority, with a priority coefficient set to 0.1 to 0.59.

[0022] Next is S2, which uses multiple hardware monitoring sensors distributed inside the chip to collect data in real time on the utilization rate, current operating frequency, operating voltage, and core temperature of the central processing unit, graphics processing unit, neural network processing unit, and digital signal processing unit, and summarizes the data to generate a multi-dimensional feature vector reflecting the current hardware load and thermal state.

[0023] Specifically, multiple hardware monitoring sensors distributed at key logic nodes within the chip are used to collect real-time operational status data of the heterogeneous computing units, including a central processing unit, a graphics processing unit, a neural network processing unit, and a digital signal processing unit. The hardware monitoring sensors acquire the utilization rate, current operating frequency, operating voltage, and core temperature of each unit at a sampling frequency of 1000 Hz.

[0024] The central processing unit (CPU) employs a multi-core architecture, supporting multi-level frequency adjustment in 25 MHz increments. Its core temperature monitoring points are distributed near the arithmetic logic unit and floating-point unit of each core, achieving a monitoring accuracy of 0.5 degrees Celsius. The graphics processing unit (GPU) features multiple stream processors and supports dynamic frequency adjustment technology. Its operating voltage is precisely adjusted in 0.01-volt increments within a preset operating voltage range of 0.6 to 1.2 volts, primarily for performing large-scale parallel image filtering, affine transformations, and feature point extraction tasks.

[0025] The neural network processing unit consists of 16 independent computation clusters, each integrating 256 multiply-accumulate units and supporting data operations with various bit widths, including INT8, INT16, and FP16. When performing object recognition inference tasks, the number of computation clusters is dynamically adjusted based on image complexity; for example, only four clusters are activated when processing low-resolution images to achieve a balance between computational performance and static power consumption. The digital signal processing unit is dedicated to performing Bayer transform, white balance correction, and gamma correction on the raw image data. It integrates a 4-megabyte high-speed static random access memory (SRAM) as a data buffer, reducing the number of accesses to external dynamic random access memory (DRAM) to lower the overall system power consumption.

[0026] The hardware monitoring sensors collect data and generate a set of multi-dimensional feature vectors that reflect the current hardware load and thermal state. The data structure of these feature vectors is defined as a 64-dimensional floating-point array, which covers fine-grained indicators such as the instantaneous power consumption estimate, cache hit rate, and bus utilization rate of each computing unit.

[0027] Next is S3, which inputs the feature parameters and feature vectors into the deep reinforcement learning model in the low-power management core of the system-on-chip. Through the multi-layer fully connected neural network inside the model, it performs nonlinear mapping, calculates and outputs voltage step instructions and frequency adjustment ratios for different heterogeneous computing units.

[0028] Specifically, the task feature parameters extracted by S1 are concatenated with the resource state vector generated by S2 to form a global state vector. This global state vector is then input into a deep reinforcement learning model pre-installed in the low-power management core of the on-chip system. The deep reinforcement learning model employs an actor-critic architecture. Its input layer receives the task feature parameters from S1 and the resource state vector from S2. The hidden layer uses a three-layer structure, with each layer containing 256 neurons, and uses a linear rectified function as the activation function to enhance nonlinear mapping capabilities. The output layer generates an action probability distribution for each computational unit through a flexible maximum function. This action probability distribution corresponds to different voltage step commands and frequency adjustment ratios.

[0029] During model training and inference, the reward function of a deep reinforcement learning model is composed of three weighted components: power consumption reduction rate, task timeliness rate, and algorithm accuracy loss. Its mathematical expression is as follows: in, R Indicates the cumulative reward value; P prev The instantaneous power consumption before adjustment; P curr The adjusted instantaneous power consumption; T deadline The deadline for the task; T actual This refers to the actual execution time. Acc req Preset accuracy requirements; Acc curr This is the current output precision; The weighting coefficients are preset. By maximizing the cumulative reward value, the power consumption control strategy is continuously optimized during long-term operation, achieving significant reduction in power consumption while maintaining the task on-time rate to meet preset requirements.

[0030] Furthermore, the power budget dynamic allocation algorithm in S3 also includes a thermal limit protection module. When the chip core temperature fed back by the hardware monitoring sensor exceeds the preset temperature threshold of 85 degrees Celsius, the thermal limit protection module forcibly compresses the total power budget to 50% of the current level and prioritizes shutting down non-critical image enhancement and noise reduction modules to ensure that the integrated circuit does not suffer irreversible physical damage due to local overheating.

[0031] Then there is S4, which drives the power management unit to perform voltage regulation or shutdown operations on multiple independent power domains according to the voltage step command and frequency adjustment ratio, and synchronously controls the clock generation unit to adjust the clock enable signals of each functional module.

[0032] Specifically, based on the voltage stepping command and frequency adjustment ratio output by S3, the low-power management core drives the power management unit to precisely operate multiple independent power domains. The power management unit adopts a high-frequency switching regulator architecture, supports 8 independent controlled outputs, each with a voltage ripple of less than 10 millivolts, and a time delay of less than 20 microseconds from receiving the command to completing voltage stabilization.

[0033] The power management unit, based on instructions, performs shutdown operations on the power domains of idle functional modules or buck operations on lightly loaded modules. Simultaneously, the clock generation unit synchronously adjusts the clock enable signals of each functional module. Clock gating technology is implemented at the register transfer level by inserting automatic clock gating units at the root and branches of the clock tree. When a functional module (such as the motion estimation module of a video codec) is detected to have no valid data input for 16 consecutive clock cycles, its clock supply is automatically cut off, thereby eliminating invalid switching power consumption within that logic region.

[0034] Furthermore, S4 also includes dynamic adjustment of the on-chip bus frequency. Based on the real-time demand for data exchange bandwidth, the system seamlessly switches between multiple preset frequency points such as 100 MHz, 200 MHz, 400 MHz and 800 MHz to match the data throughput rate between different computing units, avoid the bus being at a high frequency waiting for data requests from slow peripherals, and thus further reduce idle power consumption.

[0035] Finally, there is S5, which monitors the execution time and output accuracy of the vision algorithm in real time to determine whether it meets the real-time threshold preset by the industrial real-time control software. If the current power consumption state causes the processing delay to exceed the threshold, an emergency frequency boost response is triggered to readjust the power allocation strategy and establish a closed-loop feedback mechanism.

[0036] Specifically, the execution time and output accuracy of the vision algorithm are monitored in real time. The execution time is measured by a high-precision timer inside the integrated circuit, and the output accuracy is calculated by the confidence evaluation module of the neural network processing unit. It is then determined whether the execution time meets the real-time threshold preset by the industrial real-time control software. The real-time threshold is dynamically synchronized according to the cycle of the industrial bus protocol.

[0037] For Ethernet control automation technology protocols, the real-time threshold is set to 1 millisecond; for process fieldbus protocols, the real-time threshold is set to 10 milliseconds. If the voltage or frequency is too low due to the current power consumption state, causing the processing delay to exceed this threshold, an emergency frequency boost response is immediately triggered. At this time, the low-power management core bypasses the conventional inference of the reinforcement learning model and directly issues the highest-level frequency boost command to the power management unit and clock generation unit, switching the relevant computing units to performance mode to prioritize the execution speed of control commands.

[0038] Furthermore, the closed-loop feedback mechanism in S5 also includes a precision compensation stage. When it is detected that the neural network inference precision drops below the preset precision threshold of 90% due to low voltage, the supply voltage of the neural network processing unit will be automatically increased, and the precision loss will be compensated by increasing the number of iterations or switching to a higher bit width operator library to ensure the reliability of the visual recognition results.

[0039] Example 2 Building upon Example 1, this example further refines the resource contention handling mechanism in multi-task concurrent scenarios. When the industrial real-time control software simultaneously issues multiple vision processing requests with different priorities, the task parsing unit executes a credit-based resource reservation algorithm.

[0040] In S1, a credit limit is assigned to each task. First-priority security tasks receive 70% of the initial credit limit, second-priority detection tasks receive 20%, and third-priority statistical tasks receive 10%. The credit limit directly corresponds to the time slot allocation ratio of each heterogeneous computing unit.

[0041] In S2, hardware monitoring sensors were added to monitor L3 cache utilization. Since multitasking concurrency leads to frequent cache replacements, increasing power consumption from external memory accesses, a cache pollution metric was introduced into the feature vector. If the cache pollution exceeds a preset ratio, the deep reinforcement learning model in S3 will output instructions to reduce the execution frequency of low-priority tasks, thereby reducing their cache usage.

[0042] The deep reinforcement learning model in S3 employs a multi-agent reinforcement learning framework in a multi-task environment. Each computational unit corresponds to an independent sub-agent, and these sub-agents collaborate through a parameter-sharing mechanism. An inter-task interference factor is added to the reward function to penalize behaviors that excessively preempt bus bandwidth, causing increased latency for other high-priority tasks.

[0043] In S4, the power management unit implements finer-grained voltage domain partitioning, with each core of the central processing unit having its own independent power rail. When executing single-threaded visual preprocessing tasks, the power management unit completely powers down other idle cores, rather than simply putting them into standby mode. The clock generation unit uses a fractional frequency synthesizer, capable of fine-tuning the operating frequency in 1 MHz increments, thereby finding the local minimum of power consumption while meeting real-time requirements.

[0044] To address extreme temperature fluctuations in industrial environments, the S5's closed-loop feedback mechanism incorporates a thermal slope prediction algorithm. This algorithm not only monitors the current instantaneous temperature but also calculates the rate of temperature change over time. If the core temperature is detected to be rising at a rate exceeding 5 degrees Celsius per second, it predicts an impending overheating risk and initiates a frequency reduction process before the temperature reaches a preset threshold, thus preventing stress damage to semiconductor devices caused by drastic temperature fluctuations.

[0045] In a specific application example, this embodiment is applied to a collaborative robot vision guidance system in an automotive parts assembly line, which needs to simultaneously handle obstacle avoidance by the robotic arm (first priority), part positioning (second priority), and production progress statistics (third priority). By implementing this method, the integrated circuit successfully reduced the average operating temperature of the chip by 12 degrees Celsius while ensuring that the obstacle avoidance task always has a response latency of less than 5 milliseconds. Furthermore, in a welding workshop with severe electromagnetic interference, the execution accuracy of power consumption control commands reached 99.99%.

[0046] The foregoing has shown and described the basic principles, main features, and advantages of the present invention. It will be apparent to those skilled in the art that the invention is not limited to the details of the exemplary embodiments described above, and that the invention can be implemented in other specific forms without departing from its spirit or essential characteristics. Therefore, the embodiments should be considered illustrative and non-limiting in all respects, and the scope of the invention is defined by the appended claims rather than the foregoing description. Thus, all variations falling within the meaning and scope of equivalents of the claims are intended to be included within the scope of the invention. No reference numerals in the claims should be construed as limiting the scope of the claims.

[0047] Furthermore, it should be understood that although this specification describes embodiments, not every embodiment contains only one independent technical solution. This narrative style is merely for clarity. Those skilled in the art should consider the specification as a whole, and the technical solutions in each embodiment can also be appropriately combined to form other embodiments that can be understood by those skilled in the art.

Claims

1. A power consumption control method for a low-power multimedia visual processing integrated circuit, characterized in that, include: S1. Through the task parsing unit inside the integrated circuit, the sequence of vision processing requests issued by the industrial real-time control software is obtained in real time, and feature parameters including image resolution, color depth, target detection accuracy requirements and task deadline are extracted. Priority coefficients are assigned to each task according to the urgency of the control instructions. S2. Utilize multiple hardware monitoring sensors distributed inside the chip to collect in real time the utilization rate, current operating frequency, operating voltage, and core temperature of the central processing unit, graphics processing unit, neural network processing unit, and digital signal processing unit, and summarize them to generate a multi-dimensional feature vector reflecting the current hardware load and thermal state. S3. Input the feature parameters and the feature vector into the deep reinforcement learning model in the low-power management core of the system-on-a-chip, perform nonlinear mapping through the multi-layer fully connected neural network inside the model, calculate and output the voltage step command and frequency adjustment ratio for different heterogeneous computing units; S4. Based on the voltage step command and frequency adjustment ratio, drive the power management unit to perform voltage adjustment or shutdown operations on multiple independent power domains, and synchronously control the clock generation unit to adjust the clock enable signals of each functional module. S5. Monitor the execution time and output accuracy of the vision algorithm in real time to determine whether it meets the real-time threshold preset by the industrial real-time control software. If the current power consumption state causes the processing delay to exceed the threshold, trigger an emergency frequency boost response, readjust the power allocation strategy, and establish a closed-loop feedback mechanism.

2. The method according to claim 1, characterized in that, In S1, the step of extracting feature parameters and assigning priority coefficients through the task parsing unit inside the integrated circuit includes: The command stream sniffing module in the task parsing unit is used to intercept the sequence of vision processing requests issued by the industrial real-time control software. The visual processing request sequence is stored in a first-in-first-out circular buffer of a preset capacity, wherein each request includes a task descriptor; the task descriptor is parsed to extract image resolutions covering various industrial camera output specifications, color depths of various preset bit depths, target detection accuracy requirements, and task deadlines within a preset response time range. The task type-based priority weighting algorithm sets control commands involving safe shutdown and emergency obstacle avoidance as the first priority, tasks involving product surface defect detection as the second priority, and tasks involving logistics statistics and counting as the third priority. Priority coefficients within a preset value range are assigned to tasks of different priorities.

3. The method according to claim 1, characterized in that, In S2, the core temperature monitoring point of the central processing unit is located between the arithmetic logic unit and the floating-point operation unit; the operating voltage of the graphics processing unit is adjusted in preset voltage steps within a preset operating voltage range; the neural network processing unit consists of multiple independent computing clusters, each computing cluster integrating multiple multiply-accumulate units, and dynamically activating an appropriate number of computing clusters according to the complexity of the image; the digital signal processing unit integrates a high-speed static random access memory of a predetermined capacity as a data buffer, reducing the total power consumption of the system by reducing the number of accesses to off-chip memory; the collected data is aggregated to generate a multi-dimensional feature vector reflecting the current hardware load and thermal state, the multi-dimensional feature vector including the instantaneous power consumption estimate, cache hit rate, and bus occupancy rate of each computing unit.

4. The method according to claim 1, characterized in that, In S3, feature parameters and feature vectors are concatenated to form a global state vector, which is then input into a deep reinforcement learning model in the low-power management core. The deep reinforcement learning model adopts an actor-critic architecture, with a multi-layered hidden layer containing a preset number of neurons in each layer. A linear rectified function is used as the activation function, and the output layer generates an action probability distribution for each computing unit through a flexible maximum function. The reward function of the deep reinforcement learning model is composed of a weighted average of power consumption reduction rate, task timeliness rate, and algorithm accuracy loss, and power consumption control is optimized by maximizing the cumulative reward value.

5. The method according to claim 1, characterized in that, In S4, a power management unit employing a high-frequency switching regulator architecture is used to perform voltage regulation, shutdown, or buck operations on multiple independent power domains according to voltage step instructions. By inserting automatic clock gating units at the root and branches of the clock tree in the register transfer stage, when a specific functional module is detected to have no valid data input for a consecutive preset number of clock cycles, the clock supply to that module is automatically cut off to eliminate invalid switching power consumption. According to the real-time requirements of data exchange bandwidth, the on-chip bus frequency is dynamically adjusted and switched between multiple preset frequency points to match the data throughput rate between different computing units. The power management unit supports multiple independent controlled outputs and ensures that the voltage ripple of each output is within a preset ripple threshold, and that the time delay from receiving the command to completing voltage stabilization is within a predetermined switching time range.

6. The method according to claim 1, characterized in that, In S5, the execution time of the vision algorithm is measured by a high-precision timer inside the integrated circuit, and the output accuracy is calculated by the confidence evaluation module of the neural network processing unit. The execution time is compared with the real-time threshold of the corresponding industrial bus protocol cycle. When the processing delay is detected to exceed the real-time threshold, the low-power management core sends the highest level of frequency boosting command to the power management unit and the clock generation unit to switch the relevant computing units to performance mode.

7. The method according to claim 6, characterized in that, It also includes a precision compensation step. When the neural network inference precision is detected to drop below a preset precision threshold, the supply voltage of the neural network processing unit is increased, and the precision loss is compensated by increasing the number of iterations or switching to an operator library with a preset bit width. The real-time threshold is dynamically synchronized according to the cycle of the Ethernet control automation technology protocol to ensure that the vision processing results are delivered to the industrial real-time control software before the start of the next control cycle.

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